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2GB DDR3 SDRAM 72Bit SO-DIMM

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Apacer Memory Product Specification

2GB DDR3 SDRAM 72bit SO-DIMM

Speed Grade
Max
Frequency Latency

533MHz CL7

  • CAS
  • Component Number of

  • Part Number Bandwidth
  • Density Organization

  • Composition
  • Rank

  • 2GB
  • 256Mx72
  • 256Mx8 * 9

1

78.A2GCB.AF10C 8.5GB/sec 1066Mbps

Specifications

zzzzzz

Support ECC error detection and correction On DIMM Thermal Sensor: YES Density:2GB Organization – 256 word x 72 bits, 1rank Mounting 9 pieces of 2G bits DDR3 SDRAM sealed FBGA Package: 204-pin socket type small outline dual in line memory module (SO-DIMM) --- PCB height: 30.0mm --- Lead pitch: 0.6mm (pin) --- Lead-free (RoHS compliant)

zzzzzzzzz

Power supply: VDD = 1.5V + 0.075V Eight internal banks for concurrent operation ( components) Interface: SSTL_15 Burst lengths (BL): 8 and 4 with Burst Chop (BC) /CAS Latency (CL): 6,7,8,9 /CAS Write latency (CWL): 5,6,7 Precharge: Auto precharge option for each burst access Refresh: Auto-refresh, self-refresh Refresh cycles --- Average refresh period

  • 7.8
  • at 0℃ < TC < +85℃

㎲

3.9 at +85℃ < TC < +95℃

㎲

z

Operating case temperature range --- TC = 0℃ to +95℃

zz

Serial presence detect (SPD) VDDSPD = 3.0V to 3.6V

Apacer Memory Product Specification

Features

zzz

Double-data-rate architecture; two data transfers per clock cycle. The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture. Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver.

zzzz

DQS is edge-aligned with data for READs; center aligned with data for WRITEs. Differential clock inputs (CK and /CK) DLL aligns DQ and DQS transitions with CK transitions Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS.

zzz

Data mask (DM) for write data. Posted /CAS by programmable additive latency for better command and data bus efficiency. On-Die-Termination (ODT) for better signal quality --- Synchronous ODT --- Dynamic ODT --- Asynchronous ODT

zzzzz

Multi Purpose Register (MPR) for temperature read out. ZQ calibration for DQ drive and ODT. Programmable Partial Array Self-Refresh (PASR) /RESET pin for Power-up sequence and reset function. SRT range: --- Normal/extended --- Auto/manual self-refresh

z

Programmable Output driver impedance control

Description

The 78.A2GCB.AF10C is a 256MX72 DDR3 SDRAM high density SO-UDIMM. This memory module consists of eighteen CMOS 256MX8 bits with 8 banks DDR3 synchronous DRAMs in BGA packages and a 2K EEPROM in an 8-pin MLF package. This module is a 204-pin small outline dual in line memory module and is intended for mounting into a connector socket. Decoupling capacitors are mounted on the printed circuit board for each DDR3 SDRAM.

Apacer Memory Product Specification

Pin Configurations

204-PIN DDR3 SO-UDIMM FRONT
Pin Name Pin Name Pin Name Pin
204-PIN DDR3 SO-UDIMM BACK

  • Name Pin Name Pin Name Pin
  • Name

A2

Pin Name

  • 158 VSS
  • 1

3

  • VREFDQ 53
  • VSS
  • 105
  • A1

A0

  • 157
  • DM5
  • 2

468
VSS DQ4 DQ5 VSS
54 56 58
DQ28 106

  • DQ29 108
  • VSS

DQ0 DQ1 VSS DM0 DQ2 DQ3 VSS DQ8 DQ9 VSS
55 57 59 61 63 65 67 69 71 73

  • DQ24 107
  • 159 DQ42
  • BA1

VDD CK1 CK1# VDD
160 DQ46

  • 162 DQ47
  • 5
  • DQ25 109 VDD 161 DQ43
  • VSS
  • 110

  • 7
  • DM3

VSS

  • 111 CK0 163
  • VSS
  • 60 DQS3# 112

DQS3 114 VSS 116

  • 164
  • VSS

  • 9
  • 113 CK0# 165 DQ48
  • 10 DQS0# 62
  • 166 DQ52

  • 168 DQ53
  • 11

13 15 17 19 21 23
DQ26 115 VDD 167 DQ49 DQ27 117 A10/AP 169 VSS
12 14
DQS0 VSS
64 66 68 70 72 74 76 78 80
DQ30 118 NC/CS3# 170 DQ31 120 NC/CS2# 172
VSS

  • DM6
  • VSS

CB0 CB1 VSS

  • 119 BA0 171 DQS6# 16
  • DQ6

DQ7 VSS
121 WE# 173 DQS6 123 VDD 175 VSS 125 CAS# 177 DQ50
18 20 22 24 26 28
VSS CB4 CB5 DM8 VSS CB6 CB7
122 124 126 128 130 132 134
RAS# VDD
174 DQ54 176 DQ55
DQ12 DQ13 VSS
ODT0 ODT1 A13

  • 178
  • VSS

75 DQS8# 127 CS0# 179 DQ51
DQS8 129 CS1# 181 VSS
180 DQ60

  • 182 DQ61
  • 25 DQS1# 77

27 29 31 33 35 37 39 41
DQS1 VSS
79 81 83 85 87 89 91 93
VSS CB2 CB3 VDD
131 VDD 183 DQ56 133 DQ32 185 DQ57

  • DM1
  • VDD
  • 184
  • VSS

  • 30 RESET# 82
  • DQ36

DQ37 VSS
186 DQS7#

  • 188 DQS7
  • DQ10

DQ11 VSS
135 DQ33 187 137 VSS 189
VSS DM7
32 34 36 38 40 42
VSS DQ14 DQ15 VSS
84 VREFCA 136 86 88 90 92 94 96 98
VDD A15* A14* A9
138 140 142 144 146 148 150 152

  • 190
  • VSS

CKE0 139 DQS4# 191 DQ58 CKE1 141 DQS4 193 DQ59

  • DM4
  • 192 DQ62

  • 194 DQ63
  • DQ16

DQ17 VSS
DQ38 DQ39 VSS

  • BA2
  • 143 VSS 195

145 DQ34 197
VSS SA0
DQ20 DQ21 DM2

  • 196
  • VSS

  • VDD
  • VDD

A11 A7
198 EVENT#*

  • 43 DQS2# 95 A12/BC# 147 DQ35 199 VDDSPD 44
  • DQ44

DQ45 VSS
200 202 204
SDA SCL VTT
45 47
DQS2 VSS
97 99
A8 A5
149 VSS 201 151 DQ40 203 153 DQ41
SA1 VTT
46 48 50 52
VSS DQ22 100 DQ23 102
A6

  • 49
  • DQ18

DQ19
101 103
VDD A3
VDD A4
154 DQS5#

  • 156 DQS5
  • 51
  • 155 VSS
  • VSS
  • 104

Notes: * These pins are not used in this module.

Apacer Memory Product Specification

Pin Description

  • Pin name
  • Function

Address input

  • A0 to A14
  • Row address
  • A0 to A14

  • A0 to A9
  • Column address

Auto precharge Burst chop
A10 (AP) A12 (/BC) BA0,BA1,BA2 DQ0 to DQ63 /RAS
Bank select address Data input/output Row address strobe command Column address strobe command Write enable
/CAS /WE /CS0,/CS1 CKE0,CKE1 CK0,CK1 /CK0,/CK1 DQS0 to DQS7,/DQS0 to /DQS7 DM0 to DM7 SCL
Chip select Clock enable Clock input Differential clock input Input and output data strobe Input mask Clock input for serial PD Data input/output for serial PD Serial address input Power for internal circuit Power for serial EEPROM Reference voltage for CA Reference voltage for DQ Ground
SDA SA0,SA1 VDD VDDSPD VREFCA VREFDQ VSS

  • VTT
  • I/O termination supply for SDRAM

Set DRAM to known state ODT control
/RESET ODT0,ODT1

  • /EVENT
  • Temperature event pin

  • No connection
  • NC

Apacer Memory Product Specification

Functional Block Diagram

Figure 2: Functional Block Diagram

S0#

BA[2:0]
A[15/14/13:0]
RAS#

BA[2:0]: DDR3 SDRAM

A[15/14/13:0]: DDR3 SDRAM

RAS#: DDR3 SDRAM CAS#: DDR3 SDRAM WE#: DDR3 SDRAM

DQS0# DQS0 DM0
DQS4# DQS4 DM4

CAS#

DM CS# DQ DQS#

DQ

DM CS# DQ DQS#

WE#

DQ DQ DQ DQ DQ DQ DQ DQ
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DQ DQ DQ DQ DQ DQ DQ

CKE0

CKE0: DDR3 SDRAM ODT0: DDR3 SDRAM RESET#: DDR3 SDRAM

ODT0

  • U1
  • U6

RESET#

CK0 CK0#

  • ZQ
  • ZQ

DDR3 SDRAMs

DQS1# DQS1 DM1
DQS5# DQS5 DM5

  • V
  • V

SS

CK1 CK1#

SS

DM CS# DQ DQS#

DQ

DM CS# DQ DQS#

Clock, control, command, and address line terminations:

DQ DQ DQ DQ DQ DQ DQ DQ
DQ8 DQ9
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQ DQ DQ DQ DQ DQ DQ
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

DDR3

  • U2
  • U7

SDRAM
CKE0, A[15/14/13:0],

  • RAS#, CAS#, WE#,
  • V

TT

ODT0, BA[2:0], S0#

  • ZQ
  • ZQ

DDR3
DQS2#

DQS2 DM2
DQS6# DQS6 DM6
SDRAM

  • V
  • V

  • SS
  • SS

CK CK#

V

DD

DM CS# DQ DQS#

DQ

DM CS# DQ DQS#

DQ DQ DQ DQ DQ DQ DQ DQ
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DQ DQ DQ DQ DQ DQ DQ

  • U10
  • U3
  • U8

Temperature sensor/

  • SDA
  • SCL

SPD EEPROM

ZQ
ZQ

EVT A0 A1 A2

DQS7# DQS7 DM7
DQS3# DQS3 DM3

  • V
  • V

  • SA2
  • SA0 SA1

EVENT#

  • SS
  • SS

DM CS# DQ DQS#

DQ

DM CS# DQ DQS#

DQ DQ DQ DQ DQ DQ DQ DQ
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DQ DQ DQ DQ DQ DQ DQ

  • U4
  • U9

ZQ
ZQ

DQS8# DQS8 DM8

  • V
  • V

  • SS
  • SS

V
Temperature sensor/SPD EEPROM

DDR3 SDRAM

DDSPD

DM CS# DQ DQS#

DQ DQ DQ DQ DQ DQ DQ DQ
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7

V

DD

  • V
  • Control, command, and address termination

DDR3 SDRAM

TT REFCA

U5

VV
DDR3 SDRAM

DDR3 SDRAM

REFDQ

ZQ

V

SS

V

SS

1.
Note:
The ZQ ball on each DDR3 component is connected to an external 240Ω ±1% resistor that is tied to ground. It is used for the calibration of the component’s ODT and output driver.

Apacer Memory Product Specification

Dimensions

(All dimensions are in millimeters with ±0.15mm tolerance unless specified otherwise.)

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    Rev. 1.1, Apr. 2018 M391A1K43BB1 M391A1K43BB2 M391A2K43BB1 288pin ECC Unbuffered DIMM based on 8Gb B-die 78FBGA with Lead-Free & Halogen-Free (RoHS compliant) datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. © 2018 Samsung Electronics Co., Ltd.GG All rights reserved. - 1 - Rev. 1.1 ECC Unbuffered DIMM datasheet DDR4 SDRAM Revision History Revision No. History Draft Date Remark Editor 0.5 - First SPEC release 15th Nov, 2017 Preliminary J.Y.Bae - Separate ECC and Non ECC datasheets. J.H.Han 1.0 - Final datasheet. 13th Dec, 2017 Final J.Y.Bae - Correct typo. J.H.Han - Correct speed bin table numbering. - Add DRAM Package Electrical Specifications (x4/x8) table.
  • Dynamic Random Access Memory Topics

    Dynamic Random Access Memory Topics

    Dynamic Random Access Memory Topics Simple DRAM Fast Page Mode (FPM) DRAM Extended Data Out (EDO) DRAM Burst EDO (BEDO) DRAM Synchronous DRAM (SDRAM) Rambus DRAM (RDRAM) Double Data Rate (DDR) SDRAM One capacitor and transistor of power, the discharge y Leaks a smallcapacitor amount slowly Simplicit refresh Requires top sk de in ed Us le ti la o v General DRAM Formats • DRAM is produced as integrated circuits (ICs) bonded and mounted into plastic packages with metal pins for connection to control signals and buses • In early use individual DRAM ICs were usually either installed directly to the motherboard or on ISA expansion cards • later they were assembled into multi-chip plug-in modules (DIMMs, SIMMs, etc.) General DRAM formats • Some Standard Module Type: • DRAM chips (Integrated Circuit or IC) • Dual in-line Package (DIP) • DRAM (memory) modules • Single in-line in Package(SIPP) • Single In-line Memory Module (SIMM) • Dual In-line Memory Module (DIMM) • Rambus In-line Memory Module (RIMM) • Small outline DIMM (SO-DIMM) Dual in-line Package (DIP) • is an electronic component package with a rectangular housing and two parallel rows of electrical connecting pins • 14 pins Single in-line in Package (SIPP) • It consisted of a small printed circuit board upon which were mounted a number of memory chips. • It had 30 pins along one edge which mated with matching holes in the motherboard of the computer. Single In-line Memory Module (SIMM) SIMM can be a 30 pin memory module or a 72 pin Dual In-line Memory Module (DIMM) Two types of DIMMs: a 168-pin SDRAM module and a 184-pin DDR SDRAM module.
  • SDRAM Memory Systems: Architecture Overview and Design Verification SDRAM Memory Systems: Architecture Overview and Design Verification Primer

    SDRAM Memory Systems: Architecture Overview and Design Verification SDRAM Memory Systems: Architecture Overview and Design Verification Primer

    Primer SDRAM Memory Systems: Architecture Overview and Design Verification SDRAM Memory Systems: Architecture Overview and Design Verification Primer Table of Contents Introduction . 3 - 4 DRAM Trends . .3 DRAM . 4 - 6 SDRAM . 6 - 9 DDR SDRAM . .6 DDR2 SDRAM . .7 DDR3 SDRAM . .8 DDR4 SDRAM . .9 GDDR and LPDDR . .9 DIMMs . 9 - 13 DIMM Physical Size . 9 DIMM Data Width . 9 DIMM Rank . .10 DIMM Memory Size & Speed . .10 DIMM Architecture . .10 Serial Presence Detect . .12 Memory System Design . .13 - 15 Design Simulation . .13 Design Verification . .13 Verification Strategy . .13 SDRAM Verification . .14 Glossary . .16 - 19 2 www.tektronix.com/memory SDRAM Memory Systems: Architecture Overview and Design Verification Primer Introduction Memory needs to be compatible with a wide variety of memory controller hubs used by the computer DRAM (Dynamic Random Access Memory) is attractive to manufacturers. designers because it provides a broad range of performance Memory needs to work when a mixture of different and is used in a wide variety of memory system designs for manufacturer’s memories is used in the same memory computers and embedded systems. This DRAM memory system of the computer. primer provides an overview of DRAM concepts, presents potential future DRAM developments and offers an overview Open memory standards are useful in helping to ensure for memory design improvement through verification. memory compatibility. DRAM Trends On the other hand, embedded systems typically use a fixed There is a continual demand for computer memories to be memory configuration, meaning the user does not modify larger, faster, lower powered and physically smaller. These the memory system after purchasing the product.