
<p>Apacer Memory Product Specification </p><p><strong>2GB DDR3 SDRAM 72bit SO-DIMM </strong></p><p><strong>Speed Grade </strong><br><strong>Max </strong><br><strong>Frequency Latency </strong></p><p>533MHz CL7 </p><p></p><ul style="display: flex;"><li style="flex:1"><strong>CAS </strong></li><li style="flex:1"><strong>Component Number of </strong></li></ul><p></p><ul style="display: flex;"><li style="flex:1"><strong>Part Number Bandwidth </strong></li><li style="flex:1"><strong>Density Organization </strong></li></ul><p></p><ul style="display: flex;"><li style="flex:1"><strong>Composition </strong></li><li style="flex:1"><strong>Rank </strong></li></ul><p></p><p></p><ul style="display: flex;"><li style="flex:1">2GB </li><li style="flex:1">256Mx72 </li><li style="flex:1">256Mx8 * 9 </li></ul><p></p><p>1</p><p>78.A2GCB.AF10C 8.5GB/sec 1066Mbps </p><p><strong>Specifications </strong></p><p>zzzzzz</p><p>Support ECC error detection and correction On DIMM Thermal Sensor: YES Density:2GB Organization – 256 word x 72 bits, 1rank Mounting 9 pieces of 2G bits DDR3 SDRAM sealed FBGA Package: 204-pin socket type small outline dual in line memory module (SO-DIMM) --- PCB height: 30.0mm --- Lead pitch: 0.6mm (pin) --- Lead-free (RoHS compliant) </p><p>zzzzzzzzz</p><p>Power supply: VDD = 1.5V + 0.075V Eight internal banks for concurrent operation ( components) Interface: SSTL_15 Burst lengths (BL): 8 and 4 with Burst Chop (BC) /CAS Latency (CL): 6,7,8,9 /CAS Write latency (CWL): 5,6,7 Precharge: Auto precharge option for each burst access Refresh: Auto-refresh, self-refresh Refresh cycles --- Average refresh period </p><ul style="display: flex;"><li style="flex:1">7.8 </li><li style="flex:1">at 0℃ < TC < +85℃ </li></ul><p></p><p>㎲</p><p>3.9 at +85℃ < TC < +95℃ </p><p>㎲</p><p>z</p><p>Operating case temperature range --- TC = 0℃ to +95℃ </p><p>zz</p><p>Serial presence detect (SPD) VDDSPD = 3.0V to 3.6V </p><p>Apacer Memory Product Specification </p><p><strong>Features </strong></p><p>zzz</p><p>Double-data-rate architecture; two data transfers per clock cycle. The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture. Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver. </p><p>zzzz</p><p>DQS is edge-aligned with data for READs; center aligned with data for WRITEs. Differential clock inputs (CK and /CK) DLL aligns DQ and DQS transitions with CK transitions Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS. </p><p>zzz</p><p>Data mask (DM) for write data. Posted /CAS by programmable additive latency for better command and data bus efficiency. On-Die-Termination (ODT) for better signal quality --- Synchronous ODT --- Dynamic ODT --- Asynchronous ODT </p><p>zzzzz</p><p>Multi Purpose Register (MPR) for temperature read out. ZQ calibration for DQ drive and ODT. Programmable Partial Array Self-Refresh (PASR) /RESET pin for Power-up sequence and reset function. SRT range: --- Normal/extended --- Auto/manual self-refresh </p><p>z</p><p>Programmable Output driver impedance control </p><p><strong>Description </strong></p><p>The 78.A2GCB.AF10C is a 256MX72 DDR3 SDRAM high density SO-UDIMM. This memory module consists of eighteen CMOS 256MX8 bits with 8 banks DDR3 synchronous DRAMs in BGA packages and a 2K EEPROM in an 8-pin MLF package. This module is a 204-pin small outline dual in line memory module and is intended for mounting into a connector socket. Decoupling capacitors are mounted on the printed circuit board for each DDR3 SDRAM. </p><p>Apacer Memory Product Specification </p><p><strong>Pin Configurations </strong></p><p><strong>204-PIN DDR3 SO-UDIMM FRONT </strong><br><strong>Pin Name Pin Name Pin Name Pin </strong><br><strong>204-PIN DDR3 SO-UDIMM BACK </strong></p><ul style="display: flex;"><li style="flex:1"><strong>Name Pin Name Pin Name Pin </strong></li><li style="flex:1"><strong>Name </strong></li></ul><p></p><p>A2 </p><p><strong>Pin Name </strong></p><p></p><ul style="display: flex;"><li style="flex:1">158 VSS </li><li style="flex:1">1</li></ul><p>3</p><ul style="display: flex;"><li style="flex:1">VREFDQ 53 </li><li style="flex:1">VSS </li><li style="flex:1">105 </li><li style="flex:1">A1 </li></ul><p>A0 </p><ul style="display: flex;"><li style="flex:1">157 </li><li style="flex:1">DM5 </li><li style="flex:1">2</li></ul><p>468<br>VSS DQ4 DQ5 VSS <br>54 56 58 <br>DQ28 106 </p><ul style="display: flex;"><li style="flex:1">DQ29 108 </li><li style="flex:1">VSS </li></ul><p>DQ0 DQ1 VSS DM0 DQ2 DQ3 VSS DQ8 DQ9 VSS <br>55 57 59 61 63 65 67 69 71 73 </p><ul style="display: flex;"><li style="flex:1">DQ24 107 </li><li style="flex:1">159 DQ42 </li><li style="flex:1">BA1 </li></ul><p>VDD CK1 CK1# VDD <br>160 DQ46 </p><ul style="display: flex;"><li style="flex:1">162 DQ47 </li><li style="flex:1">5</li><li style="flex:1">DQ25 109 VDD 161 DQ43 </li><li style="flex:1">VSS </li><li style="flex:1">110 </li></ul><p></p><ul style="display: flex;"><li style="flex:1">7</li><li style="flex:1">DM3 </li></ul><p>VSS </p><ul style="display: flex;"><li style="flex:1">111 CK0 163 </li><li style="flex:1">VSS </li><li style="flex:1">60 DQS3# 112 </li></ul><p>DQS3 114 VSS 116 </p><ul style="display: flex;"><li style="flex:1">164 </li><li style="flex:1">VSS </li></ul><p></p><ul style="display: flex;"><li style="flex:1">9</li><li style="flex:1">113 CK0# 165 DQ48 </li><li style="flex:1">10 DQS0# 62 </li><li style="flex:1">166 DQ52 </li></ul><p></p><ul style="display: flex;"><li style="flex:1">168 DQ53 </li><li style="flex:1">11 </li></ul><p>13 15 17 19 21 23 <br>DQ26 115 VDD 167 DQ49 DQ27 117 A10/AP 169 VSS <br>12 14 <br>DQS0 VSS <br>64 66 68 70 72 74 76 78 80 <br>DQ30 118 NC/CS3# 170 DQ31 120 NC/CS2# 172 <br>VSS </p><ul style="display: flex;"><li style="flex:1">DM6 </li><li style="flex:1">VSS </li></ul><p>CB0 CB1 VSS </p><ul style="display: flex;"><li style="flex:1">119 BA0 171 DQS6# 16 </li><li style="flex:1">DQ6 </li></ul><p>DQ7 VSS <br>121 WE# 173 DQS6 123 VDD 175 VSS 125 CAS# 177 DQ50 <br>18 20 22 24 26 28 <br>VSS CB4 CB5 DM8 VSS CB6 CB7 <br>122 124 126 128 130 132 134 <br>RAS# VDD <br>174 DQ54 176 DQ55 <br>DQ12 DQ13 VSS <br>ODT0 ODT1 A13 </p><ul style="display: flex;"><li style="flex:1">178 </li><li style="flex:1">VSS </li></ul><p>75 DQS8# 127 CS0# 179 DQ51 <br>DQS8 129 CS1# 181 VSS <br>180 DQ60 </p><ul style="display: flex;"><li style="flex:1">182 DQ61 </li><li style="flex:1">25 DQS1# 77 </li></ul><p>27 29 31 33 35 37 39 41 <br>DQS1 VSS <br>79 81 83 85 87 89 91 93 <br>VSS CB2 CB3 VDD <br>131 VDD 183 DQ56 133 DQ32 185 DQ57 </p><ul style="display: flex;"><li style="flex:1">DM1 </li><li style="flex:1">VDD </li><li style="flex:1">184 </li><li style="flex:1">VSS </li></ul><p></p><ul style="display: flex;"><li style="flex:1">30 RESET# 82 </li><li style="flex:1">DQ36 </li></ul><p>DQ37 VSS <br>186 DQS7# </p><ul style="display: flex;"><li style="flex:1">188 DQS7 </li><li style="flex:1">DQ10 </li></ul><p>DQ11 VSS <br>135 DQ33 187 137 VSS 189 <br>VSS DM7 <br>32 34 36 38 40 42 <br>VSS DQ14 DQ15 VSS <br>84 VREFCA 136 86 88 90 92 94 96 98 <br>VDD A15* A14* A9 <br>138 140 142 144 146 148 150 152 </p><ul style="display: flex;"><li style="flex:1">190 </li><li style="flex:1">VSS </li></ul><p>CKE0 139 DQS4# 191 DQ58 CKE1 141 DQS4 193 DQ59 </p><ul style="display: flex;"><li style="flex:1">DM4 </li><li style="flex:1">192 DQ62 </li></ul><p></p><ul style="display: flex;"><li style="flex:1">194 DQ63 </li><li style="flex:1">DQ16 </li></ul><p>DQ17 VSS <br>DQ38 DQ39 VSS </p><ul style="display: flex;"><li style="flex:1">BA2 </li><li style="flex:1">143 VSS 195 </li></ul><p>145 DQ34 197 <br>VSS SA0 <br>DQ20 DQ21 DM2 </p><ul style="display: flex;"><li style="flex:1">196 </li><li style="flex:1">VSS </li></ul><p></p><ul style="display: flex;"><li style="flex:1">VDD </li><li style="flex:1">VDD </li></ul><p>A11 A7 <br>198 EVENT#* </p><ul style="display: flex;"><li style="flex:1">43 DQS2# 95 A12/BC# 147 DQ35 199 VDDSPD 44 </li><li style="flex:1">DQ44 </li></ul><p>DQ45 VSS <br>200 202 204 <br>SDA SCL VTT <br>45 47 <br>DQS2 VSS <br>97 99 <br>A8 A5 <br>149 VSS 201 151 DQ40 203 153 DQ41 <br>SA1 VTT <br>46 48 50 52 <br>VSS DQ22 100 DQ23 102 <br>A6 </p><ul style="display: flex;"><li style="flex:1">49 </li><li style="flex:1">DQ18 </li></ul><p>DQ19 <br>101 103 <br>VDD A3 <br>VDD A4 <br>154 DQS5# </p><ul style="display: flex;"><li style="flex:1">156 DQS5 </li><li style="flex:1">51 </li><li style="flex:1">155 VSS </li><li style="flex:1">VSS </li><li style="flex:1">104 </li></ul><p>Notes: * These pins are not used in this module. </p><p>Apacer Memory Product Specification </p><p><strong>Pin Description </strong></p><p></p><ul style="display: flex;"><li style="flex:1">Pin name </li><li style="flex:1">Function </li></ul><p></p><p>Address input </p><ul style="display: flex;"><li style="flex:1">A0 to A14 </li><li style="flex:1">Row address </li><li style="flex:1">A0 to A14 </li></ul><p></p><ul style="display: flex;"><li style="flex:1">A0 to A9 </li><li style="flex:1">Column address </li></ul><p>Auto precharge Burst chop <br>A10 (AP) A12 (/BC) BA0,BA1,BA2 DQ0 to DQ63 /RAS <br>Bank select address Data input/output Row address strobe command Column address strobe command Write enable <br>/CAS /WE /CS0,/CS1 CKE0,CKE1 CK0,CK1 /CK0,/CK1 DQS0 to DQS7,/DQS0 to /DQS7 DM0 to DM7 SCL <br>Chip select Clock enable Clock input Differential clock input Input and output data strobe Input mask Clock input for serial PD Data input/output for serial PD Serial address input Power for internal circuit Power for serial EEPROM Reference voltage for CA Reference voltage for DQ Ground <br>SDA SA0,SA1 VDD VDDSPD VREFCA VREFDQ VSS </p><ul style="display: flex;"><li style="flex:1">VTT </li><li style="flex:1">I/O termination supply for SDRAM </li></ul><p>Set DRAM to known state ODT control <br>/RESET ODT0,ODT1 </p><ul style="display: flex;"><li style="flex:1">/EVENT </li><li style="flex:1">Temperature event pin </li></ul><p></p><ul style="display: flex;"><li style="flex:1">No connection </li><li style="flex:1">NC </li></ul><p></p><p>Apacer Memory Product Specification </p><p>Functional Block Diagram </p><p>Figure 2: Functional Block Diagram </p><p>S0# </p><p>BA[2:0] <br>A[15/14/13:0] <br>RAS# </p><p>BA[2:0]: DDR3 SDRAM </p><p>A[15/14/13:0]: DDR3 SDRAM </p><p>RAS#: DDR3 SDRAM CAS#: DDR3 SDRAM WE#: DDR3 SDRAM </p><p>DQS0# DQS0 DM0 <br>DQS4# DQS4 DM4 </p><p>CAS# </p><p>DM CS# DQ DQS# </p><p>DQ </p><p>DM CS# DQ DQS# </p><p>WE# </p><p>DQ DQ DQ DQ DQ DQ DQ DQ <br>DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 <br>DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 <br>DQ DQ DQ DQ DQ DQ DQ </p><p>CKE0 </p><p>CKE0: DDR3 SDRAM ODT0: DDR3 SDRAM RESET#: DDR3 SDRAM </p><p>ODT0 </p><p></p><ul style="display: flex;"><li style="flex:1">U1 </li><li style="flex:1">U6 </li></ul><p></p><p>RESET# </p><p>CK0 CK0# </p><p></p><ul style="display: flex;"><li style="flex:1">ZQ </li><li style="flex:1">ZQ </li></ul><p></p><p>DDR3 SDRAMs </p><p>DQS1# DQS1 DM1 <br>DQS5# DQS5 DM5 </p><ul style="display: flex;"><li style="flex:1">V</li><li style="flex:1">V</li></ul><p></p><p>SS </p><p>CK1 CK1# </p><p>SS </p><p>DM CS# DQ DQS# </p><p>DQ </p><p>DM CS# DQ DQS# </p><p>Clock, control, command, and address line terminations: </p><p>DQ DQ DQ DQ DQ DQ DQ DQ <br>DQ8 DQ9 <br>DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 <br>DQ DQ DQ DQ DQ DQ DQ <br>DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 </p><p>DDR3 </p><p></p><ul style="display: flex;"><li style="flex:1">U2 </li><li style="flex:1">U7 </li></ul><p></p><p>SDRAM <br>CKE0, A[15/14/13:0], </p><p></p><ul style="display: flex;"><li style="flex:1">RAS#, CAS#, WE#, </li><li style="flex:1">V</li></ul><p></p><p>TT </p><p>ODT0, BA[2:0], S0# </p><p></p><ul style="display: flex;"><li style="flex:1">ZQ </li><li style="flex:1">ZQ </li></ul><p></p><p>DDR3 <br>DQS2# </p><p>DQS2 DM2 <br>DQS6# DQS6 DM6 <br>SDRAM </p><ul style="display: flex;"><li style="flex:1">V</li><li style="flex:1">V</li></ul><p></p><p></p><ul style="display: flex;"><li style="flex:1">SS </li><li style="flex:1">SS </li></ul><p></p><p>CK CK# </p><p>V</p><p>DD </p><p>DM CS# DQ DQS# </p><p>DQ </p><p>DM CS# DQ DQS# </p><p>DQ DQ DQ DQ DQ DQ DQ DQ <br>DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 <br>DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 <br>DQ DQ DQ DQ DQ DQ DQ </p><p></p><ul style="display: flex;"><li style="flex:1">U10 </li><li style="flex:1">U3 </li><li style="flex:1">U8 </li></ul><p></p><p>Temperature sensor/ </p><p></p><ul style="display: flex;"><li style="flex:1">SDA </li><li style="flex:1">SCL </li></ul><p></p><p>SPD EEPROM </p><p>ZQ <br>ZQ </p><p>EVT A0 A1 A2 </p><p>DQS7# DQS7 DM7 <br>DQS3# DQS3 DM3 </p><ul style="display: flex;"><li style="flex:1">V</li><li style="flex:1">V</li></ul><p></p><p></p><ul style="display: flex;"><li style="flex:1">SA2 </li><li style="flex:1">SA0 SA1 </li></ul><p></p><p>EVENT# </p><p></p><ul style="display: flex;"><li style="flex:1">SS </li><li style="flex:1">SS </li></ul><p></p><p>DM CS# DQ DQS# </p><p>DQ </p><p>DM CS# DQ DQS# </p><p>DQ DQ DQ DQ DQ DQ DQ DQ <br>DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 <br>DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 <br>DQ DQ DQ DQ DQ DQ DQ </p><p></p><ul style="display: flex;"><li style="flex:1">U4 </li><li style="flex:1">U9 </li></ul><p></p><p>ZQ <br>ZQ </p><p>DQS8# DQS8 DM8 </p><ul style="display: flex;"><li style="flex:1">V</li><li style="flex:1">V</li></ul><p></p><p></p><ul style="display: flex;"><li style="flex:1">SS </li><li style="flex:1">SS </li></ul><p></p><p>V<br>Temperature sensor/SPD EEPROM </p><p>DDR3 SDRAM </p><p>DDSPD </p><p>DM CS# DQ DQS# </p><p>DQ DQ DQ DQ DQ DQ DQ DQ <br>CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 </p><p>V</p><p>DD </p><p></p><ul style="display: flex;"><li style="flex:1">V</li><li style="flex:1">Control, command, and address termination </li></ul><p></p><p>DDR3 SDRAM </p><p>TT REFCA </p><p>U5 </p><p>VV<br>DDR3 SDRAM </p><p>DDR3 SDRAM </p><p>REFDQ </p><p>ZQ </p><p>V</p><p>SS </p><p>V</p><p>SS </p><p>1. <br>Note: <br>The ZQ ball on each DDR3 component is connected to an external 240Ω ±1% resistor that is tied to ground. It is used for the calibration of the component’s ODT and output driver. </p><p>Apacer Memory Product Specification </p><p><strong>Dimensions </strong></p><p>(All dimensions are in millimeters with ±0.15mm tolerance unless specified otherwise.) </p>
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