DOCSLIB.ORG

DDR4 SDRAM Registered DIMM Based on 8Gb A-Die

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
DDR4 SDRAM Registered DIMM Based on 8Gb A-Die 288pin DDR4 SDRAM Registered DIMM DDR4 SDRAM Registered DIMM Based on 8Gb A-die HMA81GR7AFR8N HMA82GR7AFR8N HMA82GR7AFR4N HMA84GR7AFR4N *SK hynix reserves the right to change products or specifications without notice. Rev. 1.2 / Jun.2016 1 Revision History Revision No. History Draft Date Remark 0.1 Initial Release Oct.2015 0.2 Added 2666Mbps Feb.2016 0.9 Updated IDD Specification Mar.2016 1.0 Updated IDD Specification(1Rx4/2Rx4) Mar.2016 1.1 Updated IPP Specification Apr.2016 1.2 Updated IDD/IPP Specification Jun.2016 Rev. 1.2 / Jun.2016 2 Description SK hynix Registered DDR4 SDRAM DIMMs (Registered Double Data Rate Synchronous DRAM Dual In-Line Memory Modules) are low power, high-speed operation memory modules that use DDR4 SDRAM devices. These Registered SDRAM DIMMs are intended for use as main memory when installed in systems such as servers and workstations. Features • Power Supply: VDD=1.2V (1.14V to 1.26V) • VDDQ = 1.2V (1.14V to 1.26V) • VPP - 2.5V (2.375V to 2.75V) • VDDSPD=2.25V to 2.75V • Functionality and operations comply with the DDR4 SDRAM datasheet • 16 internal banks • Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or dif- ferent bank group accesses are available • Data transfer rates: PC4-2666, PC4-2400, PC4-2133, PC4-1866, PC4-1600 • Bi-Directional Differential Data Strobe • 8 bit pre-fetch • Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop) • Supports ECC error correction and detection • On-Die Termination (ODT) • Temperature sensor with integrated SPD • This product is in compliance with the RoHS directive. • Per DRAM Addressability is supported • Internal Vref DQ level generation is available • Write CRC is supported at all speed grades • DBI (Data Bus Inversion) is supported(x8) • CA parity (Command/Address Parity) mode is supported Ordering Information # of Part Number Density Organization Component Composition ranks HMA81GR7AFR8N-TF/UH/VK 8GB 1Gx72 1Gx8(H5AN8G8NAFR)*9 1 HMA82GR7AFR8N-TF/UH/VK 16GB 2Gx72 1Gx8(H5AN8G8NAFR)*18 2 HMA82GR7AFR4N-TF/UH/VK 16GB 2Gx72 2Gx4(H5AN8G4NAFR)*18 1 HMA84GR7AFR4N-TF/UH/VK 32GB 4Gx72 2Gx4(H5AN8G4NAFR)*36 2 Rev. 1.2 / Jun.2016 3 Key Parameters CAS tCK tRCD tRP tRAS tRC MT/s Grade Latency CL-tRCD-tRP (ns) (ns) (ns) (ns) (ns) (tCK) 13.75 13.75 48.75 DDR4-1600 -PB 1.25 11 35 11-11-11 (13.50)* (13.50)* (48.50)* 13.92 13.92 47.92 DDR4-1866 -RD 1.071 13 34 13-13-13 (13.50)* (13.50)* (47.50)* 14.06 14.06 47.06 DDR4-2133 -TF 0.937 15 33 15-15-15 (13.50)* (13.50)* (46.50)* 14.16 14.16 46.16 DDR4-2400 -UH 0.833 17 32 17-17-17 (13.75)* (13.75)* (45.75)* 14.25 14.25 46.25 DDR4-2666 -VK 0.75 19 32 19-19-19 (13.75)* (13.75)* (45.75)* *SK hynix DRAM devices support optional downbinning to CL17, CL15, CL13 and CL11. SPD setting is programm Address Table 8GB(1Rx8) 16GB(2Rx8) 16GB(1Rx4) 32GB(2Rx4) # of Bank Groups 4444 Bank Address BG Address BG0~BG1 BG0~BG1 BG0~BG1 BG0~BG1 Bank Address in a BG BA0~BA1 BA0~BA1 BA0~BA1 BA0~BA1 Row Address A0~A15 A0~A15 A0~A16 A0~A16 Column Address A0~ A9 A0~ A9 A0~ A9 A0~ A9 Page size 1KB 1KB 512MB 512MB Rev. 1.2 / Jun.2016 4 Pin Descriptions Pin Name Description Pin Name Description I2C serial bus clock for SPD-TSE and A0-A171 Register address input SCL register I2C serial data line for SPD-TSE and BA0, BA1 Regisiter bank select input SDA register I2C slave address select for SPD-TSE BG0, BG1 Regisiter bank group select input SA0-SA2 and register RAS_n2 Register row address strobe input PAR Register parity input CAS_n3 Register column address strobe input VDD SDRAM core power supply WE_n4 Register write enable input C0, C1, C2 Chip ID lines for SDRAMx CS0_n, CS1_n, Optional Power Supply on socket but DIMM Rank Select Lines input 12V CS2_n, CS3_n not used on RDIMM SDRAM command/address reference CKE0, CEK1 Register clock enable lines input VREFCA supply Register on-die termination control ODT0, ODT1 VSS Power supply return (ground) lines input ACT_n Register input for activate input VDDSPD Serial SPD/TS positive power supply DQ0-DQ63 DIMM memory data bus ALERT_n Register ALERT_n output CB0-CB7 DIMM ECC check bits VPP SDRAM Supply TDQS9_t-TDQS17_t Dummy loads for mixed populations of TDQS9_c-TDQS17_c x4 based and x8 based RDIMMs. Data Buffer data strobes DQS0_t-DQS17_t DM0_n-DM8_n Data Mask (positive line of differential pair) Data Buffer data strobes Set Register and SDRAMs to a Known DQS0_c-DQS17_c RESET_n (negative line of differential pair) State SPD signals a thermal event has DBI0_n-DBI8_n Data Bus Inversion EVENT_n occurred Register clock input (positive line of dif- CK0_t, CK1_t VTT SDRAM I/O termination supply ferential pair) Register clocks input (negative line of CK0_c, CK1_c RFU Reserved for future use differential pair) 1. Address A17 is only valid for 16Gbx4 based SDRAMs. 2. RAS_n is a multiplexed function with A16. 3. CAS_n is a multiplexed function with A15. 4. WE_n is a multiplexed function with A14. Rev. 1.2 / Jun.2016 5 Input/Output Functional Descriptions Symbol Type Function CK0_t, CK0_c, Clock: CK_t and CK_c are differential clock inputs. All address and control input signals Input CK1_t, CK1_c are sampled on the crossing of the positive edge of CK_t and negative edge of CK_c. Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals and device input buffers and output drivers. Taking CKE LOW provides Precharge Power- Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for Self-Refresh exit. After VREFCA and Internal DQ Vref CKE0, CKE1 Input have become stable during the power on and initialization sequence, they must be maintained during all operations (including Self-Refresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK_t, CK_c, ODT and CKE, are disabled during power-down. Input buffers, excluding CKE, are disabled during Self- Refresh. CS0_n, CS1_n, Chip Select: All commands are masked when CS_n is registered HIGH. CS_n provides for Input CS2_n, CS3_n external Rank selection. CS_n is considered part of the command code. Chip ID: Chip ID is only used for 3DS for 2,4,8 high stack via TSV to select each slice of C0, C1, C2 Input stacked component. Chip ID is considered part of the command code. On-Die Termination: ODT (registered HIGH) enables RTT_NOM termination resistance internal to the DDR4 SDRAM. When enabled, ODT is only applied to each DQ, DQS_t, ODT0, ODT1 Input DQS_c, TDQS_t, and TDQS_c signal. The ODT pin will be ignored if MR1 is programmed to disable RTT_NOM. Activation Command Input: ACT_n defines the Activation command being entered along ACT_n Input with CS_n. The input into RAS_n/A16, CAS_n/A15, and WE_n/A14 will be considered as Row Address A16, A15, and A14. Command Inputs: RAS_n/A16, CAS_n/A15, and WE_n/A14 (along with CS_n) define the RAS_n/A16, command being entered. Those pins are multi-function. For example, for activation with CAS_n/A15, Input ACT_n Low, these are Addresses like A16, A15, and A14, but for non-activation WE_n/A14 command with ACT_n High, these are Command pins for Read, Write, and other commands defined in command truth table. Bank Group Inputs: BG0 - BG1 define to which bank group an Active, Read, Write, or BG0 - BG1 Input Precharge command is being applied. BG0 also determines which mode register is to be accessed during a MRS cycle. Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write, or BA0 - BA1 Input Precharge command is being applied. Bank address also determines which mode register is to be accessed during a MRS cycle. Address Inputs: Provide the row address for ACTIVATE Commands and the column address for Read/Write commands to select one location out of the memory array in the A0 - A17 Input respective bank. A10/AP, A12/BC_n, RAS_n/A16, CAS_n/A15 and WE_n/A14 have additional functions. See other rows. The address inputs also provide the op-code during Mode Register Set commands. A17 is only defined for 16Gb x4 SDRAM configurations. Rev. 1.2 / Jun.2016 6 Symbol Type Function Auto-precharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be performed to the accessed bank after the Read/Write operation. (HIGH: Autoprecharge; LOW: no Autoprecharge). A10 is sampled during a A10 / AP Input Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank addresses. Burst Chop: A12 / BC_n is sampled during Read and Write commands to determine if A12 / BC_n Input burst chop (on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped). See command truth table for details. CMOS Active Low Asynchronous Reset: Reset is active when RESET_n is LOW, and inactive RESET_n Input when RESET_n is HIGH. RESET_n must be HIGH during normal operation. Data Input/ Output: Bi-directional data bus. If CRC is enabled via Mode register, then Input / CRC code is added at the end of Data Burst. Any DQ from DQ0-DQ3 may indicate the DQ Output internal Vref level during test via Mode Register Setting MR4 A4=High. Refer to vendor specific data sheets to determine which DQ is used.
Load more

Recommended publications
  • 2GB DDR3 SDRAM 72Bit SO-DIMM
    Apacer Memory Product Specification 2GB DDR3 SDRAM 72bit SO-DIMM Speed Max CAS Component Number of Part Number Bandwidth Density Organization Grade Frequency Latency Composition Rank 0C 78.A2GCB.AF10C 8.5GB/sec 1066Mbps 533MHz CL7 2GB 256Mx72 256Mx8 * 9 1 Specifications z Support ECC error detection and correction z On DIMM Thermal Sensor: YES z Density:2GB z Organization – 256 word x 72 bits, 1rank z Mounting 9 pieces of 2G bits DDR3 SDRAM sealed FBGA z Package: 204-pin socket type small outline dual in line memory module (SO-DIMM) --- PCB height: 30.0mm --- Lead pitch: 0.6mm (pin) --- Lead-free (RoHS compliant) z Power supply: VDD = 1.5V + 0.075V z Eight internal banks for concurrent operation ( components) z Interface: SSTL_15 z Burst lengths (BL): 8 and 4 with Burst Chop (BC) z /CAS Latency (CL): 6,7,8,9 z /CAS Write latency (CWL): 5,6,7 z Precharge: Auto precharge option for each burst access z Refresh: Auto-refresh, self-refresh z Refresh cycles --- Average refresh period 7.8㎲ at 0℃ < TC < +85℃ 3.9㎲ at +85℃ < TC < +95℃ z Operating case temperature range --- TC = 0℃ to +95℃ z Serial presence detect (SPD) z VDDSPD = 3.0V to 3.6V Apacer Memory Product Specification Features z Double-data-rate architecture; two data transfers per clock cycle. z The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture. z Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver. z DQS is edge-aligned with data for READs; center aligned with data for WRITEs.
    [Show full text]
  • Different Types of RAM RAM RAM Stands for Random Access Memory. It Is Place Where Computer Stores Its Operating System. Applicat
    Different types of RAM RAM RAM stands for Random Access Memory. It is place where computer stores its Operating System. Application Program and current data. when you refer to computer memory they mostly it mean RAM. The two main forms of modern RAM are Static RAM (SRAM) and Dynamic RAM (DRAM). DRAM memories (Dynamic Random Access Module), which are inexpensive . They are used essentially for the computer's main memory SRAM memories(Static Random Access Module), which are fast and costly. SRAM memories are used in particular for the processer's cache memory. Early memories existed in the form of chips called DIP (Dual Inline Package). Nowaday's memories generally exist in the form of modules, which are cards that can be plugged into connectors for this purpose. They are generally three types of RAM module they are 1. DIP 2. SIMM 3. DIMM 4. SDRAM 1. DIP(Dual In Line Package) Older computer systems used DIP memory directely, either soldering it to the motherboard or placing it in sockets that had been soldered to the motherboard. Most memory chips are packaged into small plastic or ceramic packages called dual inline packages or DIPs . A DIP is a rectangular package with rows of pins running along its two longer edges. These are the small black boxes you see on SIMMs, DIMMs or other larger packaging styles. However , this arrangment caused many problems. Chips inserted into sockets suffered reliability problems as the chips would (over time) tend to work their way out of the sockets. 2. SIMM A SIMM, or single in-line memory module, is a type of memory module containing random access memory used in computers from the early 1980s to the late 1990s .
    [Show full text]
  • Product Guide SAMSUNG ELECTRONICS RESERVES the RIGHT to CHANGE PRODUCTS, INFORMATION and SPECIFICATIONS WITHOUT NOTICE
    May. 2018 DDR4 SDRAM Memory Product Guide SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. © 2018 Samsung Electronics Co., Ltd. All rights reserved. - 1 - May. 2018 Product Guide DDR4 SDRAM Memory 1. DDR4 SDRAM MEMORY ORDERING INFORMATION 1 2 3 4 5 6 7 8 9 10 11 K 4 A X X X X X X X - X X X X SAMSUNG Memory Speed DRAM Temp & Power DRAM Type Package Type Density Revision Bit Organization Interface (VDD, VDDQ) # of Internal Banks 1. SAMSUNG Memory : K 8. Revision M: 1st Gen. A: 2nd Gen. 2. DRAM : 4 B: 3rd Gen. C: 4th Gen. D: 5th Gen.
    [Show full text]
  • You Need to Know About Ddr4
    Overcoming DDR Challenges in High-Performance Designs Mazyar Razzaz, Applications Engineering Jeff Steinheider, Product Marketing September 2018 | AMF-NET-T3267 Company Public – NXP, the NXP logo, and NXP secure connections for a smarter world are trademarks of NXP B.V. All other product or service names are the property of their respective owners. © 2018 NXP B.V. Agenda • Basic DDR SDRAM Structure • DDR3 vs. DDR4 SDRAM Differences • DDR Bring up Issues • Configurations and Validation via QCVS Tool COMPANY PUBLIC 1 BASIC DDR SDRAM STRUCTURE COMPANY PUBLIC 2 Single Transistor Memory Cell Access Transistor Column (bit) line Row (word) line G S D “1” => Vcc “0” => Gnd “precharged” to Vcc/2 Cbit Ccol Storage Parasitic Line Capacitor Vcc/2 Capacitance COMPANY PUBLIC 3 Memory Arrays B0 B1 B2 B3 B4 B5 B6 B7 ROW ADDRESS DECODER ADDRESS ROW W0 W1 W2 SENSE AMPS & WRITE DRIVERS COLUMN ADDRESS DECODER COMPANY PUBLIC 4 Internal Memory Banks • Multiple arrays organized into banks • Multiple banks per memory device − DDR3 – 8 banks, and 3 bank address (BA) bits − DDR4 – 16 banks with 4 banks in each of 4 sub bank groups − Can have one active row in each bank at any given time • Concurrency − Can be opening or closing a row in one bank while accessing another bank Bank 0 Bank 1 Bank 2 Bank 3 Row 0 Row 1 Row 2 Row 3 Row … Row Buffers COMPANY PUBLIC 5 Memory Access • A requested row is ACTIVATED and made accessible through the bank’s row buffers • READ and/or WRITE are issued to the active row in the row buffers • The row is PRECHARGED and is no longer
    [Show full text]
  • Improving DRAM Performance by Parallelizing Refreshes
    Improving DRAM Performance by Parallelizing Refreshes with Accesses Kevin Kai-Wei Chang Donghyuk Lee Zeshan Chishti† [email protected] [email protected] [email protected] Alaa R. Alameldeen† Chris Wilkerson† Yoongu Kim Onur Mutlu [email protected] [email protected] [email protected] [email protected] Carnegie Mellon University †Intel Labs Abstract Each DRAM cell must be refreshed periodically every re- fresh interval as specified by the DRAM standards [11, 14]. Modern DRAM cells are periodically refreshed to prevent The exact refresh interval time depends on the DRAM type data loss due to leakage. Commodity DDR (double data rate) (e.g., DDR or LPDDR) and the operating temperature. While DRAM refreshes cells at the rank level. This degrades perfor- DRAM is being refreshed, it becomes unavailable to serve mance significantly because it prevents an entire DRAM rank memory requests. As a result, refresh latency significantly de- from serving memory requests while being refreshed. DRAM de- grades system performance [24, 31, 33, 41] by delaying in- signed for mobile platforms, LPDDR (low power DDR) DRAM, flight memory requests. This problem will become more preva- supports an enhanced mode, called per-bank refresh, that re- lent as DRAM density increases, leading to more DRAM rows freshes cells at the bank level. This enables a bank to be ac- to be refreshed within the same refresh interval. DRAM chip cessed while another in the same rank is being refreshed, alle- density is expected to increase from 8Gb to 32Gb by 2020 as viating part of the negative performance impact of refreshes.
    [Show full text]
  • Dual-DIMM DDR2 and DDR3 SDRAM Board Design Guidelines, External
    5. Dual-DIMM DDR2 and DDR3 SDRAM Board Design Guidelines June 2012 EMI_DG_005-4.1 EMI_DG_005-4.1 This chapter describes guidelines for implementing dual unbuffered DIMM (UDIMM) DDR2 and DDR3 SDRAM interfaces. This chapter discusses the impact on signal integrity of the data signal with the following conditions in a dual-DIMM configuration: ■ Populating just one slot versus populating both slots ■ Populating slot 1 versus slot 2 when only one DIMM is used ■ On-die termination (ODT) setting of 75 Ω versus an ODT setting of 150 Ω f For detailed information about a single-DIMM DDR2 SDRAM interface, refer to the DDR2 and DDR3 SDRAM Board Design Guidelines chapter. DDR2 SDRAM This section describes guidelines for implementing a dual slot unbuffered DDR2 SDRAM interface, operating at up to 400-MHz and 800-Mbps data rates. Figure 5–1 shows a typical DQS, DQ, and DM signal topology for a dual-DIMM interface configuration using the ODT feature of the DDR2 SDRAM components. Figure 5–1. Dual-DIMM DDR2 SDRAM Interface Configuration (1) VTT Ω RT = 54 DDR2 SDRAM DIMMs (Receiver) Board Trace FPGA Slot 1 Slot 2 (Driver) Board Trace Board Trace Note to Figure 5–1: (1) The parallel termination resistor RT = 54 Ω to VTT at the FPGA end of the line is optional for devices that support dynamic on-chip termination (OCT). © 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries.
    [Show full text]
  • Datasheet DDR4 SDRAM Revision History
    Rev. 1.4, Apr. 2018 M378A5244CB0 M378A1K43CB2 M378A2K43CB1 288pin Unbuffered DIMM based on 8Gb C-die 78FBGA with Lead-Free & Halogen-Free (RoHS compliant) datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. © 2018 Samsung Electronics Co., Ltd.GG All rights reserved. - 1 - Rev. 1.4 Unbuffered DIMM datasheet DDR4 SDRAM Revision History Revision No. History Draft Date Remark Editor 1.0 - First SPEC. Release 27th Jun. 2016 - J.Y.Lee 1.1 - Deletion of Function Block Diagram [M378A1K43CB2] on page 11 29th Jun. 2016 - J.Y.Lee - Change of Physical Dimensions [M378A1K43CB1] on page 41 1.11 - Correction of Typo 7th Mar. 2017 - J.Y.Lee 1.2 - Change of Physical Dimensions [M378A1K43CB1] on page 41 23h Mar.
    [Show full text]
  • DDR3 SODIMM Product Datasheet
    DDR3 SODIMM Product Datasheet 廣 穎 電 通 股 份 有 限 公 司 Silicon Power Computer & Communications Inc. TEL: 886-2 8797-8833 FAX: 886-2 8751-6595 台北市114內湖區洲子街106號7樓 7F, No.106, ZHO-Z ST. NEIHU DIST, 114, TAIPEI, TAIWAN, R.O.C This document is a general product description and is subject to change without notice DDR3 SODIMM Product Datasheet Index Index...................................................................................................................................................................... 2 Revision History ................................................................................................................................................ 3 Description .......................................................................................................................................................... 4 Features ............................................................................................................................................................... 5 Pin Assignments................................................................................................................................................ 7 Pin Description................................................................................................................................................... 8 Environmental Requirements......................................................................................................................... 9 Absolute Maximum DC Ratings....................................................................................................................
    [Show full text]
  • DDR4 8Gb C Die Unbuffered SODIMM Rev1.5 Apr.18.Book
    Rev. 1.5, Apr. 2018 M471A5244CB0 M471A1K43CB1 M471A2K43CB1 260pin Unbuffered SODIMM based on 8Gb C-die 78FBGA with Lead-Free & Halogen-Free (RoHS compliant) datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. © 2018 Samsung Electronics Co., Ltd. All rights reserved. - 1 - Rev. 1.5 Unbuffered SODIMM datasheet DDR4 SDRAM Revision History Revision No. History Draft Date Remark Editor 1.0 - First SPEC. Release 27th Jun. 2016 - J.Y.Lee 1.1 - Change of Function Block Diagram [M471A1K43CB1] on page 10~11 29th Jun. 2016 - J.Y.Lee - Change of Physical Dimensions on page 42~43 1.2 - Change of Physical Dimensions on page 42~43 24th Feb.
    [Show full text]
  • Performance Evaluation and Feasibility Study of Near-Data Processing on DRAM Modules (DIMM-NDP) for Scientific Applications Matthias Gries, Pau Cabré, Julio Gago
    Performance Evaluation and Feasibility Study of Near-data Processing on DRAM Modules (DIMM-NDP) for Scientific Applications Matthias Gries, Pau Cabré, Julio Gago To cite this version: Matthias Gries, Pau Cabré, Julio Gago. Performance Evaluation and Feasibility Study of Near-data Processing on DRAM Modules (DIMM-NDP) for Scientific Applications. [Technical Report] Huawei Technologies Duesseldorf GmbH, Munich Research Center (MRC). 2019. hal-02100477 HAL Id: hal-02100477 https://hal.archives-ouvertes.fr/hal-02100477 Submitted on 15 Apr 2019 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. TECHNICAL REPORT MRC-2019-04-15-R1, HUAWEI TECHNOLOGIES, MUNICH RESEARCH CENTER, GERMANY, APRIL 2019 1 Performance Evaluation and Feasibility Study of Near-data Processing on DRAM Modules (DIMM-NDP) for Scientific Applications Matthias Gries , Pau Cabre,´ Julio Gago Abstract—As the performance of DRAM devices falls more and more behind computing capabilities, the limitations of the memory and power walls are imminent. We propose a practical Near-Data Processing (NDP) architecture DIMM-NDP for mitigating the effects of the memory wall in the nearer-term targeting server applications for scientific computing. DIMM-NDP exploits existing but unused DRAM bandwidth on memory modules (DIMMs) and takes advantage of a subset of the forthcoming JEDEC NVDIMM-P protocol in order to integrate application-specific, programmable functionality near memory.
    [Show full text]
  • DDR4 2400 R-DIMM / VLP R-DIMM / ECC U-DIMM / ECC SO-DIMM Features
    DDR4 2400 R-DIMM / VLP R-DIMM / ECC U-DIMM / ECC SO-DIMM Available in densities ranging from 4GB to 16GB per module and clocked up to 2400MHz for a maximum 17GB/s bandwidth, ADATA DDR4 server memory modules are all certified Intel® Haswell-EP compatible to ensure superior performance. Products ship in four convenient form factors to accommodate diverse needs and applications: R-DIMM and ECC U-DIMM for servers and enterprises, VLP R-DIMM for high-end blade servers, and ECC SO-SIMM for micro servers. Running at a mere 1.2V, ADATA DDR4 memory modules use 20% less energy than conventional lower-performance DDR3 modules, in effect delivering more computational power for less energy draw. ADATA DDR4 server memory modules are an excellent choice for users looking to balance performance, environmental responsibility, and cost effectiveness. Features ECC U-DIMM High speed up to 2400MHz Transfer bandwidths up to 17GB/s Energy efficient: save up to 20% compared to DDR3 8-layer PCB provides improved signal transfer R-DIMM and system stability PCB gold plating: 30u and up Intel Haswell-EP compatible for extreme performance VLP R-DIMM ECC SO-DIMM Specifications Type ECC-DIMM R-DIMM VLP R-DIMM ECC SO-DIMM Standard Standard Very low profile Standard Form factor (1.18" height) (1.18" height) (0.7" height) (1.18" height) Enterprise servers / Enterprise servers / Suitable for Blade servers Micro servers data centers data centers Interface 288-pin 288-pin 288-pin 260-pin Capacity 4GB / 8GB / 16GB 4GB / 8GB / 16GB 4GB / 8GB /16GB 4GB / 8GB / 16GB Rank
    [Show full text]
  • Datasheet DDR4 SDRAM Revision History
    Rev. 1.1, Apr. 2018 M391A1K43BB1 M391A1K43BB2 M391A2K43BB1 288pin ECC Unbuffered DIMM based on 8Gb B-die 78FBGA with Lead-Free & Halogen-Free (RoHS compliant) datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. © 2018 Samsung Electronics Co., Ltd.GG All rights reserved. - 1 - Rev. 1.1 ECC Unbuffered DIMM datasheet DDR4 SDRAM Revision History Revision No. History Draft Date Remark Editor 0.5 - First SPEC release 15th Nov, 2017 Preliminary J.Y.Bae - Separate ECC and Non ECC datasheets. J.H.Han 1.0 - Final datasheet. 13th Dec, 2017 Final J.Y.Bae - Correct typo. J.H.Han - Correct speed bin table numbering. - Add DRAM Package Electrical Specifications (x4/x8) table.
    [Show full text]