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Ddr4 Sdram Memory DDR4 SDRAM MEMORY 3D4D32G72LB2758 Datasheet 2. KEY FEATURES Including decoupling and termination Industrial up to Military temperature range Organization: 512M x 64 bits + 8b ECC Max Clock rate available: 1200MHz Max Transfer Rate 2400MT/s VDD/VDDQ = 1.2V (1.14V to 1.26V) 1. PRODUCT OVERVIEW VPP = 2.5V (2.375V to 2.75V) Command/Address latency The 3D4D32G72LB2758 is a 32Gbits high speed Burst length (BL): 8 (BL8) and Burst Chop 4 DDR4 SDRAM, organized as 512M x 64 bits and (BC4) modes 8 bits additional for ECC. Bi-directional Differential Data Strobe (DQS) This synchronous device operates at a maximum DLL aligns DQ and DQS transitions with CK transfer rate of up to 2400 MT/s (DDR4-2400), for an aggregate data rate of 153.6Gbps. The module Commands entered on each positive CK is designed to comply with the key DDR4 SDRAM transition features including: (1) posted CAS by Data and data mask are referenced to both programmable additive latency, (2) On Die edges of a differential data strobe pair Termination, (3) programmable driver strength (Double data rate) data, (4) clock rate of 1200MHz. Programmable on-die termination (ODT) All the control and address inputs are Refresh: Self-refresh, Auto refresh and synchronized with a pair of externally supplied Partial array Self-refresh differential clocks. Inputs are latched at the cross ZQ calibration for DQ drive and ODT point of differential clocks (CK_t rising and CK_c falling). All I/Os are synchronized with a pair of Asynchronous RESET pin for Power-up initialization and reset function bidirectional differential data strobes (DQS_t and DQS_c) in a source synchronous fashion. The Package: 267 balls leaded FBGA address bus is used to convey row, column and bank address information in a RAS_n and CAS_n 3. FUNCTIONAL BLOCK DIAGRAM DQS0_t, DQS0_c, DM0_n, DBI0_n multiplexing style. The data bus inversion (DBI) DQS1_t, DQS1_c, DM1_n, DBI1_n DQS2_t, DQS2_c, DM2_n, DBI2_n reduces the power consumption and ground DQS3_t, DQS3_c, DM3_n, DBI3_n DQS4_t, DQS4_c, DM4_n, DBI4_n bounce. DQS5_t, DQS5_c, DM5_n, DBI5_n DQS6_t, DQS6_c, DM6_n, DBI6_n The 32Gbits DDR4 devices operate with two DQS7_t, DQS7_c, DM7_n, DBI7_n DQS8_t, DQS8_c, DM8_n, DBI8_n power supplies: 1.2V for VDD and VDDQ, and 2.5V 1 for VPP wordline supply. This device is ideal for 2 high-density memory applications that require 3 4 high-speed transfer A[16:0], BA[1:0], DQ[15:0] 5 BG0, CKE, RAS_n, CAS_n, WE_n, CK_t, DQ[31:16] CK_c, ACT_n, CS_n DQ[47:32] DQ[63:48] CB[7:0] . 3DDS-0758-2 04 2021 Page 1 / 51 This document is the property of 3D PLUS, it may not be used by or communicated to third parties without prior written authorization DDR4 SDRAM MEMORY 3D4D32G72LB2758 TABLE OF CONTENT 1. PRODUCT OVERVIEW ..................................................................................................................... 1 2. KEY FEATURES ................................................................................................................................ 1 3. FUNCTIONAL BLOCK DIAGRAM .................................................................................................... 1 4. FUNCTIONAL DESCRIPTION........................................................................................................... 6 3.1 INDUSTRIAL AND MILITARY TEMPERATURE RANGE .......................................................... 6 3.2 SIMPLIFIED STATE DIAGRAM ................................................................................................. 7 3.3 FUNCTIONAL BLOCK DIAGRAM .............................................................................................. 8 4. BALL ASSIGNMENTS ....................................................................................................................... 9 5. BALL DESCRIPTION ........................................................................................................................ 10 6. ABSOLUTE MAXIMUM RATINGS .................................................................................................... 11 7. PIN CAPACITANCE .......................................................................................................................... 12 8. CURRENT SPECIFICATIONS ........................................................................................................... 13 9. RECOMMENDED DC OPERATING CONDITIONS .......................................................................... 14 10. INPUT OPERATING CONDITIONS ................................................................................................... 14 11. OUTPUT CHARACTERISTICS AND OPERATING CONDITIONS .................................................. 15 12. OVERSHOOT AND UNDERSHOOT SPECIFICATIONS .................................................................. 15 12.1 ADDRESS, COMMAND, CONTROL OVERSHOOT/UNDERSHOOT SPECIFICATIONS........ 15 12.2 CLOCK OVERSHOOT/UNDERSHOOT SPECIFICATIONS ..................................................... 16 12.3 DATA, STROBE AND MASK OVERSHOOT/UNDERSHOOT SPECIFICATIONS ................... 16 13. EXTENDED TEMPERATURE MODE ................................................................................................ 17 14. STANDARD SPEED BINS................................................................................................................. 18 15. TIMING PARAMETERS ..................................................................................................................... 19 16. POWER-UP AND RESET INITIALIZATION ...................................................................................... 26 17. RESET INITIALIZATION WITH STABLE POWER SEQUENCE ...................................................... 29 18. UNCONTROLLED POWER-DOWN SEQUENCE ............................................................................. 29 19. MODE REGISTER DEFINITION ........................................................................................................ 30 19.1 MODE REGISTER MR0 ............................................................................................................. 30 19.2 MODE REGISTER MR1 ............................................................................................................. 31 19.3 MODE REGISTER MR2 ............................................................................................................. 33 19.4 MODE REGISTER MR3 ............................................................................................................. 34 19.4.1 Multi purpose Register (MPR) ............................................................................................. 36 19.5 MODE REGISTER MR4 ............................................................................................................. 36 19.6 MODE REGISTER MR5 ............................................................................................................. 37 19.6.1 Data Bus Inversion ............................................................................................................. 39 19.6.1 Data Mask ........................................................................................................................... 39 19.7 MODE REGISTER MR6 ............................................................................................................. 39 20. TRUTH TABLES ................................................................................................................................ 40 20.1 COMMAND TRUTH TABLE ....................................................................................................... 40 20.2 CKE TRUTH TABLE ................................................................................................................... 42 21. DLL-OFF MODE ................................................................................................................................ 43 22. DLL-ON/OFF SWITCHING PROCEDURES ...................................................................................... 44 22.1 DLL-ON TO DLL-OFF PROCEDURE ........................................................................................ 44 22.2 DLL-OFF TO DLL-ON PROCEDURE ........................................................................................ 45 Page 2 / 51 3DDS-0758-2 04 2021 This document is the property of 3D PLUS, it may not be used by or communicated to third parties without prior written authorization DDR4 SDRAM MEMORY 3D4D32G72LB2758 23. DATA BUS INVERSION (DBI)........................................................................................................... 47 23.1 DBI DURING A WRITE OPERATION ........................................................................................ 47 23.2 DBI DURING A READ OPERATION .......................................................................................... 47 24. DATA MASK ...................................................................................................................................... 48 25. FOOTPRINT ....................................................................................................................................... 49 26. MECHANICAL DRAWING ................................................................................................................. 49 27. ORDERING INFORMATION .............................................................................................................. 50 28. MODULE MARKING .........................................................................................................................
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