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You Need to Know About Ddr4 Overcoming DDR Challenges in High-Performance Designs Mazyar Razzaz, Applications Engineering Jeff Steinheider, Product Marketing September 2018 | AMF-NET-T3267 Company Public – NXP, the NXP logo, and NXP secure connections for a smarter world are trademarks of NXP B.V. All other product or service names are the property of their respective owners. © 2018 NXP B.V. Agenda • Basic DDR SDRAM Structure • DDR3 vs. DDR4 SDRAM Differences • DDR Bring up Issues • Configurations and Validation via QCVS Tool COMPANY PUBLIC 1 BASIC DDR SDRAM STRUCTURE COMPANY PUBLIC 2 Single Transistor Memory Cell Access Transistor Column (bit) line Row (word) line G S D “1” => Vcc “0” => Gnd “precharged” to Vcc/2 Cbit Ccol Storage Parasitic Line Capacitor Vcc/2 Capacitance COMPANY PUBLIC 3 Memory Arrays B0 B1 B2 B3 B4 B5 B6 B7 ROW ADDRESS DECODER ADDRESS ROW W0 W1 W2 SENSE AMPS & WRITE DRIVERS COLUMN ADDRESS DECODER COMPANY PUBLIC 4 Internal Memory Banks • Multiple arrays organized into banks • Multiple banks per memory device − DDR3 – 8 banks, and 3 bank address (BA) bits − DDR4 – 16 banks with 4 banks in each of 4 sub bank groups − Can have one active row in each bank at any given time • Concurrency − Can be opening or closing a row in one bank while accessing another bank Bank 0 Bank 1 Bank 2 Bank 3 Row 0 Row 1 Row 2 Row 3 Row … Row Buffers COMPANY PUBLIC 5 Memory Access • A requested row is ACTIVATED and made accessible through the bank’s row buffers • READ and/or WRITE are issued to the active row in the row buffers • The row is PRECHARGED and is no longer accessible through the bank’s row buffers Example: DDR4-2133 Open Page = 2.133Gb/s maximum bandwidth Closed Page = 199Mb/s maximum bandwidth 10x performance advantage to read and write from an open page COMPANY PUBLIC 6 Example – 8Gb DDR4 SDRAM • Micron MT40A1G8 • 1024M x 8 (64M x 8 x 16 banks) • 8 Gb total • 16-bit row address − 64K rows • 10-bit column address − 1K bits/row (1KB in x8 data with DRAM) • 2-bit group and 2-bit bank address ADD bus DATA bus • DATA bus: DQ, DQS, /DQS, DM (DBI) • ADD bus: A, BA, GB, ACT, /CS, /RAS, /CAS, /WE, ODT, CKE, CK, /CK, PAR, /ALERT COMPANY PUBLIC 7 Example – DDR4 UDIMM /CSn ODTn 32M x 8 A[12:0] DQ[7:0] • Micron MTA9ASF51272AZ BA[1:0] DQS MDQ[0:7], MDQS0, MDM0 /DQS /RAS MDQ[8:15], MDQS1, MDM1 DM /CAS MDQ[16:23], MDQS2, MDM2 • 9 each 512M x 8 DRAM devices /WE MDQ[24:31 MDQS3, MDM3 CKE CK MDQ[32:39], MDQS4, MDM4 • 512M x 72 overall /CK MDQ[40:47], MDQS5, MDM5 MDQ[48:55], MDQS6, MDM6 ODT /CS • 4 GB total, single “rank” MDQ[56:31], MDQS7, MDM7 • 9 “byte lanes” Two Signal Bus 32M x 8 • 1- Address, command, control, and A[12:0] DQ[7:0] BA[1:0] DQS ECC[0:7], MDQS8, MDM8 /DQS /RAS clock signals are shared among all 9 DM /CAS DRAM devices /WE CKE CK • 2- Data, strobe, data mask not shared /CK ODT /CS COMPANY PUBLIC 8 DRAM Module Type COMPANY PUBLIC 9 DDR3 VS. DDR4 SDRAM DIFFERENCES COMPANY PUBLIC 10 DDR SDRAM Highlights and Comparison Feature/Category DDR3 DDR4 Package BGA only BGA only Densities 512Mb -8Gb 2Gb -16Gb Voltage DDR3L:1.35V Core & I/O 1.2V Core DDR3: 1.5V Core & I/O 1.2V I/O, also 2.5V external VPP Data I/O Center Tab Termination (CTT) Pseudo Open Drain (POD) CMD, ADDR I/O CTT CTT Internal Memory Banks 8 16 for x4/x8, 8 for x16 Data Rate 800 DDR3/3L:2133/1866 Mbps 1600–3200 Mbps VREF VREFCA & VREFDQ external VREFCA external VREFDQ internal Data Strobes/Prefetch/Burst Differential/8-bits/BC4, BL8/ Fixed, Same as DDR3 Length/Burst Type OTF Additive/read/write Latency 0, CL-1, CL-2/ AL+CL/ AL +CWL Same as DDR3 COMPANY PUBLIC 11 DDR SDRAM Highlights and Comparison (cont’d) Feature/Category DDR3 DDR4 Yes (Parity is supported. But CRC CRC Data Bus & C/A Parity No NOT supported in QorIQ) Connectivity test (TEN pin) No Yes (TEN is not supported in QorIQ) Bank Grouping No Yes Data Bus Inversion No Yes (DBI_n pin) Write Leveling / ZQ / Reset Yes Yes ACT_n new pin & command No Yes Mirroring & DQ swizzle Yes Yes VREFDQ calibration No Yes CMD / ADDR Latency (CAL) No Yes COMPANY PUBLIC 12 DDR3/DDR3L/DDR4 Power Saving • DDR3 DRAM provides 20% power savings over DDR2 • DDR3L DRAM provides 10% power savings over DDR3 • DDR4 DRAM provides 37% power savings over DDR3L COMPANY PUBLIC 13 DDR3 vs. DDR4 DRAM Pinouts • DDR4 Pins Added − VDDQ (2) : 1.2V pins to DRAM − VPP (2): 2.5V external voltage source for DRAM internal word line driver − BG (2): Bank Group (2): pins to identify the bank groups − DBI_n: Data Bus Inversion − ACT_n: Active command − PAR: Parity error signal for address bus − ALERT_n: Both, Parity error on C\A and CRC error on data bus − TEN: Connectivity test mode • DDR3 Pins Eliminated − VREFDQ − Bank Address (1): one less BA pin − VDD (1), VSS (3), VSSQ (1) COMPANY PUBLIC 14 DRAM Densities DDR3 vs. DDR4 • 16 Banks for x4 and x8 DRAM DDR4, 8 Banks for x16 • 8Gb is DRAMs vendors choice for starting DDR4 density • Larger memory size is one reason to use x4 vs. x8 vs. x16 DRAM • Data mask or data bus inversion (DBI), not available in x4 DRAM Density 1Gb 2Gb 4Gb 8Gb 16 Gb Width x4 x8 x16 x4 x8 x16 x4 x8 x16 x4 x8 x16 x4 x8 x16 Banks 8 8 8 8 8 8 8 8 8 8 8 8 Rows 14 14 13 15 15 14 16 16 15 16 16 16 Columns 11 10 10 11 10 10 11 10 10 12 11 11 DDR3 Page Size (KB) 1 1 2 1 1 2 1 1 2 2 2 2 Banks 16 16 8 16 16 8 16 16 8 16 16 8 Rows 15 14 14 16 15 15 17 16 16 18 17 17 Columns 10 10 10 10 10 10 10 10 10 10 10 10 DDR4 Page Size (KB) 0.5 1 2 0.5 1 2 0.5 1 2 0.5 1 2 COMPANY PUBLIC 15 Modules DDR3 vs. DDR4 Module Feature DDR3 DDR4 U/RDIMM Pin Count 240 (1.0mm pin pitch) 288 (0.85mm pin pitch) Bottom Edge Flat Step Ramp (+ ~1mm on height and width) DRAM ball count and ball pitch Same ball count and ball pitch DIMM topology Fly-by for address/command bus SoDIMM Pin Count 204 260 SoDIMM ECC Support Non-compatible pin out Native (pin compatible for ECC or without ECC) COMPANY PUBLIC 16 Why DDR4 Over DDR3 • Save power − DDR4 can reduce power by up to 40% • Run faster − DDR4 offers double the data rate − DDR4 doubles the number of internal banks, increased bandwidth − New options to increase performance • Better reliability & manufacturing capabilities − Connectivity test − Data bus inversion (DBI) − Internal VREF calibration • Larger densities • Longevity COMPANY PUBLIC 17 DDR BRING UP ISSUES COMPANY PUBLIC 18 List of products and DDR capabilities Product DDR type Data bus width Data rate # of MC T1023/13 DDR3L / 4 32-bit + 4bit ECC 1600 MT/s 1 T1040/42, T1020/22, T1024/14 DDR3L / 4 64-bit + 8bit ECC 1600 MT/s 1 T2080/81 DDR3 / 3L 64-bit + 8bit ECC 2133 MT/s 1 T4240 DDR3 / 3L 64-bit + 8bit ECC 1866 MT/s 3 LS1024 DDR3 32-bit + 8bit ECC 1066 MT/s 1 LS1012 DDR3L 16-bit + 8bit ECC 1000 MT/s 1 LS1021/20/22, LS1043/23, LS1017/18/27/28 DDR3L / 4 32-bit + 4bit ECC 1600 MT/s 1 LS1088/84/48/44, LS1046/26 DDR4 64-bit + 8bit ECC 2100 MT/s 1 LS2088/ all derivatives DDR4 64-bit + 8bit ECC 2133 MT/s 2 LX2160/all derivatives DDR4 64-bit + 8bit ECC 3200 MT/s 2 COMPANY PUBLIC 19 List of DDR Bring up issues: Top HW and SW DDR Issues DDR BRING-UP Incorrect DQn_MAP setting ISSUES Setting WRLVL_START registers were incorrect SW + Reset HW SW QCVS was not used, incorrect setting used Erratum was not implemented Incorrect data rate, not matching the generated setting Bring up, DRAM reset not matched to HRESET Bring up, MDM pin, incorrect connection Bring up, A/C layout causing ECC errors 37% HW Bring up, ACTn signal not connected 63% Bring up, DQS and DQS_B swapped Bring up, incorrect bit swapping in layout Bring up, Manufacturing issue on 2 out of 20 boards. COMPANY PUBLIC 20 Memory controller Initialization failure It is an initialization failure when: 1) ERR_DETECT[ACE] is set or 2) SDRAM_CFG_2[D_INIT] does not clear DDR Initialization Failed 1 2 Example: [0x01080110] E5000000 00401011 [0x01080E40] 00000080 00000000 00000000 00000000 COMPANY PUBLIC 21 DDR Bring up HW checklist: Schematics review: Design checklist document Layout/HW guideline application note AN5097 HW specs Check all voltages: GVDD, VREF, VTT, AND VPP Check input and output DDR clocks Verify DRAM reset signal is matched to HRESET for UDIMM, SoDIMM, and discrete DRAM. AN5097 appendix B. Verify correct DRAM type strap Verify DQ pin swapping is per allowed limitation Have more than one board for bring up Check for manufacturing/fabrication/assembly issues COMPANY PUBLIC 22 DDR Bring up SW checklist Generate the setting via QCVS: Use SPD if available, otherwise Auto generation Select the DDR data rate based on the measured output clock RCW needs to be valid and correct Enter MCK to DQS skews in the DDR wizard Verify the DQn_MAP registers are correct Verify all related errata are implemented COMPANY PUBLIC 23 DDR4 Initialization Flow VPP ramped GVDD & with or DRAMs Mode Register VPP ramped Power-up before GVDD Initialized Commands Issued & stable The initialization takes between DRAM reset Asserted at DRAM ZQ ZQCL Issued (512 clocks) 3ms to 4ms.
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