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MPC107 PCI Bridge/Memory Controller Technical Summary for More Information on This Product, Go To Freescale Semiconductor, Inc. Order Number: MPC107TS/D Rev. 0, 9/1999 Semiconductor Products Sector ™ . c n I , Advance Information r o MPC107 PCI Bridge/Memory Controller t c Technical Summary u d This document provides an overview of the MPC107 PCI bridge/memory controller (PCIB/ n MC) for high-performance embedded systems. The MPC107 is a cost-effective, general- o c purpose PCI bridge/memory controller for applications using PCI in networking i infrastructure, telecommunications, and other embedded markets. It can be used in m applications such as network routers and switches, mass storage subsystems, network e appliances, and print and imaging systems. S e For errata or revisions to this document, refer to the website at http://www.motorola.com/ l a powerpc. c s e 1.1 MPC107 PCI Bridge/Memory Controller Features e r The MPC107 provides an integrated high-bandwidth, high-performance interface between F up to two 60x processors, the PCI bus, and main memory. This section summarizes the features of the MPC107. Major features of the MPC107 are as follows: • Memory interface — 64-/32-bit 100-MHz bus — Programmable timing supporting either FPM DRAM, EDO DRAM or SDRAM — High-bandwidth bus (32-/64-bit data bus) to DRAM This document contains information on a new product under development by Motorola. Motorola reserves the right to change or discontinue this product without notice. © Motorola, Inc., 1999. All rights reserved. For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MPC107 PCI Bridge/Memory Controller Features — Supports one to eight banks of 4-, 16-, 64-, or 128-Mbit memory devices, and up to four banks of 256-Mbit SDRAM devices — Supports 1-Mbyte to 1-Gbyte DRAM memory — 144 Mbytes of ROM space — 8-, 32-, or 64-bit ROM — Write buffering for PCI and processor accesses — Supports normal parity, read-modify-write (RMW), or ECC — Data-path buffering between memory interface and processor — Low-voltage TTL logic (LVTTL) interfaces — Port X: 8-, 32-, or 64-bit general-purpose I/O port using ROM controller . interface with programmable address strobe timing . c • 32-bit PCI interface operating up to 66 MHz n I — PCI 2.1-compliant , r — PCI 5.0-V tolerance o t — Support for PCI locked accesses to memory c u — Support for accesses to PCI memory, I/O, and configuration spaces d — Selectable big- or little-endian operation n o — Store gathering of processor-to-PCI write and PCI-to-memory write accesses c i — Memory prefetching of PCI read accesses m — Selectable hardware-enforced coherency e S — PCI bus arbitration unit (five request/grant pairs) e — PCI agent mode capability l a — Address translation unit c s — Some internal configuration registers accessible from PCI e • Two-channel integrated DMA controller (writes to ROM/Port X not supported) e r — Supports direct mode or chaining mode (automatic linking of DMA transfers) F — Supports scatter gathering—read or write discontinuous memory — Interrupt on completed segment, chain, and error — Local-to-local memory — PCI-to-PCI memory — PCI-to-local memory — PCI memory-to-local memory 2 MPC107 PCI Bridge/Memory Controller Technical Summary For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MPC107 PCI/MC Applications • Message unit — Two doorbell registers — An extended doorbell register mechanism that facilitates interprocessor communication through interrupts in a dual-local-processor system — Two inbound and two outbound messaging registers —I2O message controller •I2C controller with full master/slave support (except broadcast all) • Embedded programmable interrupt controller (EPIC) — Five hardware interrupts (IRQs) or 16 serial interrupts . — Four programmable timers . • Integrated PCI bus, CPU, and SDRAM clock generation c n • Programmable PCI bus, 60x, and memory interface output drivers I , • Dynamic power management—Supports 60x nap, doze, sleep, and suspend modes r o • Programmable input and output signals with watchpoint capability t c • Built-in PCI bus performance monitor facility u d • Debug features n — Error injection/capture on data path o c — IEEE 1149.1 (JTAG)/test interface i m • Processor interface e — Supports up to two PowerPC™ microprocessors with 60x bus interface S — Supports various operating frequencies and bus divider ratios e l — 32-bit address bus, 64/32-bit data bus supported at 100 MHz a c — Supports full memory coherency s e — Supports optional local bus slave e r — Decoupled address and data buses for pipelining of 60x accesses F — Store gathering on 60x-to-PCI writes — Concurrent transactions on 60x and PCI buses supported 1.2 MPC107 PCI/MC Applications The MPC107 can be used in either a system host configuration or as a peripheral device. For system applications where cost, space, and power consumption are critical parameters, yet performance cannot be sacrificed, the MPC107 provides a complete solution. The MPC107 is shown in Figure 1-1 as a host bridge. MPC107 PCI Bridge/Memory Controller Technical Summary 3 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MPC107 PCI/MC Applications PowerPC Microprocessor Local Memory: ROM / DRAM, EDO, MPC107 Port X SDRAM DMA MU(I2O) Peripheral Data I2C Logic EPIC CTRL PCI Bus up to 66 MHz . Peripheral Peripheral Peripheral PCI to PCI c 1 23Bridge n I PCI Bus , r Figure 1-1. System Using MPC107 as a Host Bridge o t c With the embedded enhancements provided in the MPC107, it is possible to use it in u distributed I/O processor applications as shown in Figure 1-2. d n o Host Processor c i m e S Host Bridge Host Memory e l PCI Bus up to 66 MHz a c s System I/O PCI to PCI e Peripheral Peripheral Controller Bridge 13 e r PCI Bus F Periph. 2 MPC107 DMA CTRL MU(I2O) Peripheral I2C Logic Data EPIC ROM / Local Memory: Port X DRAM, EDO, PowerPC Microprocessor SDRAM Figure 1-2. Embedded System Using the MPC107 as a Bridge to a Distributed I/O Processor 4 MPC107 PCI Bridge/Memory Controller Technical Summary For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MPC107 PCI/MC Applications The MPC107 can also be used with a peripheral processing device as shown in Figure 1-3. In this case, the PCI-to-PCI bridge shown Figure 1-3 could be of the PCI type 0 variety. The MPC107 would not be part of the system configuration map. This configuration is useful in applications such as RAID controllers or multi-port network controllers where the I/O devices shown are SCSI controllers or Ethernet controllers, respectively. Host Processor Host Bridge Host Memory PCI Bus . c Peripheral System I/O n Peripheral Peripheral 2 PCI-to-PCI I/O Device I/O Device Controller I 1 3 Bridge , r Local PCI Bus up to 66 MHz o t c MPC107 u CTRL d DMA n MU(I O) 2 Peripheral Data o 2 Logic I C c EPIC i ROM / Local Memory: Port X DRAM, EDO, m SDRAM e S PowerPC Microprocessor e l a Figure 1-3. Embedded System Using MPC107 with a Peripheral Processor c s The processor bus interface (60x) of the MPC107 contains all of the necessary arbitration e e and control logic to communicate with up to two PowerPC microprocessors in a symmetric r multiprocessing environment. In addition, the MPC107 also has a side-band mode to allow F an alternate bus slave to capture address tenures. This application is show in Figure 1-4. MPC107 PCI Bridge/Memory Controller Technical Summary 5 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MPC107 Major Functional Blocks PowerPC PowerPC Microprocessor Microprocessor 60x Bus Local Memory: ROM / DRAM, EDO, MPC107 Local Bus Port X SDRAM DMA Slave MU(I2O) Peripheral Data I2C Logic EPIC . CTRL . c PCI Bus n I , Figure 1-4. Multiprocessor System Using the MPC107 and a Local Bus Slave r o t c 1.3 MPC107 Major Functional Blocks u The MPC107 integrates a PCI bridge, memory controller, DMA controller, EPIC interrupt d n controller/timers, a message unit with an Intelligent Input/Output (I O) message controller, 2 2 o and an Inter-Integrated Circuit (I C) controller. The integration reduces the overall c i packaging requirements and the number of discrete devices required for an embedded system. m e Figure 1-5 shows the major functional units within the MPC107. Note that this is a S conceptual block diagram intended to show the basic features rather than an attempt to e l show how these features are physically implemented. a c s e e r F 6 MPC107 PCI Bridge/Memory Controller Technical Summary For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MPC107 Major Functional Blocks Additional features: MPC107 • Programmable I/O • with Watchpoint 60x Bus Interface (64- or 32-Bit Data Bus) • JTAG/COP Interface • Power Management Peripheral Logic Block Data (64-Bit) Data Bus Address Data Path (64- or 32-bit) Message (32-Bit) ECC Controller with 8-bit Parity Unit or ECC (with I2O) Central Memory Memory/ROM/ Control Controller Port X Control/ Unit DMA Address Controller Configuration . Registers SDRAM_SYNC_IN . 2 c I2C I C Controller SDRAM Clocks n PCI Bus DLL CPU Clocks I Interface Unit , PLL PCI_SYNC_IN EPIC r 5 IRQs/ Interrupt Address PCI o 16 Serial Controller Translator Arbiter Fanout PCI Bus t Interrupts /Timers Buffers Clocks c u d OSC_IN 32-Bit Five n PCI Interface Request/Grant o Pairs c i m Figure 1-5. MPC107 Block Diagram e S 1.3.1 60x Processor Interface e l The MPC107 supports a programmable interface to a variety of PowerPC microprocessors a operating at select bus speeds.
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