The Topology and Voltage Regulation for High-power
Switched-capacitor Converters
DISSERTATION
Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy in the Graduate School of The Ohio State University
By
Ke Zou
Graduate Program in Electrical and Computer Science
The Ohio State University
2012
Dissertation Committee:
Jin Wang, Advisor
Longya Xu
Mahesh S. Illindala
Copyright by
Ke Zou
2012
Abstract
With the rapid advancement of wide band-gap device researches, the switched- capacitor topologies have attracted more and more attentions, due to its inductor-less feature and high-temperature operation capability. This dissertation presents a series of work on high power switched-capacitor converters, including the study on both the topologies and voltage regulation methods for high-power switched-capacitor converters.
A modular cell-based switched-capacitor topology is first presented, which can be configured to realize both dc-dc and dc-ac power conversions. When used in dc-dc applications, this topology has the advantages of reduced input current ripple and minimized output capacitor size compared to traditional switched-capacitor topologies.
When used in dc-ac conversions, a multi-level inverter topology can be realized based on the proposed cell structure. With a variable-frequency control method, the zero-current- switching is achieved over the entire fundamental cycle.
To reduce the power loss, especially the conduction loss on the input capacitors due to the pulsing input current, a voltage tripler that can realize input current and output voltage interleaving is presented. Three identical stages exist in the proposed topology, with a 120 degree phase-shift between each two stages. A two-step charging scheme is utilized to realize the interleaving function. Both the conduction losses and switching losses can be minimized by using this topology.
ii
To efficiently regulate the output voltage of high-power switched-capacitor converters, a voltage regulation method is proposed, in which a RCL equivalent circuit of the capacitor charging loop is adopted. The third-quadrant operation of MOSFETs is utilized to reduce the power loss due to the voltage regulation.
A switched-capacitor dynamic voltage restorer topology is examined as an example of high-power switched-capacitor converter applications. The switched-capacitor based isolation cell, consisting of two capacitors and four switches, is used to isolate the source from the load. The zero-current-switching for the switches related with the capacitor charging is realized, which helps to reduce the EMI noises and switching loss.
Detailed theoretical analysis, simulation and experimental results are included in this dissertation.
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Dedication
This document is dedicated to my family:
My wife, Ms. Yuan Wen;
My father, Mr. Houren Zou;
And my mother, Mrs. Chunying Wang.
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Acknowledgments
I first would like to thank my wife, Ms. Yuan Wen, for her continuous support during my four-year PhD period and helped me to go through many difficulties. Even though we are apart by 3000 miles right now, I can always feel her tremendous love, encouragement and patience on me. Without her support, it would be impossible for me to accomplish what I have done. I am also grateful to my parents for their unconditional love and support.
My deepest gratitude also goes to my PhD advisor, Dr. Jin Wang, who has led me into the door of power electronics and consistently providing me guidance when I encounter academics obstacles. His all-around knowledge in both power-electronics and communication skills set a perfect example for me in my future endeavor. I would also like to thank him for offering me the luxury opportunity to let me carry my research freely in the lab, and always encourage me to give me confidence.
I also want to thank the professors in OSU, including Dr. Longya Xu, Dr. Donald
Kasten, Dr. Vadim Utkin and Dr. Mahesh S. Illindala for serving as my PhD dissertation or qualifying exam committee member and leading many beneficial discussion with me.
Special thanks to Dr. Steven Sebo for working with me in my teaching tasks for ECE 747
High Voltage Engineering. I benefited a lot from his knowledge and working attitude.
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I would also like to thank all the incredible teammates here in OSU, especially Mr.
Mark J. Scott, who worked with me every day and night in the basement of Caldwell
Labs, helping me to build many test setups and to educate me about American culture and lifestyle. Many thanks to Mr. Renxiang Wang, who helped me adapted the life in the US quickly when I first came here four years ago.
I want to give my thanks to Mr. Cong Li, Mr. Feng Guo, Mr. Chih-lun Wang, Ms.
Xiu Yao, Mr. Luis Herrera, Mr. Damoun Ahmadi, Mr. Lixing Fu, Mr. Jinzhu Li, Mr.
Ernesto Inoa, Mr. Xuan Zhang, Mr. Chengcheng Yao, Mr. Da Jiao, Mr. Jizhou Jia, Mr.
Hanning Tang, Dr. Haiying Xing, Dr. Jingyan Li, Dr. Lei Yang, Mr. Zhendong Zhang,
Dr. Jinhua Du, Mr. Kai-Chien Tsai, Dr. Yuan Zhang, Mr. Bo Guan, Mr. Yu Liu and all other fellow students I worked with.. Thank you all for companying me during my happy and difficult days in the past four years. I will not forget all the days I was embraced by your friendship, help and support.
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Vita
July 2005 B.S. Information Engineering, Xi`an Jiaotong University
July 2008 M.S. Control Science, Xi`an Jiaotong University
Sept 2008 to present Ph.D student, The Ohio State University
Publications
[1] K.Zou, M. J. Scott and J.Wang, “A Switched-capacitor Voltage Tripler with Automatic Interleaving Capability” ,IEEE Tranaction on Power Electronics , vol. 27, No.6, pp. 2857- 2868, 2012.
[2] K.Zou, M. J. Scott and J.Wang, “Switched-capacitor Based Voltage Multipliers and Dc/ac Inverters” ,IEEE Transaction on Industrial Application , Accepted, Feb.2012.
[3] K. Zou and J. Wang, “Recent Developments on High-Power Switched-Capacitor Converters”, in IEEE Power and Energy Conference at Illinois , pp. 1-5, Feb. 2012.
[4] K.Zou, Y. Huang and J.Wang, “A voltage regulation method for high power switched- capacitor circuits”, in IEEE Applied Power Electronics Conference and Exposition (APEC2012) , pp. 1387-1391, Feb. 5-9, 2012.
[5] Ke Zou, Mark J. Scott and Jin Wang, “Switched Capacitor Cell Based DC-DC and DC-AC Converters,” in IEEE Applied Power Electronics Conference (APEC2011), Fort Worth, TX,pp.224-230,March, 2011.
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[6] Ke Zou, Mark J. Scott and Jin Wang, “The Analysis of DC-DC Converter Topologies Based on Stackable Voltage Elements,” in 2010 IEEE Energy Conversion Congress and Expo(ECCE2010) , Atlanta, GA, pp.4428-4433, Sept.12-16, 2010. [7] Ke Zou, Stephen Nawrocki, Renxiang Wang and Jin Wang , “High Current Battery Impedance Testing for Power Electronics Circuit Design Optimization,” in IEEE 2009 Vehicle Power and Propulsion Conference (VPPC2009), Dearborn, MI, pp. 531-535, Sept. 7- 10, 2009. [8] Mark J. Scott, Ke Zou, and Jin Wang, “A Gallium-Nitride Switched-Capacitor Circuit Using Synchronous Rectification”, IEEE Transaction on Industrial Application , Accepted, June.2012. [9] Mark J. Scott, Ke Zou, Ernesto Inoa, Ramiro Duarte, Yi Huang and Jin Wang, “A Gallium- Nitride Switched Capacitor Power Inverter for Photovoltaic Applications,” in IEEE Applied Power Electronics Conference and Exposition (APEC2012) , Orlando, FL, 2012.
[10] Damoun Ahmadi, Ke Zou, Cong Li, Yi Huang and Jin Wang,, “A Universal Selective Harmonic Elimination Method for High Power Inverters”, IEEE Trans. on Power Electronics, vol.26, no.10,pp 2743-2752, Oct. 2011. [11] Mark J. Scott, Ke Zou, Jin Wang, Chingchi Chen, Ming Su and Lihua Chen, “A gallium- nitride switched-capacitor circuit using synchronous rectification ,” in 2011 IEEE Energy Conversion Congress and Expo (ECCE2011) , Phoenix, AZ, pp.2501-2505, Sept., 2011. [12] Damoun Ahmadi, Ke Zou and Jin Wang, “Weight oriented optimal PWM in low modulation indexes for multilevel inverters with unbalanced DC sources”, in IEEE Applied Power Electronics Conference and Exposition, Palm Spring, CA, pp.1038-1042. , Feb. 2010. [13] Jin Wang, Ke Zou, Chingchi Chen and Lihua Chen, “A High Frequency Battery Model for Current Ripple Analysis,” in IEEE Applied Power Electronics Conference and Exposition(APEC2010), Palm Spring, CA, pp.676-680, Feb. 2010. [14] Jin Wang, Ke Zou and Jeremiah Friend, “Minimum Power Loss Control – Thermoelectric Technology in Power Electronics Cooling,” in IEEE 2009 Energy Conversion Congress and Expo (ECCE2009) , San Jose, CA, pp. 2543 –2548, Sept.2009.
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Fields of Study
Major Field: Electrical and Computer Engineering
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Table of Contents
Abstract ...... ii
Dedication ...... iv
Acknowledgments ...... v
Vita ...... vii
Publications ...... vii
Fields of Study ...... ix
Table of Contents ...... x
List of Tables...... xvi
List of Figures ...... xvii
Chapter 1 Introduction ...... 1
1.1. The Generalized Forms of Traditional Non-isolated Dc-dc Converters ...... 1
1.2. Switched-capacitor Converters ...... 4
1.3. The Motivation of This Work ...... 8
1.4. Chapter Review ...... 9
Chapter 2 Existing Switched-capacitor Converter Topologies ...... 12
x
2.1. Direct-charging Based Converters ...... 13
A. Parallel-series converters...... 13
B. Converters based on the time-sharing concept...... 15
2.2. Indirect-charging Based Converters...... 16
A. Generalized multi-level switched-capacitor dc-dc converter ...... 17
B. Flying capacitor multilevel dc-dc converter (FCMDC) ...... 18
C. Multilevel modular capacitive clamped dc-dc converter (MMCCC) ...... 20
2.3. Resonant Switched-capacitor Converters (RSCC)...... 22
A. A family of two-transistor resonant switched-capacitor converters ...... 22
B. A Phase-Shift Controlled high-efficiency RSCC...... 24
C. A family of RSCC without extra inductors...... 25
Chapter 3 The Cell-based Dc-dc Converters and Dc-ac Inverters ...... 27
3.1 Basic Switching Cells ...... 27
A. Cell structure ...... 27
B. The component selection of proposed cells ...... 30
3.2 Half-Cell Based Dc-dc Multiplier ...... 32
A. Structure ...... 32 xi
B. The soft-switching principle ...... 33
C. The power loss analysis on the proposed voltage doubler ...... 39
3.3. Full-Cell and Half-Cell Based Dc-ac Inverters ...... 44
A. Full-Cell Based Inverters ...... 44
B. Half-Cell Based Inverters ...... 45
C. The multi-carrier PWM control method for a five-level switched-capacitor
inverter ...... 46
D. The soft-switching scheme for switched-capacitor inverters...... 48
E. Simulation results ...... 51
3.4 Experimental Results ...... 53
A. DC-DC multiplier test ...... 53
B. DC-AC inverter test ...... 58
3.5 Conclusion ...... 61
Chapter 4 A Switched-capacitor Voltage Tripler with Automatic Interleaving Capability
...... 62
4.1 Methods to Minimize the Power Loss in a Switched-capacitor Dc-dc Converter ... 62
A. Minimizing the switching loss — soft-switching ...... 63
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B. Minimizing the conduction loss — reducing the intermediate stages ...... 66
C. Minimizing the conduction loss — a 50% duty ratio for the charging and
discharging currents...... 67
D. Losses on the input capacitor — the interleaving operation ...... 71
4.2 The Proposed Voltage Tripler with Interleaving Capability ...... 72
A. Structure ...... 72
B. Component stress analysis...... 76
4.3 The Functional Analysis of a Practical Converter with Proposed Structure ...... 79
A. The soft-switching analysis ...... 79
B. Input current interleaving analysis ...... 85
C. Output voltage interleaving analysis ...... 87
D. A Comparison between the proposed circuit and the interleaving ZCS-
MMCCC circuit...... 91
E. The influence of unequal stray inductances of the two steps...... 92
4.4 The Experimental Results ...... 93
4.5 Conclusion ...... 99
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Chapter 5 The Voltage Regulation method for High-power Switched-capacitor Dc-dc converters ...... 100
5.1 The Traditional Voltage Regulation Methods ...... 100
5.2 The Proposed Voltage Regulation Method ...... 101
A. The shape of the capacitor charging current ...... 101
B. The capacitor voltage during the charging state ...... 105
C. The capacitor voltage during the discharging state ...... 106
D. The average capacitor voltage vs. the duty ratio ...... 106
5.3 The Design of A Voltage Doubler with Voltage Regulation Capability ...... 108
A. Structure ...... 108
B. The residual current in the stray inductance ...... 109
C. The peak current reduction...... 111
D. The snubber circuit design...... 112
5.4 The Power Loss Analysis of the Voltage Doubler with the Proposed Method ..... 116
A. The switching loss analysis ...... 116
B. The conduction loss analysis ...... 118
5.5 The Experimental Results ...... 119
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5.6 Conclusion ...... 123
Chapter 6 The Dynamic Voltage Restorer (DVR) Based on the Switched-capacitor
Concept ...... 124
6.1 Dynamic Voltage Restorer (DVR) ...... 124
6.2 The Structure of a SC Based DVR ...... 125
6.3 The Operation of the Isolation Cell...... 127
A. The structure of the isolation cell ...... 128
B. The soft-switching of the isolation cell ...... 129
6.4 The Simulation Results...... 133
Chapter 7 Summary and Future Work ...... 138
7.1 Summary ...... 138
7.2 Future Work ...... 140
References ...... 142
xv
List of Tables
Table 3.1. The RMS current and conduction loss of different components in the proposed voltage doubler...... 43
Table 3.2. A loss comparison between the proposed voltage doubler and traditional voltage doubler with soft-switching capability ...... 44
Table 4.1. Normalized Input Current Ripple and Power Loss at Different Output
Capacitances ...... 87
Table 4.2. A Comparison Between the Interleaving MMCCC and the Proposed
Converter...... 92
Table 4.3. The Optimal Duty Ratio at Different Stary Inductance Ratios...... 93
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List of Figures
Figure 1.1. (a) The canonical switching cell (the first-order cell). (b) The voltage relationship of different voltage stiff elements...... 3
Figure 1.2. The third order switching cell and the relationship between different voltage stiff elements...... 3
Figure 1.3. A switched-capacitor voltage doubler...... 5
Figure 2.1. A voltage quadrupler based on the parallel-series concept...... 14
Figure 2.2. The direct-charging 3X converter topology...... 16
Figure 2.3. The generalized three-level switched-capacitor dc-dc converter...... 18
Figure 2.4. The FCMDC topology...... 20
Figure 2.5. The MMSCC topology...... 21
Figure 2.6. Unity-mode switched-capacitor resonant converter...... 23
Figure 2.7. Switched-capacitor-based resonant converter...... 25
Figure 2.8. ZCS multilevel modular switched-capacitor dc-dc converter...... 26
Figure 3.1. The structure of switched-capacitor cells...... 28
Figure 3.2. The operation states of a full-cell...... 29
Figure 3.3. The realization of switching cells using MOSFETs...... 31
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Figure 3.4. A dc-dc voltage doubler based on half-cells...... 34
Figure 3.5. The equivalent circuit when C 1 is being charged...... 35
Figure 3.6. The equivalent circuit when C 2 is being charged...... 35
Figure 3.7. The equivalent circuit during the dead-time...... 36
Figure 3.8. The charging current of capacitor C 1...... 37
Figure 3.9. The current profiles for the switches in the left cell...... 42
Figure 3.10. A five-level full-cell switched-capacitor inverter...... 45
Figure 3.11. A five-level half-cell switched-capacitor inverter...... 46
Figure 3.12. Six sections for a five-level switched-capacitor inverter...... 48
Figure 3.13. The simulation results of the inverter...... 52
Figure 3.14. The frequency spectrum of the output voltage...... 52
Figure 3.15. The photograph of the prototype cell...... 54
Figure 3.16. The input and output voltage waveform of the voltage doubler...... 54
Figure 3.17. The current and turn-off voltage of S 1...... 55
Figure 3.18. The efficiency curve of the proposed dc-dc multiplier...... 56
Figure 3.19. The breakdown of power loss at an input power of 1000W...... 57
Figure 3.20. The input and output voltage waveforms of the inverter...... 59
Figure 3.21. The waveforms of the output current Id and the charging current I C1 ...... 59
Figure 3.22. The zoomed-in capacitor charging current of the inverter...... 60
Figure 3.23. The efficiency curve of the proposed dc-ac inverter...... 61 xviii
Figure 4.1. The equivalent circuit of the charging loop and shapes of the charging current.
...... 65
Figure 4.2. A 3X ‘direct charging’ switched-capacitor dc-dc converter...... 67
Figure 4.3. The capacitor currents of two cases with different duty ratios in one switching cycle...... 69
Figure 4.4. The structure of the 3X converter...... 74
Figure 4.5(a).The two switching steps of the top stage. (b) The current waveforms of the top stage...... 75
Figure 4.6. One state showing a path with two off-state switches...... 76
Figure 4.7. The other two 3X topologies...... 78
Figure 4.8. The charging current of the second step...... 84
Figure 4.9. The simulation results of a 55 kW switched-capacitor voltage tripler...... 90
Figure 4.10. The test setup of the experiment...... 95
Figure 4.11. The input current interleaving results...... 97
Figure 4.12. The output voltage interleaving results...... 97
Figure 4.13. The efficiency curve of the proposed converter...... 98
Figure 5.1. (a) The equivalent circuit of the capacitor charging loop. (b) The capacitor current. (c) The capacitor voltage...... 104
Figure 5.2. The voltage of the output capacitor at different duty ratios...... 108
Figure 5.3. The voltage doubler with stray inductance...... 110 xix
Figure 5.4. (a) The operation of the snubber circuit. (b) The equivalent circuit for S 1. .. 114
Figure 5.5. The photo of the proposed voltage doubler...... 120
Figure 5.6. The waveforms of the capacitor charging current I S1 and I S4 ...... 121
Figure 5.7. The waveforms of the input and output voltage...... 121
Figure 5.8. The efficiency v.s. voltage transfer ratio at normal condtion...... 122
Figure 5.9. The efficiency v.s. voltage transfer ratio with a 15 cm cable added...... 123
Figure 6.1. The operation of a traditional DVR...... 124
Figure. 6.2. The structure of the proposed DVR circuit...... 126
Figure 6.3. The structure of the isolation cell...... 129
Figure 6.4. The profile of I inv ...... 130
Figure 6.5. The capacitor charging time analysis...... 133
Figure 6.6. The voltage sage compensation waveforms...... 135
Figure 6.7. The capacitor charging waveforms in one inverter switching cycle...... 136
Figure 6.8. The zoomed-in view of the capacitor charging waveforms...... 137
Figure 7.1. The GaN HEMT switched-capacitor prototype...... 141
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Chapter 1 Introduction
Buck, boost, buck/boost, SEPIC, Cuk, … over the years, many types of dc-dc converter topologies have been proposed. For all these topologies, the inductor is the essential component, which is bulky, heavy and costly. With the wide implementation of renewable energy sources and rapid progress in electrification of personal transportations, there is an ongoing demand for simple, cost-efficient and reliable converter topologies.
This is the reason why switched-capacitor converters, which have no inductor, become one hot topic of research in recent years. However, existing switched-capacitor circuits have many limitations, including large EMI noises, low efficiency and the difficulty in realizing voltage regulation. To apply the switched-capacitor concept in high-power applications, new topologies and voltage regulation methods have to be proposed to solve the above problems.
1.1. The Generalized Forms of Traditional Non-isolated Dc-dc Converters
For traditional voltage-source converters, the components that define the voltage transfer ratio are the inductors. With a stable steady-state inductor current, one equation can be written for each inductor at one switching state to describe the relationship between different voltage stiff elements. Voltage stiff elements include capacitors and
1 voltage sources. The voltage transfer ratio of the converter can be determined by simply solving a group of equations, whose number is determined by the number of switching states.
Starting from the inductors, all switched mode dc/dc converter has to follow three rules [1]:
1. One terminal of the inductor has to be connected to at least two switches directly or indirectly through voltage stiff elements.
2. Under no circumstances should two inductors be connected in series.
3. Voltage stiff element must not be placed in parallel with a non-stiff voltage element.
Based on the three rules, the generalized form of both first order and third order dc- dc converters can be determined, which are shown in Figure 1.1 and Figure 1.2, respectively. A first order converter is the one where only one inductor presents in the circuit and no capacitors exist, aside from the input/output capacitors. A third order converter contains two inductors and a single capacitor, ignoring the input/output capacitors. All the aforementioned dc-dc topologies can be generated from the proposed first order and third order cells. For example, the buck converter can be realized by connecting the input source to port 1 and 2 of Figure 1.1(a), and connecting the output load between port 4 and 2. 2
Since the inductor is usually the most bulky, heavy and costly component in a converter, it is always desirable to develop topologies that can eliminate the inductor or largely reduce the required inductance. However, due to the essential role inductors played in traditional dc-dc converters, it is difficult to eliminate them.
1 1 2 + V1 − V 1− d + + 3 − + + +
S 1 S 2 S 1 S 2 3 d V V − V1 1 2 V1 1− d
L1 L1
− − − − 4 (a) (b)
Figure 1.1. (a) The canonical switching cell (the first-order cell). (b) The voltage relationship of different voltage stiff elements.
+ V2 − 1 3 5 + + S 1 + 1 V +V V3 V 1− d 2 3 3 − S 2 − − 2 4 6 − d + V2 1− d Figure 1.2. The third order switching cell and the relationship between different voltage stiff elements. 3
1.2. Switched-capacitor Converters
The switched-capacitor (SC) converters contain only capacitors and switching devices.
The absence of magnetic components helps to shrink the system volume and cost. For this reason they have been extensively used in low power applications, especially chip- level power conversions. Various topologies and control methods have been proposed and applied [2] [3] [4] [5] [6] [7] [8] [9] [10] [11].
The principle of switched-capacitor converters can be explained through the simple example of a voltage doubler shown in Figure 1.3. This voltage doubler consists of four switches and two capacitors. S 1 and S 3 form the first group of switches. S 2 and S 4 belong to another group. The two groups of switches operate in complimentary mode. When S 1 and S 3 are turned on, the voltage source charges the upper capacitor C 1, so C 1 has a voltage same as the voltage source. When S 2 and S 4 are turned on, C 2 is charged by the voltage source so C 2 also has the same voltage as the input voltage. The voltage of C 1 and C 2 are stacked together so the load side sees a voltage equals two times the input voltage.
From the operation of the switched-capacitor voltage doubler, it can be seen that there is no inductors involved in the energy transfer process. Due to the absence of the inductor, there is no component in the circuit to hold the current. As a result, huge current spikes present during the capacitor charging process. This uncontrolled capacitor charging current puts large current stress on semiconductor switches, reduces the 4 efficiency of the converter, and introduces a large amount of EMI noises.
For traditional chip-level switched-capacitor converters, the aforementioned problems are usually acceptable due to the low power level. However, when it comes to high power applications, where high efficiency and low components stress are emphasized, many traditional switched-capacitor circuit topologies and analysis methods are not applicable.
Figure 1.3. A switched-capacitor voltage doubler. To solve these problems, several novel topologies and control methods have been developed in recent years to push the switched-capacitor converter to higher power range.
Each of the existing topologies possesses some advantages as well as some disadvantages. Sacrifices have to be made, either on total switches counts, total capacitor counts or the efficiency of the converter. For dc-dc conversion, a switched-capacitor dc– dc converter based on the generalized multilevel converter topology was presented in
[11]. The 1 kW prototype introduced in this paper can realize bidirectional power conversion between a 42 V battery and 14 V or 42 V loads [12]. In [13], a 3X (i.e. the 5 output voltage is three times of the input voltage) dc-dc multiplier/divider was proposed and a 55 kW prototype for hybrid electric vehicles (HEVs) was built. In [14], a multilevel modular capacitor-clamped dc–dc converter topology (MMCCC) was proposed with many benefits, including its modular structure, low current and voltage stress of the switches and its bi-directional operation capability.
However, the aforementioned topologies for high-power application all require a large number of capacitors, which can significantly increase the physical size and the cost of the converter. Moreover, normally only one fixed output voltage can be achieved for these topologies. Although special control methods [13] can be adopted to realize several output voltages, the controller complexity will be increased and the time response of the output voltage will be affected.
Charging current regulation is important for improving the efficiency of switched- capacitor converters. Several methods have been proposed to regulate the charging current by using soft-switching methods. In [15] [16] [17] [18], the quasi-resonant switched-capacitor converters are investigated, where an extra inductor is added to form an oscillation loop with the capacitors to achieve soft-switching. In [20], a soft-switching scheme which does not require extra inductive components is proposed. Since the charging current can be controlled by using soft-switching methods, both the conduction loss and switching loss can be largely reduced. This soft-switching method has been successfully applied to the MMCCC switched-capacitor topology [20]. A peak efficiency 6 of over 97% for a 630 W prototype has been reported by further adopting an interleaving scheme [21].
The other challenge for high-power SC converters is how to regulate the output voltage with high efficiency. Although the voltage regulation for small-power SC converters has been extensively studied [5] [21], the existing methods are based on a RC equivalent circuit of the capacitor charging loop. Therefore, the output voltage regulation mainly relies on the equivalent resistance in the circuit, and the converter functions as a linear regulator [15] [22]. As a result, the converter efficiency is always equal to or lower than the normalized voltage transfer ratio. For example, for a step-up switched-capacitor dc-dc converter with an ideal voltage transfer ratio of N, the maximum efficiency is
Vout /(N×V in ). The existence of this maximum efficiency largely limits the voltage regulation range and the application of SC converter in high-power voltage conversion, where high converter efficiency is required.
For the dc-ac inversion, in [23], a Marx inverter was proposed, which is based on the
Marx generator concept in high-voltage engineering. A Marx cell structure was generalized from the Marx generator. By connecting several Marx cells in series, multiple output voltage levels can be achieved. A similar structure with the benefits of common input and output grounds was presented in [24]. The benefits of Marx-cell based inverters include its multiple output voltage capability, the small number of required capacitors, and its equal voltage stress on the switches and capacitors. In [25] [26], two 7 other topologies are provided that can realize multiple output voltage and can be used for dc/ac inversion. However, since the capacitor charging time in an inverter changes from cycle to cycle, the soft-switching method mentioned above cannot be utilized. Therefore, the capacitor charging current in a switched-capacitor inverter has an extremely large peak value, which generates large power losses as well as EMI.
1.3. The Motivation of This Work
The background for this work to study high-power switched-capacitor converters is the recent developments on wide-bandgap devices, such as SiC or GaN devices. The advantages of these devices include high switching frequency, high temperature capability and small on-resistance. If the high temperature operation capability of the wide-bandgap devices is utilized, it is possible to shrink the size of converters. On the passive components side, high-temperature capacitors with 125 C̊ operation capability are already available in the market. However, the inductors, which are made with magnetic cores, are easy to get saturated at a temperature higher than 70 C.̊ This makes inductors the bottleneck for the development of high-temperature-operated converters. If switched- capacitor converters concept is used, this problem can be solved.
From the other perspective, switched-capacitor circuits can also benefit from adopting wide-bandgap devices. As mentioned in the last section, the soft-switching is needed in
8 helping reduce the EMI noises and switching loss for switched-capacitor converters. But this requires adding extra inductors, which contradicts the purpose of using switched- capacitor converter [27]. With the high frequency operation capability of SiC or GaN switches, the required inductance is low enough that can be realized by using air-core inductors. Once the soft-switching is achieved, the switching loss is minimized. With the low on-resistance of the SiC or GaN devices, the conduction loss can also be reduced.
The motivation of the work presented in this dissertation is to further explore the possibility of adopting switched-capacitor circuits in high-power applications, where the cost and physical size are crucial. To achieve this goal, researches have been carried on three different topics of switched-capacitor converters: topologies, charging current control, and voltage regulation method.
1.4. Chapter Review
In Chapter 2, a literature review is performed on the existing switched-capacitor converters topologies. Three categories of switched-capacitor converters are introduced: the direct-charging based converters, the indirect-charging based converter and the resonant switched-capacitor converters.
Chapter 3 presents a cell-based switched-capacitor topology. Two switched capacitor cells, including the half-cell and full-cell are introduced. The half-cell based dc-dc
9 converter possesses the advantage of multiple voltage outputs and small input current ripple. A five-level half-cell-based dc-ac inverter is also introduced that can realize zero- current-switching over the entire fundamental cycle. The simulation and experimental results of the cell-based converters are shown in this chapter.
Chapter 4 presents a high-efficiency switched-capacitor dc-dc voltage tripler topology aimed at high-power applications. A two-step current charging method is proposed to enable the input current and output voltage interleaving function without adding an excessive amount of components. The large loss on the input capacitor that exists in the traditional switched capacitor topologies is eliminated by employing this interleaving scheme. The soft-switching and interleaving results are analyzed in detail. The experimental results on a 2 kW prototype are demonstrated to verify the proposed topology.
In Chapter 5, a voltage regulation method for high power switched-capacitor converters is proposed. The analysis method introduced in this chapter is based on a RLC equivalent circuit of the capacitor charging loop, instead of the traditional RC equivalent circuit. The output voltage is regulated by varying the termination angle of the quasi- sinusoidal charging current. With the third quadrant operation of MOSFETs and optimized stray inductance distribution, the efficiency of converters with the proposed voltage regulation method can exceed the theoretical maximum efficiency value for traditional methods. Detailed theoretical analysis and practical design concerns on a 10 switched-capacitor voltage doubler are addressed in this chapter.
Chapter 6 introduced a dynamic voltage restorer, which serves as an example of the switched-capacitor converter. A two-step isolation block is added to realize the voltage isolation function, which was usually achieved using transformers. The soft-switching of the isolation block can be achieved.
Chapter 7 summarized the dissertation and provided an outlook of the future work.
11
Chapter 2 Existing Switched-capacitor Converter Topologies
Switched-capacitor concept has been widely applied in many fields of electrical engineering, with the examples ranging from the surge generators in high voltage engineering [28] to the chip-level voltage converters and inverters [2]-[7]. In this type of converters, the capacitors function as the sole energy transfer components in a SC converter, and the voltage conversion is realized by connecting the capacitors to the voltage source and load in different manner.
There are always three operation states for a capacitor: charging state, discharging state and idle state. The capacitor can be charged by the voltage source, or by another capacitor in the circuit. On the other hand, the capacitor can discharge to the load, or to another capacitor in the circuit. The capacitors that receive energy from or send energy to another capacitor, instead of the source or the load, are called intermediate capacitors.
The existing of intermediate capacitors increases level of energy transfer and also the conduction loss. The idle state is used to describe the state when the capacitor is neither charging nor discharging. The idle state is an undesired state, since it implies a waste of time for energy transferring activity.
Based on how the electric charges are transferred from the source to the load, the switched-capacitor converter can be divided into two categories: direct-charging based converters or indirect-charging based converters.
12
2.1. Direct-charging Based Converters
Direct charging means the voltage source directly charges the output capacitor. Since
no intermediate stage exists in this type of converter, the number of capacitors can be
minimized. Moreover, since the electric charges are directly sent from the source to the
output capacitor, the conduction loss is minimized. The idle time for the capacitors in
direct charging converters is zero.
There are mainly two direct charging schemes: the parallel-series converter and the
converters based on time-sharing scheme.
A. Parallel-series converters
This is the simplest switched-capacitor converter scheme which has been widely used
for many years. The basic operation principle of this type of converter is that capacitors
are charged by the source in-parallel and discharged to the load in-series, so a higher
output voltage is achieved; or the capacitors are charged in-series and discharged in-
parallel, so a lower output voltage is achieved.
One example of the parallel-series converters is shown in Figure 2.1, which is a
voltage quadrupler than can provide an output voltage four times the input voltage. The
switches in this converter are divided into two groups, which are named as S A and S B.
The two groups of switches operate in complimentary mode. When the group of switches
SA are turned on, all the capacitors are charged by the source in parallel, and the capacitor
C1~C 3 have the same voltage as the input voltage. When the switches SB are turned on, 13 all the capacitors are discharging to the load in series. The resulted voltage is the input voltage plus the voltage of the three capacitors C 1~C 3, which yield a voltage four times the input voltage.
Figure 2.1. A voltage quadrupler based on the parallel-series concept. This topology processes many advantages. First, the voltage stress on all the capacitors and most switches is only the input voltage, except the switch connected to the output capacitor, which needs to sustain three times the input voltage. Second, all the switches has a duty ratio of 0.5, which means there is no idle state for the capacitor and the conduction loss is minimized.
Despite its simplicity and the advantages mentioned above, this topology is not suitable for high-power applications. The main reason is the large requirement on the output capacitor. It can be seen from the voltage quadrupler case that there is a voltage difference of three times the input voltage between the two switching states of the converter. In order to obtain stable output voltage, an extremely large output capacitor bank is required to filter out this voltage ripple, which is not achievable for high-power
14
applications.
B. Converters based on the time-sharing concept.
The time-sharing concept means the source takes turns to charge each output
capacitor. So if there are N capacitors need to be charged, each capacitor is only charged
for 1/N of the switching cycle.
As a direct-charging topology, there are no intermediate stages between the source and
the load, which can help to reduce the conduction loss. However, this time-sharing
scheme is not efficient when the voltage transfer ratio is high. As the voltage transfer
ratio increases, both the voltage stress on the switches and the peak charging current will
increase, which generates a larger conduction losses and converter cost.
A voltage tripler topology based on the time-sharing concept is shown in Figure 2.2.
In this topology, there are three stages, with each stage contains two switches and one
capacitor. The three stages operate in complimentary mode, so each stage only have one
third of the switching cycle to charge the capacitor. For example, in the top stage, S 1 and
S2 are used to charge the capacitor C 1. All the electric charge need to be transferred from
the source to C 1 in 1/3 of the switching cycle, which results in a larger peak current value
and a higher conduction loss.
For the component stress, all the capacitors only withstand a voltage stress equals the
input voltage. However, each switch in Figure 2.2 need to either block two times the
input voltage or block both positive and negative voltages which equal the input voltage. 15
This large voltage requirement on switches is another disadvantage of this topology.
Iswitch
S1 Icap
C1 Iin S2
Vin Cin S3 C2 R S4
S5 C3
S6
Figure 2.2. The direct-charging 3X converter topology.
2.2. Indirect-charging Based Converters.
Indirect charging based converter corresponding to those converter in which intermediate capacitors are added to help the energy transfer from the source to the load.
In this type of topologies, the electric charges need to flow into and out of the intermediate capacitors before they were finally delivered to the load, which will increase the conduction loss. However, with the added capacitors, both the peak charging current and the required number of switches can be reduced. Most recently developed high- power switched-capacitor converters belong to this category.
16
A. Generalized multi-level switched-capacitor dc-dc converter
The first converter topology investigated is a bidirectional switched capacitor dc–dc
converter presented in [11]. In this topology, a group of switching cells is used, which is
shown in Figure 2.2. Each cell consists of two switches and one capacitor. The voltage
rating of both the capacitor and the switches in the cell equals the input voltage. For this
reason, it is suitable for high voltage applications.
The converter shown in Figure 2.2 is a voltage tripler. It can be seen clearly that there
are three stages. The first stage has only one switching cell (S 1P , S 1N and C 1). The second
and the third stage have two and three switching cells, respectively. Multiple operation
modes are involved in this converter. The duty ratio for each switch in the circuit is 1/3,
which is not ideal for the conduction loss consideration.
The main drawback of this topology is the large amount of components it required. If
one capacitor or one switch is defined to have a voltage stress of the input voltage, to
realize a voltage conversion ratio of N, a total of N(N+1) switches and N(N+1)/2
capacitors are required. So this converter can only be used to achieve low conversion
ratio converters.
17
Figure 2.3. The generalized three-level switched-capacitor dc-dc converter.
B. Flying capacitor multilevel dc-dc converter (FCMDC)
An improved structure is the flying capacitor multilevel dc-dc converter (FCMDC)
shown in Figure 2.4 [29]. In this topology, the number of switches is reduced to 2N. In
[13], a control method is presented so three different levels of output voltage can be
realized by a 3X converter using this topology.
The FCMDC topology is derived from the generalized topology introduced in the last
section. The number of both the switches and the capacitors are reduced in this topology.
18
For a converter with a voltage transfer ratio of N, only N capacitors and 2N switches are needed. The reduction of the total component number can improve the stability of the converter in high power applications.
However, this topology still suffers from several serious problems. Firstly, although the total number of components is reduced, the voltage and current stress of each component is increased. For example, the voltage stresses for C 1, C 2 and C 3 are V in , 2V in and 3V in , respectively. Also, the current stresses for the switches are not equal. The inner swithcs, S 1P, S1N will have much larger stress than outer switches. This unequal voltage rating of capacitors and current stress on switches increases the total cost of the converters.
Another disadvantage of this topology is the reduced duty ratio, which is the same problem of the generalized topology introduced in the last section. During operation, each switch is only turned on for 1/3 of the switching cycle. This low utilization of the switch generates large conduction loss.
19
Figure 2.4. The FCMDC topology.
C. Multilevel modular capacitive clamped dc-dc converter (MMCCC)
The MMCCC topology is presented in [14] [30]. A MMCCC based voltage
quadrupler is shown in Figure 2.5. There are two groups of switches, S A and S B, which
operate in compliments mode. When SA are turned on, the source charges C 1 to make it
maintain a voltage equals V in . The source and C 2 are cascaded together to charge C 3, so
C3 has a voltage equals the sum of C 2 and the sources. C 4 discharges to the load. When S B
are turned on, the source is connected in series with C 1 and provide energy to C 2, so C 2
equals two times the input voltage. At the same time, the source and C 3 are connected in
20 series to charge C 4. As a result, the voltage on C 1, C 2, C 3 and C 4 are V in , 2V in , 3V in and
4V in , respectively.
The MMCCC topology has many advantages compared to the previously introduced topologies. First, the charging current duty ratio is always 0.5, regardless of the voltage conversion ratio. This feature results in a low conduction loss. Also, all the switches have the same voltage rating, which can help to lower the converter cost. The total number of switches is another advantage, with only 3N-1 switches required to achieve a converter with a voltage conversion ratio of N.
However, the MMCCC topology still has some drawbacks. The most important one is the fact that the capacitor count is a large number. To achieve a voltage conversion ratio of N, a total of N(N+1)/2 normalized capacitors are required. Since the stress of capacitors in each stage is not identical, it is hard for this topology functions as a modular structure for high voltage applications.
Figure 2.5. The MMSCC topology.
21
2.3. Resonant Switched-capacitor Converters (RSCC).
The aforementioned topologies are the traditional switched-capacitor converters. One
common feature of these topologies is that the capacitor charging current is not regulated.
The unregulated capacitor charging current is the main reason for EMI noise, which
largely limits the switched-capacitor converters in high-power applications. In recent
years, a type of resonant switched-capacitor converter has been proposed [30]. For
resonant converter, the capacitor charging loop is composed of the loop resistance,
capacitance and also the loop inductance. An RCL resonance can be induced in this
charging loop, which generates a quasi-sinusoidal shape of the capacitor charging
current. To form a RCL resonant circuit, a small resonant inductor can be added into the
circuit. Also, in some topologies, especially in converters with large physical size, the
loop stray inductance can be used, instead of adding an extra inductor.
A. A family of two-transistor resonant switched-capacitor converters
This type of RSCC [15] utilized the traditional switched-capacitor topologies, which
compose of two transistors, two diodes and one intermediate capacitor. An extra inductor
is added in series with the intermediate capacitor to form an oscillation loop. During its
operation, no matter the capacitor is at charging or discharging state, the capacitor current
is always sinusoidal. As a result, the large initial current spike is eliminated.
Figure 2.6 shows a unity-mode RSCC, which generates an output voltage equals the 22 input voltage. Switch S 1 and S 2 work in complimentary mode. When S 1 is on, The capacitor is charged by the source. Because the presence of the resonant inductor Lr, the capacitor charging current has a sinusoidal shape. When S 2 is on, the capacitor discharges to the load with the same sinusoidal current. If the inductance of Lr is adjusted so that the
LC oscillation frequency equals to the switching frequency, the sinusoidal current will drops to zero when the switches are turning off. As a result, zero-current-switching can be realized in this topology.
Figure 2.6. Unity-mode switched-capacitor resonant converter. This topology can significantly reduce the switching loss as well as the EMI noise.
However, as pointed out in [27], there are several limitations of this topology that prevent it from widely used in real applications. The most obvious drawback of this topology is that it cannot realize voltage regulation. Since the oscillation frequency is a fixed value, the traditional PWM method for switched-capacitor converters cannot be used to regulate the output voltage.
23
B. A Phase-Shift Controlled high-efficiency RSCC.
To solve the problem that the voltage cannot be regulated in a RSCC, a new topology
with phase-shift control is proposed in [30], which is can regulate the output voltage
from 19% to 81% of the input voltage.
The topology of the converter is shown in Figure 2.7. This converter consists of two
half-bridge inverters with four switches S 1~S 4 and a series resonant circuit Lr and Cr.
There are four switching state exist which are divided into two groups: S 1 and S 2, and S 3
and S 4. All switches work with a 50% duty ratio. The switches within one group work in
complimentary mode. There is a phase shift between two groups. By adjusting the angle
of the phase shift, the output voltage regulation can be achieved.
During it operation, the voltage on Cr is maintained to be half the input voltage. The
switching frequency is set to be higher than the resonant frequency so the zero-voltage-
switching can be achieved. In other words, the LC oscillation is used to reduce the EMI
noise and the soft-switching is realized through ZVS.
The advantages of this topology include that all the switches operate in 50% duty
ratio, which largely reduce the conduction loss. Also, since the ZVS is achieved, the
switching loss is minimized. As a result, this topology can achieve a very high efficiency,
which is reported as high as 99%.
However, there are still several disadvantages regards to this topology. First, this is
only a buck type converter, but for many real applications, boost converters are used. 24
Also, the structure and control of this converter is complicated, since extra snubber
circuit has to be added to realize the soft-switching.
S1
Lr S2 Iin
Vin Cr S3 R Co
S4
Figure 2.7. Switched-capacitor-based resonant converter.
C. A family of RSCC without extra inductors.
The aforementioned RSCC topologies all require extra inductor to realize soft-
switching. But for many large-size converters, the loop stray inductance is large enough
to induce an acceptable oscillation frequency. In [20], a family of zero-current-switching
SCCs is proposed which utilized the stray inductance in the loop.
Figure 2.8 shows the MMCCC topology with the stray inductance. The stray
inductance comes from the cable inductance, ESR of the capacitors and the parasitic
inductance of any component in the capacitor charging loop. To achieve the zero-
current-switching, the LC oscillation frequency, which is resulted from the loop stray
25 inductance and the main capacitors, has to be equal to the switching frequency.
Therefore, there is a minimum requirement of the value of the stray inductance so the oscillation frequency can be achieved using available switching devices. With the adoption of high band-width devices such as SiC and GaN devices, the requirement can be easier to meet. Most topologies proposed in this dissertation is based on this soft- switching scheme and utilizes the stray inductance to realize zero-current-switching.
SA1 SB2 SA4 SB5
C1 C2 C3 Vin C4 R Cin SB1 SA3 S SA2 SB3 B4 SA5
Figure 2.8. ZCS multilevel modular switched-capacitor dc-dc converter.
26
Chapter 3 The Cell-based Dc-dc Converters and Dc-ac
Inverters
3.1 Basic Switching Cells
A. Cell structure
The full switched-capacitor cell is shown in Figure 3.1(a) [31]. It is a four-port system
consisting of four switches and one capacitor. The half-cell (Marx cell) is shown in
Figure 3.1(b), with only three switches and one capacitor. The final converter is a series
connection of these cells, as shown in Figure 3.1(c). Each cell is charged by the cell of
the previous stage and discharges to the cell of the next stage. Here the voltage source is
placed before the first cell, while an alternative method is to put the voltage source in the
middle of the series so the current stress of central cells can be reduced.
Figure 3.2 shows the switching states of one full cell. In this figure, C 1 is the capacitor
from the previous stage and has a voltage of V C. Port 2 is assumed to have a voltage
potential of V 2. Among the four switches in Figure 3.2(a), S 1 and S 2 form one group and
are switched together. S 3 and S 4 are independent switches and cannot be turned on along
with any other switches. As a result, there are three switching states:
I. S 1 and S 2 are on (Figure 3.2(b)). The two capacitors are connected in parallel. Port 4
has the same potential as port 2. The potential of port 1 and 3 is V 2+V C.
27
II. S 3 is on (Figure 3.2(c)). Port 1 and port 4 have the potential of V 2+V C and port 3 has a potential of V 2+2V C.
III. S4 is on (Figure 3.2(d)). Port 3 has a potential of V 2. The potentials of port 1 and port 4 are V2+V C and V 2-VC, respectively.
(a) (b)
(c)
Figure 3.1. The structure of switched-capacitor cells.
(a). The full-cell. (b). The half-cell. (c). The series connection of switched-capacitor cells.
28
(a) (b)
(c) (d)
Figure 3.2. The operation states of a full-cell.
(a). The full switched-capacitor cell. (b). State I. (c). State II. (d). State III. In switching state I, two capacitors are connected in parallel and the one with higher voltage charges the other. In states II and III, the two capacitors are connected in series so various voltage levels can be achieved. For one single full switching cell, there are three achievable voltage levels for port 4: V 2, V 2+V C and V 2-VC. Port 3 also has three achievable voltage levels: V 2, V 2+V C and V 2+2V C.
By connecting N switching cells in series, there are 2N+1 achievable levels between port 3 or port 4 of the last stage and port 2 of the first stage. If port 2 of the first stage has zero voltage potential, then for port 4 of the last stage, the achievable voltage levels are
29
i×V C, where i is an integer between -N and N. Since both positive and negative voltage
levels can be generated in a symmetric manner, the full switched-capacitor cell is suitable
for dc-ac inverting applications.
For the half switched-capacitor cell, there are only two switching states: I: S 1 and S 2 on
and II: S 3 on, which correspond to Figure 3.2(b) and (c). The number of achievable
voltage levels for port 3 or port 4 in a converter with N stages of half switched-capacitor
cell is N+1. If port 2 of the first stage has zero voltage potential, then for port 3 of the
last stage, the achievable voltage levels are (i+1)×V C, where i is an integer between 0 and
N. The dc-dc voltage multiplier can be realized by connecting the load to port 2 of the
first stage and port 3 of the last stage.
For the half cell, negative voltage can also be achieved by connecting the previous
stage between port 3 and port 4. In this way, the dc-ac inverting operation can be
achieved by employing half-cells, which is the Marx inverter topology presented in [23].
B. The component selection of proposed cells
For a half-cell, the diagonal switch S 3 only conducts forward current and blocks
forward voltage. For the other two switches S 1 and S 2, however, in order to prevent the
shoot-through when S 3 is closed, one switch has to block the forward voltage and another
has to block the reversed voltage. As such, there are two forward current conducting,
forward voltage blocking switches such as an IGBT or a MOSFET and one forward 30 current conducting, reversed voltage blocking switch like a diode. To achieve bi- directional power flow capability of the converter, all switches can be realized by
MOSFETs and some MOSFETs operate in the third-quadrant.
For a full-cell, when it operates in state II (Figure 3.2(c)), the diagonal switch S 4 needs to block a voltage which equals to two times the capacitors voltage V C. Similarly, the diagonal switch S 3 needs to block 2V C in state III. The other two switches need to block both positive and negative voltages during state II and state III. As a result, the two diagonal switches S 3 and S 4 can be realized by MOSFETs or IGBTs with a voltage rating of 2Vc and a parallel free-wheeling diode. While each of the other two switches, S 1 and
S2, requires two MOSFETs or IGBTs, with a voltage rating of V C. The realizations of the half-cell and full-cell using MOSFETs are shown in Figure 3.3(a) and (b), respectively.
(a) (b)
Figure 3.3. The realization of switching cells using MOSFETs.
(a) The half-cell circuit. (b) The full-cell circuit. 31
3.2 Half-Cell Based Dc-dc Multiplier
A. Structure
For half-cell based dc-dc multipliers, port 3 of the last stage and port 2 of the first
stage are used as output ports to achieve the largest voltage transfer ratio. Although N+1
voltage levels can be achieved between these two ports in an N-stage half-cell multiplier,
it is not possible to have (N+1):1 voltage transfer ratio, since there is only one switching
state to achieve (N+1)×V C and the capacitors in this state are all in the discharging mode.
As a result, the output voltage cannot be maintained.
With this modular switching cell structure, a rotationally charging scheme can be
adopted to reduce the requirements of the output capacitor. This is achieved by adding
one extra half-cell to the multiplier. By doing this, the multiplier has N+1 stages and two
switching states are available to achieve an output of (N+1)×V C. This extra available
state makes it possible to generate a stable output voltage by charging the capacitors
rotationally. At any time except the dead-time, there will be one capacitor in the charging
state, and other capacitors are discharging to the load in series. The output voltage is
stable and only a small output capacitor is needed to filter out the voltage ripple during
the dead-time. Another benefit of the proposed topology is that multiple output voltages
can be achieved. For example, a three-stage multiplier with an input voltage of V in can
output V in , 2V in and 3V in .
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B. The soft-switching principle
One major problem of a switched-capacitor circuit is the unregulated charging current
during the capacitor charging process, which generates large in-rush current and EMI
noise. In [20], a soft-switching scheme is proposed by utilizing the stray inductance in
the circuit to resonate with the main capacitors. This paper employs the same idea;
however, due to the particular structure of the proposed multiplier, the soft-switching
scheme has some unique features.
Figure 3.4 shows a voltage doubler which consists of two half-cells. The dc source is
placed in the middle so the switches of the both cells experience the same charging
current. In this structure, when S 4 and S 5 are closed, the charging current of C 1 flows
from the source to the drain of S 4, instead of the normal drain to source conduction mode.
Therefore, S4 operates in the third quadrant. S 2 on the other cell has the same third-
quadrant operation mode. Other MOSFETs in the circuit operate in the first-quadrant.
The stray inductances, expressed as L S1 - LS5, mainly come from the stray inductance of
cables, the package inductance of the MOSFETs and the ESL of the capacitors. If the
layout of each cell is the same, the stray inductance difference among different cells can
be considered small, so a single resonant switching frequency works for both cells.
33
Figure 3.4. A dc-dc voltage doubler based on half-cells. The equivalent circuits in the two switching states are shown in Figure 3.5 and Figure
3.6. To simplify the analysis, the load current is assumed to be constant as Id. The capacitor charging currents are named as I C1 and I C2 , which flow from the voltage source to C 1 and C 2, respectively. It can be seen that S 1 and S 5, which operate in the first quadrant, carry only the capacitor charging current. On the other hand, S 2 and S 4, which operate in the third quadrant, carry both the capacitor charging current and the load current I d.
The proposed soft-switching scheme involves choosing a switching frequency such that the charging current drops to zero at the time when S 1 or S 5 are turning off. As a result, zero-current-switching is realized for S 1 and S 5. For S 2 and S 4, at the moment when they are turning off, the remaining current is I d. Due to the third-quadrant operation, their body diodes D 2 and D 4 will immediately take over the current. As a
34 result, the soft-switching of S 2 and S 4 is achieved. After the dead-time, the current is shifting from the diode D 2 or D 4 to the diagonal MOSFETs S 3 or S 6, so there will be reverse recovery loss of diodes. However, if SiC diodes is used to replace D 2 and D 4, this reverse recovery loss can be minimized.
Figure 3.5. The equivalent circuit when C 1 is being charged.
Figure 3.6. The equivalent circuit when C2 is being charged.
During the dead time, the load current flows through the body diodes D 1, D 2, D 4 and
35
D5. Assuming the two half-cells are made the same and the deadtime is long enough for any oscillation transients to decay, the load current will be equally split into two parts, as shown in Figure 3.7. The only voltage across these diodes is the diode forward voltage, so when their corresponding MOSFETs are turning on after the dead-time, they will experience a minimum voltage. Therefore, the zero-voltage turn-on can be achieved for
S1, S 2, S 4 and S 5.
Figure 3.7. The equivalent circuit during the dead-time. It should be noted that this soft-switching scheme only applies to the MOSFETs that are used to charge the capacitors. For the other two MOSFETs (S 3 and S 6), soft-switching cannot be achieved using this scheme. However, since the main purpose of utilizing soft- switching is to reduce the associated power loss and EMI noise due to unregulated charging current, this soft-switching scheme can still help the proposed topology in large power applications.
36
If the equivalent resistance in the charging loop can be neglected, the impedance of the capacitor charging loop can be represented by a simple LC circuit. Under this assumption, the capacitor charging current has a sinusoidal shape. The current profile of
IC1 is shown in Figure 3.8. The initial current -I0 is due to the load current conduction during the dead-time before S 1 and S 2 are turned on. Therefore, the charging current has a negative initial angle -θ0. The current reaches zero again at the angle π, which is the soft- switching point. This means the charging process needs to be finished in more than half an oscillation cycle to achieve soft-switching.
Figure 3.8. The charging current of capacitor C 1. After the charging process, the capacitor discharges to the load with the load current
Id. Therefore, the capacitor current can be written as:
37
I peak sin( ωosc t −θ0), 0 < t < DT S iC1 t)( = ， (3.1) − Id , DT S < t < TS where D is the duty ratio of S 1 and S 2, and T S is the switching cycle. Ipeak and ωosc are the amplitude and angular frequency of the sinusoidal part of the charging current, respectively. The relationship between ωosc and angular switching frequency ωsw is:
π +θ ω = 0 ω . (3.2) osc 2πD sw
Assuming that during the dead time the free-wheeling load current is evenly distributed into two branches, then the initial value of the capacitor charging current I 0 is
1 I = i )0( = − I ， (3.3) 0 c1 2 d and θ0 can be found from the following relationship:
I d = I × sin θ . (3.4) 2 peak 0
On the other hand, due to the current balance of the capacitor in one switching cycle:
π DT S ∫ I( peak sin θ )dθ = Id 1( − D)TS . (3.5) π +θ0 −θ0
Solving (3.5),
38
1+ cos θ 0 D = (2 π +θ 0 )( ). (3.6) sin θ 0 1− D
Equation (3.6) gives the relationship between θ0 and the duty ratio D. For the dc-dc
voltage doubler, since D=0.5, θ0 can be calculated to be 0.29 or 16.6º.
From (3.4), the peak value of the capacitor charging current Ipeak can be calculated
as:
Id I peak = = 75.1 Id . (3.7) 2 × sin( θ0 )
The capacitor charging time T ch can be calculated using (3.8),
π +θ T = 0 T , (3.8) ch 2π osc
where Tosc is the oscillation cycle of the charging current.
The soft-switching frequency fsw can be calculated:
2πD fsw = . (3.9) (π +θ0)Tosc
For the switched-capacitor voltage doubler, D is 0.5, thus:
π fsw = . (3.10) (π +θ0)Tosc
C. The power loss analysis on the proposed voltage doubler
The switching losses on switch S 1, S 2, S 4 and S 5 of the proposed voltage doubler can
39 be neglected due to their soft-switching operation. The switching loss analysis on the other two switches (S 3 and S 6) is similar to the analysis in traditional boost converters, which is not elaborated here.
There are three types of conduction losses: the conduction loss on the switches, on two main capacitors, and on the input capacitor. The conduction loss can be calculated from the RMS value of their corresponding current.
1) The RMS current of switches.
Figure 3.9 shows the current profiles of the three switches in the left cell (S 1, S 2 and
S3). S 1 and S 2 only conduct in the first half cycle and S 3 only conducts in the second half cycle. S 1 carries the capacitor charging current so it shares the same current as the charging current of C 1. The third-quadrant-operated switched S 2 carries the capacitor charging current as well as the load current. The switch S 3 carries only the load current during the second half cycle. The three current can be written as:
40
(2 π +θ0 ) 75.1 I d sin[ t −θ0 ], 0 < t < TS 2/ I S1 = TS . (3.11) ,0 TS 2/ < t < TS
(2 π + θ0 ) 75.1 I d sin[ t − θ0 ] + Id , 0 < t < TS 2/ I S 2 = TS . (3.12) ,0 TS 2/ < t < TS
,0 0 < t < TS 2/ IS3 = . (3.13) − Id , TS 2/ < t < TS
The RMS value of the three current can be calculated as:
1 T 2/ (2 π +θ ) 2 I = 75.1( I sin( 0 t −θ )) dt = .0 833 I . (3.14) S1_ RMS ∫0 d 0 d T TS
1 T 2/ (2 π +θ ) I = 75.1( I sin( 0 t −θ ) + I )2dt = .1 447 I . (3.15) S2_ RMS ∫0 d 0 d d T TS
1 T / 2 I = I 2dt = .0 707 I . (3.16) S3 _ RMS T ∫0 d d
Due to the symmetric structure of this doubler, the three switches in the right cell have the same current profile and RMS values as the corresponding switches in the left cell.
41
Figure 3.9. The current profiles for the switches in the left cell.
2) The RMS current of the two main capacitors.
The two main capacitors experience the same current, as the current shown in Figure
3.8 when D is 0.5. The RMS value of the current on the two capacitors can be calculated as:
1 T 2/ (2 π +θ ) 1 I = 75.1( I sin( 0 t −θ )) 2 dt + I 2 = .1 093 I . (3.17) C1_ RMS ∫0 d 0 d d T TS 2
3) The RMS current of the input capacitor.
The input current is the sum of I S2 and I S4 . It has an average value of 2I d and an ac ripple. The ac part of the input current flows into the input capacitor and generates loss.
42
The RMS value of the input current ripple is:
1 π I = 1( .75 I sin θ + I − 2I )2 dθ = .0 387 I . (3.18) Cin _ RMS ∫−θ d d d d π + θ0 0
Table 3.1 provides the RMS current and the conduction loss of different components in the proposed voltage doubler. R S, R C and R C_in represent the on-resistance of the switch, the ESR of the main capacitors and the ESR of the input capacitor, respectively.
Table 3.1. The RMS current and conduction loss of different components in the proposed voltage doubler.
Compone Current Conduction
nts RMS value loss
S , S .0 833 I 2 1 5 d .0 694 I d RS
S ,S .1 477 I 2 2 4 d .2 181 I d RS
I 2 S3,S 6 .0 707 d 5.0 Id RS
2 C1,C 2 .1 093 I d .1 195 I d RC
.0 387 I 2 Cin d .0 150 Id RC _in
Table 3.2 provides a comparison between the proposed voltage doubler and the traditional switched-capacitor voltage doubler with soft-switching capability. Ploss_S,
Ploss_C, and Ploss_Cin represent the total conduction loss on all of the switches, on the
43
two main capacitors, and on the input capacitor, respectively. The proposed switched-
capacitor has a much smaller input current ripple and conduction loss compared to the
traditional voltage doubler. This is because in the proposed topology, the voltage source
is always connected in series with one capacitor. Therefore, half of the power is directly
sent to the load.
Table 3.2. A loss comparison between the proposed voltage doubler and traditional voltage doubler with soft-switching capability
Conduction Proposed Traditional
loss doubler doubler
2 2 Ploss_S 75.6 Id RS 87.9 I d RS
2 2 Ploss_C 39.2 I d RC 38.3 I d RC
2 2 Ploss_Cin .0 150 I d RC _ in .0 934 Id RC _in
3.3. Full-Cell and Half-Cell Based Dc-ac Inverters
A. Full-Cell Based Inverters
From the analysis in Section II, for an N-stage full switched-capacitor cell based
converter, there are 2N+1 achievable voltage levels between port 2 of the first stage and
port 4 of the last stage. As a result, to realize a 2N+1 level of inverter, only N full-cells
are required.
Figure 3.10 shows one five-level dc-ac inverter consists of one full-cell and four extra
44
switches S 5-S8. The extra switches are always connected to the load and function as
current bypass routes. By adding these four switches, the total achievable voltage levels
can be increased by 2. Therefore, only N-1 full-cells are required to have a 2N+1 inverter.
In Figure 3.10, one full cell is enough to realize a five-level inverter. It should be noted
here that this inverter has a good switching redundancy, which can help to balance the
capacitor voltage and improve the fault tolerance capability of the circuit.
Figure 3.10. A five-level full-cell switched-capacitor inverter.
B. Half-Cell Based Inverters
Due to the high switching component requirements for the full-cell based inverter,
half-cell based inverters can be the alternative choice. To realize a 2N+1 level inverter,
2N half-cells are required. If four extra bypass switches are employed, 2N-2 half-cells are
45
required to have a 2N+1 level inverter. The number of stages required for a half-cell
based inverter is two times the requirement for a full-cell based inverter. The capacitor
count is doubled and more current stress is added to central cells.
A half-cell based five-level inverter is shown in Figure 3.11. This topology was
introduced in [23]. It consists of two half-cells and four extra bypass switches S 7-S10 .
C. The multi-carrier PWM control method for a five-level switched-capacitor inverter
The design of a high power switched-capacitor dc-ac inverter is more complex than
the dc-dc multiplier. The main reason is that the duty ratio of the inverter changes from
cycle to cycle, so is the capacitor charging time. Therefore, the charging current cannot
be well controlled. Two methods are proposed to solve this problem: a multi-carrier
PWM control method and a soft-switching scheme using variable frequency control.
Figure 3.11. A five-level half-cell switched-capacitor inverter.
46
The multi-carrier PWM control scheme is used to eliminate unnecessary capacitor charging. The half-cell based five-level inverter, as shown in Figure 3.11, is used to illustrate this method. Based on the capacitor charging characteristics, the voltage modulation waveform for this inverter can be divided into six sections, as shown in
Figure 3.12. The angle θ1 in Figure 3.12 can be calculated by using the modulation index ma:
1- 1 θ1 = sin ( ). (3.19) 2ma
In order to minimize the capacitor charging loss, the capacitor charging and discharging only occur in sections II and V, where positive or negative 2Vin are needed.
In other sections where the inverter only output ±Vin or zero voltage, the capacitors are in the idle state and there is no charging activity. The source is directly connected to the load to output Vin or –Vin, and it is bypassed when zero voltage is needed. In these regions, the inverter functions as a normal H-bridge inverter.
47
Figure 3.12. Six sections for a five-level switched-capacitor inverter.
D. The soft-switching scheme for switched-capacitor inverters.
To realize soft-switching at Section II and V, a variable frequency control scheme is
proposed. In this scheme, the switching frequency changes with the duty ratio to
maintain a constant capacitor charging time. Therefore, soft-switching can be realized for
all cycles.
The relationship between the charging time and the instantaneous duty ratio is:
1 Tch (t) = 1( − D(t)) . (3.20) fsw (t)
Note here the instantaneous duty ratio D(t) is defined as:
48
2ma sin( ωt) − ,1 θ1 < ωt < π −θ1 D(t) = . (3.21) − 2ma sin( ωt) − ,1 π +θ1 < ωt < 2π −θ1
The switching frequency can be calculated from (3.8) and (3.26):
1( − D(t)) × 2π 1 fsw (t) = × ， (3.22) π +θ0 (t) Tosc
Equation (3.28) provides a relationship between D(t) and the switching frequency.
Since θ0 only depends on D(t), a look-up table of θ0 can be made for different duty ratios to expedite the calculation of the switching frequency in real applications.
It should be noted that the switching frequency should have a low limit. Otherwise the capacitor will be over-discharged. The capacitor voltage variation in one switching cycle is:
1 1 1 π +θ0 (t) 1 ∆VC = Id (t)D t)( = Id (t)Tosc ( − ).1 (3.23) C fsw t)( C 2π 1− D t)(
It can be seen from (3.29) that the capacitor voltage ripple increases with the load current I d(t) as well as D(t). The worst scenario is at unity power factor, in which the load current I d(t) and D(t) reach their peak value simultaneously. From (3.27),
Dmax (t) = 2ma − .1 Then the peak capacitor voltage ripple is:
1 π +θ0 t)( 2ma −1 ∆VC _ max = Id _ peak Tosc ( ). (3.24) C 2π 2− 2ma
The initial angle θ0 can be neglected at large duty ratio conditions, due to the fact that
49
θ0 becomes negligible when the peak current is large, then ∆VC _ max can be estimated as:
1 2ma −1 ∆VC _ max ≈ Id _ peak Tosc ( ). (3.25) 2C 2 − 2ma
The peak capacitor charging current can be calculated:
1( − D t))( π ∫ Ich _ peak sin( θ)dθ = D(t) Id t).( (3.26) π −θ0
Solve (3.32),
1 π Ich _ peak = ( − )1 I d (t .) (3.27) 2 − 2ma sin( θ ) 1( + cos( θ0 ))
Under the condition where the power factor is large, the peak current occurs near the peak voltage point, and cos( θ0) ≈1, then:
π 1 Ich _ peak ≈ ( − )1 Id _ peak . (3.28) 2 2 − 2ma
Equation (3.34) gives the estimated maximum capacitor charging current of the proposed method. It can be seen that both the modulation index and the load current affect the maximum charging current.
The third quadrant operated switches (S 1 and S 4 in Figure 3.11), which carry both the capacitor charging current and load current, experience the highest current stress:
π π I ≈ ( − + )1 I . S1 _ peak d _ peak (3.29) 4 − 4ma 2
Given the peak load current and maximum safety current of the switching devices, the 50
maximum modulation index can be calculated from (3.35).
E. Simulation results
A simulation on a 20 kVA switched-capacitor inverter has been performed using
PSIM to verify the control method proposed in this paper. In this simulation, the dc input
of this inverter is 300 V and the modulation index is 0.8. The load is a constant RL load
with a resistance of 2 Ω and an inductance of 3.5 mH. The power factor of this converter
is 0.83. To realize soft-switching at around 20 kHz, the loop inductance is selected to be
200 nH and the capacitance of the capacitor is 300 µF.
Figure 3.13 shows the output voltage, output current, the current of S 2 and the
switching frequency. It can be seen that, the switching frequency is kept constant at 20
kHz in section I, III, IV and VI. In section II and V, where capacitor charging occurs, the
switching frequency varies from 15 kHz to 25 kHz. The peak current of S 2 is about 426A
while the peak load current is 197 A. This ratio of peak charging current over peak load
current is 2.16, which is consistent with the estimated value of 2.36 from (3.34).
Figure 3.14 shows the frequency spectrum of the output voltage. Because of the
variable frequency control, there is a band of frequency components between 15 kHz and
25 kHz.
51
Figure 3.13. The simulation results of the inverter.
Figure 3.14. The frequency spectrum of the output voltage.
52
3.4 Experimental Results
A group of 1 kW half-cell prototypes have been built to verify the ideas presented in
this paper. The photograph of this cell is shown in Figure 3.15. Three MOSFETs
(IRFI4410ZPbF) are placed in parallel to form one switching device. To reduce the
reverse recovery loss of the body diode, a power Schottky diode (STPS30100ST) is used.
Ten 100 V, 4.7 µF ceramic capacitors (C5750X7R2A475K) are used together as the main
capacitor. The soft-switching frequency of a voltage doubler is measured at an input
voltage of 5 V and room temperature. When the switching frequency is adjusted to 62.7
kHz, the zero-current turn-off is achieved. With the assumption that the capacitance of
the capacitor under this test condition is 47 µF, the total loop stray inductance can be
calculated as 117.6 nH.
A. DC-DC multiplier test
A half-cell dc-dc voltage doubler, which consists of two prototype boards, is used to
verify the soft-switching scheme and the efficiency. The circuit topology is shown in
Figure 3.4. The dead time is set to be 200 nS. A small 10 µF film capacitor is added to
the output terminal to filter out the ripples during the dead time. At an input voltage of 40
V, the zero-current turn-off is achieved for S 1 and S 5 at a switching frequency of 75.9
kHz. Compared to the case when the input voltage is 5V, the soft-switching frequency is
increased, which is because the capacitance of the ceramic capacitors decreases with the
increase of voltage. 53
Figure 3.15. The photograph of the prototype cell.
Figure 3.16. The input and output voltage waveform of the voltage doubler. 54
Figure 3.16 shows the input and output voltage together at a load current of 10 A.
Figure 3.17 shows with the drain-source voltage (V s1 ) and the drain current (I S1 ) of S 1. It can be seen that I S1 drops to zero before the switching transient so the zero-current turn- off is realized. The peak value of I S1 is 17.2 A, which is consistent with (3.7).
Figure 3.17. The current and turn-off voltage of S1. Figure 3.18 shows the efficiency of the prototype from 200 W to 2000 W with 40 V fixed input voltage. It is measured with a Yokogawa WT3000 power meter and LEM IT
700-S high performance current transducer.
55
Figure 3.18. The efficiency curve of the proposed dc-dc multiplier. Figure 3.19 shows the calculated power loss breakdown among different components at an input power of 1000 W. The calculation on conduction losses is based on Table I.
Since the converter is built on a PCB with 2 Oz/ft 2 and a trace width of 300~500 mils, the loss on PCB traces contributes to a large portion (around 30% - 40%) of the total loss.
Therefore, in this power loss breakdown, the resistances of the capacitor and switches are estimated together with the ac resistance (at 70 kHz) of the PCB traces they are connected to. The switches have an average resistance of 8 m Ω. The resistance of the main capacitors and the input capacitor is estimated to be 3.4 m Ω and 10 m Ω, respectively. The switching power loss of the two diagonal switches S 3 and S 6 is estimated using the turn-on time and turn-off time of the MOSFETs from the datasheet.
56
The diode loss is the conduction loss of the four Schottky diodes during the deadtime.
Other losses include the conduction losses on the connection cables, the reverse recovery loss of the diodes, the loss due to charging the body capacitance of the MOSFETs during operation, and estimation error.
Figure 3.19. The breakdown of power loss at an input power of 1000W. The control power contributes to around 25% of the total loss. The conduction loss of the switches and capacitors consists of more than 45% of the total loss. The switching loss is only 12% of the total loss, which proves the effectiveness of the soft-switching method.
57
B. DC-AC inverter test
A five level dc-ac inverter is built and tested using the switching-cell prototypes. The
circuit structure is shown in Figure 3.11. It is realized by four switched-capacitor
prototype boards. The modulation index is set to be 0.8. An adjustable RL load with a
constant power factor of 0.83 is used. In the experiment, the switching frequency changes
from 48.6 kHz to 83.3 kHz to realize the soft-switching for all capacitor charging cycles.
Figure 3.20 shows the waveforms of input voltage V in , output voltage V out at a load
condition of 17.4 mH and 9.4 Ω. The active power at this load condition is 272 W. The
RMS value of the fundamental output voltage and current is 58.74 V and 5.38 A,
respectively. The RMS value of the total output voltage is 62.00 V. According to IEEE
Standard 519 [32], in which the total harmonics distortion (THD) is calculated up to 40th
order, the voltage THD is 4.98%. The main reason for the harmonics is the large stray
inductance of the current paths when the inverter functions as an H-bridge inverter. This
occurs because four identical prototype boards are connected using external cables in this
experiment, and unnecessary large inductance is present even if the capacitor charging is
not required. An integrated inverter design can help to optimize the stray inductance
distribution and solve this problem.
Figure 3.21 shows the waveforms of load current I d and the charging current of
capacitor C 1. The peak value of I C1 is 21.0 A, while the peak value of I d is 9.0 A. The ratio
between the two peak values is 2.33, which is consistent with the estimation result. 58
Figure 3.20. The input and output voltage waveforms of the inverter.
Figure 3.21. The waveforms of the output current Id and the charging current I C1 . 59
Figure 3.22 shows the zoomed-in view of the capacitor charging current of C 1. It can be seen that the zero-current switching is realized for all cycles.
Figure 3.22. The zoomed-in capacitor charging current of the inverter. Figure 3.23 shows the efficiency curve of the proposed dc-ac inverter with an input power from 100 W to 1000 W. The efficiency value is about 3% lower than the efficiency of the voltage doubler. The main reason is that four extra switching devices are involved in the inverter topology, which introduce more conduction loss and control power loss. Also, the peak value of the charging current of the inverter is higher than that of the voltage doubler, which generates higher conduction loss.
60
Figure 3.23. The efficiency curve of the proposed dc-ac inverter.
3.5 Conclusion
In this chapter, two types of switched-capacitor cells are introduced—the half-cell and the full-cell. Both the dc-dc multipliers and the dc-ac inverters based on these cells are analyzed. For the dc-dc multiplier, a rotational charging scheme is proposed so the large output capacitor required by traditional switched-capacitor topologies can be eliminated.
For the dc-ac inversion, a multi-level inverter with voltage boost function can be realized by using either the full-cell or the half-cell. To increase the efficiency, a soft-switching scheme without adding extra components is adopted and a variable frequency control for the inverter is proposed. The proposed topologies and control methods can be used in applications with a power range from sub-kilowatts to tens of kilowatts.
61
Chapter 4 A Switched-capacitor Voltage Tripler with
Automatic Interleaving Capability
For many large power applications, such as the front dc-dc converter in hybrid electric vehicles (HEVs), a large voltage conversion ratio is not needed and usually a voltage conversion ratio of three or four is sufficient. Moreover, for this dc-dc converter, efficiency, cost, and volume are more important than the accuracy of the output voltage regulation. Based on these observations, this chapter presents a high efficiency switched- capacitor voltage tripler that employs soft-switching and current/voltage interleaving. The interleaving operation is automatically achieved without adding extra components. This paper introduces three different voltage triplers based on the proposed topology.
4.1 Methods to Minimize the Power Loss in a Switched-capacitor Dc-dc Converter
There are four types of power losses in a switched-capacitor converter: the capacitor charging loss, conduction loss, switching loss and control circuit loss [33]. Since the capacitor charging loss and the control loss mainly depend on the capacitance of the capacitors or the switching frequency, only the other two types of losses, the switching loss and conduction loss, will be analyzed here.
62
A. Minimizing the switching loss — soft-switching
A simple circuit to analyze the charging current of a switched-capacitor converter is
the series RLC circuit shown in Figure 4.1(a). In this circuit, the switch S is closed at t=0.
The voltage source ∆V represents the voltage difference between the voltage sources and
the capacitor being charged. The stray inductance and resistance of this current charging
loop are lumped together as L S and R S. For this RLC circuit, the charging current i ch (t)
can be expressed using the differential equation (4.1):
2 d (ich t))( di ch (t) 2 + 2α + ω0 ich (t) = 0 (4.1) dt 2 dt
where α = Rs 2/ Ls , the angular oscillation frequency ω0 = /1 LsC , and the damping
factor is calculated as:
α R C ς = = s . (4.2) ω0 2 Ls
The damping factor determines the shape of the charging current. Figure 4.1(b) shows
the shape of the charging current at three different damping factors in one switching cycle
of a switched-capacitor converter. The switching frequency of this converter is 20 kHz. It
can be seen in Figure 4.1(b) that with a damping factor of 10, the charging current has
only a small oscillation and can be regarded as a square waveform. While with a damping
factor of 0.1, the shape of the charging current is almost sinusoidal. In this case, if the
charging time is adjusted to be close to half the oscillation cycle of the series RLC circuit,
63 the turn off transient of the switch S occurs at nearly zero charging current condition. As a result, zero-current-switching can be achieved.
For converters with large current ratings, it is required that both capacitors have low
ESR and the switches have low on-resistance to guarantee the high efficiency. The large physical size of the converter may also result in a large stray inductance of the charging loop. In this case, the loop resistance may not dominate in the charging current equation and the damping factor can be much smaller than 1, which will result in a sinusoidal charging current shape. The smaller the damping factor, the more sinusoidal the charging current shapes. For the purpose of simplicity, the following analysis assumes that the damping factor is much smaller than one and the charging current has a pure sinusoidal shape.
To realize this soft-switching scheme, it is important for the charging loop to have sufficient stray inductance so that the oscillation frequency is small enough to be achieved by available semiconductor devices. The adoption of devices with higher switching frequency will significantly reduce the requirement of both capacitance and stray inductance. Therefore, this soft-switching scheme can be easily realized by wide band-gap switching devices, which have high switching capabilities. With the assumption that the capacitance and stray inductance are reduced by the same proportion, and the loop resistance remains constant, the damping factor will not be affected.
64
Figure 4.1. The equivalent circuit of the charging loop and shapes of the charging current.
(a) The RLC equivalent circuit for the charging loop. (b) The shapes of the charging current under different damping factors. By implementing the soft-switching scheme, the switching power loss can be minimized, the large in-rush charging current can be avoided and high efficiency can be achieved. The sinusoidal current shape is also a prerequisite for other control methods, such as the interleaving method, to improve the efficiency. 65
B. Minimizing the conduction loss — reducing the intermediate stages
If soft-switching is achieved, the converter losses mainly come from the conduction
loss of the switching devices and the capacitors. There are mainly three types of
capacitors in a switched-capacitor converter: input capacitors, output capacitors and the
intermediate capacitors. The input capacitors and output capacitors are connected to the
input voltage source and the load, respectively. They are required in a dc-dc circuit to
filter out the input and output voltage ripple. The intermediate capacitors are added to aid
in the energy transfer from the input capacitors to the output capacitors.
The most effective way to reduce the conduction loss is to reduce the number of
intermediate capacitor stages from the source to the load. A type of “direct charging”
topology can be developed based on this principle. A 3X “direct charging” converter is
shown in Figure 4.2. In this converter, there are no intermediate capacitors. There is only
one input capacitor and the output capacitor consists of three capacitors in series. The dc
source charges each output capacitor in turn. Although the intermediate stages are
eliminated in this converter, there are several flaws that hinder it from being used in high
power applications. First, the voltage stress on each switch is large. In this 3X converter
case, each switch either needs to block a voltage that is two times the input voltage or
needs to block both positive and negative voltages with a value equal to the input voltage.
This will dramatically increase the cost, conduction losses and the difficulty of realizing
soft-switching. Second, this topology is based on a time-sharing charging principle so the 66
charging time allowed for each capacitor is 1/3 of a switching cycle. This will increase
the peak charging current and reduce the efficiency. Furthermore, the input current ripple
is large and a huge input capacitor bank is required, which also increases the cost and
reduces the efficiency.
Figure 4.2. A 3X ‘direct charging’ switched-capacitor dc-dc converter. Due to the mentioned direct charging topology problems, the next best candidate
should be a topology with only one intermediate stage, which is the case of the proposed
converter.
C. Minimizing the conduction loss — a 50% duty ratio for the charging and discharging currents
For a converter with one or more intermediate capacitor stages, the conduction loss is 67 determined by the shape of the charging and discharging currents. It is desired for the intermediate capacitors to continuously work at either charging or discharging state, i.e. there is no ‘idle’ state. In this way, time is fully utilized and the peak charging current is smaller.
In one switching cycle, the intermediate capacitors need to be first charged and then discharged. The capacitor charging and discharging current during a switching cycle T of two different cases is shown in Figure 4.3. The load current is assumed to be I D in both cases so the amount of electric charges that needs to be delivered to the load in one switching cycle is T× I D. The solid curve I 1, represents a sinusoidal capacitor current with a duty ratio of 1/3 for the charging part. In the last 2/3’s of the cycle, the capacitor is discharging. The current I 2, represented by the dashed curve, is also sinusoidal, but with
0.5 duty ratio for the charging part.
68
Figure 4.3. The capacitor currents of two cases with different duty ratios in one switching cycle.
The peaks of the charging part of the current I 1 can be calculated using (4.3):
2π
3 I ×sin( θ)dθ = I ×2π. (4.3) ∫ 0 1_ peak _ ch D
Solving this equation, the peak of the charging part of I 1 is 3π 2/ × ID . Similarly, the peak of the discharging part of I 1 is 2π 3/ × ID . The peak of both the charging and discharging part of I 2 can be calculated to be π×ID.
Assuming R S is the equivalent loop resistance, the conduction power loss of I 1 and I 2 can be calculated as in (4.4)-(4.8):
69
2π 1 3π 3π 2 P = 3 ( I ×sin( θ )) 2R dθ = I 2 R . (4.4) loss 1_ ch 2π ∫ 0 2 D S 8 D S
2 1 2 π 2π 2 π 2 P = 2π ( I × sin( θ )) R dθ = I R . loss 1_ dis ∫ D S D S (4.5) 2π 3 3 6
13 P = P + P = I 2 R . (4.6) loss 1 loss 1_ ch loss 1_ dis 24 D S
1 π π 2 P = 2× (πI ×sin( θ )) 2R dθ = I 2 R . (4.7) loss 2 2π ∫ 0 D S 2 D S
Ploss 1 = 108 3. %. (4.8) Ploss 2
From the power loss comparison, it can be seen that a larger conduction power loss will be generated for the 1/3 duty ratio of the charging current compared to the 1/2 duty ratio.
The relationship between the duty ratio d and the power loss on the intermediate capacitor can be expressed in a form of:
1 π 2 P = 2( d + ) I 2 R , (4.9) loss _ c 2d 4 D S where d is the duty ratio of the charging current.
The optimized d, which minimizes the conduction loss, is 0.5. For most switched- capacitor topologies, the currents that go through the switches will be the same as either the charging or discharging currents of the intermediate capacitors. Therefore, the loss on
70
the intermediate capacitors can represent the conduction loss of the switches in a
switched-capacitor circuit. As a result, the conduction loss on the switches can also be
minimized using 0.5 duty ratio charging current.
Another benefit of using the 50% duty ratio charging current is that the charging and
discharging time of the capacitor is the same. Therefore, one single switching frequency
can be adopted to realize soft-switching on both the switches used to charge and those
used to discharge the intermediate capacitors. This results in an easier circuit realization.
D. Losses on the input capacitor — the interleaving operation
The aforementioned loss analysis only considers the losses on the switches and
intermediate capacitors. However, the large power loss occurring on the input capacitor
should also be addressed. In fact, due to the sinusoidal charging/discharging current
shape, the input capacitor suffers from large ac ripples. This requires a huge input
capacitor to filter out the noise, but still any remaining noise may affect the lifespan of
the power source.
An effective way to solve the large input current problem is to use the interleaving
structure [37]. The output capacitance can also be largely reduced by employing this
interleaving scheme. The traditional interleaving concept uses several identical switched-
capacitor converter modules in parallel with a constant phase shift between the modules.
The main problem of this scheme is the large number of components that needs to be
added. Although the current rating of each single device can be reduced using the 71
interleaving structure, the voltage of each component remains the same, which can cause
an increase in the cost and volume. A more serious problem is that by adding more
components to the converter, the chance of component failure increases.
In order to eliminate the large input capacitor, increase the efficiency, and at the same
time maintain low cost and high reliability, a topology that can realize the interleaving
without adding extra components is needed.
4.2 The Proposed Voltage Tripler with Interleaving Capability
A. Structure
As discussed above, to achieve high efficiency, a desirable switched-capacitor
topology should have the following features: ease of soft-switching realization, minimum
intermediate capacitor stages, a 50% charging current duty ratio, and have interleaving
capability.
A 3X converter or voltage tripler based on this concept is shown in Figure 4.4. In this
converter, three stages with an identical structure, including two capacitors and four
switches, are used. The output voltage is derived from the three stages stacked together.
The structure of one single stage was first introduced in [35], with the purpose of
separating the ground of the input and output voltages. This paper adopted this idea so
that the input source can be isolated from the output capacitors and interleaving can be
achieved without shorting two different voltage potentials.
72
For each stage, a two-step charging scheme is used. All the switches within one step are switched together while the switches in different steps work in complimentary mode.
Take the top stage for example; S1 and S 2 are switched on in the first step while S 3 and S 4 are switched on in the second step. Assume the turn-on duty ratio of the first step and second step are D 1 and D 2 respectively. Ideally, D 1 and D 2 should be both 0.5 and thus the conduction loss can be minimized. The switching frequency is adjusted so that soft- switching can be achieved on both steps. In reality, since a deadtime has to be added in the switching cycle, D 1 and D 2 cannot reach 0.5 simultaneously. To minimize the conduction loss, D 1 should equal D 2.
In the first step, the voltage source charges the intermediate capacitor C 1 through S 1 and S 2. At the same time the output capacitor C 4 discharges to the load with a load current of I D. If a 120 degree phase shift is applied among the three stages, input current interleaving can be achieved with maximum effect. The charging current of the first stage and the total input current under this interleaving operation are shown in the top and middle plot in Figure 4.5 (a), respectively. The three dotted waveforms in the middle plot are the charging currents of each stage while the solid waveform is the total input current.
In the second step, C 1 charges C 4 through S 3 and S 4 with a charging current of I C4 . At the same time, C 1 provides the load current I D to the load, so the total current goes through S 3 and S 4 equals to the sum of I D and I C4 . To achieve zero-current-switching of
S3 and S 4, the charging current needs to have a sinusoidal shape but with an angle 73 spanning more than half of a cycle. The current waveforms of the switch S 1 and the output capacitor C 4 are shown in the bottom plot of Figure 4.5(b). With a 120° phase shift between each two stages, the output voltage ripple can also be largely reduced.
Figure 4.4. The structure of the 3X converter.
74
(a)
(b)
Figure 4.5(a).The two switching steps of the top stage. (b) The current waveforms of the top stage. 75
Figure 4.6. One state showing a path with two off-state switches.
B. Component stress analysis
All the capacitors in the proposed converter need to sustain a voltage equal to the input
voltage V in , which is one third of the output voltage.
Figure 4.6 is used to help determine the voltage rating of the switches. Due to the
complimentary operation of the two steps, at any time instance, there will be two
switches in the on state and other two in the off state within in one stage. For example,
Figure 4.6 shows that in the top stage, S 1 and S 2 are turned on while S 3 and S 4 are turned
off. Figure 4.6 also shows the case that along the dotted path, S 3 and S 9 are in the off
state and they need to block a voltage difference of 2V in . As a result, each of these two
76 switches needs to sustain a voltage stress of V in . Similar analysis can be applied to other switches and the result shows that all the eight switches in the top and bottom stages have a voltage stress of Vin . If the switches with a voltage rating of V in are used in the top and bottom stages, then the switches in the middle stage can theoretically have zero voltage rating since the voltage difference between the middle stage and other stages is only one times V in , which can be fully blocked by the switches in the top or bottom stages.
The fact that the switches in the middle stage can have zero voltage stress leads to two other voltage tripler structures with reduced component counts. One has only two switches and no capacitor in the middle stage, as shown in Figure 4.7(a). In this structure, the input current interleaving can still be achieved with small degradation compared to the voltage tripler proposed in Figure 4.4. The output voltage interleaving will not be available since the middle stage output capacitor is not having a 120 degree shifted with the other two output capacitors.
Another topology is shown in Figure 4.7(b). There are no components in the middle stage for this structure, and the voltage source is directly connected to the output capacitor in the middle stage. Although no interleaving can be achieved, the input current ripple can still be reduced since one third of the energy is directly sent from the source to the load. Compared to the multilevel modular capacitor-clamped dc–dc converter
(MMCCC) circuit, the input current ripple is reduced by 1/3 and the size of the input capacitor can be reduced by more than one half. 77
(a)
(b) Figure 4.7. The other two 3X topologies.
(a) The 3X converter with only two switches in the middle stage. (b) The 3X converter with no component in the middle stage.
78
4.3 The Functional Analysis of a Practical Converter with Proposed Structure
The waveforms shown in Figure 4.5 (b) are obtained under ideal conditions where the
duty ratios of the first and second steps have the same value of 0.5. However, because of
the structural difference between the first and second step, in order to achieve the 0.5
duty ratio, the required capacitance of the output capacitors needs to be larger than that of
the intermediate capacitors, which can increase the total cost of the converter. On the
other hand, if output capacitors with the same capacitance as the intermediate capacitors
are used, the interleaving function will still be available with only small degradations. In
this section, a practical converter with identical capacitance, which is assumed to be C,
for all the capacitors, will be analyzed.
A. The soft-switching analysis
There are two structural differences between the two charging steps. The first
difference is that during the first step, only the intermediate capacitor resonates with the
stray inductance of the charging loop. While during the second step, both the
intermediate and the output capacitor are in the charging loop. Therefore, the equivalent
capacitance of the second step will be a result of two capacitors connected in series,
which generates a larger oscillation frequency than the first step. The second difference is
that during the second charging step, the intermediate capacitor has to provide both the
charging current for the output capacitor and the load current I D. As a result, if the current
needs to be zero before the switches are turned off, the angle span of the charging current 79 has to be larger than 180° to offset the extra load current.
Figure 4.8 is used to determine the exact duty ratio of the two steps. In this analysis, the stray inductances in the charging loop of the first and second steps are assumed to be the same. In Figure 4.8(a), if S 3 and S 4 are turned on, the following relationship can be established:
di S3(t) VC1(t) −VC4 (t) = L dt dV (t) i (t) = −C C 4 C4 dt . (4.10) dV C1(t) iS1(t) = C dt iS3(t) = iC4 (t) + ID
Get the derivative of the first equation in (4.10):
d(V (t) −V (t)) d 2i (t) C1 C 4 = L S3 . ( 4.11) dt dt 2
Then the middle two equations of (4.10) are substituted into (4.11), and the following equation is derived:
i (t) + i (t) d 2i (t) C 4 S3 = L S3 . (4.12) C dt 2
By assuming that the load current changes much slower than the switching frequency, we have:
80
d 2i (t) d 2i (t) S3 = C4 . (4.13) dt dt
So (4.12) can be rewritten as:
2 1 d (iS3(t) + iC4(t)) iS3(t) + iC4 t)( = CL ( ). (4.14) 2 dt 2
The pattern of (4.14) shows that the sum of iS 3 (t) and iC 4 (t ) is a sinusoidal waveform
with an oscillation frequency ω2 = 2 / LC . If the amplitude is assumed to be 2A ,
iS3 t)( + iC4 t)( can be expressed as:
iS3 (t) + iC4 t)( = 2Asin( ω2t +ϕ). (4.15)
Then iS3 and iC4 can be calculated using (4.16) and (4.17):
iS3 = Asin( ω2t +ϕ) + ID .2/ (4.16)
iC4 = Asin( ω2t +ϕ) − ID .2/ (4.17)
Given the boundary conditions that the current at the beginning and end of the charging process are both zero:
− I Asin( ϕ) = D 2 , (4.18) − I Asin( ωT +ϕ) = D 2 2
where ϕ <0 and π 2/ < ωT2 +ϕ < π , T2 is the turn on time of the switches in the second step. Correspondingly, the turn on time of the switches in the first step should be
81
T1 = π LC .
To fulfill (4.18), ωT2 +ϕ = π −ϕ , let θ0 = −ϕ , so:
1 LC T = (π + 2θ ) = (π + 2θ ) . (4.19) 2 0 ω 0 2
Then the duty ratio of the two steps can be calculated:
D T 2π 1 = 1 = . (4.20) D2 T2 (π + 2θ0 )
Because the sum of D 1 and D 2 equals one,
2π (2 π + 2θ0 ) D1 = , D2 = . (4.21) 2π + (2 π + 2θ0 ) 2π + (2 π + 2θ0 )
To determine the value of θ0 , the conservation of electric charge is used:
D × 2π π +θ I 2 (Asin( θ −θ ) + D )dθ = 2πI . ∫ −θ 0 D (4.22) π + 2θ0 2
By solving this equation, A can be expressed as:
1 1 A = ( − )( π + 2θ0 )I D 2/ cos θ0. (4.23) D2 2
Substituting (4.23) into (4.18), and noticing that θ0 = −ϕ :
1 tg θ0 = . (4.24) ( 2 + )5.0 π +θ0
Solving this, θ0 = 20.9 °, A = .3 1275 I D . Substituting the result into (4.16) and (4.23), the
82 current of S 3 can be written as:
IS3 = .3 1275 ID sin( ωt − 20.9 °) + ID .2/ (4.25)
D 2π 1 = = .1 283 . (4.26) D2 (π + 2θ0 )
As a result, the charging duty ratio of the two steps is D1 = .0 562 , D2 = .0 438 . This will generate a slightly larger conduction power loss compared to the ideal case where both steps have the same duty ratio of 0.5. Using (4.9), the result shows an increase on the conduction loss of 0.6%, which is negligible. The peak values of the switch currents in the first and second step are .72 95 ID and .3 6275 ID , respectively. Adding a deadtime will not change the ratio between D 1 and D 2 but it will change their absolute values.
To reach the 0.5 duty ratio for both stages, the loop capacitance in the second step C X
2 needs to be π . As a result, the output capacitance needs to be CX = 2 C ≈ 8.0 C (π + 2θ0 )
Cout = 4C , which will significantly increase the cost. For this reason, the output capacitance remains the same as the intermediate capacitors in this analysis.
83
(a)
(b)
Figure 4.8. The charging current of the second step.
(a) The current flow in the second step. (b) The current waveforms of S 3 and C 4.
84
B. Input current interleaving analysis
Since the duty ratio of the charging current in the first step is 0.562, the interleaving
results will be affected. To analyze the interleaving results under this non-optimum
condition, the first-step charging currents of the top stage can be represented by (4.27):
θ .2 795 ID sin( ), 0 < θ < .1 124 π I1 = .1 124 . (4.27) ,0 .1 124 π < θ < 2π
If the converter is running without any interleaving operation and the three stages
operates with no phase shift, the input current ripple of the converter is three times the
ripples of the top stages. The RMS value of the input current ripple can be calculated
using (4.28):
3 1.124 π θ I = .2( 795 I sin − I )2dθ + .0 876 πI 2 = .1 314 I . (4.28) ripple _ rms 2π ∫ D 12.1 D D D 0
Assuming the ESR of the input capacitor to be RC _ in , the power loss on the input
capacitor can be calculated using (4.29):
2 2 Pripple _ rms = Iripple _ rms RC _ in = .1 727 I D RC _ in . (4.29)
If the proposed interleaving scheme is adopted, the first-step charging current, in each
of the three stages will still have the same amplitudes and shapes, but with 120° phase
shift in between. The resultant input current has a frequency three times the switching
frequency. The equations for the first interval ( 0 < θ < 3/2 π ) are:
85
θ + 60 o 60 ° .2 795 I sin( ) cos( ), 0 < θ < .0 457 π D .1 124 .1 124 Iin_ 1 = . (4.30) θ 2 .2 795 I sin( ), .0 457 π < θ < π D .1 124 3
The RMS value of the input current ripple and corresponding input capacitor power loss can be calculated from (4.30). The results of the case where the output capacitance equals the intermediate capacitance are shown in the first row of Table I. Here, the RMS value of the input current ripple and the input capacitor power loss are normalized to their value for the same converter without interleaving. It can be seen that the ripple is reduced to less than 1/5 of the original value and the power loss on the input capacitor is reduced to only 3.15% of the original value.
Table 4.1 also shows the interleaving results at different output capacitances. The output capacitance is normalized with respect to the capacitance of the intermediate capacitors. It can be seen that by increasing the output capacitance, the duty ratio of the first step can be reduced and the interleaving results can be improved. The loss on the input capacitor will be reduced to less than 1% of the original value if the output capacitance is three or four times the capacitance on the intermediate capacitors.
However, the cost will also increase and the benefits of the interleaving are limited.
86
Table 4.1. Normalized Input Current Ripple and Power Loss at Different Output Capacitances
Normalized output Duty ratio Relative input Relative power loss
capacitance of the first step current ripple (RMS on the input capacitor
value)
1 0.562 17.75% 3.15%
2 0.524 11.50% 1.32%
3 0.508 9.66% 0.93%
4 0.500 9.59% 0.92%
C. Output voltage interleaving analysis
When the output capacitors are at charging state, the charging current has a sinusoidal
shape with an angle span larger than half a cycle and a dc offset is equal to minus half the
load current. When they are discharging, their currents are the dc load current. The output
capacitor current waveform is shown in the bottom curve of Figure 4.8(b). The shape of
the capacitor current determines the voltage of each output capacitor. The current on the
output capacitor of the top stage can be expressed using (4.31):
− I , 0 ≤ θ < 2D π D 1 I = . C1 I D (4.31) Asin( B(θ − 2D1π ) − θ0 )I D − 2, D1π ≤ θ < 2π 2
In the case where the capacitance of the output capacitor equals the intermediate one
A=3.1275, B= ( π+2 θ0)/ (2 πD2) =1.258, θ0=9.20°=0.1606.
87
If the initial capacitor voltage at θ=0° is assumed to be V 0 and the angular switching frequency is ω, then the capacitor voltage equation can be written as (4.32):
I V − D θ, 0 ≤θ < 2D π 0 Cω 1 VC1 = , (4.32) I D A 1 V0 − 2D1π + []cos( B(θ − 2D1π ) −θ0 ) − cos θ0 − (θ − 2D1π ) 2, D1π ≤ θ < 2π Cω B 2
To get the maximum and minimum values, the derivative of the capacitor voltage during the second step is calculated:
dV I C1 = (Asin[ B(θ − 2D π ) −θ )] = D . (4.33) dθ 1 0 2
Solving (4.33), the two extremals can be derived: θ 1 = 2θ 0 / B + 2 D1π and
θ 2 = π / B + 2D1π .
The final maximum and minimum points can then be calculated:
I 2A π V = V − D 2D π − cos θ + . (4.34) max 0 Cω 1 B 0 2B
I θ V =V − D 2D π + 0 . (4.35) min 0 Cω 1 B
Then the voltage ripple of one output capacitor can be calculated:
I 2Acos θ − π 2/ + θ I ∆V = V −V = D 0 0 = D × .3 787 . (4.36) C max min Cω B Cω
The total output voltage is the sum of the three stage voltages. The resultant voltage will have a frequency three times that of the switching frequency. So it can be
88 represented using the three stage voltage at 0< θ<120°. The voltage can be expressed as
(4.37):
I D 2 θ1 A 3V0 − 5.2 θ + 2( D1 + )π − + []cos( B(θ −θ1) − .0 1606 ) − cos( θ0 ) 0, < θ < 2D1π 3/ Cω 3 2 B Vout = , (4.37) I (θ + θ ) A cos( B(θ − θ ) − .0 1606 ) 3V − D 2θ + 4D π − 1 2 + 1 2, D π 3/ < θ < 2π 3/ 0 1 1 Cω 2 B + cos( B(θ − θ 2 ) − .0 1606 ) − 2 cos( θ0 )
The two extremal points of the output voltage can thus be calculated as,
θ1 = 2( D1 + 3/2 − )2 π ,θ 2 = 2( D1 + 3/4 − )2 π , and then the voltage ripple of the output voltage is:
I ∆V = V −V = D × .0 425 . (4.38) Cout max min Cω
From (4.36) and (4.38) it can be seen that the interleaving operation can reduce the total output voltage ripple to around one ninth of the original value. This will effectively reduce the requirement of the output capacitance.
Figure 4.9 shows the simulation results for a 55 kW switched-capacitor voltage tripler with the proposed topology. In this simulation, the input voltage and the load current are
200 V and 100 A, respectively. The capacitance of each capacitor is assumed to be 100 uF and the switching frequency is set to 50 kHz. Under this switching frequency, the loop stray inductance needs to be at least 100 nH to achieve the adopted soft-switching scheme. With the development of SiC and GaN technologies, devices with higher switching speed and greater voltage blocking capability should become affordable in the near future. The increase of switching frequency will largely reduce the requirement on 89 the stray inductance of the charging loops.
Using (4.36), each individual capacitor has a peak to peak voltage ripple of 12.06 V.
However, the total output voltage ripple is fairly small, which is around 1.35 V peak to peak. Figure 4.9(a) shows the current interleaving results and Figure 4.9(b) shows the voltage interleaving results. The simulation results in Figure 4.9 verify the above calculations.
(a) (b) Figure 4.9. The simulation results of a 55 kW switched-capacitor voltage tripler.
(a) The input current (Iin) and the charging current of three stages (Iin1, Iin2 and Iin3). (b)The total output voltage (Vout) and the voltages on the three output capacitors.
90
D. A Comparison between the proposed circuit and the interleaving ZCS-
MMCCC circuit.
Table 4.2 shows the comparison between the interleaving zero-current-switching
MMCCC (ZCS-MMCCC)] and the proposed circuit. In this comparison, soft-switching
and interleaving are assumed to be realized in both topologies. The first and third row of
Table II shows the number of capacitors and switches required for each topology. It can
be seen that the numbers of both capacitors and switches are smaller in the proposed
topology compared to the interleaving ZCS-MMCCC topology.
The last two rows of Table II take both the component count and the component stress
into consideration. Here the ‘base capacitor’ and ‘base switch’ concepts are used to make
comparisons. One base capacitor is defined to have a voltage rating of V in and a
capacitance that satisfies the voltage drop requirements in one switching cycle. One base
switch is defined to have a voltage rating of V in and current rating of I D. It can be seen
that the proposed circuit employs far fewer capacitors than the interleaving ZCS-
MMCCC circuit. This is because the sizing of capacitors has a square relationship versus
their voltage stress. For example, to realize a capacitor with 3V in rating while keeping the
capacitance the same, a total of 9 capacitors with a rating of V in are needed. Since the
capacitors in the proposed topology are all rated at V in while the ZCS-MMCCC topology
employs capacitors with higher capacitor ratings, a smaller number of capacitors is
expected for the proposed topology. 91
On the other hand, the total number of switches for the proposed converter is larger
than that of the interleaving ZVS-MMCCC circuit. This is due to the fact that the current
in the interleaving ZCS-MMCCC is separated into three identical voltage triplers so the
current stress of each switch is 1/3 of its original value. However, due to the large number
of switches required by the interleaving ZCS-MMCCC circuit, the cost of the switches
may not be lower than the proposed circuit and the chance of switch failure is much
higher.
Table 4.2. A Comparison Between the Interleaving MMCCC and the Proposed Converter. Topology Interleaving ZCS- Proposed MMCCC converters No. of capacitors 9 6
Voltage rating of capacitors Vin ,2V in and 3V in Vin No. of switches 21 12 Voltage rating of switches Vin or 2V in Vin Current rating of each I /3 I capacitors and switches D D Total No . of base capacitors 14 6 Total No. of base switches 8 12
E. The influence of unequal stray inductances of the two steps.
The above analysis assumed that the stray inductances of the two steps are the same.
However, this may not always be the case in the practical design. The difference of stray
inductances affects the duty ratios of the two steps to achieve soft-switching. If the stray 92 inductances of the first-step and second-step are assumed to be L 1 and L 2, respectively, then the values of D 1 and D 2 are determined by the ratio of L 1 to L 2.
Table 4.3 shows the duty ratio of the two steps at different values of L 1/L 2. Table III is calculated under the assumption that the capacitance of the output capacitor equals the intermediate capacitor. It can be seen that if L 1/L 2 equals to 0.6, the duty ratio of both steps is close to 0.5 and the converter can have best interleaving results. This feature can be used in the practical converter design.
Table 4.3. The Optimal Duty Ratio at Different Stary Inductance Ratios.
L1/L 2 D1 D2
1.1 0.578 0.422
0.9 0.547 0.452
0.8 0.531 0.469
0.7 0.513 0.486
0.6 0.499 0.501
4.4 The Experimental Results
A 2 kW switched-capacitor voltage tripler prototype using a group of multi-purpose switched-capacitor testing boards has been built to verify the ideas presented in this paper. Each tests board contains four switches and two capacitors, but only two switches
93 and one capacitor are used in this experiment. Therefore a total of six boards are employed to build the voltage tripler.
Ten C5750X7R2A475K ceramic capacitors with a voltage rating of 100 V and a capacitance of 4.7 uF are put in parallel to form one main capacitor. At a switching frequency of 80 kHz and a load current of 25 A, the voltage ripple on the capacitors is around 5V. Please note that, for ceramic capacitors, the capacitance variation with their operation voltage can be as high as 40%. Therefore, film capacitors should be used in a better design to achieve a stable oscillation frequency.
Different test boards are connected through external cables. The cable lengths are made the same so the stray inductances of different charging loops are similar. To calculate the stray inductance of each charging loop, the oscillation frequencies are measured at a capacitor voltage of 5 V. The measured oscillation frequencies of the three first-step charging currents (from the top stage to the bottom stage) are 63.4 kHz, 65.7 kHz, 65.1 kHz, respectively. The corresponding loop inductances are calculated to be 134 nH, 125 nH and 127 nH, respectively.
Three IRFI4410ZPbF MOSFETs are connected in parallel to form a single switching device. The on-resistance of each MOSFET is 10 m Ω. The PCB traces in the charging loop add another 7-8 m Ω resistance so the total loop resistance is around 15 m Ω and the damping factor is around 0.15.
To control the proposed voltage tripler, three complementary signals with 120º phase 94 shift in between are needed. A 200 nS deadband is added between two complimentary signals to avoid the shoot-through. A TI TMS320F2812 DSP is used as the main controller.
Figure 4.10 shows the test setup of the experiment. The duty ratios of the first and second steps are 0.466 and 0.520, respectively. At a 50 V input voltage, soft-switching is achieved for both steps at a switching frequency of 72.0 kHz. Since the surface area of this prototype is large, the heatsink is not needed during the test.
Figure 4.10. The test setup of the experiment. Figure 4.11 shows the input current interleaving effect at a load current of 10 A. The lower three waveforms are the charging current (I S1 , I S5 and I S9 ) of the three stages in the first step. The peak value of the I S1 , I S5 and I S9 are 31.6 A, 30.8 A and 31.0 A, 95 respectively. Both I S5 and I S9 drop to 0.2 A when their corresponding switches are turned- off, demonstrating that zero-current-switching is well achieved. However, when S 1 is turned off, the value of I S1 is -1.6 A. The reason is that the charging loop of I S1 has a larger stray inductance than the other two charging loops.
The top two waveforms in Figure 4.11 are the sum of the three charging currents
(I S1 +I S5 +I S9 ) and the input current I in , respectively. The sum of the three charging currents has a peak-peak ripple 14.6 A and a RMS ripple of 2.95 A. This RMS ripple value corresponds to 22.4% of the ripple if no interleaving method is used in this topology.
Based on Table II, if the stray inductances of the three stages are the same, the RMS value of the current ripple should be 17.75% of the case when no interleaving method is used. This shows that the variation of parameters can affect the interleaving results. A 47 uF input capacitor is used to filter out the input current ripple. It can be seen that the input current has very small ripple on it, with a RMS value of 0.456 A.
Figure 4.12 shows interleaving results of the output voltage. The lower two waveforms are the output capacitor voltage of the top (V C4 ) and bottom (V C6 ) stage, respectively. They have a peak-to-peak voltage ripple of 6 V. The top waveform is the total output voltage, which has a voltage ripple less than 1 V.
96
Figure 4.11. The input current interleaving results.
Figure 4.12. The output voltage interleaving results. 97
Figure 4.13 shows the efficiency of the prototype over the operation range from 200
W to 2000 W with 50 V input voltage. It is measured using a Yokogawa WT3000 power meter. Two LEM Danfysik IT-700s high performance closed-loop current transducers are utilized to ensure the measurement accuracy. The control power loss is separately measured from the control power supply and added to the total loss.
The efficiency is higher than 96% for most of the test range. It should be noted that since different testing boards are connected through external cables, the stray inductance is not optimized, which adds the inaccuracy of soft-switching and interleaving and thus reduces the efficiency in this test. A dedicated and integrated design can increase the total efficiency of the converter.
Figure 4.13. The efficiency curve of the proposed converter. 98
4.5 Conclusion
A switched-capacitor voltage tripler with interleaving capability is presented in this chapter. This converter possesses the advantage of minimized intermediate capacitor stages, 50% duty ratio for the charging current, soft-switching and interleaving capability without additional components. Detailed structural and functional analyses are performed. The experimental results on a 2 kW prototype verified the proposed topology.
This circuit can be utilized in applications ranging from sub-kilowatt to many hundreds of kilo-watts with the advantage of low input current and output voltage ripple, low volume and high efficiency.
99
Chapter 5 The Voltage Regulation method for High-power
Switched-capacitor Dc-dc converters
5.1 The Traditional Voltage Regulation Methods
One of the largest challenges for high-power SC converters is how to regulate the output voltage with high efficiency. Although the voltage regulation for small-power SC converters has been extensively studied, the existing methods are based on a RC equivalent circuit of the capacitor charging loop. Therefore, the output voltage regulation mainly relies on the equivalent resistance in the circuit, and the converter functions as a linear regulator [36] [37] [38]. As a result, the converter efficiency is always equal to or lower than the normalized voltage transfer ratio [5] [21]. For example, for a step-up switched-capacitor dc-dc converter with an ideal voltage transfer ratio of N, the maximum efficiency is V out /(N×V in ). The existence of this maximum efficiency largely limits the voltage regulation range and the application of SC converter in high-power voltage conversion, where high converter efficiency is required. Although recent studies have provided new methods, such as phase-shift control [16] [30], to regulate the voltage, they can be only used in particular topologies, which severely limit their application.
The purpose of this paper is to address the aforementioned problems. Starting from an analysis on the impedance of the capacitor charging loop and the shape of the capacitor
100
charging current, a voltage regulation method is provided, which has a higher efficiency
than traditional methods. An RLC equivalent circuit of the capacitor charging loop,
which is more accurate in describing the charging loop impedance for high-power SC
converters, is utilized in this method. By adjusting the duty ratio of the charging current,
the termination angle of the quasi-sinusoidal charging current changes and the output
voltage regulation is realized.
Since the switches are turning off at non-zero-current conditions by adopting this
voltage regulation method, effort has to be made to reduce the power loss and EMI noise.
In this paper, a practical design analysis is performed on a traditional SC voltage doubler
with the proposed voltage regulation method. The third quadrant operation of switching
devices (MOSFETs) is used and the stray inductance distribution is optimized, so the
converter can operate with high-efficiency and with low EMI emission. It is also shown
in the analysis that, although the zero-current turn-off cannot be realized, the zero-voltage
turn-off can be achieved, which gives the converter soft-switching capability.
5.2 The Proposed Voltage Regulation Method
A. The shape of the capacitor charging current
To analyze the voltage regulation for a switched-capacitor converter, the capacitor
charging current is first investigated. Figure 5.1(a) shows the equivalent circuit of the
101 capacitor charging loop in a SC converter. In Figure 5.1(a), R S and L S represent the loop resistance and stray inductance, respectively. When the switch S 1 is off, the output capacitor discharges to the load with the load current I D. When S 1 is on, the voltage source V in charges the output capacitor with a current of I C. At the same time, the source provides I D to the load. By assuming the switching cycle is T sw and the duty ratio is D, the instantaneous capacitor current i c(t) can be expressed as:
−αt (5.1) e Asin( ωd t −θ0 ), 0 < t ≤ DT sw ic t)( = . − I D , DT sw < t < Tsw
In (5.1), the term Asin( ωdt-θ0) reflects the LC oscillation of the capacitor charging loop, in which A and ωd represent the amplitude and frequency of the oscillation, respectively.
θ0 is the initial angle of the oscillation, which depends on the instantaneous capacitor current when S 1 is turning on. For an output capacitor, since it continuously providing
-αt current to the load, i c(0) equals –ID. The term e reflects the attenuation of the LC
α oscillation due to the loop resistance R S. is the attenuation factor and α = RS / 2LS . The
ω damping factor is defined as ς = Rs C / Ls 2/ , then the oscillation frequency d can be calculated to be 1( −ς 2 /) LC .
The waveform of the capacitor current is shown in Figure 5.1(b). The switch S 1 is turned on at t=0, and the capacitor charging current starts to rise from –ID, which corresponds to the initial angle of the capacitor charging current θ=-θ0. At t=t 0, the 102 charging current rises to zero, and θ=0. The switch S 1 is turned off at t= D×T sw ., which corresponds to the termination angle of θ=θ1. The following relationship can be established:
θ0 + θ1 = ωd DT sw . (5.2)
At t=0, the charging current for an output capacitor is –ID, therefore,
(5.3) A × sin( −θ0 ) = −I D .
Based on the charge balance on the capacitor over one switching cycle:
DT SW −αt ∫ e Asin( ωdt −θ0 )) dt = 1( − D)Tsw × ID , (5.4) 0
Equation (5.4) can be rewritten as:
θ0 +θ1 −αθ /ωd ∫ e Asin( θ − θ0 )) dθ = 1( − D)Tsw ωd × I D , (5.5) 0
By substituting (5.3) into (5.5), θ0 can be calculated:
−αDT sw e sin( ωd DT sw + ϕ) − sin( ϕ) θ0 (D) = arctan( ), (5.6) −αDT sw cos( ϕ) + e cos( ωd DT sw + ϕ) − 1( − D)Tωd
θ whereϕ = arctan( α /ωd ) . After 0 is calculated, the value of A can be calculated from (5.3).
103
(a)
(b)
(c) Figure 5.1. (a) The equivalent circuit of the capacitor charging loop. (b) The capacitor current. (c) The capacitor voltage. 104
B. The capacitor voltage during the charging state
The shape of the capacitor voltage in one switching cycle is shown in Figure 5.1(c).
When the capacitor is being charged, its voltage changes in a non-linear manner. The
instantaneous voltage on the output capacitor V C(t) can be calculated by subtracting the
voltage drop on R S and L S from the source voltage V in :
di (t) V t)( =V − R i t)( − L L C in S L S dt (5.7) R =V − I R − S Ae −αt sin( ω t −θ ) − L ω Ae −αt cos( ω t −θ ), 0 < t < DT . in D S 2 d 0 S d d 0 sw
In (5.7), there is a constant voltage drop of I D×R S, which is due to the constant load
current I D and loop resistance R S. The two other terms are time-variant, which
corresponds to the voltage drop on the loop resistor and stray inductor due to the
sinusoidal capacitor charging current.
The initial capacitor voltage at t=0 is assumed to be V C0 :
I R V =V )0( =V − D S − Lω Acos θ . (5.8) C0 C in 2 d 0
The minimum and maximum capacitor voltage can be calculated by using the voltage
at t=t 0 and t=D×T sw , respectively:
−ςθ 0 V C _ min = V C(t0 ) = Vin − I D RS − Lωd Ae . (5.9)
−αDT sw V C _ max = V C(DT sw ) =Vin − IDRS − Lωd Ae (ς sin θ1 + cos θ1). (10)
The average capacitor voltage in the charging period of the capacitor can be calculated: 105
2 LA −αDT 1−ς V = V − I R − (e sw sin θ + sin θ ). C _ avg 1 in D S 1 2 0 (5.11) DT sw 1+ς
C. The capacitor voltage during the discharging state
When the capacitor is discharging to the load with I D, its voltage drops in a linear
manner, which can be expressed in (5.12):
I V t)( = V (DT ) − D (t − DT ), DT < t < T . (5.12) C C sw C sw sw sw
The average capacitor voltage in the discharging period is the average of the maximum
and minimum voltage:
VC _ max +VC0 3I R 1 −αDT V = = V − D S − L ω A(cos θ + e sw (ς sin θ + cos θ )). C _ avg 2 2 in 4 2 S d 0 1 1
D. The average capacitor voltage vs. (5.13) the duty ratio
For constant load current condition, the average capacitor voltage can be calculated
from (5.11) and (5.13),
D 3 V = DV + 1( − D)V = V − ( + )I R − C _ avg C _ avg 1 C _ avg 2 in 4 4 D S
2 (5.14) I D 1 −αDT 1 − ς 1 − D −αDT L [ (e sw sin θ + sin θ ) + ω (cos θ + e sw (ς sin θ + cos θ ))]. S 1 2 0 d 0 1 1 sin θ 0 Tsw 1 + ς 2
By knowing that:
VC_avg I D = . (5.15) RLoad
The average capacitor voltage for constant load resistance condition can be calculated
106 by substituting (5.15) into (5.14):
RLoad V C _ avg = Vin , 3 D LS 1 1 − D (16) RLoad + ( + )RS + [ E A + ωd EB ] 4 4 sin θ0 Tsw 2
2 −αDT sw 1−ς −αDT sw where EA = (e sin θ1 + sin θ0 ), EB = (cos θ0 + e (ς sin θ1 + cos θ1)). 1+ς 2
For a switched-capacitor converter with fixed circuit parameters (R Load , R S, L S and C) and switching cycle T SW , both θ0 and θ1 can be expressed as a function of the duty ratio
D. As a result, the average capacitor voltage can be expressed as a function of the duty ratio D. By controlling the duty ratio D, the output voltage can be regulated.
Figure 5.2 shows the calculation results of the output capacitor voltage with a duty ratio ranges from 0.1 to 0.9. The input voltage is 40 V and the load resistance is 5 Ω. The loop resistance, stray inductance and the capacitance of the capacitor are 10 m Ω, 150 nH and
25 µF, respectively, which results in an oscillation frequency of 82.2 kHz. The switching frequency is fixed at 100 kHz. The calculation result shows that, the output changes with the duty ratio in a non-linear manner. The region with lower duty ratios has higher voltage regulation capability than the region with higher duty ratios. Closed-loop control of the duty ratio can be used to achieve accurate output voltage.
107
Figure 5.2. The voltage of the output capacitor at different duty ratios.
5.3 The Design of A Voltage Doubler with Voltage Regulation Capability
The last section provides a general method on how to regulate the output voltage by
controlling the duty ratio. However, to achieve high conversion efficiency in a practical
design, there are several problems that need to be solved. In this section, a switched-
capacitor voltage doubler is used as an example to address the practical design concerns.
A. Structure
The topology of switched-capacitor voltage doubler is shown in Figure 5.3(a). It
contains four MOSFETs and two output capacitors. Among the four MOSFETs, S 1 and
S2 is one group and switch together, while S 3 and S 4 form another group. When S 1 and S 2
are on, the voltage source charges the top capacitor C 1; when S 3 and S 4 are on, the source
108
charges the bottom capacitor C 2. L S1 to L S4 represent the stray inductance in the branches
associated with the four MOSFETs, respectively.
B. The residual current in the stray inductance
If the proposed voltage regulation method is adopted, the switches are turned off at
non-zero conditions. Therefore, the residual current in the stray inductance LS1 -LS4 has to
find a path to flow; otherwise a large induced voltage will be resulted and the energy
stored in the stray inductance will be wasted. To solve this problem, in the design of the
voltage doubler, the stray inductance distribution is optimized and the third quadrant
operation of MOSFETs is used.
In this voltage doubler, the MOSFETs S 1 and S 4 work in the third quadrant, since the
charging current flows from the source to the drain. As a result, even these two
MOSFETs are turned off; the remaining current in the leakage inductance can flow
through their body diodes. A red-marked line in Figure 5.3(b) shows one possible current
flowing path of the residual current in L 1 after S 1 is turned off.
109
(a)The SC voltage doubler topology. (b) The free-wheeling path of I LS1 after S 1 is turned off.
Figure 5.3. The voltage doubler with stray inductance.
Since the other two switches S 2 and S 3 work in the first quadrant, the remaining current in their associated stray inductance does not have a free-wheeling path when they are turned off. To avoid the large voltage overshoot and achieve maximum efficiency, the stray inductances associated with S 2 and S 3 are minimized in the circuit design. On the other hand, the stray inductances associated with S1 and S 4 are maximized to reduce the
LC oscillation frequency for an achievable switching frequency.
The remaining current when the switches are turning off can be calculated using:
I sin θ −αDT sw d 1 I LS = e . (5.17) sin θ0
The time needed for the free-wheeling current reduces to zero is: 110
LS1 × I LS t fw = , (5.18) VC
Where L S1 represents the stray inductance associated with S 1 and S 4. The energy from
the stray inductance will be absorbed by the capacitor C1, the voltage rise ∆VC can be
calculated from (5.16):
1 1 L I 2 = C[( V + ∆V )2 −V 2 ]. (5.19) 2 S1 LS 2 C C C
2 1 LS1I LS Solving (5.19), ∆VC ≈ . 2 CV C
C. The peak current reduction.
To achieve the output voltage regulation, the capacitor charging time needs to be
changed. A reduction of the charging time results in problems of larger peak charging
current and increased conduction losses of MOSFETs. For example, both stages of the
voltage doubler have a maximum duty ratio of 0.5. Under the maximum duty ratio
operation condition, the electric charge is delivered from the source to the load in a time
of T/2. If the duty ratio changes to 0.25, then the same amount of electric charge needs to
be delivered in T/4, which results in a peak charging current around two times the value
in the first case. As a result, the regulation capability of the proposed method is limited
by the maximum conduction power loss of the converter, as well as the maximum safe
peak current of the MOSFETs.
From Figure 5.2, it can be seen that, with the reduction of duty ratio, which reduces the 111
termination angle of the sinusoidal charging current, the voltage regulation capability
increase exponentially. To achieve a good voltage regulation range while avoiding a
large peak current, it would be beneficial for the voltage doubler to have a switching
frequency larger than the oscillation frequency of the capacitor charging loop. In this
case, the converter operates in the region with high voltage regulation capability and a
small duty ratio reduction can results in sufficient voltage reduction.
D. The snubber circuit design.
Since most of the loop stray inductance is distributed on the branches associated with
S1 and S 4, a LC oscillation could be induced when the voltage across the MOSFETs is
building up, due to the output capacitance of the MOSFETs and the stray inductance.
Figure 5.4 is used to illustrate the generation of the oscillation. In Figure 5.4, point A, B
and C on the output-capacitor string have fixed steady-state potentials, while the voltage
potentials on the input source are floating. When S1 and S 2 are on, the voltage source is
connected to the higher output capacitor and the voltage across C S1 , which is the output
capacitor of S 1, is zero. When S 1 and S 2 are turned off and then S 3 and S 4 are turning on,
as shown in Figure 5.4, the voltage source is tied to the lower capacitor. As a result, C S1
needs to be charged to V C and a LC oscillation may occur. Since the damping factor is
usually small, the MOSFETs need to suffer from a large voltage oscillation.
To prevent this large voltage oscillation, one RCD snubber circuit is proposed, which is 112 shown in Figure 5.4. In this design, the snubber capacitor is set to have a capacitance that is much larger than the output capacitance of the MOSFET. The resistance of the snubber resistor is designed to be large enough so that the capacitor maintains an average voltage of V C during its operation. When the voltage across the MOSFET rises higher than V C, the diode conducts and the energy in the stray inductance is sent to the snubber capacitor
CS1 . Since the capacitance of C S1 is much larger than that of the output capacitor, the oscillation energy will be absorbed by the snubber capacitor without a large voltage rise.
Since the voltage variation on the snubber circuit is very small, the power loss is minimized.
For switch S 1, The LC oscillation induced by the voltage difference between point A and point C, which is Vc. The induced current travels through C S1 , L S1 and L S3 , which is represented by the dotted line in Figure 5.4. A simple LC circuit can be used for the analysis, as shown in Figure 5.4 b).
By knowing the initial switch voltage and current is zero, i S1 and V S1 can be found:
V i (t) = C × sin( ωt). S1 ωL , (5.20) VS1(t) = VC −VC × cos( ωt).
where L is the sum of L S1 and L S3 , and ω = /1 LC S1.
113
(a)
(b)
Figure 5.4. (a) The operation of the snubber circuit. (b) The equivalent circuit for S 1.
114
With the snubber capacitor is involved in the LC oscillation, the following equations can be obtained:
C i t)( = V S1 × cos( ω t). S1 C L 2 , (5.21) VC VS1(t) = VC + × sin( ω2t). n +1
CCS 1 1 where n = , and ω2 = . CS1 (n + )1 LC S1
From the above equations, it can be seen that the peak switch value is reduced by adding a snubber circuit. The voltage overshoot equals VC / n +1, which means the larger capacitance of the snubber capacitor, the smaller the overshoot.
To maintain the voltage on the snubber capacitor, the snubber resistor is added. When
S1 is closed, a simple RC circuit is formed by Ccs and Rs, and the snubber capacitor voltage discharges in an exponential way. When S 1 is open while S 2 and S 4 are closed,
Ccs is not discharging. But when all the four switches are open, the snubber capacitor discharges in a slower rate, which is not considered here.
T − sw V 1 2R C C s cs (5.22) =VC × 1( + )( 1− e ). n +1 n +1
Solving the above equation, the resistance can be calculated:
115
(5.23) Tsw 1 RS = ln( 1+ ). 2Ccs n +1
5.4 The Power Loss Analysis of the Voltage Doubler with the Proposed Method
There are three types of power losses in the voltage doubler with the proposed voltage
regulation method: conduction loss, switching loss and control circuit loss. Since the
control circuit loss only depends on the switching frequency and gate driver voltage, only
the switching loss and conduction loss are analyzed here.
A. The switching loss analysis
The zero-current turn-on and zero voltage turn-off can be automatically realized for the
switched-capacitor circuit so the switching loss is minimized.
Based on the equation of the capacitor charging current (5.1), the current goes through
the switches can be expressed as:
−αt iS (t) = ic (t) + I D = e Asin( ωd t −θ0 ) + I D. (5.24)
At t=0,
iS )0( = Asin( −θ0 ) + I D = −I D+I D = .0 (5.25)
So the zero current turn-on is achieved for all the switches.
With the proposed voltage regulation method, the switches are turning off at non-zero
current condition, and the soft-switching scheme cannot be utilized. However, the zero-
116 voltage turn-off can still be realized. Figure 5.4 shows the state when S 1 and S 2 are turned off and S 3 and S 4 are turned on, and the voltage source is tied to the lower capacitor. Before the next switching state there will be a dead time, and S 1 and S 2 will not be turned on until S 3 and S 4 are fully turned off. So the voltage potential of the source is still tied with the lower capacitor. Therefore, there is no voltage difference across S 3 and
S4 when they are turning off, and the zero-voltage turn-off can be realized.
Although zero-current turn-on and zero-voltage turn off can be realized, there are still two losses associated with the switching action, including the loss on the stray inductance and the loss on the output capacitance of the MOSFETs.
Since S 2 and S 3 operate in the first quadrant and turn off at non-zero-current conditions, the residual energy stored in their stray inductance will be converted into power loss when they are turning off. The loss on the stray inductance can be calculated as:
1 P = L I 2 (DT ) f , (5.26) LS 2 S2 LS SW where I LS (DT) and L S2 represents the residual current and stray inductance associated with the MOSFETs work in the first quadrant, respectively.
The loss on the output capacitance can be calculated using the output capacitance of the
MOSFETs C out , the input voltage V in :
1 P = C V 2 f . (5.27) Cout 2 out in SW
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B. The conduction loss analysis
The two types of conduction losses in a SC voltage doubler include: the conduction
loss on the ESR of the main capacitor P Cond_Rc and the conduction loss on the MOSFETs
and traces P Cond_Rs .
Based in (5.1) and (5.24), the instantaneous value for the conduction losses can be
calculated as:
−αt 2 (e Asin( ωd t −θ0 )) RC , 0 < t < DT P (t) = . (5.28) Cond _ Rc 2 I DRC , DT < t < T
−αt 2 (e Asin( ωdt −θ0) + ID ) RC 0, < t < DT PCond _ Rs (t) = . (5.29) ,0 DT < t < T
The average power loss in one switching cycle can be calculated:
1 DT 1 T P = (e−αt Asin( ω t −θ )) 2 R dt + I 2 R dt Cond _ Rc T ∫0 d 0 C T ∫DT D C
2 (5.30) 2 I D RC 1 −2αDT 1 = 1( − D)I R + { 1( − e sw ) − S }. D C 2 2 B 4ωd Tsw sin θ0 ς 1+ ς
1 DT P = (e−αt Asin( ω t −θ ) + I )2 R dt Cond _ Rs T ∫0 d 0 D s
2 2 (5.31) 2 2I D Rs 1 I D Rs 1 −2αDT 1 = DI R − S + { 1( − e sw ) − S , D s T 2 A 2 2 B ωd sw sin θ 0 1+ς 4ωd Tsw sin θ 0 ς 1+ς
−αDT sw where SA = e (ς sin( θ1 ) + cos( θ1)) − ς sin( θ 0 ) − cos( θ 0 )],
−2αDT sw and SB = e (sin( 2θ1) −ς cos( 2θ1)) + sin( 2θ0 ) +ς cos( 2θ0 ).
The above two equations show the conduction loss at constant load current conditions. 118
The conduction loss with constant load resistance condition can also be derived by replacing the load current I D with V avg /R Load .
5.5 The Experimental Results
A 300 W switched-capacitor voltage doubler prototype has been designed and built to test the validity of the proposed voltage regulation method. The photograph of this voltage doubler is shown in Figure 5.5. An IRFI4410ZPbF MOSFET is used as the switching device. To reduce the reverse recovery loss of the body diode, a power
Schottky diode STPS30100ST is used. Five C5750X7R2A475K 4.7 uF capacitors are put in parallel as the main capacitor to increase the current handling capability and make the total capacitance more accurate.
2 For the PCB design, 1 Oz/ft copper layer is used. The trace length associated with S 2 and S 3 is designed to be around 1 cm to reduce the stray inductance. On the other hand, the trace length associated with S 1 and S4 is designed to be around 7 cm. In the snubber circuit design, small packages 0805 capacitor and resistor are used.
119
Figure 5.5. The photo of the proposed voltage doubler. To measure the stray inductance, a low-voltage low-frequency test is performed at 5 V input voltage and 30 kHz. The shape of the charging current has measured and then the parameters are found through a curve fitting process, with the assumption that the capacitance maintains the value suggested by the datasheet at low voltage and room temperature. The measured loop inductance value and resistance are 70 nH and 30 m Ω, respectively. The oscillation frequency can be calculated to be 123 kHz.
Figure 5.6 and Figure 5.7 show the operation waveforms of the converter at 29 V input voltage and 13 Ω resistive load condition. The switching frequency is 200 kHz and the duty ratio is 0.4. At this switching frequency, the control power loss is measured with a constant value of 2.1 W.
Figure 5.6 shows the current waveforms of S 1 and S 4, with the sinusoidal current can be seen on both cases.
120
Figure 5.6. The waveforms of the capacitor charging current I S1 and I S4 .
Figure 5.7 shows the waveforms of the input voltage V in and output voltage V out .
Figure 5.7. The waveforms of the input and output voltage. Figure 5.8 shows the measured efficiency of the voltage doubler at a test condition of
29 V input voltage and a load resistance of 13 Ω. The efficiency values with and without 121 the control power are represented by ‘Eadj’ and ‘Eff’, respectively. The efficiency curves are compared with the normalized voltage transfer ratio ‘Vratio’, which equals to
Vout /2V in . For traditional voltage regulation method, the efficiency values without the control power should be lower than or equal to the voltage transfer ratio. However, in most test points, the value of ‘Eff’ is higher than the voltage transfer ratio, which proves that the proposed method can achieve higher efficiency than traditional methods.
0.97 0.95 0.93 0.91 0.89 0.87 Eff 0.85 Eadj 0.83 0.81 Vratio 0.79 0.77 0.75 0.73 Duty Ratio 0.1 0.2 0.3 0.4 0.5
Figure 5.8. The efficiency v.s. voltage transfer ratio at normal condtion. It should be noticed that by adding an external air-core inductor, the voltage regulation capability can be increased and the converter efficiency can be improved. Figure 5.9 shows the efficiency and voltage transfer ratio at the condition when an external 15 cm,
AWG 14 cable is added to the branches associated with S 1 and S 4. At this test condition, the loop impedance is around 170 nH and the switching frequency is maintained to be
200 kHz. The total converter efficiency is higher than 90% when the output voltage drops 122 to 80% of the ideal value, and higher than 94% when the output voltage drops to 90% of the ideal value.
0.98 0.96 0.94 0.92 0.9 Eff 0.88 Eadj 0.86 0.84 Vratio 0.82 0.8 0.78 Duty Ratio 0.22 0.27 0.32 0.37 0.42
Figure 5.9. The efficiency v.s. voltage transfer ratio with a 15 cm cable added.
5.6 Conclusion
A voltage regulation method for high power switched-capacitor converters is presented in this chapter. The proposed method adopts a RLC equivalent circuit of the capacitor charging loop. The output voltage regulation is achieved by varying the switching angle of the sinusoidal charging current. To reduce the power loss and EMI noise, the third quadrant operation of MOSFETs and optimized stray inductance distribution are utilized.
The experimental results show that, for a SC voltage doubler with the proposed method, the efficiency can exceed the maximum value of traditional methods.
123
Chapter 6 The Dynamic Voltage Restorer (DVR) Based on the
Switched-capacitor Concept
6.1 Dynamic Voltage Restorer (DVR)
Dynamic Voltage Restorer (DVR) is a series-connected device that is used in power distribution networks to protect consumers from sudden sags (and swells) in grid voltage.
DVR is used to mitigate the voltage sag by injecting the same amount of voltage as the missing voltage. Over the years, there are several DVR topologies have been proposed and applied in field [39] [40] [41] [42].
Figure 6.1. The operation of a traditional DVR. The three basic elements in a traditional DVR includes:
1. Converter and inverters: The purpose of the converters and inverters is to generate
124 the desired ac voltage from the supply voltage. It may contain a rectifier and an inverter for a non-storage type of DVR, or there is only the inverter for storage type of DVR.
2. Injection transformer: Most traditional DVR topologies have this injection transformer to ensure galvanic isolation.
3. Energy storage devices; most DVRs equipt with energy storage devices such as battery to provide the energy during voltage sag.
Because the traditional DVR includes heavy and costly components such as the isolation transformers or even batteries, it is usually bulky and expensive. With the development of the renewable generation technologies, there are more and more needs for lighter and cheaper DVR solutions. The purpose of this chapter is to utilize the switched-capacitor concept to propose a DVR that eliminate the transformer and the battery, so it can be widely used in the future in a smart grid.
6.2 The Structure of a SC Based DVR
The structure of proposed switched-capacitor based DVR is shown for one phase in
125
. The three-phase DVR consists of three identical single-phase DVR. There are mainly three parts in the proposed structure: the H-bridge rectifier, the isolation cell with power factor correction function, and the H-bridge inverter.
Figure. 6.2. The structure of the proposed DVR circuit.
The reason to use three separate H-bridge rectifiers and inverters, instead of using one three-phase rectifier and inverter, is to reduce component voltage stresses. Assume a three-phase system with a phase RMS voltage of V ph . Then the output dc voltage of a single-phase rectifier V rec is:
(6.1) Vrec ≈ 9.0 Vph .
Because the PFC circuit is boost type, the voltage on the capacitor C 1 is always higher
126
than Vrec . The isolation circuit will not change the dc-voltage, so the voltage on C 2 is:
(6.2) VC1 = VC2 > 9.0 Vph .
The RMS output voltage of the DVR, which is also the series injection voltage, can be
calculated:
VDVR > ma × 9.0 Vph , (6.3)
where m a is the modulation index of the single-phase inverter.
From the above equations, the voltage stress of the switches in the rectifier is 2Vph ,
the voltage stress for the two capacitors C 1, C 2, and the switches in the inverter is larger
than 0.9V ph , the exact value depends on the desired dc bus voltage, which can be
controlled by control the PFC.
For the proposed DVR, it is designed to compensate voltage sag from 10% to 50% of
the source voltage. To compensate 10% voltage sag, the modulation index should be
smaller than 1/9. To compensate 50% voltage sag, the modulation index should be
smaller than 5/9.
6.3 The Operation of the Isolation Cell.
A. The structure of the isolation cell
There are two functions of the isolation cell: to realize the power factor correction and
127 to realize the galvanic isolation between the source and the output of the DVR.
The isolation cell has a structure same as one single stage in the voltage tripler proposed in Chapter 4. The idea has been proposed in [35] for in micro-chip
There are four switches (S 1~S 4) and two capacitors (C 1 and C 2) in one isolation cell. To realize the full isolation, the bi-directional blocking switches have to be used, which is composed of two IGBTs. As seen in Figure 6.3, the two IGBTs S 1A and S 1B are connected in series to form one bi-directional switch S 1. Similarly, S 2 and S 3 are composed of IGBTs S 2A , S 2B and S 3A , S 3B , respectively. As a special case, the switch S 4 consists of one diode S 4A and one IGBT S 4B . The purpose of this is to prevent the unnecessary power loss due to reverse capacitor charging, which means C 1 charges C 2.
To realize the isolation function, S 1 and S 2 cannot be turned on together with either S 3 or S 4. During normal operations, the two-step charging scheme is utilized. In the first step, S 1 and S 2 are closed so the capacitor C 1 is charged by the current IPFC in the PFC inductor. Since the charging current is limited by the PFC inductor, there is no need for realizing the resonant charging. In the second step, S 3 and S 4 are closed, so the capacitor
C1 charges the capacitor C 2 to maintain the voltage on C2. Since no dedicated inductors present in this charging loop, large current spike could occur, which can generate large
EMI noises. To solve this problem, the soft-switching method is utilized here. The stray inductance L S3 and L S4 are utilized here to oscillate with C 1 and C 2 to achieve a sinusoidal shape of charging current. 128
Figure 6.3. The structure of the isolation cell.
B. The soft-switching of the isolation cell
In the following analysis, it is assumed that the inverter operates in bi-directional PWM
mode. The load current is expressed as:
(6.4) iac t)( = I ac _ peak sin( ωt),
where Iac_peak is the peak value of output current.
In Figure 6.4, the dotted waveform is the load current, and the solid waveform is the
profile of I inv .
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Figure 6.4. The profile of I inv .
It can be seen that I inv has a switching frequency that doubles the fundamental load frequency, and both positive part and negative part exist in one inverter switching cycle.
When I inv is negative, the capacitor C 2 receives charges and it has a voltage higher than
C1. Due to the blocking of the diode S 4B , there is no charging activity.
When I inv is positive, the capacitor C 2 supplies charges to the load and its voltage drops.
If the voltage of C 2 drops below the voltage of C 1, the capacitor C 1 charges C 2 when S 3 and S 4 are closed to maintain its voltage. Since the charging activity only happens during the negative part of the inverter switching cycle, in order to achieve the soft-switching, both the oscillation frequency of the capacitor charging loop f osc and the switching frequency of the isolation cell fiso has to be larger than f inv .
The duty ratio of the positive inverter current d(t) can be expressed as”
130
d(t) = ma sin( ωt +θ0 ) + 0,5.0 < ωt +θ0 < π (6.5)
where m a is the modulation index of the inverter PWM modulation waveform, and cos θ0 is the power factor of the DVR output.
Assuming the voltage change on capacitors C 1 and C 2 in one inverter switching cycle is negligible, the total charge Q inv (t) that needs to be transferred from C 2 to the load can be calculated as:
Qinv (t) = (d(t) − 1( − d(t))) iac (t)Tinv = 2ma sin( ωt + θ0 ) iac (t)Tinv 0, < ωt + θ 0 < π , (6.6)
To calculate the peak value of the charging current, the capacitor charging time also needs to be considered. Figure 6.5 shows various current and voltage waveforms in one inverter switching cycle that can help for capacitor charging time analysis. The duty ratio is d(t).
The top plot in Figure 6.5 is the inverter current I inv (t). It is assumed here that the switching frequency of the inverter f inv is much higher than the fundamental frequency fac . As a result, in one inverter switching cycle, I inv (t) can be regarded as a constant value.
Before (1-d(t))Tinv , it has negative value. After (1-d(t))Tinv , it has positive value.
The second plot in Figure 6.5 is the voltage of the two capacitors C 1 and C 2. When the inverter current is negative, the capacitor C 2 receives charges from the inverter. By assuming the initial voltage of both C 1 and C 2 is C 0, and the capacitance of both capacitors is C, then V C2 can be expressed as:
131
I ac (t) (6.7) V (t) = V + t 0, < t < 1( − d(t)) T . C 2 C 0 C inv
At the same time, C 1 receives current from the PFC inductor. Its voltage can be expressed as:
Qinv (t) (6.8) VC1 (t) =VC0 + t = VC0 + 2mat sin( ωt +θ0 ) I ac (t /) C 0, < t < a(t)Tinv . CT inv
After (1-d(t))T inv , C 2 discharges to the load with the inverter current.
I ac (t) (6.9) V (t) = V + 1(2( − d(t)) T − t), 1( − d(t)) T < t < a(t)T . C2 C0 C inv inv inv
C1 will not charge C 2 until the voltage of C 2 drops lower than C 2. The moment when the V C1 =V C2 can be calculated as:
1(2 − d t))( 1− 2m sin( ωt +θ ) (6.10) a(t) = = a 0 . 1+ 2ma sin( ωt +θ0 ) 1+ 2ma sin( ωt +θ0 )
The time window allowed for capacitor charging is:
1− 2ma sin( ωt +θ0 ) 4ma sin( ωt +θ0 ) (6.11) Tch _ win = 1( − )Tinv = Tinv . 1+ 2ma sin( ωt +θ0 ) 1+ 2ma sin( ωt +θ0 )
During this time frame, the capacitor C 1 can charge C 2. The average charging current can be calculated:
132
(6.12) Q (t) 2m sin( ωt + θ )i (t)T 1+ 2m sin( ωt + θ ) I = inv = a 0 ac inv = a 0 i (t .) ch _ avg 4m sin( ωt + θ ) ac Tch _ win a 0 2 Tinv 1+ 2ma sin( ωt + θ0 )
Figure 6.5. The capacitor charging time analysis.
6.4 The Simulation Results
In the simulation, the model of a three-phase DVR is built to verify the theory
133 presented in this chapter. The voltage and power rating of this DVR is 480 V rms and 50 kVA, respectively. From (6.2), the capacitor voltage is larger than 392 V. In the simulation, the capacitor voltage is controlled to be 500 V.
In the simulation model, the capacitances of all the capacitors are set to be 500 uF. The inductance of the PFC inductor is set to be 100 uF. The fundamental frequency is 60 Hz and the switching frequency of the inverter is 3 kHz. To realize the soft-switching, the switching frequency of the PFC and isolation cell is set at 30 kHz. A RL load is used in the simulation, with a power factor of 0.8.
The voltage sag compensation waveforms are shown in Figure 6.6. The voltage source originally outputs a line-line voltage of 480 Vrms. The phase load current is 60 Arms.
Then at t=0.05s, there is a 50% voltage sage and the source voltage drops to 240 Vrms and the load current drops to around 30 Arms. The voltage sage is detected in less than one fundamental cycle and the DVR compensate 50% of the voltage, so the load current change back to 60 Arms.
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Figure 6.6. The voltage sage compensation waveforms. Figure 6.7 shows several waveforms regarding the capacitor charging. The top plot shows the voltage on the two capacitors C 1 and C 2. The second plot shows the capacitor charging current, and the third plot shows the inverter current. It can be seen that the capacitor charging current is a series of impulse type of waveforms.
135
Figure 6.7. The capacitor charging waveforms in one inverter switching cycle.
Figure 6.8 shows the zoomed-in views of Figure 6.7, which shows the details in an inverter charging cycle. It can be seen that Figure 6.8 is consist with the analysis in
Figure 6.5. There are four capacitor charging pulses during one inverter cycle.
136
Figure 6.8. The zoomed-in view of the capacitor charging waveforms.
137
Chapter 7 Summary and Future Work
7.1 Summary
The major motivations and goals of this work are to develop the topologies and voltage control methods for high power switched-capacitor converters. The major contribution of this work includes:
• The capacitor charging current profile in a high-power switched-capacitor
converter is analyzed. It is found that for many high-power switched-capacitor
converters, the charging current has a quasi-sinusoidal shape, instead of the
exponential shape of the charging current which low-power SC converters have.
The quasi-sinusoidal shape of the charging current is one requirement for high-
power SC converters, since it can help to reduce the EMI noises and conduction
losses. The zero-current switching can be achieved from this current shape.
• For dc-dc conversion, a voltage tripler topology that has automatically
interleaving operation capability is presented. With the proposed two-step
charging scheme, both input current interleaving and output voltage interleaving
can be achieved. With the zero-current-switching and interleaving operation
methods, both the switching loss and conduction loss are minimized. The
experimental results on a 2 kW prototype show the convertor efficiency is
higher than 96% for most operation points. 138
• A group of switched-capacitor cells based converter are introduced for both dc-
dc and dc-ac applications. A rotational charging scheme is proposed for the dc-
dc multiplier, so the large output capacitor required by traditional switched-
capacitor topologies can be eliminated. For the dc-ac application, a boot type
five-level inverter topology is proposed and analyzed in details. A variable-
frequency control scheme is proposed, so that zero-current-switching is
achieved over the entire fundamental cycle. A peak efficiency of 96% can be
achieved for the proposed boost five-level inverter.
• To solve the low efficiency problem for most voltage regulation methods of SC
converters, a method that can realize high-efficiency voltage regulation is
proposed. In the proposed method, the output voltage regulation is achieved by
varying the termination angle of the sinusoidal charging current. To reduce the
power loss and EMI noise, the third quadrant operation of MOSFETs and
optimized stray inductance distribution are utilized. The experimental results
show that, for a SC voltage doubler with the proposed method, the efficiency
can exceed the maximum value of traditional methods.
• A Dynamic Voltage Restorer (DVR) circuit based on the switched-capacitor
concept is presented. An isolation cell is presented, which has four switches and
two capacitors. Bidirectional switches are used to realize the voltage isolation
function. The soft-switching can be realized, if the switching frequency of the 139
isolation cell is larger than the inverter switching frequency. The average
charging current analysis and simulation results are also provided in this
dissertation.
7.2 Future Work
• To develop wide band-gap device based switched-capacitor converters. It
is proved in this dissertation that there are several benefits switched-capacitor
converters could be benefits by adopting wide band-gap devices. The high
switching frequency capability of SiC or GaN devices makes it much easier to
realize LC resonance. The zero-current-switching can be realized by merely
utilizing the stray inductance in the circuit. The converter can also realize high-
temperature operation. A GaN based switched-capacitor voltage doubler testing
board has already been built and tested in the lab [43]. The picture is shown in
Figure 7.1. More work needs to be done on both the optimization of the
operation of switched-capacitor converter in high-frequency conditions,
including reduce the power loss caused by stray parameters and the EMI noises
reduction in MHz frequency conditions.
140
Figure 7.1. The GaN HEMT switched-capacitor prototype.
• A study on the oscillation due to stray parameters should be carried on in the
future. It is observed in the experiment that multiple oscillations are induced
due to the existing of stray parameters. For example, there is an oscillation
when the output capacitor of the switching devices and the stray inductance in
the capacitor charging loop. This oscillation may generate overvoltage for
switches and EMI noises. To design a circuit that can suppress or even
eliminate these oscillations will help to make the switched-capacitor converters
more reliable for high-power applications.
141
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