electronics

Review A Review of Topologies for the Power Management of IoT Nodes

Andrea Ballo , Alfio Dario Grasso * and Gaetano Palumbo Dipartimento di Ingegneria Elettrica Elettronica e Informatica (DIEEI), University of Catania, I-95125 Catania, Italy; [email protected] (A.B.); [email protected] (G.P.) * Correspondence: [email protected]; Tel.: +39-095-738-2317

 Received: 11 April 2019; Accepted: 24 April 2019; Published: 29 April 2019 

Abstract: With the aim of providing designer guidelines for choosing the most suitable solution, according to the given design specifications, in this paper a review of charge pump (CP) topologies for the power management of Internet of Things (IoT) nodes is presented. Power management of IoT nodes represents a challenging task, especially when the output of the energy harvester is in the order of few hundreds of millivolts. In these applications, the power management section can be profitably implemented, exploiting CPs. Indeed, presently, many different CP topologies have been presented in literature. Finally, a data-driven comparison is also provided, allowing for quantitative insight into the state-of-the-art of integrated CPs.

Keywords: charge pump (CP); Dickson charge pump; energy harvesting; IoT node; power management; switched-

1. Introduction The Internet of Things (IoT) paradigm is expected to have a pervasive impact in the next years. The ubiquitous character of IoT nodes implies that they must be untethered and energy autonomous. In IoT nodes, power-autonomy is achieved by scavenging energy from the ambient using transducers, such as photovoltaic (PV) cells, thermoelectric generators (TEG), and vibration sensors [1–4]. Nevertheless, due to the heavy dependence of their output signal from the operating conditions, these transducers are often unsuitable to feed directly to the circuit where they are applied. Therefore, they employ a power management (PMIC) to maximize conversion efficiency. In Figure1 a simplified block diagram of a PMIC is shown. The input voltage, VIN, provided by an external transducer, feeds a DC-DC converter and a clock generation block. The converter is then opportunely managed to obtain a precisely stable output voltage or to optimize power consumption in function of the required load current. The main components of a PMIC are the DC-DC converter and the clock generator. These blocks must also enable self-startup in critical conditions, i.e., low voltage and low power levels provided by the external energy harvesters [1–3]. The DC-DC converter can be implemented using switched (SI) or switched (SC) converters. SI converters are suitable for applications requiring high power (typically larger than 100 mW), but require bulky off-chip for their implementation. In low-power and low-area applications, such as IoT nodes, SC converters represent a better alternative, since they are amenable for full on-chip integration [5–8]. In literature, SC converters with a voltage gain higher than one are usually referred to as voltage multipliers or charge pumps (CPs). Charge pumps have been traditionally adopted in nonvolatile memories and SRAMs, in which the design is driven by settling time and low area, or RF antenna controllers and LCD drivers, where the main design constraint is the current drivability [9–11]. More recently, CPs are widely used to adapt the voltage levels between two or more functional blocks and to convey the electric energy,

Electronics 2019, 8, 480; doi:10.3390/electronics8050480 www.mdpi.com/journal/electronics Electronics 2018, 7, x FOR PEER REVIEW 2 of 14 extracted from surrounding environment, towards a storage buffer. Hence, presently their field of application includes energy-autonomous systems, such as battery-less circuits, biomedical implants and, more recently, IoT nodes [1–4,12–23]. In this latter context, the design of a PMIC based on CPs is a challenging task since it must fulfill a very low input voltage supply (few hundreds of millivolts and high-power conversion efficiency). In literature, several works on charge pump circuits are presented. In many of them the authors focusedElectronics 2019on ,optimization8, 480 design strategies, mainly for memory applications [24–31]. In order2 of to 15 furtherElectronics strengthen 2018, 7, x FOR the PEER knowledge REVIEW about these important circuital blocks, this paper is aimed2 of at14 reviewingextracted fromthe state-of-the-art surrounding environment,review of integrated towards CPs, a storage focusing bu onffer. IoT Hence, applications, presently where their the field main of constraintsextractedapplication from are includes surroundingarea energy-autonomousand power environment, conversion systems, towards efficienc such a y.storage asIn battery-lessparticular, buffer. Hence, we circuits, will pr esentlyconsider biomedical their the implants fieldwidely of adoptedapplicationand, more linear recently, includes CP, IoTdue energy-autonomous nodes to its [better1–4,12 general–23]. Insystems, perfor this lattermance, such context, as as battery-less compared the design circuithe of other ats, PMIC biomedical topologies, based on implants CPsnamely is a Fibonacci,and,challenging more recently,series-parallel, task since IoT it nodes must exponential, fulfill[1–4,12–23]. a very and lowIn Cockcroft–Walton this input latter voltage context, supply [5,32]. the design (few A data-driven hundreds of a PMIC of comparison millivoltsbased on CPs and is alsoishigh-power a challenging provided, conversion allowing task since e ffithe itciency). mustdesigner fulfill to a get very a lowquanti inputtative voltage insight supply into current(few hundreds status of of integrated millivolts CPs.and high-power conversion efficiency). In literature, several works on charge pump circuits are presented. In many of them the authors focused on optimization design strategies, mainly for memory applications [24–31]. In order to further strengthen the knowledge about these important circuital blocks, this paper is aimed at reviewing the state-of-the-art review of integrated CPs, focusing on IoT applications, where the main constraints are area and power conversion efficiency. In particular, we will consider the widely adopted linear CP, due to its better general performance, as compared the other topologies, namely Fibonacci, series-parallel, exponential, and Cockcroft–Walton [5,32]. A data-driven comparison is also provided, allowing the designer to get a quantitative insight into current status of integrated CPs.

Figure 1.1.Simplified Simplified block block diagram diagram of a chargeof a pumpcharge (CP)-based pump (CP)-based energy harvesting energy powerharvesting management power managementintegrated circuit integrated (PMIC). circuit (PMIC).

2. ChargeIn literature, Pump Topologies several works on charge pump circuits are presented. In many of them the authors focused on optimization design strategies, mainly for memory applications [24–31]. In order to further Charge pumps fall into the class of the inductor-less DC-DC converters. They are clocked circuits strengthen the knowledge about these important circuital blocks, this paper is aimed at reviewing the implemented by switched capacitors. Therefore, they are suitable to be fully integrated and have been state-of-the-art review of integrated CPs, focusing on IoT applications, where the main constraints are widely used in solid-state electronic systems since 1976 [33]. area and power conversion efficiency. In particular, we will consider the widely adopted linear CP, due A general block scheme of an N-stage CP is shown in Figure 2, where each i-th stage is made up to its better general performance, as compared the other topologies, namely Fibonacci, series-parallel, of a charge transfer switch (CTS) and a pumping capacitor, C. The last pair CTS and CL form the exponential, and Cockcroft–Walton [5,32]. A data-driven comparison is also provided, allowing the outputFigure stage. 1. TheSimplified acronym block CTS diagram was first of introduced a charge pubymp Wu (CP)-based and Chang energy [34] to harvesting emphasize power the main designer to get a quantitative insight into current status of integrated CPs. goal managementof this block, integrated which is circuit to irreversibly (PMIC). transfer charge from the input to the output. The circuit topology2. Charge of Pump the CTS Topologies constitutes the main diversification factor among the various proposed CP 2. Charge Pump Topologies architectures and, of course, is an important key aspect to consider. Charge pumps fall into the class of the inductor-less DC-DC converters. They are clocked circuits Charge pumps fall into the class of the inductor-less DC-DC converters. They are clocked circuits implemented by switched capacitors. Therefore, they are suitable to be fully integrated and have been implemented by switched capacitors. Therefore, they are suitable to be fully integrated and have been widely used in solid-state electronic systems since 1976 [33]. widely used in solid-state electronic systems since 1976 [33]. A general block scheme of an N-stage CP is shown in Figure2, where each i-th stage is made up of A general block scheme of an N-stage CP is shown in Figure 2, where each i-th stage is made up a charge transfer switch (CTS) and a pumping capacitor, C. The last pair CTS and CL form the output of a charge transfer switch (CTS) and a pumping capacitor, C. The last pair CTS and CL form the stage. The acronym CTS was first introduced by Wu and Chang [34] to emphasize the main goal of output stage. The acronym CTS was first introduced by Wu and Chang [34] to emphasize the main this block, which is to irreversibly transfer charge from the input to the output. The circuit topology of goal of this block, which is to irreversibly transfer charge from the input to the output. The circuit the CTS constitutes the main diversification factor among the various proposed CP architectures and, topology of the CTS constitutesFigure 2. Simplified the main scheme divers of aification linear Dickson factor chargeamong pump. the various proposed CP of course, is an important key aspect to consider. architectures and, of course, is an important key aspect to consider. In the first monolithic integrated CP [33], the CTS was simply implemented with a - connected n-type MOSFET, which works in saturation or in the cut-off region, and the output CP steady-state voltage is given by [5,9,33]

Figure 2. SimplifiedSimplified scheme scheme of a li linearnear Dickson charge pump.

In the first monolithic integrated CP [33], the CTS was simply implemented with a diode-connected In the first monolithic integrated CP [33], the CTS was simply implemented with a diode- n-type MOSFET, which works in saturation or in the cut-off region, and the output CP steady-state connected n-type MOSFET, which works in saturation or in the cut-off region, and the output CP voltage is given by [5,9,33] steady-state voltage is given by [5,9,33]

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𝑉 = (𝑉 𝑉) 𝑁 𝑉𝑁 , (1) ( )

ElectronicswhereElectronics V 2018CK2019 is,, 7the8,, x 480 FOR clock PEER voltage REVIEW amplitude, VTH is the threshold voltages (which in turn is a function33 of of 14of 15 the source-to-bulk voltage), IOUT is the load current, fCK is the clock frequency, and αT is the ratio between top parasitic capacitance and the pumping capacitance C. Although the Dickson CP is simple 𝑉 = (𝑉 𝑉) 𝑁 𝑉𝑁 , (1) VCK (I OUT) and allows an adequateVOUT current= (VIN drivability,VTH) + Nits( efficiencyV THand) voltageN gain are ,strongly affected by (1) − 1 + α − − f (1 + α )C the threshold voltage, as can be observed inT Equation (1).CK T where VCK is the clock voltage amplitude, VTH is the threshold voltages (which in turn is a function of whereIn Vgeneral,CK is the the clock CTS voltage is constituted amplitude, by oneVTH oris two the main threshold , voltages acting (which as a in switch, turn is and a function whose the source-to-bulk voltage), IOUT is the load current, fCK is the clock frequency, and αT is the ratio gatesof the are source-to-bulk properly driven voltage), by theIOUT following:is the load current, fCK is the clock frequency, and αT is the ratio betweenbetween top top parasitic parasitic capacitance capacitance and and the the pumping pumping capacitance capacitance CC.. Although Although the the Dickson Dickson CP CP is is simple simple 1. Other CP nodes; andand allows allows an adequate currentcurrent drivability,drivability, its its e ffiefficiencyciency and and voltage voltage gain gain are are strongly strongly aff ectedaffected by theby 2. Auxiliary circuits inside the CTS block. thetransistor transistor threshold threshold voltage, voltage, as canas can be observedbe observed in Equation in Equation (1). (1). ForIn general, example, the an CTS evolution is constituted of the basic by one Dickso or twon topology main transistors, was proposed acting and as patented a switch, by and Dickson whose In general, the CTS is constituted by one or two main transistors, acting as a switch, and whose ingates 1980 are [35]. properly In thisdriven solution, by reported the following: in Figure 3a, the CTS is made up of a single NMOS transistor, gates are properly driven by the following: with 1.the Other bulk CP connected nodes; to ground, whose gate is connected to a forward node to increase the 1. Other CP nodes; overdrive2. Auxiliary voltage circuitsand avoid inside the theloss CTSdue block.to the transistor threshold voltage, thus allowing a reduction of the2. ForAuxiliary minimum example, circuits supply an evolution inside voltage. the of CTS theHowever, basicblock. Dickson its main topology drawback was is proposed due to the and not patented totally byturned-off Dickson CTSs.in 1980For Hence, [example,35]. In a thisnon-negligible an solution, evolution reported ofreverse the basic incurrent Figure Dickso flows3a,n topology the from CTS the is was made output proposed up to of the a and single input patented NMOS when by the transistor, Dickson CTS is inswitchedwith 1980 the [35]. bulk off, In thus connected this reducing solution, to ground, the reported power whose in conversion Figure gate is 3a, connected efficiency. the CTS to is amade forward up nodeof a single to increase NMOS the transistor, overdrive withvoltage Athe more andbulk avoid performingconnected the loss tovariant due ground, to theof thewhose transistor traditional gate threshold is connectedDickson voltage, CP to isa thus obtainedforward allowing nodeby areplacing reductionto increase NMOS of the the overdrivetransistorsminimum voltage supplywith PMOS and voltage. avoid transistors the However, loss whosedue its to mainthebulk transi drawbackis connectedstor threshold is dueto the tovoltage, source, the not thus as totally allowingshown turned-o in a Figurereductionff CTSs. 3b, ofwhichHence, the minimumallows a non-negligible equal supply threshold reversevoltage. voltages current However, during flows its fromturn main theon. drawback outputMoreover, to is the itsdue inputvalue to the whenis increasednot the totally CTS during isturned-off switched turn- CTSs.off,off, thus Hence, reducingreducing a non-negligible thethe powerreverse conversion current.reverse currentThis effi ciency.soluti flowson fromis effective the output when to the the available input when technology the CTS is is a switchedstandard off,double thus well reducing and the the bulk power of each conversion NMOS efficiency.transistor cannot be independently controlled. A more performing variant of the traditional Dickson CP is obtained by replacing NMOS transistors with PMOS transistors whose bulk is connected to the source, as shown in Figure 3b, which allows equal threshold voltages during turn on. Moreover, its value is increased during turn- off, thus reducing the reverse current. This solution is effective when the available technology is a standard double well and the bulk of each NMOS transistor cannot be independently controlled.

Figure 3. DicksonDickson charge charge pump: pump: ( (aa)) NMOS NMOS enhanced enhanced version version [35]; [35]; ( (bb)) all-PMOS all-PMOS implementation. implementation.

A more performing variant of the traditional Dickson CP is obtained by replacing NMOS transistors The basic idea exploited in the solutions depicted in Figure 3 can be adopted to reduce the with PMOS transistors whose bulk is connected to the source, as shown in Figure3b, which allows adverse effect of threshold voltage by adopting auxiliary circuits to drive the two control terminals equal threshold voltages during turn on. Moreover, its value is increased during turn-off, thus reducing of the transistor, as shown in Figure 4. Indeed, gate biasing and body (or bulk) biasing techniques the reverse current. This solution is effective when the available technology is a standard double well can be applied to better manage the transistor during on and off phases and to improve its electrical and theFigure bulk 3. of Dickson each NMOS charge transistorpump: (a) NMOS cannot enhanced be independently version [35]; controlled. (b) all-PMOS implementation. properties, such as threshold voltage and on/off resistance. These techniques are further analyzed in The basic idea exploited in the solutions depicted in Figure3 can be adopted to reduce the adverse the followingThe basic sections. idea exploited in the solutions depicted in Figure 3 can be adopted to reduce the effect of threshold voltage by adopting auxiliary circuits to drive the two control terminals of the adverse effect of threshold voltage by adopting auxiliary circuits to drive the two control terminals transistor, as shown in Figure4. Indeed, gate biasing and body (or bulk) biasing techniques can of the transistor, as shown in Figure 4. Indeed, gate biasing and body (or bulk) biasing techniques be applied to better manage the transistor during on and off phases and to improve its electrical can be applied to better manage the transistor during on and off phases and to improve its electrical properties, such as threshold voltage and on/off resistance. These techniques are further analyzed in properties, such as threshold voltage and on/off resistance. These techniques are further analyzed in the following sections. the following sections.

Figure 4. Simplified schematic of (a) gate biasing technique and (b) bulk biasing technique.

FigureFigure 4. 4. SimplifiedSimplified schematic schematic of of (a (a) )gate gate biasing biasing technique technique and and ( (bb)) bulk bulk biasing biasing technique. technique.

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2.1.2.1. GateGate BiasingBiasing TechniqueTechnique GateGate biasingbiasing techniquestechniques cancan bebe classifiedclassified intointo controlled-switchcontrolled-switch andand not-controlled-switchnot-controlled-switch techniques.techniques.techniques. InIn thethe firstfirst first casecase case aa a controlcontrol control signal,signal, signal, generategenerate generatedd by by an an auxiliary auxiliary circuit, circuit, is isdirectly directly connected connected to tothethe the gategate gate ofof of eacheach each transistor.transistor. transistor. InIn In thethe the secondsecond second casecase case thethe the gategate gate ofof of eacheach each transistortransistor isis connectedconnected toto thethethe nodenodenode signalssignals presentpresent inin thethe CPCP itself.itself. AA CPCP adoptingadopting controlled-switchcontrolled-switch techniquetechnique waswas appliedapplied forfor thethe firstfirst timetimetime on onon memories memoriesmemories by byby D’Arrigo D’ArrigoD’Arrigo et al. etet [ 36 alal].. and,[36][36] successively, and,and, successively,successively, in the complementary inin thethe complementarycomplementary version by versionversion Umezawa byby etUmezawa al. [37], to et generateal. [37],[37], toto both generategenerate negative bothboth voltages negativenegative for voltagesvoltages erasing forfor operation erasingerasing operation andoperation positive andand voltage positivepositive to voltagevoltage program toto EEPROMprogram EEPROM cells. cells. TheThe simplifiedsimplified scheme scheme and and clock clock signal signal diagrams diagrams are are reported reported in inFigure Figure 5. 5A. four-phase A four-phase non- non-overlappedoverlapped clock clock is needed is needed and a and small a small auxiliary auxiliary locall localboostingboosting boosting capacitorcapacitor capacitor isis addedadded is added inin orderorder in order toto boostboost to boostgate voltage gate voltage during during the forward the forward conduction conduction phase. phase. With With this this strategy, strategy, during during the the boosting boosting phase, gategate voltagevoltage staysstays constantconstant andand isis independentindependent ofof thethethe otherotherother voltages.voltages.voltages. Consequently,Consequently, thethethe transistortransistortransistor MMMiii worksworks inin thethe linearlinear regionregion asas longlong asas its its gate-to-source gate-to-source voltage voltage is is greater greater than than the the threshold threshold voltage. voltage.

Figure 5. Charge transfer switch (CTS) in bootstrap CP, proposed by D’Arrigo et al. [36], and time Figure 5. Charge transfer switch (CTS) in bootstrap CP, proposed by D’Arrigo et al. [36], and time diagram of the clock phases. diagram of the clock phases. Despite that this circuit allows the reduction of the voltage drop across the switch, its drawback Despite that this circuit allows the reduction of thethe voltagevoltage dropdrop acrossacross thethe switch,switch, itsits drawbackdrawback is that, during steady-state (i.e., when the pumping capacitors are charged near their maximum isis that,that, duringduring steady-statesteady-state (i.e.,(i.e., whenwhen thethe pupumping capacitors are charged near their maximum voltage), the MOSFET works in the sub-threshold region where its conduction properties abruptly voltage), the MOSFET works in the sub-threshold region where its conduction properties abruptly fall-down. To overcome this drawback, the use of a boosted clock signal (red-text voltages in Figure5) fall-down.fall-down. ToTo overcomeovercome thisthis drawback,drawback, thethe useuse ofof aa boostedboosted clockclock sisignal (red-text voltages in Figure 5) was introduced in [38]. This topology is usually named bootstrap CP. The transistor works in the was introduced in [38]. This topology is usually named bootstrap CP.. TheThe transistortransistor worksworks inin thethe region because the overdrive results increase by the difference between the amplitude of the triodetriode regionregion becausebecause thethe overdriveoverdrive resultsresults increaseincrease byby thethe differencedifference betweenbetween thethe amplitudeamplitude ofof thethe two clock signals. Thus, the CP efficiency and driving capability are improved at the cost of an twotwo clockclock signals.signals. Thus,Thus, thethe CPCP efficiencyefficiency andand drivingdriving capabilitycapability areare improvedimproved atat thethe costcost ofof anan additional circuit to generate the boosted signal. More recently, Fuketa et al. [12] introduced a modified additional circuit to generate the boosted signal.. MoreMore recently,recently, FuketaFuketa etet al.al. [12][12] introducedintroduced aa bootstrap CP in which phases φ1b and φ1b are switched between 0 and the output voltage to further modified bootstrap CP in which phases φ1b1b andand φ1b1b areare switchedswitched betweenbetween 00 andand thethe outputoutput voltagevoltage toto increase performance. furtherfurther increaseincrease performance.performance. Another kind of bootstrap CP is represented by the topologies where the negated clock signal is Another kind of bootstrap CP is represented by the topologies where the negated clock signal is locally implemented. A first example of this topology was introduced by Ansari et al. [39], as shown locallylocally implemented.implemented. AA firstfirst exampleexample ofof thisthis topologytopology waswas introducedintroduced byby AnsariAnsari etet al.al. [39],[39], asas shownshown in Figure6a, and then improved by Mondal and Paily [ 20,40] by adoption of the scheme depicted in inin FigureFigure 6a,6a, andand thenthen improvedimproved byby MondalMondal andand PailyPaily [20,40][20,40] byby adoptionadoption ofof thethe schemescheme depicteddepicted inin Figure6b. Figure 6b.

Figure 6. Bootstrap CP with locally generated negated clock signal, (a) conventional [39] and (b) improvedFigure 6. [Bootstrap20]. CP with locally generatedrated negatednegated clockclock signal,signal, ((a)) conventionalconventional [39][39] andand ((b)) improvedimproved [20].[20].

A dynamic version of the basic topology in Figure 3a was introduced by Wu and Chang in [34]. A simplified schematic of this solution is reported in Figure 7. The topology of the CTS commutes

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from diode-connection, during the off state, to the classical static connection during the on state. In both proposals, the last switch strongly limits CP’s performance because it cannot be bootstrapped unless extra circuitry is implemented [13].

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A dynamic version of the basic topology in Figure3a was introduced by Wu and Chang in [ 34]. ElectronicsA simplified 2018, 7 schematic, x FOR PEER of REVIEW this solution is reported in Figure7. The topology of the CTS commutes5 from of 14 diode-connection, during the off state, to the classical static connection during the on state. In both fromproposals, diode-connection, the last switch during strongly the limitsoff state, CP’s to performance the classical becausestatic connection it cannot beduring bootstrapped the on state. unless In bothextra proposals, circuitry is the implemented last switch [strongly13]. limits CP’s performance because it cannot be bootstrapped unless extra circuitryFigure is 7. implemented Block scheme of[13]. the charge pump proposed by Wu and Chang [34].

2.2. Body Biasing Technique Focusing on the body effect of the threshold voltage, some interesting solutions employ the bias of the wells of the single transistors (n-well for PMOS and p-well for NMOS in triple-well technologies) in order to reduce VTH and allow the use of the CP in low-voltage applications. A simple body biasing solution was initially adopted by Sawada et al. [41] to implement a bootstrap all-PMOS charge pump in which the single MOSFET had source and bulk short-circuited together, as shown in Figure 8a. This connection assures that all transistors have the same threshold and minimizes reverse losses. A more complexFigure 7. Blockstructure scheme was of employed the charge pumpby Bloch proposed et al. [42], by Wu as and reported Chang [in34 Figure]. 8b, where Figure 7. Block scheme of the charge pump proposed by Wu and Chang [34]. separated p-well of the main devices were permanently kept at the lowest voltage level, within the 2.2.pump Body stage, Biasing by means Technique of cross-coupled transistors. Note that P-well managing avoids the parasitic 2.2. Body Biasing Technique bipolarFocusing junction on transistors the body e ffturnect ofon. the threshold voltage, some interesting solutions employ the bias of the wellsFocusingAccording of the on singleto the the body transistorstechnique effect of (n-wellused the thresholdto forbias PMOS the voltage, source-to-body and p-well some forinteresting or NMOS drain-to-body insolutions triple-well junction,employ technologies) the we bias can ofdistinguish the wells three of the different single bias transistors methods, (n-well as follows: for forwardPMOS andbody p-well biasing for (FBB) NMOS and backwardin triple-well body in order to reduce VTH and allow the use of the CP in low-voltage applications. A simple body biasing technologies)solutionbiasing (BBB), was in initially in order which adoptedto diodesreduce byare VTH Sawada forward and allow et and al. the [back41 use] toward of implement the biased, CP in low-voltage arespectively, bootstrap all-PMOSapplications. and a mixed charge Aapproach simple pump bodyincalled which biasing dynamic the solution single body MOSFET wasbiasing initially (DBB). had adopted source While and by the Sawada bulk earlie short-circuitedr etapproach al. [41] to lowers implement together, the threshold as a bootstrap shown voltage in all-PMOS Figure at 8thea. chargeThisexpense connection pump of an in increment which assures the that singleof the all MOSFET transistorsreverse current, had have source DB theB and same technique bulk threshold short-circuited is more and efficient, minimizes together, considering reverse as shown losses. that in FigureAduring more 8a. turn complex This off, connection the structure backward-switched wasassures employed that all wells bytransistors Bloch lead et to al.have an [42 increase the], as same reported of threshold the inthreshold Figure and8 b,minimizesvoltage. where separated reverse losses.p-wellMore A of more the recently, main complex devices Zhang structure wereet al. permanently [43],was employedPeng et keptal. by [14], at Bl the ochKim lowest et et al. al. [42], voltage [15], as and reported level, Ashraf within in and Figure the Masoumi pump 8b, where stage, [16] separatedbymake means extensive p-well of cross-coupled useof the of themain transistors.body devices bias ingwere Note techniques permanently that P-well to managingrealize kept atcharge the avoids lowest pumps the voltage parasitic able to level, work bipolar within in junction in verythe pumptransistorslow voltage stage, turn applications.by means on. of cross-coupled transistors. Note that P-well managing avoids the parasitic bipolar junction transistors turn on. According to the technique used to bias the source-to-body or drain-to-body junction, we can distinguish three different bias methods, as follows: forward body biasing (FBB) and backward body biasing (BBB), in which are forward and backward biased, respectively, and a mixed approach called dynamic body biasing (DBB). While the earlier approach lowers the threshold voltage at the expense of an increment of the reverse current, DBB technique is more efficient, considering that during turn off, the backward-switched wells lead to an increase of the threshold voltage. More recently, Zhang et al. [43], Peng et al. [14], Kim et al. [15], and Ashraf and Masoumi [16] make extensive use of the body biasing techniques to realize charge pumps able to work in in very low voltage applications.

Figure 8. (a) Body biasing technique applied by Sawada et al. [41] with PMOS transistors and (b) by BlochFigure et 8. al. (a [)42 Body] with biasing NMOS technique transistors. applied by Sawada et al. [41] with PMOS transistors and (b) by Bloch et al. [42] with NMOS transistors. According to the technique used to bias the source-to-body or drain-to-body junction, we can distinguish2.3. Composite three Charge diff erentPumps bias methods, as follows: forward body biasing (FBB) and backward body biasingIn general, (BBB), in the which CP diodesresults arein a forward noisy block. and backwardIndeed, it biased,has an respectively,output voltage and ripple a mixed given approach by the calledfollowing: dynamic body biasing (DBB). While the earlier approach lowers the threshold voltage at the expense of an increment of the reverse current, DBB technique is more efficient, considering that during turn off, the backward-switched wells lead to an increase of the threshold voltage. More recently, Zhang et al. [43], Peng et al. [14], Kim et al. [15], and Ashraf and Masoumi [16 ] make extensive use of the body biasing techniques to realize charge pumps able to work in in very low voltageFigure applications. 8. (a) Body biasing technique applied by Sawada et al. [41] with PMOS transistors and (b) by Bloch et al. [42] with NMOS transistors.

2.3. Composite Charge Pumps In general, the CP results in a noisy block. Indeed, it has an output voltage ripple given by the following:

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𝐼 𝑉 = (2) 2.3. Composite Charge Pumps 𝑓𝐶

Thus,In general, specs theon CPoutput results voltage in a noisyripple block.should Indeed, bind the it choice has an of output a minimum voltage value ripple for given the output by the capacitance.following: Moreover, a high input current ripple makes the use of large input by-pass capacitors IL necessary. Vripple = (2) A solution to both problems is given by employingfCKCL a dual-branch charge pump [44,45] as an implementationThus, specs of on the output most generic voltage time-interlea ripple shouldved bindcharge the pumps choice [18,46], of a minimum whose simplified value for block the diagramoutput capacitance. is reported in Moreover, Figure 9. The a high idea input behind current these ripplekinds of makes charge the pumps use of is large to split input a single by-pass CP intocapacitors two or necessary. more smaller pumps, which work in complementary time slots. This strategy increases the equivalentA solution frequency to both problems with which is giventhe current by employing is sunk from a dual-branch the charge and pump delivered [44,45] to as the an load,implementation thus lowering of thethe mostvoltage generic ripple. time-interleaved Moreover, in this charge topology, pumps resizing [18,46 the], whose components simplified ( block anddiagram pumping is reported capacitors) in Figure also9 allows. The idea for the behind increase these of kinds the maximum of charge pumpsswitching is to frequency split a single limit CP of theinto converter. two or more On smaller the other pumps, hand, which the price work to pay in complementary is a higher complexity time slots. of Thisthe clock-phase strategy increases generator the andequivalent a greater frequency power consumption. with which the current is sunk from the power supply and delivered to the load, thusMore lowering recently, the voltage Wang ripple.et al. [18] Moreover, introduced in this the topology,multistep resizing split-merge the components charge transfer (switches technique and topumping get a higher capacitors) power also efficiency allows for for a the charge increase pump of thefor maximumsolar energy switching harvesting. frequency It exploits limit charge of the redistributionconverter. On theamong other the hand, pumping the price capacitors to pay isof a pa higherrallel complexityCPs by means of theof switches clock-phase inserted generator between and capacitorsa greater power belonging consumption. to different CPs.

Figure 9. Composite charge pump.

More recently, Wang et al. [18Figure] introduced 9. Composite the multistep charge pump. split-merge charge transfer technique to get a higher power efficiency for a charge pump for solar energy harvesting. It exploits charge 2.4. Cross-Coupled Charge Pumps redistribution among the pumping capacitors of parallel CPs by means of switches inserted between capacitorsBefore belonging treating cross-coupled to different CPs. CPs, also referred as latched CPs, it is appropriate to introduce a particular 2-stage CP, often employed as voltage shifter or doubler. Designed for the first time by Nakagome2.4. Cross-Coupled et al. [47] Charge as a Pumps feedback CP for a DRAM word-line driver, the well-known Nakagome’s cell, depictedBefore treating in Figure cross-coupled 10a, is commonly CPs, also adopted referred to as generate latched differential CPs, it is appropriate doubled output to introduce voltage a withparticular zero drop 2-stage across CP, oftenits transistors. employed If as couple voltaged to shifter dual orseries-connected doubler. Designed PMOS for switches, the first a time single by outputNakagome is obtained, et al. [47 as] asshown a feedback in Figure CP 10b. for aThis DRAM combination word-line is driver,the basic the cell well-known of the cross-coupled Nakagome’s CP independentlycell, depicted in proposed Figure 10 bya, Gariboldi is commonly and Pulvirenti adopted to in generate their quad diff monolithicerential doubled line driver output [48,49] voltage and successivelywith zero drop reported across in its [50]. transistors. If coupled to dual series-connected PMOS switches, a single output is obtained, as shown in Figure 10b. This combination is the basic cell of the cross-coupled CP independently proposed by Gariboldi and Pulvirenti in their quad monolithic line driver [48,49] and successively reported in [50]. Like the dual-branch structures, the latch configuration allows for reduction of the ripple and enhance charge transfer, thus improving the power efficiency. Transistors work in the linear region in on-state and are completely turned off in the opposite phase. Small auxiliary circuitry is often present with the aim of controlling the charge transfer from the input to the output. Since cross-coupled CPs are similar to dual-branch CPs, pumping capacitances of a single stage are halved, with respect to the classical Dickson CP. Therefore, transistors should be made smaller. Moreover, gate and body biasing techniques can also be applied to improve their operations. Additionally, the employment of CMOS solutionFigure should 10. Nakagome’s entail some cell limitation block scheme on the(a) without conduction and (b level) with given PMOS by switches, the series and connection (c) a cross- that includescoupled the charge p-type pump. MOSFET.

Electronics 2018, 7, x FOR PEER REVIEW 6 of 14

𝐼 𝑉 = (2) 𝑓𝐶

Thus, specs on output voltage ripple should bind the choice of a minimum value for the output capacitance. Moreover, a high input current ripple makes the use of large input by-pass capacitors necessary. A solution to both problems is given by employing a dual-branch charge pump [44,45] as an implementation of the most generic time-interleaved charge pumps [18,46], whose simplified block diagram is reported in Figure 9. The idea behind these kinds of charge pumps is to split a single CP into two or more smaller pumps, which work in complementary time slots. This strategy increases the equivalent frequency with which the current is sunk from the power supply and delivered to the load, thus lowering the voltage ripple. Moreover, in this topology, resizing the components (switches and pumping capacitors) also allows for the increase of the maximum switching frequency limit of the converter. On the other hand, the price to pay is a higher complexity of the clock-phase generator and a greater power consumption. More recently, Wang et al. [18] introduced the multistep split-merge charge transfer technique to get a higher power efficiency for a charge pump for solar energy harvesting. It exploits charge redistribution among the pumping capacitors of parallel CPs by means of switches inserted between capacitors belonging to different CPs.

Figure 9. Composite charge pump.

2.4. Cross-Coupled Charge Pumps Before treating cross-coupled CPs, also referred as latched CPs, it is appropriate to introduce a particular 2-stage CP, often employed as voltage shifter or doubler. Designed for the first time by Nakagome et al. [47] as a feedback CP for a DRAM word-line driver, the well-known Nakagome’s cell, depicted in Figure 10a, is commonly adopted to generate differential doubled output voltage with zero drop across its transistors. If coupled to dual series-connected PMOS switches, a single output is obtained, as shown in Figure 10b. This combination is the basic cell of the cross-coupled CP Electronicsindependently2019, 8, 480proposed by Gariboldi and Pulvirenti in their quad monolithic line driver [48,49]7 ofand 15 Electronics 2018, 7, x FOR PEER REVIEW 7 of 14 successively reported in [50]. Like the dual-branch structures, the latch configuration allows for reduction of the ripple and enhance charge transfer, thus improving the power efficiency. Transistors work in the linear region in on-state and are completely turned off in the opposite phase. Small auxiliary circuitry is often present with the aim of controlling the charge transfer from the input to the output. Since cross- coupled CPs are similar to dual-branch CPs, pumping capacitances of a single stage are halved, with respect to the classical Dickson CP. Therefore, transistors should be made smaller. Moreover, gate and body biasing techniques can also be applied to improve their operations. Additionally, the employment of CMOS solution should entail some limitation on the conduction level given by the series connection that includes the p-type MOSFET. In literature many variants have been proposed for the basic topology of Figure 10c. One of these topologiesFigure was 10. proposedNakagome’sNakagome’s by cell Luo cell block et block al. scheme [51], scheme in (a which) (withouta) without pMOSFETs and and(b) with (b are) with PMOS bootstrapped PMOS switches, switches, toand improve (c and) a cross- (c )power a efficiencycross-coupledcoupled up tocharge 69%, charge pump. with pump. an output current of 3.5 mA and a voltage of 10.5 V. In the same year, Tsuji et al. [19] suggested a low-leakage driver for the main complementary of a latched CP to improve In literature current drivability many variants with have a low been input proposed voltage for(100 the mV). basic topology of Figure 10c. One of these topologiesAnother was high-performance proposed by Luo cross-coupled et al. [51], in whichCP was pMOSFETs proposed are by bootstrappedPeng et al. [14], to improve where bodies power andeffi ciencygates upare todynamically 69%, with an biased output to currentlower the of 3.5 minimum mA and asupply voltage voltage of 10.5 (320 V. In mV). the same Its weakness year, Tsuji resideset al. [19 in] the suggested need for a extra low-leakage stages, driverand complex for the circ mainuits, complementary to work-well. More MOSFETs effective of a solutions latched CP are to givenimprove by currentFravat drivabilityet al. [52], withwhich a lowused input two voltage auxiliary (100 transistors mV). to apply the principle of bulk switchingAnother and high-performanceimprove PMOS current cross-coupled drivability CP wasand proposedpower efficiency by Peng of et al.the [ 14Nakagome’s], where bodies cell, andas depictedgates are in dynamically Figure 11. biased to lower the minimum supply voltage (320 mV). Its weakness resides in theFinally, need fora further extra stages,improved and cross-coupled complex circuits, CP was to work-well. given by Chen More et e ffal.ective [53], solutionswhich for arethe givenfirst timeby Fravat applied et FBB al. [ on52], a whichthree-stage used CP, two and auxiliary by Kim transistors et al. [15], which to apply applied the principle the dynamic of bulk body switching biasing onand both improve transistors PMOS with current the drivabilityacquired benefits and power of very effi ciencylow start-up of the Nakagome’svoltage at 150 cell, mV as and depicted a high in efficiencyFigure 11 .of 72.5%.

Figure 11. Cross-coupled CP with bulk switching [52]. Figure 11. Cross-coupled CP with bulk switching [52]. Finally, a further improved cross-coupled CP was given by Chen et al. [53], which for the first time 2.5.applied Clock FBBBoosted on aCharge three-stage Pumps CP, and by Kim et al. [15], which applied the dynamic body biasing on bothA transistors technique with allowing the acquired for the benefits reduction of veryof rise low ti start-upme or silicon voltage area at 150 occupation, mV and a thanks high effi tociency the reductionof 72.5%. on the number of stages and using a clock boosted topology, is presented in [54,55]. These CPs use clock signals with amplitudes higher than the supply voltage, thus requiring additional 2.5. Clock Boosted Charge Pumps blocks (other charge pumps) to boost the preexisted clock. InA [54] technique a clock allowingbooster was for adopted the reduction to increase of rise the time stea ordy silicon state output area occupation, voltage. In this thanks solution, to the areduction cascade of on Nakagome’s the number ofcells stages was and used using as a a mult clocki-output boosted boosted topology, clock, is presented where opposite in [54,55 ].output These signalsCPs use of clock the single signals cell with were amplitudes applied, as higher to the than single the pump supply stage voltage, (Figure thus 12b). requiring A qualitative additional analysis blocks of(other this structure charge pumps) highlights to boost that, thealthough preexisted a reductio clock.n of stages can be obtained, the rushing fall in the drivingIn [capability,54] a clock due booster to cascade was adopted configuration, to increase constrains the steady to statean increase output of voltage. the total In thiscapacitance solution, valuesa cascade of the of Nakagome’swhole pump, cells nullif wasying used the as proposal’s a multi-output benefits. boosted clock, where opposite output signals of the single cell were applied, as to the single pump stage (Figure 12b). A qualitative analysis of this structure highlights that, although a reduction of stages can be obtained, the rushing fall in the driving

Electronics 2019, 8, 480 8 of 15

capability, due to cascade configuration, constrains to an increase of the total capacitance values of the Electronicswhole pump, 2018, 7, nullifying x FOR PEER the REVIEW proposal’s benefits. 8 of 14 Electronics 2018, 7, x FOR PEER REVIEW 8 of 14

Figure 12. Clock boosted charge pumps, (a) simplified block scheme and (b) multi-stage clock [54]. Figure 12. Clock boosted charge pumps, (a) simplified block scheme and (b) multi-stage clock [54]. Recently,Figure 12. the Clock authors boosted in [charge55] adopted pumps, the (a) clock simplified booster block to reducescheme theand rise (b) multi-stage time or area clock occupation [54]. in CPs,Recently, with a clock the amplitudeauthors in doubled[55] adop withted the respect clock to booster supply to voltage, reduce provingthe rise time proper or sizingarea occupation strategies. Recently, the authors in [55] adopted the clock booster to reduce the rise time or area occupation inIn general,CPs, with despite a clock the amplitude achieved benefits,doubled this with approach respect isto not supply suitable voltage, for low-power proving andproper/or energysizing in CPs, with a clock amplitude doubled with respect to supply voltage, proving proper sizing strategies.efficient application. In general, despite the achieved benefits, this approach is not suitable for low-power and/orstrategies. energy In general,efficient despiteapplication. the achieved benefits, this approach is not suitable for low-power 2.6.and/or Adiabatic energy Charge efficient Pumps application. 2.6. Adiabatic Charge Pumps 2.6. AdiabaticIn order Charge to lower Pumps power consumption, an adiabatic CP has been proposed. The strategy is focusedIn order on the to slow lower charging power condition consumption, in order an toadia reducebatic theCP energyhas been which proposed. is not transferred The strategy to the is focusedload.In In orderon particular, the to slow lower the charging adiabaticpower condition consumption, strategy, in whichorder an to wasadia reduce originallybatic the CP energy exploitedhas been which inproposed. ais digital not transferred The domain strategy [ 56to ,the57 is], load.isfocused applied In particular,on following the slow the twocharging adiabatic strategies. condition strategy, In the in which former, order wasto two-time reduce originally the step energy exploited charge which sharing in a is digital andnot transferred a domain particular [56,57], to clock the isschemeload. applied In areparticular, following used [58 the two]. Thisadiabatic strategies. strategy strategy, In is the adopted former, which bywas tw Ulaganathano-time originally step chargeexploited et al. sharing [21 in] on a digital aand linear a particulardomain charge [56,57], pump clock schemeforis applied energy are following harvestingused [58]. two This applications. strategies. strategy isIn Inadopted the Figure former, by13 a, Ulaganathantw theo-time three-stage step et charge al. charge [21] sharing on pump a linear and proposed acharge particular pump in [ 21clock for] is scheme are used [58]. This strategy is adopted by Ulaganathan et al. [21] on a linear charge pump for energydepicted, harvesting in which applications. two-step waveform In Figure applied 13a, the on thr nodeee-stageVG allowscharge topump transfer proposed the charge in [21] in is two depicted, times, energy harvesting applications. In Figure 13a, the three-stage charge pump proposed in [21] is depicted, incharacterized which two-step by two waveform different voltageapplied levels.on node Therefore, VG allows the totalto transfer transferred the energychargeE Tinis two given times, by in which two-step waveform applied on node VG allows to transfer the charge in two times, characterized by two different voltage levels. Therefore, the total transferred energy ET is given by characterized by two different voltage2 levels. Therefore,2 the total transferred2 energy ET is given by 1 V f 1 V f V f 1 = ( ) + [ ( + )] = ( ) ( )2 𝐸 = E𝐶(T C𝑉) V𝐶𝑉i (C V𝑉f ) = 𝐶(Vi 𝑉)C 𝐶(𝑉Vi < 𝑉C) ,V f Vi ,(3) (3) 𝐸 = 𝐶( 2 𝑉)2 − 𝐶𝑉 (2 𝑉−)2= 𝐶( 𝑉) 2 −𝐶(𝑉 2𝑉), − (3) where Vi and Vf are the initial and final capacitor voltage levels, respectively. where Vi and Vf are the initial and final capacitor voltage levels, respectively. where Vi and Vf are the initial and final capacitor voltage levels, respectively.

Figure 13. Adiabatic charge pumps, (a) two-time step charge sharing [21] and (b) charge recycling Figure 13. Adiabatic charge pumps, (a) two-time step charge sharing [21] and (b) charge recycling blockFigure scheme 13. Adiabatic [59]. charge pumps, (a) two-time step charge sharing [21] and (b) charge recycling block scheme [[59].59]. The second strategy exploits the recycling of charges collected and the realization of auxiliary The second strategy exploits the recycling of chargescharges collected and the realization of auxiliary ground and VDD nodes, as shown in Figure 13b, where the working principle used by Keung et al. in ground and VDD nodes, as shown in Figure 13b, where the working principle used by Keung et al. ground and VDD nodes, as shown in Figure 13b, where the working principle used by Keung et al. in [59]in [59 is] reported. is reported. During During a first a first time time slot, slot, thanks thanks to to the the virtual virtual ground, ground, charges charges consumed consumed by by a a source source logic[59] is block reported. are collected During a infirst the time capacitor. slot, thanks Meanwh to theile, virtual supply ground, voltage charges feeds theconsumed target logic by a sourceblock. Then,logic blockwhen arethe collectedauxiliary inground the capacitor. node is high, Meanwh the circuitsile, supply are switchedvoltage feeds and thethe collectedtarget logic charge block. is Then, when the auxiliary ground node is high, the circuits are switched and the collected charge is pumped up by the charge pump to the right-side capacitor in order to generate the auxiliary VDD, whichpumped goes up to by supply the charge the target pump logic to block.the right-side In conclusion, capacitor this inapproach order to allows generate about the 9.95% auxiliary of power VDD, consumptionwhich goes to reduction, supply the with target only logic 1–2% block. of areaIn conc penalty.lusion, this approach allows about 9.95% of power consumption reduction, with only 1–2% of area penalty.

Electronics 2019, 8, 480 9 of 15 logic block are collected in the capacitor. Meanwhile, supply voltage feeds the target logic block. Then, when the auxiliary ground node is high, the circuits are switched and the collected charge is pumped up by the charge pump to the right-side capacitor in order to generate the auxiliary VDD, which goes to supply the target logic block. In conclusion, this approach allows about 9.95% of power consumption reduction, with only 1–2% of area penalty.

2.7. Adaptive Charge Pumps Adaptive charge pumps, also known as reconfigurable CPs, are designed to be able to switch their number of stages [50,51] or change their voltage conversion ratio [22,60–63] in order to adaptively change current driving capability to the load or to improve very low-voltage start-up operation [23]. In this category, which also includes CPs that commute from a linear to an exponential or Fibonacci topology [64], CPs devoted to low voltage operation for microscale energy harvesting [65] and to the energy reduction in the sleep to active transition [66] were developed. Adoption of adaptative CPs must be carefully considered since, in general, the advantage obtained in terms of flexibility is paid for in circuit complexity.

3. Performance Comparison The adoption of a specific topology among those reported in the previous section depends upon the specific application, the CMOS technology, and design specifications. Starting from the analysis of the previous section, some general guidelines are in the following. In low-supply-voltage applications, such as energy scavenging from TEGs, gate and body control schemes could represent a good choice since they allow for lowering the minimum input voltage. In applications requiring low power consumption, energy recycling or active/idle mode transition offered by adiabatic CPs or adaptive CPs can represent an efficient solution at the expense of higher settling times and area overhead. In flash memories in which the main goal of internal DC-DC converters is to generate different voltage levels with low settling times, clock-boosted or reconfigurable CPs may represent a suitable choice. Analysis of the reported experimental measurements of the different topologies represent an important step in the assessment of the state-of-the-art. Indeed, it may reveal additional and sometimes unexpected benefits of a particular topology. Therefore, in order to provide a deeper knowledge to the designer, performance metrics of different previously reported solutions are collected in a spreadsheet and made available online to allow independent exploration [67]. Moreover, for the sake of conciseness, a selection of 11 solutions, out of 27 in [67], targeted for energy harvesting applications, is reported in Table1. Except for the CP in [20], where large pumping capacitors were used to drive high current loads, in energy harvesting applications output power levels of CPs fall down in the range of tens of microwatts. Moreover, defining the power efficiency as

P η = out , (4) Pin CP + Paux − where Pin-CP is the input power of the CP only and Paux is the power consumption of the auxiliary circuits. The maximum η ranges from 10% to 79% (this latter value achieved by [18]). Most of the examined topologies (bootstrap or cross-coupled) exhibit a η of about 30–60%, despite that they should be inherently highly efficient. These low η values are due to the auxiliary circuits (in particular the clock generators and drivers) which can heavily affect the overall power consumption when Paux is comparable with Pin-CP. Electronics 2019, 8, 480 10 of 15

Table 1. Comparison of different charge pumps.

Ref. [2][3][12][13][14][15][17][18][20][58] a [23] Cross-coupled/ Dickson-with Cross-coupled Cross-coupled Topology Cross-coupled Bootstrap Bootstrap Bootstrap Bootstrap Adiabatic Adaptive composite DGB with BGB DBB No. Of Stages 6 pararallel 24 3 10 4 6 3 3 5 1 3 7 10 Clock booster Clock Dynamic G Backward G Dynamic B Split-merge Low-threshold Aux. Circuit Start-up circuit - - - 3x booster 2x control Biasing control four-branches diode in every CTS Technology 130 65 65 65 180 130 130 130 180 130 65 (nm) Min. Supply 70 150 100 550 320 150 270 500 390 125 120 (mV) Clock Frequency 0.040 15.2 10 1.8 0.45 0.25 0.8 2.5 23 0.360 1 (MHz) Total Pumping Cap. (pF) 46.08 22.5 1001 160 288 36,000 b 150 310 500 96 224 286 Load Cap. (pF) 10,000 b 30 100 400 50.7 10,000 b 500 800 4000 b 100 - Load Current at Peak η 12 1.74 0.76 10 - 21 5 30 620 0.1 3.9 (µA) Max Output Power 15 1.5 6.6 4.7 - 10.5 7 75 620 0.061 0.035 3 (µW) Peak VCE (%) 50 80 76 96 89 86 65 93 93 70 80 58 Peak η (%) 58 38.8 33 66 - 34 c 58 78.6 c 76 59 62 38.8 Area (mm2) 0.6 0.032 1.32 0.17 0.14 mm2 0.066 b 0.42 0.98 0.48 0.15 0.1 0.78 a simulations; b off-chip capacitors; c external clock generator Electronics 2019, 8, 480 11 of 15

Analysis of data reported in Table1 reveals that the lowest minimum supply voltage is achieved by the cross-coupled topology in [2] thanks to the adoption of an auxiliary CP for startup. Unexpectedly, solutions adopting gate and body control schemes, [12–15,41–43], show higher minimum supply Electronicsvoltages, 2018 thus, 7, showing x FOR PEER that REVIEW the comparison among the different designs is not straightforward because10 of 14 of the different functionality and constraints required by the various applications. where Vout and Vout,id are the actual and ideal CP output voltage, respectively, N is the CP number of A better comparison can be carried out by considering more than one parameter at the same time stages, and VDD is the power supply and power conversion efficiency. Such a comparison is reported and also includes the voltage conversion efficiency, defined as in Figure 14a,b where VCE and η vs. the output power density is reported, respectively, for all the solutions in [67], which have available data to Vbe used. By inspectionV of Figure 14a it is apparent that the VCE = out = out , (5) solution reported in [2] achieves the lowest valueVout, idof minimum(N + 1) VsupplyDD voltage (75 mV), but with one of the lowest values of VCE (50%). Consequently, its overall performance appears lower than [3,15,19] which,where Vwhileout and exhibitingVout,id are higher the actual values and of ideal minimum CP output supply voltage, voltage respectively, (100 mV, N150is mV, the CPand number 150 mV, of respectively),stages, and V DDshowis the much power higher supply values and of power VCE (91%, conversion 86% and effi ciency.80%, respectively). Such a comparison is reported in FigureAdditional 14a,b whereinformationVCE and is ηgatheredvs. the outputby inspec powertion densityof Figure isreported, 14b. Considering respectively, the forexample all the analyzedsolutions above, in [67], it which is now have apparent available that data[2] sh toows be used.better performance By inspection due of Figureto the higher14a it isvalue apparent of η andthat output the solution power reported density, in while [2] achieves occupying the much lowest mo valuere area of minimum than [3]. However, supply voltage Figure (75 14b mV), shows but that,with from one ofthe the power lowest efficiency values ofandVCE power(50%). density Consequently, point of view, its overallthe best performanceperformance appearsis achieved lower by [13,18,20].than [3,15, 19Note] which, however, while exhibitingthat [18] higheradopts values an external of minimum clock supplygenerator voltage and, (100 consequently, mV, 150 mV, andthe evaluation150 mV, respectively), of the η does show not muchtake into higher account values its ofadditionalVCE (91%, power 86% consumption. and 80%, respectively).

Figure 14. Performance comparison, (a) VCE versus minimum input voltage and (b) η versus output η Figurepower density.14. Performance comparison, (a) VCE versus minimum input voltage and (b) versus output power density. Additional information is gathered by inspection of Figure 14b. Considering the example analyzed 4.above, Conclusion it is now apparent that [2] shows better performance due to the higher value of η and output powerIn density,this work, while a review occupying of several much more solutions areathan of linear [3]. However, CP topologies Figure reported14b shows in that, literature from the is presented.power efficiency After and a powergeneral density presentation point of view,of th thee besttopologies, performance the isanalysis achieved is byfocused [13,18,20 on]. Notethe implementationhowever, that [18 of] adoptsthe power an externalmanagement clock section generator of IoT and, nodes. consequently, Historically, theevaluation the CP topologies of the η havedoes evolvednot take to into cope account with technological its additional powerprogress, consumption. thus satisfying increasingly stringent constraints given by current applications (e.g., low input voltage, high efficiency, low settling time). Quantitative 4. Conclusions comparison of the state-of-the-art reveals that the choice of a particular topology is strongly dependentIn this upon work, the a design review constraints of several an solutionsd the specific of linear technology CP topologies adopted. reported in literature is presented.Particular After attention a general must presentation be given of to the the topologies, design of the auxiliary analysis iscircuits, focused in on particular the implementation the clock generatorof the power and managementdrivers, whose section power of consumption IoT nodes. Historically, may seriously the degrade CP topologies the power have conversion evolved to efficiencycope with of technological the overall CP. progress, thus satisfying increasingly stringent constraints given by current applicationsOperation (e.g., of lowenergy input harvesting voltage, high applications efficiency, wi lowth settlingsub-100 time). mV supply Quantitative voltages comparison opens up of the the progressstate-of-the-art of new reveals CPs topologies that the choice and, mainly, of a particular on the topologyCTSs adopted. is strongly At this dependent purpose, uponthe use the of design low- thresholdconstraints devices, and the if specific available, technology can be considered, adopted. but due to their high leakage current the possible powerParticular efficiency attention reduction must should be given be taken to the into design consideration. of auxiliary On circuits, the other in particular hand, the the use clock of standard-thresholdgenerator and drivers, devices whose working power in consumption the sub-threshold may seriously region leads degrade to thereduced power capability conversion of transferefficiency charge. of the overallIn this CP.case, higher efficiency can be acquired at the cost of a large area of active devices.

Author Contributions: Conceptualization: A.B. and A.D.G.; original draft preparation: A.B.; writing, review and editing: A.D.G. and G.P.; formal analysis: all authors; supervision: A.D.G. and G.P.

Funding: This work was funded by University of Catania “ricerca di Ateneo - piano per la ricerca 2016/2018”.

Conflict of Interest: The authors declare no conflict of interest

Electronics 2019, 8, 480 12 of 15

Operation of energy harvesting applications with sub-100 mV supply voltages opens up the progress of new CPs topologies and, mainly, on the CTSs adopted. At this purpose, the use of low-threshold devices, if available, can be considered, but due to their high leakage current the possible power efficiency reduction should be taken into consideration. On the other hand, the use of standard-threshold devices working in the sub-threshold region leads to reduced capability of transfer charge. In this case, higher efficiency can be acquired at the cost of a large area of active devices.

Author Contributions: Conceptualization: A.B. and A.D.G.; original draft preparation: A.B.; writing, review and editing: A.D.G. and G.P.; formal analysis: all authors; supervision: A.D.G. and G.P. Funding: This work was funded by University of Catania “ricerca di Ateneo-piano per la ricerca 2016/2018”. Conflicts of Interest: The authors declare no conflict of interest.

References

1. Çilingiro˘glu,U.; Tar, B.; Özmen, Ç. On-Chip Photovoltaic Energy Conversion in Bulk-CMOS for Indoor Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 2014, 61, 2491–2504. [CrossRef] 2. Goeppert, J.; Manoli, Y. Fully Integrated Startup at 70 mV of Boost Converters for Thermoelectric Energy Harvesting. IEEE J. Solid-State Circuits 2016, 51, 1716–1726. [CrossRef] 3. Yi, H.; Yin, J.; Mak, P.; Martins, R.P.A 0.032-mm20.15-V Three-Stage Charge-Pump Scheme Using a Differential Bootstrapped Ring-VCO for Energy-Harvesting Applications. IEEE Trans. Circuits Syst. Ii Express Briefs 2018, 65, 146–150. [CrossRef] 4. Alioto, M. Enabling the Internet of Things: From Integrated Circuits to Integrated Systems; Springer International Publishing: Berlin/Heidelberg, Germany, 2017. 5. Tanzawa, T. On-Chip High-Voltage Generator Design: Design Methodology for Charge Pumps, 2nd ed.; Springer International Publishing: Berlin/Heidelberg, Germany, 2016. 6. Grasso, A.D.; Pennisi, S. Micro-scale inductorless maximum power point tracking DC-DC converter. Iet Power Electron. 2013, 6, 1634–1639. [CrossRef] 7. Grasso, A.D.; Palumbo, G.; Pennisi, S. Switched-Capacitor Power Management Integrated Circuit for Autonomous Internet of Things Node. IEEE Trans. Circuits Syst. Ii Express Briefs 2018, 65, 1455–1459. [CrossRef] 8. Le, H.; Sanders, S.R.; Alon, E. Design Techniques for Fully Integrated Switched-Capacitor DC-DC Converters. IEEE J. Solid-State Circuits 2011, 46, 2120–2131. [CrossRef] 9. Palumbo, G.; Pappalardo, D. Charge Pump Circuits: An Overview on Design Strategies and Topologies. IEEE Circuits Syst. Mag. 2010, 10, 31–45. [CrossRef] 10. Tanzawa, T. Innovation of Switched-Capacitor : Part 1: A Brief History. IEEE Solid-State Circuits Mag. 2016, 8, 51–59. [CrossRef] 11. Tanzawa, T. Innovation of Switched-Capacitor Voltage Multiplier: Part 3: State of the Art of Switching Circuits and Applications of Charge Pumps. IEEE Solid-State Circuits Mag. 2016, 8, 63–73. [CrossRef] 12. Fuketa, H.; O’uchi, S.; Matsukawa, T. Fully Integrated, 100-mV Minimum Input Voltage Converter with Gate-Boosted Charge Pump Kick-Started by LC Oscillator for Energy Harvesting. IEEE Trans. Circuits Syst. Ii Express Briefs 2017, 64, 392–396. [CrossRef] 13. Mahmoud, A.; Alhawari, M.; Mohammad, B.; Saleh, H.; Ismail, M. A Charge Pump Based Power Management Unit With 66%-Efficiency in 65 nm CMOS. In Proceedings of the 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 27–30 May 2018; pp. 1–4. 14. Peng, H.; Tang, N.; Yang, Y.; Heo, D. CMOS Startup Charge Pump With Body Bias and Backward Control for Energy HarvestingStep-Up Converters. IEEE Trans. Circuits Syst. I Regul. Pap. 2014, 61, 1618–1628. [CrossRef] 15. Kim, J.; Mok, P.K.T.; Kim, C. A 0.15 V Input Energy Harvesting Charge Pump With Dynamic Body Biasing and Adaptive Dead-Time for Efficiency Improvement. IEEE J. Solid-State Circuits 2015, 50, 414–425. [CrossRef] 16. Ashraf, M.; Masoumi, N. A Thermal Energy Harvesting Power Supply With an Internal Startup Circuit for Pacemakers. IEEE Trans. Very Large Scale Integr. Vlsi Syst. 2016, 24, 26–37. [CrossRef] 17. Shih, Y.; Otis, B.P.An Inductorless DC–DC Converter for Energy Harvesting With a 1.2-W Bandgap-Referenced Output Controller. IEEE Trans. Circuits Syst. Ii Express Briefs 2011, 58, 832–836. [CrossRef] Electronics 2019, 8, 480 13 of 15

18. Wang, Y.; Yan, N.; Min, H.; Shi, C.-R. A High-Efficiency Split–Merge Charge Pump for Solar Energy Harvesting. IEEE Trans. Circuits Syst. Ii Express Briefs 2017, 64, 545–549. [CrossRef] 19. Tsuji, Y.; Hirose, T.; Ozaki, T.; Asano, H.; Kuroki, N.; Numa, M. A 0.1–0.6 V input range voltage boost converter with low-leakage driver for low-voltage energy harvesting. In Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Batumi, Georgia, 5–8 December 2017; pp. 502–505. 20. Mondal, S.; Paily, R. An Efficient On-Chip Switched-Capacitor-Based Power Converter for a Microscale Energy Transducer. IEEE Trans. Circuits Syst. Ii Express Briefs 2016, 63, 254–258. [CrossRef] 21. Ulaganathan, C.; Blalock, B.J.; Holleman, J.; Britton, C.L. An ultra-low voltage self-startup charge pump for energy harvesting applications. In Proceedings of the 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), Boise, ID, USA, 5–8 August 2012; pp. 206–209. 22. Vaisband, I.; Saadat, M.; Murmann, B. A Closed-Loop Reconfigurable Switched-Capacitor DC-DC Converter for Sub-mW Energy Harvesting Applications. IEEE Trans. Circuits Syst. Regul. Pap. 2015, 62, 385–394. [CrossRef] 23. Chen, P.H.; Ishida, K.; Zhang, X.; Okuma, Y.; Ryu, Y.; Takamiya, M.; Sakurai, T. A 120-mV input, fully integrated dual-mode charge pump in 65-nm CMOS for thermoelectric energy harvester. In Proceedings of the 17th Asia and South Pacific Design Automation Conference, Sydney, NSW, Australia, 30 January–2 February 2012; pp. 469–470. 24. Cataldo, G.D.; Palumbo, G. Double and triple charge pump for power IC: Dynamic models which take parasitic effects into account. IEEE Trans. Circuits Syst. I Regul. Pap. 1993, 40, 92–101. [CrossRef] 25. Palumbo, G.; Barniol, N.; Bethaoui, M. Improved behavioral and design model of an Nth-order charge pump. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 2000, 47, 264–268. [CrossRef] 26. di Cataldo, G.; Palumbo, G. Design of an nth order Dickson voltage multiplier. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 1996, 43, 414–418. [CrossRef] 27. Palumbo, G.; Pappalardo, D.; Gaibotti, M. Charge-pump circuits: Power-consumption optimization. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 2002, 49, 1535–1542. [CrossRef] 28. Boccuni, I.; Gulino, R.; Palumbo, G. Behavioral Model of Analog Circuits for Nonvolatile Memories with VHDL-AMS. Analog Integr. Circuits Signal Process. 2002, 33, 19–28. [CrossRef] 29. Palumbo, G.; Pappalardo, D. Charge pump circuits with only capacitive loads: Optimized design. IEEE Trans. Circuits Syst. Ii Express Briefs 2006, 53, 128–132. [CrossRef] 30. Tanzawa, T.; Tanaka, T. A dynamic analysis of the Dickson charge pump circuit. IEEE J. Solid-State Circuits 1997, 32, 1231–1240. [CrossRef] 31. Tanzawa, T. An Optimum Design for Integrated Switched-Capacitor Dickson Charge Pump Multipliers With Area Power Balance. IEEE Trans. Power Electron. 2014, 29, 534–538. [CrossRef] 32. Cabrini, A.; Gobbi, L.; Torelli, G. Voltage Gain Analysis of Integrated Fibonacci-Like Charge Pumps for Low Power Applications. IEEE Trans. Circuits Syst. Ii Express Briefs 2007, 54, 929–933. [CrossRef] 33. Dickson, J.F. On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique. IEEE J. Solid-State Circuits 1976, 11, 374–378. [CrossRef] 34. Wu, J.-T.; Chang, K.-L. MOS charge pumps for low-voltage operation. IEEE J. Solid-State Circuits 1998, 33, 592–597. 35. Dickson, J.F. Voltage Multiplier Employing Clock Gated Transistor Chain. U.S. Patent US4214174A, 22 July 1980. 36. D’Arrigo, S.; Imondi, G.; Santin, G.; Gill, M.; Cleavelin, R.; Spagliccia, S.; Tomassetti, E.; Lin, S.; Nguyen, A.; Shah, P.; et al. A 5 V-only 256 kbit CMOS flash EEPROM. In Proceedings of the IEEE International Solid-State Circuits Conference, 1989 ISSCC, New York, NY, USA, 15–17 February 1989; pp. 132–133. 37. Umezawa, A.; Atsumi, S.; Kuriyama, M.; Banba, H.; Imamiya, K.I.; Naruke, K.; Yamada, S.; Obi, E.; Oshikiri, M.; Suzuki, T.; et al. A 5-V-only operation 0.6- mu m flash EEPROM with row decoder scheme in triple-well structure. IEEE J. Solid-State Circuits 1992, 27, 1540–1546. [CrossRef] 38. Atsumi, S.; Kuriyama, M.; Umezawa, A.; Banba, H.; Naruke, K.; Yamada, S.; Ohshima, Y.; Oshikiri, M.; Hiura, Y.; Yamane, T.; et al. A 16-Mb flash EEPROM with a new self-data-refresh scheme for a sector erase operation. IEEE J. Solid-State Circuits 1994, 29, 461–469. [CrossRef] Electronics 2019, 8, 480 14 of 15

39. Ansari, M.A.; Ahmad, W.; Signell, S.R. Single clock charge pump designed in 0.35µm technology. In Proceedings of the 18th International Conference Mixed Design of Integrated Circuits and Systems, Gliwice, Poland, 16–18 June 2011; pp. 552–556. 40. Mondal, S.; Paily, R.P. A strategy to enhance the output voltage of a charge pump circuit suitable for energy harvesting. In Proceedings of the 2013 Annual International Conference on Emerging Research Areas and 2013 International Conference on Microelectronics, Kanjirapally, India, 4–6 June 2013; pp. 1–5. 41. Sawada, K.; Sugawara, Y.; Masui, S. An on-chip high-voltage generator circuit for with a power supply voltage below 2 V. In Proceedings of the Symposium on VLSI Circuits, Kyoto, Japan, 8–10 June 1995; pp. 75–76. 42. Bloch, M.; Lauterbauch, C.; Weber, W. High efficiency charge pump circuit for negative generation at 2 V supply voltage. In Proceedings of the 24th European Solid-State Circuits Conference, The Hague, The Netherlands, 22–24 September 1998; pp. 100–103. 43. Zhang, X.; Lee, H. Gain-Enhanced Monolithic Charge Pump With Simultaneous Dynamic Gate and Substrate Control. IEEE Trans. Very Large Scale Integr. Vlsi Syst. 2013, 21, 593–596. [CrossRef] 44. Kleveland, B. Multi-Stage Charge Pump. Patent US6486728B2, 26 November 2002. 45. New, L.F.; Aziz, Z.A.b.A.; Leong, M.F. A low ripple CMOS charge Pump for low-voltage application. Proc. ICIAS 2012, 2, 784–789. 46. Ma, D.; Bondade, R. Reconfigurable Switched—Capacitor Power Converters; Springer: New York, NY, USA. 47. Nakagome, Y.; Tanaka, H.; Takeuchi, K.; Kume, E.; Watanabe, Y.; Kaga, T.; Kawamoto, Y.; Murai, F.; Izawa, R.; Hisamoto, D.; et al. An experimental 1.5-V 64-Mb DRAM. IEEE J. Solid-State Circuits 1991, 26, 465–472. [CrossRef] 48. Gariboldi, R.; Pulvirenti, F. A monolithic quad line driver for industrial applications. IEEE J. Solid-State Circuits 1994, 29, 957–962. [CrossRef] 49. Gariboldi, R.; Pulvirenti, F. A 70 m/spl Omega/ intelligent high side switch with full diagnostics. IEEE J. Solid-State Circuits 1996, 31, 915–923. [CrossRef] 50. Ker, M.-D.; Chen, S.-L.; Tsai, C.-S. Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes. IEEE J. Solid-State Circuits 2006, 41, 1100–1107. [CrossRef] 51. Luo, Z.; Ker, M.; Cheng, W.; Yen, T. Regulated Charge Pump with New Clocking Scheme for Smoothing the Charging Current in Low Voltage CMOS Process. IEEE Trans. Circuits Syst. I Regul. Pap. 2017, 64, 528–536. [CrossRef] 52. Favrat, P.; Deval, P.; Declercq, M.J. A high-efficiency CMOS . IEEE J. Solid-State Circuits 1998, 33, 410–416. [CrossRef] 53. Chen, P.H.; Ishida, K.; Zhang, X.; Okuma, Y.; Ryu, Y.; Takamiya, M.; Sakurai, T. 0.18-V input charge pump with forward body biasing in startup circuit using 65nm CMOS. In Proceedings of the IEEE Custom Integrated Circuits Conference 2010, San Jose, CA, USA, 19–22 September 2010; pp. 1–4. 54. Huang, W.C.; Cheng, J.C.; Liou, P.C.; Liou, C.W. A charge pump circuit using multi-staged voltage doubler clock scheme. In Proceedings of the 2007 Internatonal Conference on Microelectronics, Cairo, Egypt, 29–31 December 2007; pp. 317–320. 55. Ballo, A.; Grasso, A.D.; Giustolisi, G.; Palumbo, G. Optimized charge pump with clock booster for reduced rise time or silicon area. IEEE Tran. Circuits Syst. II: Express Briefs 2019, in press. [CrossRef] 56. Athas, W.C.; Svensson, L.J.; Koller, J.G.; Tzartzanis, N.; Chou, E.Y.-C. Low-power digital systems based on adiabatic-switching principles. IEEE Trans. Very Large Scale Integr. Vlsi Syst. 1994, 2, 398–407. [CrossRef] 57. Alioto, M.; Palumbo, G. Performance evaluation of adiabatic gates. IEEE Trans. Circuits Syst. Fundam. Theory Appl. 2000, 47, 1297–1308. 58. Lauterbach, C.; Weber, W.; Romer, D. Charge sharing concept and new clocking scheme for power efficiency and electromagnetic emission improvement of boosted charge pumps. IEEE J. Solid-State Circuits 2000, 35, 719–723. [CrossRef] 59. Keung, K.; Manne, V.; Tyagi, A. A Novel Charge Recycling Design Scheme Based on Adiabatic Charge Pump. IEEE Trans. Very Large Scale Integr. Vlsi Syst. 2007, 15, 733–745. [CrossRef] 60. Tanzawa, T.; Tanaka, T.; Takeuchi, K.; Nakamura, H. Circuit techniques for a 1.8-V-only NAND flash memory. IEEE J. Solid-State Circuits 2002, 37, 84–89. [CrossRef] 61. Palumbo, G.; Pappalardo, D.; Gaibotti, M. Charge pump with adaptive stages for non-volatile memories. IEEE Proc. Circuits Devices Syst. 2006, 153, 136–142. [CrossRef] Electronics 2019, 8, 480 15 of 15

62. Zhang, X.; Lee, H. An Efficiency-Enhanced Auto-Reconfigurable 2-/3-SC Charge Pump for Transcutaneous Power Transmission. IEEE J. Solid-State Circuits 2010, 45, 1906–1922. [CrossRef] 63. Beck, Y.; Singer, S. Capacitive Transposed Series-Parallel Topology With Fine Tuning Capabilities. IEEE Trans. Circuits Syst. I Regul. Pap. 2011, 58, 51–61. [CrossRef] 64. Ueno, F.; Inoue, T.; Oota, I.; Harada, I. Emergency power supply for small computer systems. In Proceedings of the IEEE International Sympoisum on Circuits and Systems, Singapore, 11–14 June 1991; pp. 1065–1068. 65. Gupta, A.K.; Joshi, A.; Gajare, V.; Ghanshyam, H.S.; Dutta, A. Power efficient reconfigurable charge pump for micro scale energy harvesting. In Proceedings of the 2013 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), Visakhapatnam, India, 19–21 December 2013; pp. 73–76. 66. Alioto, M.; Consoli, E.; Rabaey, J.M. ‘EChO’ Reconfigurable Power Management Unit for Energy Reduction in Sleep-Active Transitions. IEEE J. Solid-State Circuits 2013, 48, 1921–1932. [CrossRef] 67. Ballo, A.; Grasso, A.D.; Palumbo, G. Linear Charge Pumps Survey. Available online: https://bit.ly/2Ieicoe (accessed on 11 April 2019).

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