Zero-Voltage Switching Flyback- with Voltage-Doubler for High Step-up Applications

Hyun-Wook Seong, Hyoung-Suk Kim, Ki-Bum Park, Gun-Woo Moon, and Myung-Joong Youn Department of Electrical Engineering, KAIST 373-1 Guseong-dong, Yuseong-gu, Daegeon, Republic of Korea, 305-701 [email protected]

Abstract -- A zero-voltage switching (ZVS) flyback-boost (FB) output rectifier produces the high voltage spike. Thus, the converter with a voltage-doubler rectifier (VDR) has been snubber network is required across the output rectifier, which proposed. By combining the common part between a flyback results in a degraded efficiency. converter and a boost converter as a parallel-input/series-output As an attractive solution over aforementioned topologies, (PISO) configuration, this proposed circuit can increase a step- up ratio and clamp the surge voltage of switches. The secondary the flyback-boost (FB) converter was proposed as shown in VDR provides a further extended step-up ratio as well as its Fig. 1 [5], [6]. It can achieve a higher step-up ratio due to voltage stress to be clamped. An auxiliary switch instead of a both a and a parallel-input/series-output (PISO) boost diode enables all switches to be turned on under ZVS configuration. Since the voltage spike across the switch is conditions. The zero-current turn-off of the secondary VDR limited to the output voltage of the boost converter, no alleviates its reverse-recovery losses. The operation principles, protection circuit is required. Furthermore, since the energy the theoretical analysis, and the design consideration are investigated. The experimental results from a 250W and 42V-to- stored in the leakage inductance is effectively recycled and 400V prototype are shown to verify the proposed scheme. transferred to the load, a high efficiency can be achieved. However, despite of those advantageous features, the Index Terms—Zero-voltage switching (ZVS), Voltage- voltage spike across the output rectifier is inevitable. Thus, to doubler rectifier (VDR), and Step-up ratio. achieve the voltage clamping of the switch and output simultaneously, the concept of the voltage-doubler I. INTRODUCTION presented in [2], [3] can be adopted in an FB converter [7]. It The DC-DC conversion systems powered by battery can protect the output rectifiers from a high peak voltage as sources such as high intensity discharge (HID) lamps, well as provide a higher step-up ratio than an FB converter. uninterruptible power supplies (UPS), fuel cell systems, and Moreover, since the boost diode and output rectifier are LED drivers call for high-performance step-up converters [1]. turned off at zero current, the reverse-recovery losses can be The major concerns for the step-up converters are how to alleviated. Hence, among various alternatives, the FB extend a step-up ratio and how to alleviate the voltage spike converter with a VDR is one of the most attractive candidates across the switching devices led from the leakage inductance for high step-up applications. of the transformer. However, most of abovementioned circuits including the To handle the mentioned concerns, several non-isolated FB converter with a VDR suffer from considerable switching converter topologies have been proposed, since the galvanic losses due to the hard switching. It confines to increase the isolation is not the critical requirement for those applications switching frequency and to minimize the size of magnetic [1]-[6]. In [2]-[3], it has been demonstrated that the voltage- components and filter capacitors. doublers using additional diodes and capacitors on the output stage effectively contribute to extend a step-up ratio without the penalty of the extreme duty ratio and to limit the voltage stress of the output rectifiers. However, dissipative protection circuits across the switches increase the cost, losses, and design complexity. Another approach to extend a step-up ratio is using clamp-mode coupled-inductor boost converters [1], [4]. Since the leakage energy can be recycled due to the non-dissipative clamp circuits across the switch, it can achieve a high efficiency as well as protect the switch from the high peak voltage. Nevertheless, the resonance between the leakage inductance and the parasitic capacitance of the Fig. 1. Circuit diagram of the flyback-boost (FB) converter.

978-1-4244-5287-3/10/$26.00 ©2010 IEEE 823

I L C I D I lkg lkg 1:n b Cb o2 Do2 DTS (1-D)TS

Vlkg VCb IO Q1 Q2 Q1 Lm VLm Do1 IDo1 Co2 VCo2 ILm VCb/n VLm (VCo2 VCb)/n VI Ro VO Q2 IQ2 VI VCb/n VI+(VCo2 VCb)/n IQ1 Vlkg

VI-VCo1-VCb/n Q1 Co1 VCo1 VI VCo1+(VCo2 VCb)/n

I Lm Fig. 2. Circuit diagram of the proposed ZVS FB converter with VDR. Ilkg

IQ1 In order to reduce switching losses while maintaining the advantageous features, a zero-voltage switching (ZVS) FB IQ2 converter with a VDR is proposed as shown in Fig. 2. By VQ1 VCo1 using an auxiliary switch instead of a boost diode in the FB VQ2 converter, all switches can be turned on under ZVS ICb conditions. Therefore, the proposed converter can ensure the higher operating frequency, higher step-up ratio, lower IDo1 voltage stresses across the switches and output rectifiers with IDo2 an improved conversion efficiency. The operation principle VDo1 and the theoretical analysis are investigated. The VCo2 V experimental results are then presented for the verifications. Do2

t0 t1 t2 t3 t4 t5 t6 t7 II. OPERATION PRINCIPLES OF THE PROPOSED CONVERTER Fig. 3. Steady-state waveforms of the proposed converter.

Fig. 2 shows the circuit diagram of the proposed ZVS FB through the anti-parallel diode of Q1. Therefore, the zero converter with a VDR. The structure of the proposed voltage across Q1 is maintained. Since the voltage across the converter is the same as that of the FB converter except for magnetizing inductor VLm is -(VCo2-VCb)/n due to the the existence of a VDR and an auxiliary switch Q2. The VDR forward-biased output rectifier DO2, Ilkg(t) is increased is composed of a link capacitor Cb and rectifying diodes DO1 linearly as given by the following equation. and DO2. The auxiliary switch Q2 is turned on and off in a VVICoCb()/2 V n complementary way to the main switch Q . To illustrate the Ilkg()tttIt (00 ) lkg ( ) (1) 1 L steady-state operation, several assumptions are made as lkg follows: Mode 2 (t1-t2) : At t=t1, the switch Q1 is turned on under ▪ The values of the output capacitors are large enough to be ZVS conditions while its anti-parallel diode is conducting. regarded as constant voltage sources V and V . The current Ilkg(t) continuously increases with the slope Co1 Co2 expressed in (1) and reaches the magnetizing inductor current ▪ The link capacitor Cb is kept on being charged with a constant voltage V . at t2. It means that the rectifier DO2 is turned off at zero Cb current, which can alleviate the reverse-recovery problem. ▪ The magnetizing current I is always positive. Lm Mode 3 (t -t ) : At t=t , the diode D is turned off. After ▪ The leakage inductor L is much less than the magnetizing 2 3 2 O2 lkg that, the diverted current through the transformer charges the inductor Lm. junction capacitor of D to V and discharges that of D Fig. 3 and Fig. 4 illustrate the steady-state waveforms and O2 Co2 O1 to 0V for a short time, respectively. Then, it flows through topological states of the proposed converter, respectively. To the output rectifier D to charge the link capacitor C . present the operation of each mode sequentially, it is assumed O1 b Because the applied voltage across Lm is VCb/n, the current that the switch Q1 was turned off and the switch Q2 was Ilkg(t) can be expressed as follows: turned on before t0. Due to an auxiliary switch Q2, the VVICb / n regenerated current from the output capacitor CO1 flows to Ilkg()tttIt (22 ) lkg ( ) (2) the input source. Thus, the direction of the primary current Llkg Ilkg(t) is reversed with a negative slope before t0. Mode 4 (t3-t4) : At t=t3, the switch Q1 is turned off. The Mode 1 (t0-t1) : At t=t0, the switch Q2 is turned off. The current Ilkg(t) charges the junction capacitor of Q1 to VCo1 and primary leakage current Ilkg(t) charges the junction capacitor discharges that of Q2 to 0V rapidly. Then, it flows through of Q2 to VCo1 and discharges that of Q1 to 0V, respectively in the anti-parallel diode of Q2. Since the voltage across Q1 is a resonant manner for a very brief time. Then, it flows clamped to VCo1 due to the anti-parallel diode of Q2, no

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(a) (b) (c)

(d) (e) (f)

(g)

Fig. 4. Topological states of the proposed converter (a) Mode 1 (t0-t1), (b) Mode 2 (t1-t2), (c) Mode 3 (t2-t3), (d) Mode 4 (t3-t4), (e) Mode 5 (t4-t5), (f) Mode 6 (t5-t6), and (g) Mode 7 (t6-t7).

protection circuit is required and the conduction loss can be off at t7. The reverse-directed current Ilkg(t) flows to the input reduced by using lower voltage-rated power switches. The source. conducted anti-parallel diode provides the zero voltage across Q2 until the next mode. The current Ilkg(t) can be easily III. ANALYSIS AND DESIGN CONSIDERATION OF THE PROPOSED obtained as follows: CONVERTER

VVICoCb1 V/ n Ilkg()tttIt (33 ) lkg ( ) (3) A. Step-up Ratio L lkg Due to the series-output configurations, each output Mode 5 (t -t ) : At t=t , the switch Q is turned on under 4 5 4 2 capacitor voltage is put together and the overall output ZVS conditions. The current I (t) continuously decreases lkg voltage is extended as until it reaches the magnetizing current at t5. Since, at t5, the VVOCoCo 12 V. (5) rectifier DO1 is turned off at zero current, the reverse- recovery losses can be reduced. By imposing the node equations across the output capacitor Co2, the steady-state output current equation can be Mode 6 (t5-t6) : At t=t5, the diode DO1 is turned off. After that, the diverted current through the transformer charges the derived as I  It()  I () t  , (6) junction capacitor of DO1 to VCo2 and discharges that of DO2 OQ22 Do to 0V for a short time, respectively. Then, it results in where <*> denotes the average value of *. conducting the output rectifier DO2 and discharging the link As a matter of convenience to derive the step-up ratio, the capacitor Cb. The applied voltage across Lm is -(VCo2-VCb)/n relatively narrow intervals, t0-t2 and t3-t5, are assumed to be and the current Ilkg(t) can be expressed as follows: zero and the ripple-free current ILm(t) is assumed. Figure 5

VVICoCoCb12()/ V  V n shows the simplified current waveforms under these Ilkg()tttIt (55 ) lkg ( ) (4) Llkg assumptions. By applying the volt-second balance rule on Llkg and Lm and the current-second balance rule on Cb while Mode 7 (t6-t7) : The current Ilkg(t) reaches zero at t6 and considering (5) and (6), the step-up ratio of overall system, M, keeps the negative slope as (4) until the switch Q2 is turned

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The step-up ratio of the proposed converter is higher than that of the flyback and FB converter as shown in Fig. 6 (a). Figure 6 (b) shows the step-up ratio M according to Q variations depending on the leakage inductor, output current, and switching frequency fS. As shown in this figure, since the overall step-up ratio M falls as Q increases, the turns-ratio n and the nominal duty ratio D should be selected by considering the damping effect of Q. In practice, because the value of the leakage inductor is a dominant factor affecting the effect of Q, a smaller leakage inductor is preferable to the higher step-up ratio. However, for a different point of view, the value of the leakage inductor should be higher than the designated value for the ZVS of all switches as will be presented in following section. Fig. 5. Simplified current waveforms. B. ZVS Conditions To achieve the ZVS of the switch Q , the energy stored in can be found as 1 the leakage inductor at t0 must be large enough to fully V n 1 O , (7) charge and discharge the junction capacitor of Q2 and Q1, M  2 VI 2n respectively, before the switch Q1 is turned on. Following 1D 2 Q D equations are the ZVS conditions of the switch Q1. where the dimensionless parameter Q is defined as (L f )/R . 22 lkg S O 0.5LIlkg lkg ( t0121 ) 0.5( C OSS C OSS ) V Co (8) Provided that Q is small enough, M can be approximated to 2n VO (n+1)/(1-D) which can represent the step-up ratio of the Itlkg ()0  ( M ) (9) classical boost converter when n=0. 1 D RO COSS1 and COSS2 denote the junction capacitor of Q1 and Q2, respectively. Similarly, the ZVS conditions of the auxiliary switch Q2 can be found as 22 0.5LIlkg lkg ( t3121 ) 0.5( C OSS C OSS ) V Co (10)

2n VO Itlkg ()3  ( M ) . (11) D RO To assure the ZVS of all switches, (8) should be satisfied. Step-up Ratio Ratio Step-up The desired leakage inductor which decides the ZVS range according to the load current ratio can be determined as shown in Fig. 7.

0.60

(a) 0.55 25 0.50 V / V O I 0.45 20 VCo2 / VI V / V Co1 I 0.40 Zero-Voltage Switching Q= 0.109 X10-4 Q= 1.094 X10-4 -4 0.35 15 Q= 4.375 X10 Q= 7.656 X10-4 Q=10.937 X10-4 0.30 10 0.25

M=9.52 0.20 L =10μH 5 D=0.61 lkg I =0.15A (25% load) 0.15 Hard Switching O

0 0.10 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 024 6810 12 14 16 18 20 Duty Ratio (D) Leakage inductor for ZVS (μH) (b) Fig. 6. Step-up ratio when n=3.5 (a) Comparison of the step-up ratios when Q=0 and Fig. 7. Minimum load current for the ZVS of all switches according to (b) VCo1/VI, VCo2/VI, and VO/VI according to Q variations. the leakage inductor.

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C. Output Capacitors CO1 and CO2 By calculating the quantity of electric charge or discharge on C and C with assumptions used in Section III-A, the ) O1 O2 O voltage ripple of each output capacitor can be derived as /I

follows: Q_max. V n Co1  (12) VDRCfOOOS4 1 V (1 D ) 2 Co2  . (13) Normalized current stress current Normalized of the switches (I switches the of VRCfOOOS4 2 The overall output voltage ripple is smaller than the sum of (12) and (13). From this fact, CO1 and CO2 can be selected while satisfying desired voltage ripple conditions. (a) 22 D. Link Capacitor Cb 20 With the same process used in the selection of the output 18 capacitors, the necessary value of the link capacitor can be 16 determined from the following voltage ripple equation. 14 V 1 Cb  (14) 12 VRCfOObS 10 IDo2_max.=3.2A 8 @ full load E. Device Stresses 6 IDo1_max.=2.0A Since the maximum current of the switch Q1 or Q2 is equal 4 @ full load to that of the primary leakage current at t3, i.e., Ilkg(t3), the 2 current stress of the switches can be inferred as (15). 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Duty Ratio (D) 2n V O (15) (b) IIQQ1_ max . 2 _ max . () M Fig. 8. Normalized current stresses D RO (a) IQ_max./IO according to n and Q variation and (b) IDo1_max./IO and Meanwhile, the maximum currents of the output rectifiers IDo2_max./IO. DO1 and DO2 are the peak absolute values of the secondary link capacitor current as given by following equations. 2V IV. EXPERIMENTAL RESULTS I  O (16) Do1_max. To verify the validity of the proposed circuit and analysis, DRO a 250W prototype converter is implemented with design 2VO IDo2_max.  (17) specifications and circuit parameters as indicated in Table I. (1 D ) RO Fig. 8 shows the current stresses of the devices normalized by the output current. As can be seen in Fig 8(a), the current TABLE I stress of the switches relies on the transformer turns-ratio n, DESIGN SPECIFICATIONS AND CIRCUIT PARAMETERS the duty ratio D, and the previously defined parameter Q. As Input Voltage, VI 42V n increases, both current stresses of switches increase. The Output Voltage, VO 400V current stress of the switches consists of ILm and nIDo1, where Maximum Output Power, PO_max. 250W ILm increases and IDo1 decreases as the duty ratio increases. Thus, the current stress of the switches is parabolic in shape. Switching Frequency, fS 70kHz

In addition, the current damping effect also appears due to NP : NS 18 : 63 (n=3.5) the parameter Q. Fig. 8(b) plots the current stress of the Transformer Lm 280μH output rectifiers. As the duty ratio increases, the current stress Llkg 10μH of Do1 decreases and that of Do2 increases. The current stresses of the proposed converter are actually lower than the Link Capacitor, Cb 8.8μF/630V indicated values in Fig. 8 due to the assumptions in section Output Capacitors, CO1 and CO2 100μF/400V III-A. It is clear that the voltage stresses of the switches and FQA38N30 (38.4A/300V) Power Switches, Q1 and Q2 output rectifiers are VCo1 and VCo2, respectively, because the RDS(on)= 85mΩ and COSS=670pF switches and output rectifiers can be clamped to VCo1 and Rectifiers, DO1 and DO2 FFP04U40DN (4A/400V) VCo2.

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(a) (a)

(b) (b)

(c) (c) Fig. 9. Key experimental waveforms at the full load (a) primary leakage current and secondary blocking capacitor current, (b) current and voltage waveforms of the switches, and (c) current and voltage waveforms of the output rectifiers.

Fig. 9 indicates the key experimental waveforms of the prototype converter at the full load, which are well coincided with aforementioned theoretical results. Fig. 9(a) shows the primary leakage current and secondary link capacitor current of the prototype converter. Fig. 9(b) shows current and voltage waveforms of the switches and Fig. 9(c) shows the current and voltage waveforms of the output rectifiers. As can be seen in these figures, the voltages across the switches (d) and output rectifiers are well clamped to VCo1 and VCo2, Fig. 10. ZVS waveforms of the switches respectively, and a zero current turned-off of each output (a) Q1 at full load, (b) Q1 at half load, (c) Q2 at full load, and (d) Q2 at half load. rectifier is also achieved. Fig. 10 shows that the switches Q1 and Q2 are turned on after VQ1 and VQ2 drop to 0V, i.e., the ZVS of all switches is achieved. With the values of the in the experiment, the ZVS of all switches is guaranteed from leakage inductor and junction capacitors of the switches used 25% to 100% load conditions. Fig. 11 shows the measured

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Resonant Elements,” Journal of Power Electronics, vol. 10, no. 2, pp. 107-114, March, 2010. [9] Sang-Kyoo Han, Hyun-Ki Yoon, Gun-Woo Moon, Myung-Joong Youn, Yoon-Ho Kim, and Kang-Hee Lee, “A New Active Clamping Zero- Voltage Switching PWM Current-Fed Half-Bridge converter,” IEEE Transactions on Power Electronics, vol. 20, no. 6, pp. 1271-1279, Nov, 2005.J. F. Fuller, E. F. Fuchs, and K. J. Roesler, "Influence of harmonics on power distribution system protection," IEEE Trans. Power Delivery, vol. 3, pp. 549-557, Apr. 1988. Efficiency (%)

Fig. 11. Measured efficiency. efficiency compared to the FB converter with a VDR according to the output power. The efficiency improvement by using an auxiliary switch to obtain the ZVS turn on is noticeable in the ZVS load range.

V. CONCLUSION In this paper, the ZVS FB converter with a VDR has been proposed. Its auxiliary switch can not only absorb the voltage surge across the turned-off switch, but achieve the ZVS of all switches as well. The circuit configuration of the proposed converter can extend a step-up ratio without the penalty of the extreme duty ratio. The VDR also alleviates the reverse- recovery losses of the output rectifiers. The experimental results demonstrate that the proposed converter can improve the overall efficiency because of those advantageous features. As a result, the proposed converter is well suited for high frequency step-up applications.

REFERENCES [1] Qun Zhao and F. C. Lee, “High-Efficiency, High Step-up DC-DC Converters,” IEEE Transactions on Power Electronics, vol. 18, no. 1, pp. 65-73, Jan, 2003. [2] Marcos Prudente, Liciano L. Pfitscher, Gustavo Emmendoerfer, Eduardo F. Romaneli, and Roger Gules, “ Cells Applied to Non-Isolated DC-DC Converters,” IEEE Transactions on Power Electronics, vol. 23, no. 2, pp. 871-887, March, 2008. [3] R. D. Middlebrook, “Transformerless dc-to-dc Converters with Large Conversion Ratios,” IEEE Transactions on Power Electronics, vol. 3, no. 4, pp. 484-488, Oct, 1988. [4] R. J. Wai and R. Y. Duan, “High Step-up Converter with Coupled Inductor,” IEEE Transactions on Power Electronics, vol. 20, no. 5, pp. 1025-1035, Sep, 2005. [5] T. J. Liang and K.C. Tseng, “Analysis of Integrated Boost-Flyback Step-up Converter,” in IEE Proceeding of Electric Power Applications, vol. 152, no. 2, pp. 217-225, March, 2005. [6] T. Dumrongkittigule, V. Tarateeraseth, and W. Khan-ngern, “A New Integrated Inductor with Balanced Switching Technique for Common Mode EMI Reduction in High Step-up DC/DC Converter,” in Proceeding of 17th International Zurich Symposium on Electromagnetic Compatibility, pp. 541-544, Feb, 2006. [7] Ju-Won Baek, Myung-Hyo Ryoo, Tae-Jin Kim, Dong-Wook Yoo, and Jong-Soo Kim. “High Boost Converter Using Voltage Multipler,” in Proceeding of IECON 2005 31th Annual Conference of IEEE, pp. 567- 572, Nov, 2005. [8] Sung-Soo Hong, Sang-Keun Ji, Young-Jin Jung, and Chung-Wook Roh, “Analysis and Design of a High Voltage Flyback Converter with

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