High Efficiency Charge Pump Circuit for Negative High Voltage Generation at 2 V Supply Voltage
Total Page：16
File Type：pdf, Size：1020Kb
100 High Efficiency Charge Pump Circuit for Negative High Voltage Generation at 2 V Supply Voltage Martin Bloch Christ1 Lauterbach, Werner Weber Siemens AG, HL DC E EM Siemens AG, ZT ME 2 St. -Martin-Str. 76, 0-8154IMiinchen Otto-Hahn-Ring 6, 0-81730 Miinchen martin. [email protected] christl,[email protected],de [email protected] Abstract A charge pump circuit has been developed for 2. Chargepump principles the generation of negative high voltage at supply voltage levels down to 2K The generated high vol- The well-known Dickson circuit [3] consists of tage is suitable for programming Flash EEPROM asimple diode chain and two alternatingpump cells, that use Fowler-Nordheim tunneling. The key pulses at the pump capacitors. The voltage gain at issue of the circuit design has been high eflciency each stage is reduced by the forward voltage of the and small chip area. The circuit consists of n-MOS diode. Charge pumps using transfer gates with V, transfer gatesin a triple-well structure and is cancellation [4] avoidthe loss of the threshold driven by a four phase clocking scheme. The power voltage at each stage and increase the efficiency of eflciency of acharge pump, designed for low thesevoltage generators at the cost of amore power applications, is better than 25% at an output complicated clocking scheme. One approach for the power of IOOpW, including clock generation and generationof negative high voltage is acharge voltage regulation. pump with p-MOS transfer gates [4]. The common n-well of the p-MOS transfer gates is zero biased. 1. Introduction Therefore, the body effect increases with each stage ofthe charge pump and limits the attainable Thegrowing demand for lowvoltage battery negative output voltage. operation in theportable applications market, requiresFlash EEPROMs with low powercon- sumption and supply voltage. Several works have been reported on 3V-only Flash memories [ 1,2]. In order to reducepower consumption significantly, programming and erase operations are usually per- formedby the Fowler-Nordheim (FN) tunneling effect.FN has the advantage oflow power dissipation and the drawback of long program and erasetimes, in therange of several ms. For the generation of the required high voltages small and efficient charge pumps are necessary. Duringpage erase mode in FlashEEPROMs, the gate of the EEPROM cell, with a tunnel oxide thickness of 9 nm and an ON0 dielectric of 21 nm between the floating gate and the control gate, is biased at a positive high voltage (16V), with source and drain of the EEPROM cell at OV. The program operation is performednegativeby gate programming (-12V). This method requires a zero biased source and a positively biased drain (5V). In thisprogram mode, the highband-to-band tunneling, observed in 12V source programming, is reduced. In this work a charge pump is proposed, for the Figure 1. Negativecharge pump with n-MOS generation of the discussed negative voltage at a transfer gates and four phase clocking scheme supplyvoltage level of 2V, withhigh efficiency, suitable for low power applications. 101 The use of n-MOS transfer gates in triple-well the effective clock voltage and is reduced by technologyresults in adistinct reduction of the '/US,? ' body effect. In [5] a negative chargepump is proposed for generating -9.5V for the wordline of a 8Mbx16 NOR Flash memory. Thecircuit uses (2) intrinsic n-channel transistors in a triple-well and is is reduced in comparison with the clock voltage driven by a four phase clocking scheme (Figure 1). $, according to (3). In order to reduce the body effect, the common p- well(Vp) is pumpeddown to low voltage.The diode connected transistors Dl and D2 help starting 4eff = - 4 cp /( cp+ Cb + cpar, (3) up the pump and also support the discharging. The clocking scheme comprises two overlapping clocks C, is the capacitance of the pump capacitor, Ch the $1 and $2 for charge pumping and two clocks $bl capacitanceof the boost capacitorand CPGrthe and $b2 forboosting the gates during charge parasiticcapacitance, which is mainlyoriginating transfer. from the pn-junction of the p-well and the n-well in During a first pump cycle, $2 couples node N1 the triple-well transistor. V,,,,, depends on the out- to low level. While $1 is high, the precharge tran- put current, the clock frequencyf and Cp: sistor Tbl and transistorT2 are turned off. Transistor Tb2 is turnedon and nodeM2 is Vloss = - IOU* / (f cpI (4) precharged. Then, during the boost cycle, the boost clock $lb couples theprecharged node M1 to a Oncondition V,,,v,,2 Vng, theparasitic bipolar higher voltage and transistor T1 passes the negative transistor within the triple-well scheme turns on and charge from node N 1 to node N2. theoutput of the chargepump is connected to In the course of the next pump cycle, $ 1 couples ground. This fact has been shown by experimental node N2 to low level, the precharge transistor Tb2 evidence and circuit simulation. The diode connec- andtransistor T1 areturned off,while transistor ted transistor Dl in Figure 1 has the same forward Tbl is turnedon and precharges node M1. The voltage as the emitter base diode and therefore does boost clock $2b then couples the precharged node not reliablyprevent the bipolartransistor from M2 to a higher voltage and transistor T2 passes the switching. negative charge from node N2to the nextstage. Simultaneously, to this pump cycle, $2 couples 3. Negative charge pump with p-well node N1 to a high leveland, as our experiments have shown, likely causes a forward bias Vn, of the switching emitterbase diode of the parasitic n'pn-bipolar transistorwithin the triple-well(Figure 2). We The proposed new charge pump circuit, shown found,that this forward biascorrelates with the in Figure 3, can avoid this parasitic effect. voltage loss V,,,,s,s,which is due to the output current of the pump stage. 4bl 4b2 1- Cbl I p-substrate I Figure 2. Triple-well n-MOS transistor with parasitic n'pn-bipolar transistor Figure 3. Negative charge pump with n-MOS transfer gates and p-well switching In general,the output voltage V,Jlll of the negative chargepump with n stagescan be The functionsof the charge transfer (Tl, T2) described by the followingequations: and the boost transistors (Tb 1, Tb2) correspond to that of the charge pump circuit in Figure 1 and the identicalclock scheme is used. The n-well in the charge pump is kept at OV. Two n-MOS transistors (Tcl and Twl) are implemented forpermanently The voltage gain Vguinof a pump stage depends on keepingthe p-well atthe lowest voltage level 102 within the pump stage. The drain of Twl is con- higheroutput voltage cangeneratedbe by nected to node N2 and the drain of Tcl to N1. The increasing the number of pump stages, without any sourcesof both transistors are connected to the loss of voltage gain. Since the parasitic capacitance commonp-well of the pump stage. The gates of of the p-wells is not included in the simulation, the Tcl and Tw 1 are crosswise connected to N2 and measuredoutput voltage remains below the N1, respectively. Transistor Twl turns on, when the simulatedvalues at higherload resistance. The voltage at node N1 is on a higher level. This is the higher output current with smaller load resistors can case, when $1 and $2 are both high. During charge be explained by improved transistor on-resistance. pumping, transistor Tcl does not contribute to the 22 charge transfer to and from the p-well, but reduces 20 ................... the p-well voltage below the voltage at the nodes n N1 or N2 solely by capacitive coupling. 18 ................................. I................. ..... ....... .................... 4. Experimental results A negativecharge pump circuit, according to theprinciple in Figure 3 andsuitable for supply voltages down to 2V, has been designed. The key issue of the design was to minimize chip area. For ............... ............. ......... fabrication of thedevices, a 0Sym triple-well ..................... CMOS process with two metal layers and two poly- ............. .......... siliconlayers was used. Thecapacitors were 0 fabricated by aseries connection of two polyl- 0 1 2 3 4 5 ONO-poly2structures, for reducingthe electric field over the dielectric (ONO). supply voltage (V) Simulatedand measured output characteristics of a negative charge pump with seven pump stages Figure 5. Negative output voltage versus are depicted in Figure 4. supply voltage (seven pump stages, Cp=2pF, 14 output resistance 2 MR, clock frequency 1OMHz) 12 2 The comparison of the simulated and measured negative output voltage of the charge pump versus the supply voltage is shown in Figure 5. Simulated ............. ...........~ ......................... .- andmeasured data are in goodagreement. Ata 0 supply voltage of 2 V, a load resistance of 2 MR ................; ....................... ;........... ~ ..........,..... .......................... and a clock frequency of 10 MHz, the charge pump shows -9V output voltage. The output limitation at -18 V is due to maximum reverse bias of the pn- junctionbetween p-well and n-well. Below a supplyvoltage of 1.8V theperformance of the Ai charge pump decreases rapidly, due to the relatively 01 high threshold voltage (approx. l.0V) of the high- 0 2 4 6 8 10 voltage n-MOS transistors used. negative output current (FA) Figure 4. Comparison of the simulated and measured output characteristic of a negative charge pump (seven stages, Cp=2pF, clock frequency 1OMHz) For the charge pump circuit pump capacitors of 2 pF,boost capacitors of 100 fF andaclock frequency of 10 MHz are used. The input voltage is OV andthe supply voltage 2V. The charge pump has a maximum output voltage of - 1 1.5V and an Figure 6. Micrograph of one stage of the output resistance of 900kR. A higher output current proposed negative charge pump with a 100fF can beachieved by larger pump capacitors.