Masters Thesis: Wideband PLL System As a Clock Multiplier

Master of Science Thesis Wideband PLL System as a Clock Multiplier Aylin Donmez August 17, 2009 Wideband PLL System as a Clock Multiplier Master of Science Thesis For obtaining the degree of Master of Science in Electrical Engineering at Delft University of Technology Aylin Donmez August 17, 2009 Faculty of Electrical Engineering · Delft University of Technology Delft University of Technology Copyright c Electrical Engineering, Delft University of Technology All rights reserved. DELFT UNIVERSITY OF TECHNOLOGY DEPARTMENT OF MICROELECTRONICS The undersigned hereby certify that they have read and recommend to the Faculty of - Electrical Engineering for acceptance the thesis entitled \Wideband PLL System as a Clock Multiplier" by Aylin Donmez in fulfillment of the requirements for the degree of Master of Science. Dated: August 17, 2009 Supervisors: Prof. dr. J. Long Ir. Gerard Lassche Ir. Frans Sessink Ir. Kave Kianush Summary In this study, the theory, design and analysis of PLL circuits are examined and a 4:9GHz ∼ 5:9GHz Wideband CMOS PLL Frequency Synthesizer is designed and implemented in IBM 65nm digital-process. The objective of this thesis work is to understand the limitations in Wideband PLL systems when the application frequency range extends to multiple gigahertz. This study explores the inband noise contribution of PLL blocks and also investigates solutions to high frequency operation of phase frequency detectors and charge pumps. A high frequency phase-frequency detector topology is presented. With this topology, static phase error of the loop remains close to zero even if the charge-pump has a large amount of current mismatch. A design which is capable correct operation up to a frequency 1.74 GHz is designed. A high frequency differential charge pump circuit with glitch suppression is presented. The VCO of the PLL is implemented with a mutlipath loop ring oscillator. The VCO has a better supply noise performance compared to conventional ring oscillators but however it is still not suitable for applications with noisy supply, thus off chip supply decoupling is used. VCO operates within 4:79GHz ∼ 6:54GHz for all process corners. The frequency divider which is used from project library has a constant division ratio of 6. Entire PLL design consumes 14.9 mW from 1.2 V supply, under typical conditions. Total area of the PLL is 1 mm x 800 um including the pads. M.Sc. thesis Aylin Donmez ii Summary Aylin Donmez M.Sc. thesis Acknowledgments The past two years I have spent at TU Delft have been a fabulous journey mostly because of the amazing people I have met, who have been a part of it. I feel to have built a great knowledge and perspective both in my career and social life. First and foremost, I would like to thank my company supervisors, Gerard Lassche and Frans Sessink whose support was always available when needed. I am grateful to Gerard Lassche for his inestimable guidance and interest in the project. His significant contribution during the layout design has been a priceless support. I would like to thank Frans Sessink for his valuable assistance on system level analysis of PLL, and his trainings on frequency domain loop analyses in Simetrix have been informative. I would also like to thank Kave Kianush for giving me this opportunity and sponsoring the project. I am grateful to valuable inputs and reviews of Prof. John Long as a university supervisor, during the design reviews. I also wish to thank some of the other excellent engineers of Catena Microelectronics who have shaped my point of view on various design phases. I am grateful to Koen van Hartingsveldt for his precious guidance regarding to RF perspective of the system. I am especially thankful to Nicole Eisenberg, Ivaylo Bakalski and Mattias Wallberg for resolving countless issues and being excellent admins during the layout design. I would like to thank Atze van der Goot, for providing the assistance to get my design processed. I am also thankful to Hans Rosenberg for his support on test board design. Words cannot express my gratitude to my dear friend Serpil Sevilay Senturk, for her constant love, support, and understanding. I can only hope to preserve our heartfelt relationship. My warmest thanks also go to Tuba Yilmaz, Unal Kocabas, Ibrahim Over for their support, great friendship, and many wonderful memories. I am truly lucky to have made great friends such as Remziye Nasuhoglu, Guner Arici, Burak Sozgen and Cigdem Demirel with whom we have set up the innovative institution More en de Ruif that basically offers fun activities and moral support services. Finally, I would like to express my enormous thanks to my mother Muruvvet Donmez, my father Ibrahim Donmez, my sister Pervin Donmez, and the rest of my family. No matter how far away they may be physically, they are never far from my heart and mind. All my endeavors are to deserve their boundless love and support without which I would never have had the strength and courage to pursue my dreams, and for that I dedicate this thesis to them. M.Sc. thesis Aylin Donmez Table of Contents Summary i Acknowledgments iii 1 Introduction 1 1.1 Project Description . 1 VCO Pulling Avoidance . 2 Response of a PLL system to VCO Pulling . 4 1.2 Report Outline . 4 2 Background 5 2.1 WideBand PLL Basics . 5 2.2 Noise . 6 2.2.1 Interference Noise . 6 2.2.2 Intrinsic Noise . 6 2.3 Noise in Wideband PLLs . 6 2.3.1 Phase Noise Definition . 7 2.3.2 Frequency Domain Noise Analysis . 8 Input Reference Noise . 8 Phase Detector Noise . 9 Noise Injected to Loop by Charge Pump . 9 Noise on Control Line . 11 VCO Noise . 13 Divider Noise . 14 PLL Total Output Phase Noise . 15 2.4 Time Domain Noise Analysis . 15 2.4.1 Jitter Metrics . 16 2.4.2 Time Domain and Frequency Domain Noise Relation . 18 M.Sc. thesis Aylin Donmez vi Table of Contents 3 PFD & Charge Pump 19 3.1 Phase Frequency Detectors . 19 3.1.1 Multiplier Phase-Detectors . 20 3.1.2 XOR Phase Detector . 21 3.1.3 Tri State Conventional Phase Detector . 22 3.1.4 High Frequency Limitations of Conventional Phase Detectors . 22 3.1.5 Dynamic Logic Phase Detectors . 25 3.1.6 Phase Frequency Detector Design . 27 3.2 Charge Pumps . 31 3.2.1 Current and Pulsewidth Mismatch . 31 3.2.2 Timing Mismatch . 31 3.2.3 Leakage Current . 32 3.2.4 Charge Injection . 33 3.2.5 Clock Feedthrough . 34 3.2.6 Charge Sharing . 34 3.2.7 Charge Pump Architectures . 34 Single-ended charge pumps . 34 Differential Charge Pumps . 36 3.2.8 Differential Charge Pump Design . 36 Switch Design . 37 Common Mode Feedback Circuit . 38 Unity Gain Buffer Circuit . 43 Bias Block . 44 Glitch Suppression . 46 4 VCO & Divider 51 4.1 Ring Oscillator VCOs . 52 4.1.1 Single Loop Ring Oscillator Design . 53 4.1.2 Multi Loop Ring Oscillator Design . 55 Odd Number of Stages . 55 Even Number of Stages . 58 4.1.3 Loop Architecture Decision . 59 4.2 Gain Stages . 59 4.2.1 CMOS Digital Inverter . 60 4.2.2 Differential Pair . 61 4.2.3 Delay Cell with push pull inverters (DC1)[12] ............... 62 4.2.4 Delay Cell with feedback control (DC2)[24] ................ 64 4.2.5 Delay Cell with common mode noise rejection (DC3)[15] ......... 66 4.3 Delay Cells Performance List . 68 4.4 Ring Oscillator Design . 68 4.4.1 VCO Tuning Range . 70 4.5 Layout of the VCO . 73 4.6 Divider Performance . 73 Aylin Donmez M.Sc. thesis Table of Contents vii 5 Top Level 77 5.1 Loop Parameters . 77 5.2 Wideband PLL Characteristics Validation . 85 5.2.1 Loop Bandwidth . 85 5.2.2 Phase Noise Measurement and Other Design Metrics . 85 6 Conclusion and Recommendations 87 6.1 Conclusions . 87 6.2 Future Work . 87 A PLL Basics 89 A.1 PLL Dynamics . 89 A.1.1 Loop Order and Loop Type . 90 A.1.2 Loop response to a step change in phase . 91 A.1.3 Loop response to a step change in frequency . 92 Bibliography 95 M.Sc. thesis Aylin Donmez viii Table of Contents Aylin Donmez M.Sc. thesis List of Figures 1.1 VCO Pulling in transceiver systems . 2 1.2 LO generation from a low frequency reference . 2 1.3 LO generation with injection locked mixing . 3 1.4 LO Generation with a PLL system . 3 2.1 PLL Loop Basic Components . 5 2.2 Noise Contributers in the Loop . 7 2.3 Output spectrum of an ideal oscillator . 8 2.4 Phase noise definition . 8 2.5 Input reference noise contribution . 9 2.6 Phase frequency detector noise contribution . 10 2.7 Charge pump noise contribution . 11 2.8 Control line noise contribution . 12 2.9 VCO noise contribution . 13 2.10 Divider noise transfer function . 14 2.11 Total output noise . ..

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