Masters Thesis: Wideband PLL System As a Clock Multiplier

Master of Science Thesis

Wideband PLL System as a Clock Multiplier

Aylin Donmez

August 17, 2009

Wideband PLL System as a Clock Multiplier

Master of Science Thesis

For obtaining the degree of Master of Science in Electrical Engineering at Delft University of Technology

Aylin Donmez

August 17, 2009

Faculty of Electrical Engineering · Delft University of Technology Delft University of Technology

The undersigned hereby certify that they have read and recommend to the Faculty of - Electrical Engineering for acceptance the thesis entitled “Wideband PLL System as a Clock Multiplier” by Aylin Donmez in fulﬁllment of the requirements for the degree of Master of Science.

Dated: August 17, 2009

Supervisors: Prof. dr. J. Long

Ir. Gerard Lassche

Ir. Frans Sessink

Ir. Kave Kianush

Summary

In this study, the theory, design and analysis of PLL circuits are examined and a 4.9GHz ∼ 5.9GHz Wideband CMOS PLL Frequency Synthesizer is designed and implemented in IBM 65nm digital-process. The objective of this thesis work is to understand the limitations in Wideband PLL systems when the application frequency range extends to multiple gigahertz. This study explores the inband noise contribution of PLL blocks and also investigates solutions to high frequency operation of phase frequency detectors and charge pumps. A high frequency phase-frequency detector topology is presented. With this topology, static phase error of the loop remains close to zero even if the charge-pump has a large amount of current mismatch. A design which is capable correct operation up to a frequency 1.74 GHz is designed. A high frequency diﬀerential charge pump circuit with glitch suppression is presented. The VCO of the PLL is implemented with a mutlipath loop ring oscillator. The VCO has a better supply noise performance compared to conventional ring oscillators but however it is still not suitable for applications with noisy supply, thus oﬀ chip supply decoupling is used. VCO operates within 4.79GHz ∼ 6.54GHz for all process corners. The frequency divider which is used from project library has a constant division ratio of 6. Entire PLL design consumes 14.9 mW from 1.2 V supply, under typical conditions. Total area of the PLL is 1 mm x 800 um including the pads.

M.Sc. thesis Aylin Donmez ii Summary

Aylin Donmez M.Sc. thesis Acknowledgments

The past two years I have spent at TU Delft have been a fabulous journey mostly because of the amazing people I have met, who have been a part of it. I feel to have built a great knowledge and perspective both in my career and social life. First and foremost, I would like to thank my company supervisors, Gerard Lassche and Frans Sessink whose support was always available when needed. I am grateful to Gerard Lassche for his inestimable guidance and interest in the project. His signiﬁcant contribution during the layout design has been a priceless support. I would like to thank Frans Sessink for his valuable assistance on system level analysis of PLL, and his trainings on frequency domain loop analyses in Simetrix have been informative. I would also like to thank Kave Kianush for giving me this opportunity and sponsoring the project. I am grateful to valuable inputs and reviews of Prof. John Long as a university supervisor, during the design reviews. I also wish to thank some of the other excellent engineers of Catena Microelectronics who have shaped my point of view on various design phases. I am grateful to Koen van Hartingsveldt for his precious guidance regarding to RF perspective of the system. I am especially thankful to Nicole Eisenberg, Ivaylo Bakalski and Mattias Wallberg for resolving countless issues and being excellent admins during the layout design. I would like to thank Atze van der Goot, for providing the assistance to get my design processed. I am also thankful to Hans Rosenberg for his support on test board design. Words cannot express my gratitude to my dear friend Serpil Sevilay Senturk, for her constant love, support, and understanding. I can only hope to preserve our heartfelt relationship. My warmest thanks also go to Tuba Yilmaz, Unal Kocabas, Ibrahim Over for their support, great friendship, and many wonderful memories. I am truly lucky to have made great friends such as Remziye Nasuhoglu, Guner Arici, Burak Sozgen and Cigdem Demirel with whom we have set up the innovative institution More en de Ruif that basically oﬀers fun activities and moral support services. Finally, I would like to express my enormous thanks to my mother Muruvvet Donmez, my father Ibrahim Donmez, my sister Pervin Donmez, and the rest of my family. No matter how far away they may be physically, they are never far from my heart and mind. All my endeavors are to deserve their boundless love and support without which I would never have had the strength and courage to pursue my dreams, and for that I dedicate this thesis to them.

M.Sc. thesis Aylin Donmez

Table of Contents

Summary i

Acknowledgments iii

1 Introduction 1 1.1 Project Description ...... 1 VCO Pulling Avoidance ...... 2 Response of a PLL system to VCO Pulling ...... 4 1.2 Report Outline ...... 4

2 Background 5 2.1 WideBand PLL Basics ...... 5 2.2 Noise ...... 6 2.2.1 Interference Noise ...... 6 2.2.2 Intrinsic Noise ...... 6 2.3 Noise in Wideband PLLs ...... 6 2.3.1 Phase Noise Deﬁnition ...... 7 2.3.2 Frequency Domain Noise Analysis ...... 8 Input Reference Noise ...... 8 Phase Detector Noise ...... 9 Noise Injected to Loop by Charge Pump ...... 9 Noise on Control Line ...... 11 VCO Noise ...... 13 Divider Noise ...... 14 PLL Total Output Phase Noise ...... 15 2.4 Time Domain Noise Analysis ...... 15 2.4.1 Jitter Metrics ...... 16 2.4.2 Time Domain and Frequency Domain Noise Relation ...... 18

M.Sc. thesis Aylin Donmez vi Table of Contents

3 PFD & Charge Pump 19 3.1 Phase Frequency Detectors ...... 19 3.1.1 Multiplier Phase-Detectors ...... 20 3.1.2 XOR Phase Detector ...... 21 3.1.3 Tri State Conventional Phase Detector ...... 22 3.1.4 High Frequency Limitations of Conventional Phase Detectors ...... 22 3.1.5 Dynamic Logic Phase Detectors ...... 25 3.1.6 Phase Frequency Detector Design ...... 27 3.2 Charge Pumps ...... 31 3.2.1 Current and Pulsewidth Mismatch ...... 31 3.2.2 Timing Mismatch ...... 31 3.2.3 Leakage Current ...... 32 3.2.4 Charge Injection ...... 33 3.2.5 Clock Feedthrough ...... 34 3.2.6 Charge Sharing ...... 34 3.2.7 Charge Pump Architectures ...... 34 Single-ended charge pumps ...... 34 Differential Charge Pumps ...... 36 3.2.8 Differential Charge Pump Design ...... 36 Switch Design ...... 37 Common Mode Feedback Circuit ...... 38 Unity Gain Buffer Circuit ...... 43 Bias Block ...... 44 Glitch Suppression ...... 46

4 VCO & Divider 51 4.1 Ring Oscillator VCOs ...... 52 4.1.1 Single Loop Ring Oscillator Design ...... 53 4.1.2 Multi Loop Ring Oscillator Design ...... 55 Odd Number of Stages ...... 55 Even Number of Stages ...... 58 4.1.3 Loop Architecture Decision ...... 59 4.2 Gain Stages ...... 59 4.2.1 CMOS Digital Inverter ...... 60 4.2.2 Diﬀerential Pair ...... 61 4.2.3 Delay Cell with push pull inverters (DC1)[12] ...... 62

4.2.4 Delay Cell with feedback control (DC2)[24] ...... 64

4.2.5 Delay Cell with common mode noise rejection (DC3)[15] ...... 66 4.3 Delay Cells Performance List ...... 68 4.4 Ring Oscillator Design ...... 68 4.4.1 VCO Tuning Range ...... 70 4.5 Layout of the VCO ...... 73 4.6 Divider Performance ...... 73

Aylin Donmez M.Sc. thesis Table of Contents vii

5 Top Level 77 5.1 Loop Parameters ...... 77 5.2 Wideband PLL Characteristics Validation ...... 85 5.2.1 Loop Bandwidth ...... 85 5.2.2 Phase Noise Measurement and Other Design Metrics ...... 85

6 Conclusion and Recommendations 87 6.1 Conclusions ...... 87 6.2 Future Work ...... 87

A PLL Basics 89 A.1 PLL Dynamics ...... 89 A.1.1 Loop Order and Loop Type ...... 90 A.1.2 Loop response to a step change in phase ...... 91 A.1.3 Loop response to a step change in frequency ...... 92

Bibliography 95

M.Sc. thesis Aylin Donmez viii Table of Contents

Aylin Donmez M.Sc. thesis List of Figures

1.1 VCO Pulling in transceiver systems ...... 2 1.2 LO generation from a low frequency reference ...... 2 1.3 LO generation with injection locked mixing ...... 3 1.4 LO Generation with a PLL system ...... 3

2.1 PLL Loop Basic Components ...... 5 2.2 Noise Contributers in the Loop ...... 7 2.3 Output spectrum of an ideal oscillator ...... 8 2.4 Phase noise deﬁnition ...... 8 2.5 Input reference noise contribution ...... 9 2.6 Phase frequency detector noise contribution ...... 10 2.7 Charge pump noise contribution ...... 11 2.8 Control line noise contribution ...... 12 2.9 VCO noise contribution ...... 13 2.10 Divider noise transfer function ...... 14 2.11 Total output noise ...... 15 2.12 Digital waveform with jitter ...... 16 2.13 Waveforms illustrating the period cycles ...... 16 2.14 Edge to edge jitter ...... 17 2.15 Cycle to Cycle Jitter ...... 17 2.16 k-cycle jitter ...... 17

3.1 Ideal phase frequency detector characteristic ...... 19 3.2 Analog Multiplier as a Phase Detector ...... 20 3.3 Analog Multiplier Output ...... 20

M.Sc. thesis Aylin Donmez x List of Figures

3.4 Output Characteristic of Exor PFD ...... 21 3.5 Exor Output Waveforms ...... 22 3.6 Tri State Phase Frequency Detector ...... 22 3.7 UPDN ...... 23 3.8 UPcharacteristic ...... 23 3.9 Output Characteristic of a PFD at high frequencies [18] ...... 24 3.10 Waveforms during blind zone ...... 25 3.11 Architecture proposed by Johansson ...... 25 3.12 Architecture proposed by Mansuri ...... 26 3.13 Architecture proposed by Tak ...... 27 3.14 Output characteristic in [10] ...... 27 3.15 Shorter delay problem in reset path ...... 28 3.16 Phase Frequency Detector used in this work ...... 29 3.17 PFD output for in phase 1GHz square wave inputs ...... 29 3.18 PFD outputs at 1GHz when the reference signal leads for 300 ps ...... 30 3.19 PFD Characteristic ...... 30 3.20 PFD Output Jitter ...... 31 3.21 Phase Frequency Detector Layout ...... 32 3.22 Charge Pump leakage current ...... 33 3.23 Single ended charge pumps ...... 35 3.24 Single ended charge pump architectures a)with current steering switch b)with active output buffer c)with NMOS switches only ...... 36 3.25 CPhigh speed ...... 37 3.26 Noise voltage at charge pump output ...... 39 3.27 Switch layout ...... 39 3.28 Common Mode Circuit ...... 40 3.29 Transconductance of common mode loop ...... 41 3.30 Layouts of common mode circuit and unity gain buffer ...... 42 3.31 Unity gain buffer used in this work ...... 43 3.32 AC response for different input levels of UGB ...... 45 3.33 CP-Bias Block ...... 45 3.34 Layout for CP bias block ...... 46 3.35 Transmission gate as a switch ...... 47

Aylin Donmez M.Sc. thesis List of Figures xi

3.36 Modiﬁcation for Glitch Suppression ...... 47 3.37 Charge pump Full Schematic ...... 48 3.38 Complete Charge pump layout ...... 49

4.1 Three-stage ring oscillator ...... 53 4.2 4 Stage Multi Loop Ring Oscillator ...... 55 4.3 3-stage ring oscillator with multi loop architecture ...... 55 4.4 3 stage ring oscillator 1st order model ...... 56 4.5 4 stage multiple pass ring oscillator architecture ...... 58 4.6 Simple Inverter ...... 60 4.7 Delay Control in Diﬀerential Gain Stages ...... 61

4.8 (DC1) Delay Cell Proposed by [12] ...... 63

4.9 Phase Noise of DC1 @ 5.053GHz ...... 63

4.10 Small signal equivalent model of DC1 used to calculate PSRR [12] ...... 64

4.11 (DC2) Delay Cell [24] ...... 64

4.12 Phase noise of DC2 ...... 65

4.13 Small Signal Model of DC2 used to calculate PSRR in [24] ...... 65

4.14 Schematic of the DC3 [15] ...... 67

4.15 Small signal model of DC3 for PSRR calculation ...... 67 4.16 Schematic and block schematic of the delay cell used in this work ...... 69 4.17 Phase Noise performance of the delay cell used in this work 5GHz ...... 70 4.18 Small Signal Equivalent to half circuit for PSRR calculation ...... 71 4.19 Schematic of VCO delay cell used in this work ...... 72 4.20 VCO delay cell ...... 74 4.21 VCO top level layout ...... 74 4.22 Block Schematic of the divider used in this work ...... 75 4.23 Jitter performance of the divider ...... 75 4.24 Divider phase noise performance ...... 76

5.1 Loop Components ...... 78 5.2 Diﬀerential loop ﬁlter used in this work ...... 78 5.3 Simetrix Model of the Loop ...... 80 5.4 Loop AC response in Simetrix ...... 80 5.5 Noise Behaviour of the loop in Simetrix ...... 81

M.Sc. thesis Aylin Donmez xii List of Figures

5.6 Settling Behavior in Fast Corner ...... 81 5.7 Top level Layout - Core Only ...... 82 5.8 Top level layout including the pads ...... 83 5.9 bonding diagram ...... 84 5.10 Loop bandwidth measurement setup ...... 85

A.1 Basic phase-locked loop block diagram ...... 89 A.2 Loop ﬁlter with stabilization zero ...... 90

Aylin Donmez M.Sc. thesis List of Tables

3.1 UGB transistor sizes ...... 41 3.2 UGB transistor sizes ...... 44 3.3 Bias Block transistor sizes ...... 46

4.1 Comparison of performance metrics of delay cells ...... 68 4.2 VCO Tuning Range ...... 71

5.1 PLL Performance Summary ...... 79

M.Sc. thesis Aylin Donmez xiv List of Symbols

Aylin Donmez M.Sc. thesis Chapter 1

Introduction

In this work a Wideband PLL system is proposed to reduce the effects of the voltage controlled oscillator, VCO, pulling in zero-IF and low-IF wireless transceiver systems. The system is consist of a phase frequency detector, PFD and a charge pump, CP , which are capable high frequency operation. A differential loop filter, a fixed divide-by-6 divider and a ring oscillator which is implemented with a novel architecture of multipath configuration are other components of the system. Wideband PLL is fabricated in a standard CMOS IBM 65nm process, and is efficient with respect to its die area.

1.1 Project Description

In transceiver systems, both zero IF and low IF transceivers, VCO frequency is the same as the antenna frequency. This causes the generally known problem, VCO pulling [21] due to the coupling of RF input signal or the power amplifier signal into oscillator. An oscillator under injection pulling starts oscillating at the injected signal’s frequency depending on the injected amplitude. This effect is strongly dependent on the injected signal’s amplitude and the frequency offset from the VCO free running frequency. Two mechanism can be listed as the cause to VCO pulling a given in Figure 1.1;

• Transmitted signal may couple to VCO, through a parasitic path. A similar mechanism occurs when the supply voltage of the oscillator varies. For example, in a transceiver system where the power ampliﬁer is switched ON & OFF, due to the ﬁnite output impedance of the supply source, supply voltage includes harmonics from the switching frequency of the PA [21].

• Receiver signal may include strong inband interferers which are amplified by the LNA and may couple to VCO. When the interferer frequency is close to the LO frequency coupling through the mixer may pull VCO frequency to interferer frequency. With a buffer between VCO and mixer would increase the reverse isolation and reduce the pulling effect.

M.Sc. thesis Aylin Donmez 2 Introduction

(a) PA leakage to VCO

(b) Large interferer at input

Figure 1.1: VCO Pulling in transceiver systems

VCO Pulling Avoidance

In transceiver systems, VCO central frequency may shift to an undesired frequency due to the leakage from parasitic paths, or coupling of PA signal to VCO through the bulky inductors used in VCO, as previously explained. Due to the integer relation between the PA output frequency and the VCO frequency, this pulling eﬀect increases. There are several options for LO generation in transceiver systems;

Figure 1.2: LO generation from a low frequency reference

• In zero IF transceivers, generally the local oscillator of the transceiver is designed to operate at RF frequency, fRF . Thus the RF spectrum is directly transferred into the baseband. This architecture relaxes the requirements on IF ﬁlter, it is now consist of

Aylin Donmez M.Sc. thesis 1.1 Project Description 3

a low pass filter since the information band after mixing is at baseband. However, it is clear that such an architecture is more susceptible to 1/f noise and DC offsets. Moreover, in such an architecture, since PA frequency and VCO frequency is designed to be same, any leakage from transmitted signal to VCO is double mixed with the received signal leading to pollution of the information band. This effect is generally regarded as cross talk and it is undesirable.

• In some architectures, the local oscillator of the transceiver is designed to operate at 2 × fLO. It is followed by a quadrature divide by 2 block in order to perform image rejection. The coupling effect of PA to VCO resonator is then reduced, however 2nd harmonic of transmitted signal still couples to VCO and receiver suffers from pulling effects.

• Another solution would be the implementation of a low frequency VCO followed by a frequency multiplier as given in Figure 1.2. This frequency multiplication can be performed with an injection locked divider and a mixer as illustrated in Figure 1.3. This conﬁguration allows the usage of an LO frequency that has a non integer relation between the PA frequency. However, main draw back of this system is the spurious components produced after mixing.

Figure 1.3: LO generation with injection locked mixing

• Alternatively, a PLL loop could be a candidate for a system. Reference oscillator which could be implemented with an LC oscillator runs at a lower frequency and the LO frequency is generated by a PLL loop. VCO of the PLL loop can be implemented with a simple ring oscillator.

Figure 1.4: LO Generation with a PLL system

M.Sc. thesis Aylin Donmez 4 Introduction

Response of a PLL system to VCO Pulling

As a negative feedback control system, PLL would try to compensate for the phase error at the output of the PLL phase detector. Thus, PLL responds to any phase-frequency changes. However, the rate of change in phase-frequency is also important since there exist a limit in phase-frequency change that drives the loop out of stability. Brief explanation on this limitation is given in Appendix A. Depending on the frequency offset of the injected signal, PLL sensitivity to the injected signal also changes. Since the PLL suppresses the effect of the injection within the PLL bandwidth, the injection effects within PLL bandwidth reduce. A wideband PLL system offers a solution to VCO pulling from two perspectives; Firstly, The non integer relation between the reference VCO and the transmitter frequency reduces the pulling. Secondly, because of the wide loop bandwidth the injection pulling is also suppressed.

1.2 Report Outline

The goal of this thesis is to review the theory, design and analysis of PLL circuits and complete a detailed design of a 4.9 ∼ 5.9 GHz Wideband CMOS PLL Frequency Synthesizer. Chapter 2 presents the noise fundamentals of PLLs and explains how noise is defined both in time and frequency domains. Transfer functions are derived to calculate the output noise contribution of the loop components. Relation between time domain and frequency domain analysis is also given briefly. Chapter 3 concentrates on the phase frequency detector and charge pump design up to their final phase; layout extraction. In this chapter, high frequency operation of these components are explained, and techniques that offer a solution to problems that occur from high frequency operation, are described. Chapter 4 discusses the methods of high frequency operation in ring oscillators. Frequency improvement in multi loop architectures are investigated and gain stages that can be used in multiloop configuration are identified. Since the gain of ring VCOs, KVCO, is sufficiently high, techniques to reduce KVCO are derived. Layout limitations on operating frequency of the VCO are also given in this chapter. Chapter 5 is a review of overall performance of the Wideband PLL. It explains how the stability of the loop is satisfied for all the operating range. Top level layout routings are also explained in this chapter. Chapter 6 is a review of the thesis, conclusions and recommendations are given.

Aylin Donmez M.Sc. thesis Chapter 2

Background

2.1 WideBand PLL Basics

A phase locked loop is a feedback system that functions on the phase differences of its two periodic inputs. This property of a PLL system is the basic distinction from other feedback systems where the change in voltage or current magnitudes is of importance. In a simple PLL loop phase frequency detector, PFD, produces output that carries the information on the excess phase of the PLL inputs. Charge pump, CP, supplies the required current, based on the phase frequency detector output. CP current is converted into voltage by means of the loop filter impedance. Loop filter has always a low pass characteristic and high frequency components in the control voltage are filtered out by the loop filter.

Figure 2.1: PLL Loop Basic Components

The loop is considered to be locked when the excess phase is constant with the time. In wideband PLLs main concern is the high frequency limitations of the PFD and CP. Phase frequency detector is possibly conﬁgured based on either a mixing function or sequential logic. The frequency divider in the loop divides the output frequency by N, division ratio, thus produces an input signal to phase frequency detector. Since frequency is the derivative of phase, output phase is also divided by N. As a result, when the loop is locked below relation is valid for input φIN and output phase φOUT ;

1 φIN = N φOUT

M.Sc. thesis Aylin Donmez 6 Background

∂φIN 1 ∂φOUT 1 ωIN = ∂τ = N ∂τ = N ωOUT

ωOUT = NωIN

Detailed information on loop dynamics can be found in Appendix A.

2.2 Noise

2.2.1 Interference Noise

Interference noise is mainly caused by the undesirable interaction between the circuit blocks in a system-on-chip architecture. In many chips all of the clocks and events are harmonically related to each other thus interference noise may be regarded as cyclostationary in its nature [3]. Power supply noise or electromagnetic interference between wires are the two most common sources of the interference noise. This kind of noise can be reduced down to a signiﬁcant extent by a careful layout techniques.

2.2.2 Intrinsic Noise

Intrinsic noise is mainly originated from the elemental properties of devices and circuits. In contrast to interference noise, intrinsic noise refers to random noise signals that can be reduced but never eliminated. Here, a brief descriptions of electronic components is given. Resistors produce a type of noise, called thermal noise. It is originated by kinetic energy gained by the free charge carriers [26]. Thermal energy causes carriers to move randomly instead of following polarities. Diodes produce a type of noise called shot noise. The diﬀusion mechanism in diodes is the origin of this type of noise. The displacement of individual carriers is a random process, there occurs slight ﬂuctuations across the junction. It has a white power spectral density. MOS Transistor operates as a gate modulated resistance between the source and drain area. Thus its noise is mainly thermal origin.

2.3 Noise in Wideband PLLs

Output spectrum of an oscillator is basically determined by the transfer functions of each block to output. Thus, PLL response to noise contributions of each block is greatly important. In Wideband PLLs, phase noise of oscillators and charge pump are critical issues that basically determine the system performances. PLL inband noise is dominated by charge pump while the vco has considerable superiority in the noise outside the loop bandwidth. The response of a PLL system to abrupt phase changes, non idealities such that spurious peaks, noise etc. shall be well characterized. Location of various signal noise sources are seen in Figure 2.2. Analysis of PLL noise transfer functions reveals more insight on the noise shaping eﬀect of PLL loop.

Aylin Donmez M.Sc. thesis 2.3 Noise in Wideband PLLs 7

Figure 2.2: Noise Contributers in the Loop

2.3.1 Phase Noise Deﬁnition

The most desirable speciﬁcation of any type of oscillator is its spectral purity. An ideal oscillator has an impulse in its spectrum at its oscillation frequency, ωO. However, in most practical applications total power of such an oscillator is distributed over its harmonics (i.e. 2ωO, 3ωO, 4ωO...) as shown in Figure 2.3. Thus, instantaneous output wave expression for a practical oscillator can be given as;

V (t) = Vo + A0(t) sin (ωOt + φ (t))

+ A1(t) sin (2ωOt + φ (t))

+ A2(t) sin (3ωOt + φ (t)) + higher order harmonics (2.1) where A(t) and φ (t) are the expressions for the amplitude and phase ﬂuctuations. Two diﬀerent types of non ideality terms appear at the output spectrum of a practical oscillator;

• Random phase ﬂuctuations, are basically originated from the internal noise components of the oscillator, such as 1/f noise, shot noise. Internal noise sources, being random in nature, set a natural limit to the minimum attainable phase noise performance. It is measured as the random phase ﬂuctuations at zero crossings of the signal.

• Spurious tones or signals, are distinct components in the spectrum and they are generally considered as interferers. These external noise sources are deterministic and they do not have a direct relation with the oscillator spectrum. Tones in power supply, tones in control voltage of oscillator or clock signals coupled via bias current appear in oscillator output spectrum and appoint a critical speciﬁcation for the PLL system.

As seen in Figure 2.3 these phase noise components have different amplitude behavior. Typ- ically phase noise is defined as the ratio of noise power in 1 Hz bandwidth at an offset, fm, to the total signal power, as shown in Figure 2.4. Thus, single side band, (SSB), phase noise is specified in dBc/Hz,(dB relative to the carrier) at a given frequency offset as;

PNOISE (fm) L (fm) =10log PSIGNAL

M.Sc. thesis Aylin Donmez 8 Background

Figure 2.3: Output spectrum of an ideal oscillator

Figure 2.4: Phase noise deﬁnition

2.3.2 Frequency Domain Noise Analysis

In the linear noise model of the PLL loop given in Figure 2.2, φref stands√ for the noise that appears at the reference input to the PFD and it has the form rad/ Hz. It is comprised of the noise components such as reference crystal oscillator, crystal√ buﬀer and reference divider if available. φdiv represents the output noise of divider in√rad/ Hz. φvco is the phase noise of the free running oscillator, it is also expressed in rad/ Hz. φpfd is the noise of the phase frequency detector that appears at PFD output. υn,cnt is the noise voltage at VCO control line in consequence√ of loop ﬁlter noise or any noise sources coupled to control line. υn,cnt is expressed√ in V/ Hz. in,cp represents the noise current of charge pump and has a unit of A/ Hz. Noise contribution of each block are studied separately here that other noise contributions are assumed to be zero while calculating contribution of one block.

Input Reference Noise

Input reference noise is one of dominant noise sources in a PLL loop. For the cases that input signal is not a pure sinusoid i.e. input phase varies with time, transfer function of excess phase from reference input to VCO output is given as in Equation-2.2;

Kvco φout(s) F (s) × Kpfd × s Href (s) = = (2.2) φ (s) Kvco ref 1 + F (s) × Kpfd × N×s

For any type of loop ﬁlter, F (s), as input phase varies very slowly, i.e. as s → 0, Href → N, transfer function converges to a constant, N, division ratio. And for inﬁnitely fast changes transfer function converges to 0 indicating that PLL system does not respond to high frequency inputs. As a result noise from reference input has a low pass characteristic. Thus,

Aylin Donmez M.Sc. thesis 2.3 Noise in Wideband PLLs 9

Href corresponds to low pass ﬁltering of the reference noise multiplied by the division ratio, N.

(a) Input reference noise (b) Transfer function of reference (c) Total reference noise appear- input ing at output

Figure 2.5: Input reference noise contribution

Power spectral density of the reference phase noise contribution is given in Figure ??. In this figure, loop filter is supposed to have a single pole and a stabilization zero. Reference noise 1 only has f 2 component which is practically not the case. For low frequencies, output power spectrum has the same slope with the input reference power spectrum, however its magnitude is multiplied by N 2. At cutoff frequency additional slope of −20dB/dec is introduced by the loop filter.

Phase Detector Noise

Phase detector noise is generally much smaller than the reference noise and in most cases it is skipped in calculations. Phase Detector of the PLL loop exhibits the transfer function given with Equation 2.3. Kvco φout(s) F (s) × s Hpfd(s) = = (2.3) φ (s) Kvco pfd 1 + F (s) × Kpfd × N×s

Disregarding of the loop ﬁlter type, for frequencies close to 0, s → 0, transfer function converges to N . This result means that for low frequencies phase detector’s noise magnitude Kpfd appears at the output of PLL with multiplied by N . Kpfd For frequencies s → ∞, transfer function goes to 0 with −20dB slope meaning that outside the loop bandwidth phase detectors noise is not dominant contributer to VCO output noise, which is a sensible result. PLL loop responds to PFD noise in the same way as reference input. Only the magnitude of transfer function at low frequencies is now N . Kpfd

Noise Injected to Loop by Charge Pump

For a practical PLL system, when the loop is locked the average current transfer to the loop is zero. However, charge pump noise current is injected to the loop ﬁlter during the non zero UP & DN pulse widths. Charge pump noise current can be calculated as in Equation 2.4.

M.Sc. thesis Aylin Donmez 10 Background

(a) Phase frequency detector (b) Transfer function of PFD (c) Total phase detector noise ap- noise pearing at output

Figure 2.6: Phase frequency detector noise contribution

2 τdz 2 incp = 2 × × ICP,noise (2.4) Tref

√ where ICP,noise stands for the total current noise density of the charge pump in A/ Hz. τdz is the duration of the UP & DN pulse widths during the lock condition. Factor of 2 refers to the noise contributions of both UP & DN pulses. Tref is the period of the reference input signal. The magnitude of charge pump current noise power density i2 is proportional to the nCP duty cycle of the charge pump and the frequency of the reference input as seen in Equation 2.4. Thus, for high frequencies, switching of the UP & DN current sources becomes more critical. Charge pump of the PLL loop exhibits the transfer function given with Equation 2.5.

Kvco φout(s) 2π F (s) × Kpfd × s HCP (s) = = × (2.5) i (s) I Kvco ncp CP 1 + F (s) × Kpfd × Ns

Here noise current of charge pump is assumed to be white. For frequencies s → 0, transfer function converges to;

20log( 2πN ) ICP

Magnitude of low frequency noise contribution of charge pump current is multiplied by 20log( 2πN ). For frequencies higher than the loop bandwidth, transfer function has a −20dB ICP of slope and goes to 0. As a result, it can be concluded that charge pump noise is dominant within the loop bandwidth and its contribution is negligible outside the loop bandwidth. In a practical charge pump circuit, non ideal eﬀects such as leakage currents, magnitude mismatch between UP & DN currents or switching time mismatch between UP & DN currents are critical in reference spur calculation. However, they are not critical issues in CP noise contribution as Equation 2.4 adequately includes the parameters that control CP noise.

Aylin Donmez M.Sc. thesis 2.3 Noise in Wideband PLLs 11

(a) Charge pump noise (b) Transfer function of CP

Figure 2.7: Charge pump noise contribution

Noise on Control Line

Thermal noise originated from the loop ﬁlter’s resistance, power supply noise coupled to control line or voltage buﬀer used in control line contributes to total PLL output noise. These contributors are investigated here in details.

• Loop Filter Noise Low pass ﬁlter of the PLL loop exhibits the transfer function given with Equation 2.6.

Kvco φout(s) s Hlpf (s) = = (2.6) υ (s) Kvco lpf 1 + F (s) × Kpfd × N×s

It is interesting that loop ﬁlter’s noise transfer function is dependent on the type of the low pass ﬁlter. In case the loop is a 1st order, i.e F (s) = 1 the transfer function has a low pass characteristic as seen in Equation 2.7.

For F (s) = 1

φout(s) Kvco Hlpf (s) = = K ×K (2.7) υlpf (s) pfd vco s + N However, if the ﬁlter has a zero and a pole,i.e.;

M.Sc. thesis Aylin Donmez 12 Background

F (s) = 1+sτ1 sτ2

transfer function characteristic becomes band pass. The closed loop noise power density contribution of loop ﬁlter to output is then given in Figure 2.8;

(a) Loop Filter noise voltage (b) Closed loop transfer function of loop ﬁl- ter

Figure 2.8: Control line noise contribution

Hlpf (s) is the bode plot of the noise transfer function and only the thermal noise of loop filter resistance is taken into account. However if loop filter is implemented in an active configuration, it is likely that active part of the circuit contributes to the output noise of the loop filter as well.

• Power Supply Noise Transfer through VCO Control Line In a PLL system the magnitude of phase noise, i.e., the amount of jitter is strongly dependent of the power supply voltage. It is generally assumed that the maximum supply voltage variation is ±10% percent. An oscillator under power supply noise interference, can be regarded as a voltage controlled oscillator that has power supply as control input. Its dependence on Vdd is considered as supply sensitivity or supply gain. This gain is measured easily by observ- ing the output frequency spectrum of VCO while the actual control inputs are zero. If this gain is expressed as Kvdd, phase noise induced by power supply noise can be given as in Equation 2.8 [6];

2 Kvdd Sφ (s) = Sυ (s) (2.8) vdd f 2 Nvdd Oscillator phase noise due to impulsive supply noise;

Aylin Donmez M.Sc. thesis 2.3 Noise in Wideband PLLs 13

Kvco φout(s) s Hvdd(s) = = (2.9) φ (s) Kvco vdd 1 + F (s) × Kpfd × N×s

The resulting supply noise transfer function is pretty similar to the Hlpf and it has a bandpass ﬁlter characteristic as shown in Figure 2.8. Thus its low frequency components are rejected by the loop [3].

VCO Noise

Another noise source, in fact the dominant noise in the band of interest, is VCO phase noise and can be modeled by transfer function given in Equation 2.10;

φout(s) 1 Hvco(s) = = (2.10) φ (s) Kvco vco 1 + F (s) × Kpfd × N×s

For any type of loop ﬁlter, F (s), as s → 0, Hvco = 0, and as s → ∞, Hvco = 1. When the loop ﬁlter has a zero and a pole, i.e. ;

F (s) = 1+sτ1 sτ2 it can easily be seen that transfer function has two zeros at the origin realizing a high pass characteristic with +40dB/dec slope for low frequencies. The zeros at the origin acquires that for small changes of φvco, output phase noise is negligibly small. When the PLL loop is locked, excess phase of VCO is sensed and converted into voltage via PFD, CP and loop ﬁlter path. Thus the voltage variations on the control line compensates for the small phase variations in VCO performing a negative feedback.

(a) VCO open loop noise (b) Transfer function of VCO (c) Total VCO noise appearing at output

Figure 2.9: VCO noise contribution

For very fast changes of input phase VCO phase noise is transferred to output with a gain of 1. This property reveals an interesting conclusion that phase noise of VCO is subject to integration.

M.Sc. thesis Aylin Donmez 14 Background

One basic solution is increasing the loop bandwidth of PLL system i.e. lowering the lock time of PLL; however this would cause the low pass ﬁlter response to higher frequencies leading more instable VCO control voltage. The loop bandwidth should be as larger as possible, in order to minimize the output phase noise due to the VCO intrinsic phase noise. On the other hand, it is essential to keep the loop bandwidth smaller than the reference signal in order to keep the loop stable and suppress the reference spurs.There is a strict trade oﬀ on keeping the in-band phase noise minimum and retaining the spurious levels.

Divider Noise

Frequency divider of the PLL loop theoretically converts the high input frequency to lower frequencies by a factor of the division ratio. This division ratio may be integer or fractional based on the application. Modeling the noise of frequency divider of the PLL is mode critical than the other blocks in the loop [14]. This is mainly because the condition that dividers are generally followed by blocks that are sensitive to the threshold crossings of the divider output signal. This reveals an interesting property that overall noise behavior of the PLL loop is aﬀected by the divider only during the threshold crossings. Divider of the PLL loop exhibits the transfer function given with Equation 2.11.

Kvco φout(s) F (s) × Kpfd × s Hdiv = = (2.11) φ (s) Kvco div 1 + F (s) × Kpfd × N×s

It has the same transfer function as the reference signal. This is an expected result, because it is one of the two inputs of the phase-detector. For any loop ﬁlter F(s), Hdiv(s) = N for s=0, and Hdiv(s) = 0 for s = ∞.

(a) Divider Open Loop Noise (b) Transfer Function of Divider (c) Total divider noise appearing at output

Figure 2.10: Divider noise transfer function

Intrinsic noise contribution of divider generally has a flat spectrum, white noise floor, except from the 1/f, flicker noise effect [14]. Ignoring the 1/f components, the transfer function Hdiv corresponds to a low pass filtering of the divider noise multiplied by N as given in Figure 2.10. As a result, noise from the divider has a low pass characteristic.

Aylin Donmez M.Sc. thesis 2.4 Time Domain Noise Analysis 15

PLL Total Output Phase Noise

Phase noise contribution of each block to the output in a PLL is already calculated in above sections. Overall PLL phase noise is achieved by using the Equation 2.12.

Observation of Equation 2.12 shows that at low frequencies, the reference signal, the phase- detector, the loop filter and the divider are the significant noise contributors within the bandwidth of the PLL. At offset frequencies higher than the PLL bandwidth, the phase noise of the PLL is approximately dominated by VCO.

Figure 2.11: Total output noise

In order to minimize the reference noise contribution, the loop bandwidth must be set to smaller values as possible. However, in this case acquisition time increases, acquisition range decreases and the stability degrades. To minimize the VCO noise contribution at high frequencies, the loop bandwidth must be maximized. In this case, acquisition time is decreased, acquisition range is increased and stability is improved. In applications where the input has negligible noise, like a crystal oscillator, the loop bandwidth is maximized for an improved performance.

2.4 Time Domain Noise Analysis

Noise sources such as thermal noise, frequency modulation (FM), amplitude modulation (AM), phase modulation (PM), and spurious components that are produced by the system contribute to total noise that causes jitter in the clock signal and this total noise is accepted as a general measure in calculation of jitter. Jitter is the instantaneous variations in the phase of a signal that causes the signal deviate from the ideal position. In a PLL system this momentary variations can be observed as the

M.Sc. thesis Aylin Donmez 16 Background time variations in zero crossings of the signal. The expected crossings in a signal never occur exactly where desired as given in Figure 2.12. Deﬁning and measuring the timing accuracy of those crossings (jitter) is a critical measure of the performance of communication systems.

Figure 2.12: Digital waveform with jitter

In a system where the blocks are generally driven by square wave signals, it is more convenient to express the noise in terms of jitter. To draw a complete picture of jitter control mechanism, jitter metrics have to be well deﬁned.

2.4.1 Jitter Metrics

Transitions of any type of periodic signal can be expressed as the sequence of positive edge threshold crossings, {τi}. Ideally, for a noise-free signal, the following condition should be valid for all cases ; τi = iT where T represents the period of the signal. When the clock signal is noisy, τi can be given in a statistical form as τi = iT + δτi.

Figure 2.13: Waveforms illustrating the period cycles

• Edge to Edge jitter

Jee is a measure of jitter as the difference between the threshold crossings of noise free reference trigger and its response [14]. In other words it is the delay variations of input and output of a driven block under a noise free reference input assumption. Jee is an input referred jitter metric defined only for the driven systems such as phase frequency detectors, dividers or clock buffers. Since a fixed noise free reference signal is assumed,

Aylin Donmez M.Sc. thesis 2.4 Time Domain Noise Analysis 17

Jee can not be used for autonomous systems such as VCOs. Jee is illustrated in Figure 2.14. Thus edge to edge jitter is given as;

2 Jee(i) = var(τi − iT ) = var(δτi) = var(τi) (2.13)

Figure 2.14: Edge to edge jitter

• Cycle to cycle jitter Cycle to cycle jitter is the probability distribution of diﬀerences in the period length of adjacent clock cycles [14]. For calculation of cycle to cycle jitter, a new form for sequence period is considered as Ti = τi+1 − τi. Jcc is calculated as;

2 Jcc(i) = var(Ti+1 − Ti) (2.14)

Jcc is a measure for short term jitter and it is used for both driven and autonomous

Figure 2.15: Cycle to Cycle Jitter

systems.

• K-cycle jitter

K cycle jitter is the standard deviation of k cycles, τi+k − τi, in a periodic signal. It is a measure of uncertainty in the length of k cycles and expressed in time units [14]. For k=1, J1 stands for the standard deviation of a single period, and often represents the period jitter. 2 Jk (i) = var(τi+k − τi) (2.15)

Figure 2.16: k-cycle jitter

M.Sc. thesis Aylin Donmez 18 Background

2.4.2 Time Domain and Frequency Domain Noise Relation

Phase noise is a continuous stochastic process modeling the random changes in the phase of periodic signal that has a constant frequency while jitter arises from the uncertainty at the sampling point of a periodic signal [14]. These two concepts are different in their nature and the relationship between two is not obvious. However, if two noise domains can be separately analyzed and can be related to each other by means of noise power definition in each domain, simplified relationship between two domains can be obtained. Noise power in frequency domain can be given as the integral of all noise components over a frequency range from 0 ∼ ∞ as; Z ∞ PAV = Sθ(f)df (2.16) 0 where average noise power in time domain is given as;

2 PAV = σθ (2.17)

As a result, the relation between two domain noise analysis becomes;

Z ∞ 2 σθ = Sθ(f)df (2.18) 0

Detailed derivations can be found in [14].

Aylin Donmez M.Sc. thesis Chapter 3

PFD & Charge Pump

3.1 Phase Frequency Detectors

Phase-detectors are the circuit blocks of PLL systems that are a type of comparator providing a DC output signal proportional to the input phase diﬀerence between two input signals, φREF − φDIV = φERR. This error signal is produced through PLL loops feedback system. This may be written as in Equation 3.1.

VD = KPFD × φERR (3.1) where VD is the average output voltage, φERR is the phase diﬀerence between the input signals and KPFD is the phase-detector gain in volts per radian, V/rad. In ideal case output voltage is linearly dependent on the input phase diﬀerence as seen in Figure 3.1. However, in practice the response of the phase-detectors is generally nonlinear and repeats in a cyclic fashion over a limited phase range. The response is usually linear in a narrow phase range close to the point at which the loop will normally lock, and the slope of the characteristic in this range gives the phase-detector gain KPFD. Phase frequency detectors can be grouped into two as; multiplier and sequential phase detectors.

Figure 3.1: Ideal phase frequency detector characteristic

M.Sc. thesis Aylin Donmez 20 PFD & Charge Pump

3.1.1 Multiplier Phase-Detectors

Multiplier phase-detectors rely on the DC component that results when multiplying two alternating input signals. The input signals are mostly sinusoidal for this type of phase- detectors and the DC component at the output is dependent on the phase diﬀerence between the inputs. The simplest example of a multiplier type phase-detector is the analog multiplier of Figure 3.2. This multiplier block usually consists of a double-balanced mixer or four

Figure 3.2: Analog Multiplier as a Phase Detector quadrant multiplier that performs the multiplication operation of the input signals. Phase detection behavior of a simple analog multiplier can easily be understood from considering two input signals x1(t) = A1 cos(ω1t + φ1) and x2(t) = A2 cos(ω2t + φ2). Multiplication result from these two signals can be given as in Equation 3.2;

VD = K × x1(t) × x1(t) KA A = 1 2 {cos [(ω − ω )t + (φ − φ )] + cos [(ω + ω )t + (φ + φ )]} (3.2) 2 1 2 1 2 1 2 1 2

When two input signals are equal in frequencies, i.e. ω1 = ω2 , output component becomes a DC term that is proportional to the phase diﬀerence of the input signals. In Figure 3.3, output voltage with respect to the input phase diﬀerence is given.

Figure 3.3: Analog Multiplier Output

Gain of such characteristic is given by the derivative of its output voltage with respect to the input phase diﬀerence as below;

∂VD ∂ KA1A2 KA1A2 KPFD = = cos φERR = sin φERR (3.3) ∂φERR ∂φERR 2 2

Aylin Donmez M.Sc. thesis 3.1 Phase Frequency Detectors 21

This function is periodic with the phase error. Phase detectors gain is zero when phase error zero and it is maximum when the phase error 90o and equal to the maximum output voltage of multiplier. and phase detector gain varies sinusoidally with the phase difference. When the output voltage is zero, i.e. the phase difference between input signals is 90o, locking in multiplier type phase detectors can be considered as quadrature phase detector. Thus the loop locks for a phase difference of 90o producing zero output. This makes the useful phase detection range to be limited by ±π/1.

o • As φERR departs from 90 , the slope of cos φERR and hence the equivalent KPFD decreases.

• Also KPFD is a function of input signal amplitudes, A1 and A2, which is an undesirable attribute, because a PLL employing such a phase-detector exhibits amplitude dependent static and dynamic behavior.

• Another disadvantage of multiplier-type phase-detectors is, they produce zero DC output when the input signal frequencies are different, ω1 6= ω1. As a result, the acquisition performance of the loop depends on how much the difference component at ∆ω = ω1 6= ω1 is passed by the loop-filter.

3.1.2 XOR Phase Detector

Similar operation principle is useful in explanation of XOR phase detectors. XOR component may be considered as an overdriven analog multiplier. However, in this case output voltage is not a function of input signal amplitudes since the output swing is between logic levels, ground and supply voltage, VDD.

Figure 3.4: Output Characteristic of Exor PFD

Output characteristic of XOR gate with respect to its input phase offset is given in Figure 3.4. Since the output voltage of an XOR phase-detector varies between the two logic levels, a DC offset equal to the mean of logic 1 and logic 0 levels, VDD/2, needs to be provided at the loop-filter for the detector to function correctly [21]. In other words, XOR phase-detectors also lock for a static phase error of 900, at the middle of the linear range, which is π/2 rads. The phase-detector gain is; V K = DD (3.4) PFD π On the other hand, XOR produces output voltage on both rising and falling edges of the input signals, thus the output signal has double frequency component as seen in Figure 3.5.

M.Sc. thesis Aylin Donmez 22 PFD & Charge Pump

Figure 3.5: Exor Output Waveforms

3.1.3 Tri State Conventional Phase Detector

A Tri State conventional phase detector is consist of two D type flip flops and an AND gate for reset path. Output of the block takes one of the values from (0,0),(0,1),(1,0),(1,1). However during the state (0,0), the PFD does not respond to any input signal. Thus flip flops have to be reset after a certain reset delay time.

Figure 3.6: Tri State Phase Frequency Detector

At the rising edge of REF, U signal is activated and kept high till reset. At the rising of DIV, D signal is activated and it is kept high till reset comes. The difference is phase/frequency of the input signal corresponds to the difference of U and D signal’s high duration. Thus if the reference input leads the divider output, mean value of U signal becomes the term that is proportional to the phase difference while D signal is logic 0. Opposite is also valid for divider leading the reference. The difference between the mean values of the output signals determines the phase detectors gain characteristic which is given in Figure 3.8. The amount of gain is given by;

V K = DD (3.5) PFD 2π

3.1.4 High Frequency Limitations of Conventional Phase Detectors

Operation of a conventional phase frequency detector is explained in previous sections. Rising edge of reference signal sets the output U high. Following rising edge of divider output sets

Aylin Donmez M.Sc. thesis 3.1 Phase Frequency Detectors 23

Figure 3.7: UPDN

Figure 3.8: UPcharacteristic

M.Sc. thesis Aylin Donmez 24 PFD & Charge Pump the D signal high thus creating a reset pulse at the output of the AND gate. This pulse resets both of the outputs to zero. When both outputs are set to low, the reset pulse also is inverted so that the circuit is made ready for following transitions. Certain gate delays of the transistors and the delay of the AND gate used in reset path determines a certain time interval, ∆R, for the reset operation. Thus the output signals are kept high during a certain time interval which is deﬁned as reset delay, ∆R. This time interval, that is required to make the circuit ready for next transitions, puts some limitations to the maximum operation frequency.

Figure 3.9: Output Characteristic of a PFD at high frequencies [18]

Figure 3.9 shows the characteristic of a phase frequency at high frequencies. During the time interval {tREF − ∆R, tREF }, where tREF is defined as the period of reference signal, the phase detector is not ready for new transitions. Thus the rising edge of reference or divider clock is lost. Solid line in Figure 3.9 corresponds to the output characteristic when the time delay, ∆R, equals to π. With such a phase frequency characteristic, loops lock to a phase difference of 0o and the linear range that gain is constant becomes ±π. Generalized input phase difference range can be given as {±2π(1 − ∆R/tREF )}. Thus the detection range becomes inversely proportional to the input frequencies. As the reference frequency increases, assuming the reset delay constant, detection range degrades considerably. Waveforms in Figure 3.10 show the case that is likely to happen during the reset delay. During the interval that both outputs and reset signal are activated, new transition of reference is ignored and after reset pulse ends divider signal activates the D pulse thus making the mean difference of output voltage negative although the reference frequency is higher. This phenomenon causes a negative output voltage during {tREF − ∆R, tREF }, that is demonstrated in Figure 3.10.

On the other hand, this time interval range {tREF − ∆R, tREF } may be considered as blind zone. During this zone phase detector outputs wrongly. This wrong output voltage increases locking time. During the loop settling the frequency would lose lock since the PFD produces wrong output signals periodically. With increasing reference frequency, settling of PLL increases.It can be concluded that, during the time interval {tREF − ∆R, tREF } conventional PFD loses edges and the following input sets the output to a negative voltage.

Aylin Donmez M.Sc. thesis 3.1 Phase Frequency Detectors 25

Figure 3.10: Waveforms during blind zone

3.1.5 Dynamic Logic Phase Detectors

In case D type flip flops are implemented in a true state pre-charge, TSPC, dynamic logic, it may easily be expected that operation frequency increases remarkably. Basic property that allows high frequency operation with dynamic logic is simplicity of flip flop circuit thus reduced the number of gate delays. There are many applications of dynamic phase frequency detectors available in literature as in [10]. Here few of them are generally discussed and compared from their operating frequency, linear input range, power consumption, jitter production perspectives.

Figure 3.11: Architecture proposed by Johansson

Simple precharged phase frequency detector of [13] which is given in Figure 3.11, makes use of one clocked inverter for phase detection and one normal inverter to produce output

M.Sc. thesis Aylin Donmez 26 PFD & Charge Pump thus the delay between the reference input and U signal, i.e., intrinsic ﬂip ﬂop delay becomes tINV + tINVC , where tINV is the delay of a single inverter and tINVC is the delay of a clocked inverter. However main drawbacks of such a phase detector are;

• Its output voltages are both active during the lock of the system. This property requires a perfect matching in sink and source current sources of the charge pump.

• Since the output is produced with rising edge of input signal and kept constant during high level of input, deviation from 50 duty cycle degrades the performance.

• Linear range is limited within ±π.

Architecture of Figure 3.12, proposed in [17] ﬁnds a solution to the improvement of the linear range by preventing phase detector produce wrong output signals during {tREF − ∆R, tREF }.

Figure 3.12: Architecture proposed by Mansuri

This is achieved by making use of two inverter based latch structures. Output signal is made level sensitive to the input reference signal, thus even the rising edge is lost, phase detector is capable of producing correct output signals with improved input phase range. PFD output becomes high at the end of reset output signal width stays constant i.e. gain of PFD saturates for phase differences greater than {tREF − ∆R}. However in such a circuit input reference pulse is generated through a clock generator circuit with a certain inverted delay block. This block determines the input pulse width that needs to be set to a width slightly smaller than the reset delay. Few disadvantages exist originated from this delay line such as; This delay line used for pulse generation is expected to set a certain limitation on operating frequency. Moreover, this delay increases the power consumption of the block. Another type of dynamic flip flop circuit from [10] is given Figure 3.13. Operation principle of this circuit is as follows; at initial state, REF, DIV, reset, UP and DN signals are assumed to be logic low. Thus node X is precharged to VDD. At the rising edge of the reference signal UPN node is discharged to 0, thus producing an UP pulse. The same principle holds for the divider signal, that rising edge of the divider signal sets DN signal to VDD. When both UP

Aylin Donmez M.Sc. thesis 3.1 Phase Frequency Detectors 27

Figure 3.13: Architecture proposed by Tak and DN signals are received, outputs are reset through a NOR gate. For the following periods of reference signal, same principle holds. Reference signal is applied to input through a delay block that precharges the node X to VDD together with reset signal with an AND operation. At the rising edge of reference signal delayed input should still be logic low. Otherwise the edge information would be lost. On the other hand, inserted delay should be slightly smaller than reset delay to prevent PLL losing lock for 0 phase diﬀerence. If the inserted delay is bigger than reset delay, than the input clock information of previous period activates the outputs after reset.

Figure 3.14: Output characteristic in [10]

A good arrangement of these delay lines result in the characteristic given in Figure 3.14. Here ∆ corresponds to the total time delay including reset path, ∆tREF , and gate delays of the transistors.

3.1.6 Phase Frequency Detector Design

The phase-detector used in this work is similar to the one given in Figure 3.13 with a small diﬀerence as given in Figure 3.16 where NOR gate is replaced with an AND gate. The reason

M.Sc. thesis Aylin Donmez 28 PFD & Charge Pump for this can be explained as below; The goal of PFD design is to minimize delay from the reference or divider to output pulses in order to satisfy high frequency operation. In this topology this delay equals to total delay through one NMOS gate and the output inverters, X1 or X2. In IBM 65nm technology, transition times of a single inverter, ∆tINV , are in the order of 10ps. Driving capability of the inverter is also important in order to avoid additional delay in between PFD and charge pump which would be introduced by the additional buﬀer circuitry. ∆tREF in Figure 3.16 is simply one gate delay and in the order of 10ps. With the original structure the outputs are reset with a NOR gate. In order to do so, negative outputs are applied to the NOR gate. Total reset delay of this structure is ∆tREF and the delays through the transistors. With the rising-edge of the reference signal, UP output is set high after a transition time equal to the delay of transistors and the inverter, ∆tINV . When the rising-edge of the VCO output arrives, DN output starts to rise. However, when negative of DN output, DNN , reaches the threshold of the NOR gate, both outputs are reset immediately as a result of the short reset-path delay, as given in Figure 3.15. If the delay is increased from ∆tot to ∆tot + tex, UP will be high for tex seconds longer and the charge deposited on charge pump will increase by ICP × tex. To solve this phenomenon, it is obvious that the reset-path delay must be more than the transition delay from reference input to a correct UP output, or similarly the transition delay from VCO output to a correct DN signal. This additional delay can be introduced with an AND gate with UP and DN inputs instead of negative ones as in Figure 3.16.

Figure 3.15: Shorter delay problem in reset path

The output frequency of the PLL systems is in 4.9GHz5.9GHz. With a ﬁxed division ratio of 6, required operation frequency for phase frequency detector should be 984MHz minimum. This frequency is considered to be minimum since PFD frequency range should also include parasitic eﬀects from extraction. Figure 3.17 shows the output waveforms of the extracted PFD, when the reference input and the divider output are in phase 1GHz square wave signals. Both UP and DOWN signal paths must be identical for symmetrical operation. This simulation is included here in order to show that this property assures the symmetrical operation in charge pump. In Figure 3.18, REF is leading VCO for 300ps.

Aylin Donmez M.Sc. thesis 3.1 Phase Frequency Detectors 29

Figure 3.16: Phase Frequency Detector used in this work

Figure 3.17: PFD output for in phase 1GHz square wave inputs

M.Sc. thesis Aylin Donmez 30 PFD & Charge Pump

Figure 3.18: PFD outputs at 1GHz when the reference signal leads for 300 ps

In both ﬁgures, propagation delay from an input to a correct UP or DN output is marked as 82ps and total reset delay of the PFD after extraction is 288ps allowing a maximum operation frequency of 1.74GHz. Power consumption during locked condition under typical operation is 0.246 mW from 1.2 V power supply.

Figure 3.19: PFD Characteristic

In Figure 3.20, output jitter of the phase frequency detector is given. The period jitter, (i.e., the standard deviation of the length of a single period which is measured as Jc k-cycle jitter when k=1) is 140fs as can be seen from Figure 3.20. In Figure 3.21, layout of the phase frequency detector is given. Area consumption for the layout was not a design constraint thus no extra eﬀort for area compaction is performed due to limited layout time, but carefully drawn layout can reduce the current are consumption

Aylin Donmez M.Sc. thesis 3.2 Charge Pumps 31

Figure 3.20: PFD Output Jitter area considerably.

3.2 Charge Pumps

3.2.1 Current and Pulsewidth Mismatch

The current sources IUP and IDN when implemented using MOS transistors, charge pump suffer from current mismatches. When the UP current source is implemented with PMOS and DN current source with NMOS, for same amount of current sources would have certain switching speed difference. This mismatch gives rise to a change or ripple in the control voltage Vc at each phase comparison. Phase offset due to charge pump mismatches is given by Equation 3.6;

∆TON ∆I φCTMIS = 2π × (3.6) TREF I

To minimize phase error originated from current mismatch, turn on time of current sources should be minimized.

3.2.2 Timing Mismatch

For the cases that charge pump is single ended, inverted UP signal is required to switch on the PMOS current source. This introduces certain amount of timing mismatch between the UP and DN inputs. When there is a certain time delay, between inputs then the phase oﬀset is given by;

M.Sc. thesis Aylin Donmez 32 PFD & Charge Pump

Figure 3.21: Phase Frequency Detector Layout

∆TON ∆TD φTIMEMIS = 2π × (3.7) TREF TREF

3.2.3 Leakage Current

One of the basic problems in charge pumps is the leakage current which may be caused by the charge pump itself, loop filter impedance, or the VCO control line. The amount of leakage current can be as high as 1nA in sub micron CMOS [23] . The loop response for this DC leakage current is a difference between the UP and DN signals that would produce the same amount of current equal to leakage current over one period. In other words, charge pump outputs a certain phase offset to compensate for this leakage current. This phase offset might be negligible for the cases that charge pump current is high however since the loop compensation current is periodic with fREF , this gives rise to spurious component at the output spectrum.

The phase oﬀset originated from leakage current can be calculated as;

ILEAK φLEAK = 2π (rad) (3.8) ICP

Thus total spurious component at the output is given by the total phase oﬀset caused by these components;

Aylin Donmez M.Sc. thesis 3.2 Charge Pumps 33

Figure 3.22: Charge Pump leakage current

φTOT = φLEAK + φCTMIS + φTIMEMIS I ∆T ∆ ∆T ∆T = 2π( LEAK + ON × I + ON × D ) (3.9) ICP TREF ICP TREF TREF

The magnitude of the spurious breakthrough is directly related to the total phase oﬀset and is calculated as [23];

N × fBW × φTOT fREF PSPURIOUS = 20 log √ − 20 log (3.10) 2fREF fP 1

st where N is the division ratio, fBW is the loop bandwidth, fP 1is the 1 pole frequency of the loop ﬁlter. It can be concluded that to reduce the amplitude of the reference spurs, division ratio, loop bandwidth and total phase mismatch should be minimized while increasing reference frequency.

3.2.4 Charge Injection

When the switches are ON, finite amount of charge is held in the channel. The charge that is held during ON time flows partially through both drain and source of the device. The amount that is injected through the load capacitance gives rise to control voltage even the inputs are OFF. This leads to wrong output signal. However if the MOS transistor is turned off while in saturation then all the channel charge flows into the source leaving the drain terminal unaffected. Cgd capacitance of a MOS transistor in triode region is given as; C W LC C = C = gg = ox (3.11) gd gs 2 2

For this condition gate to drain capacitance is larger compared to the capacitance magnitude in saturation. Thus it is always desirable to keep the output transistors in saturation in order to minimize the glitch current. In practical applications, this is hardly the case. Switches are generally operated in triode in order to have small on resistance. There is constant amount of charge in the channel which

M.Sc. thesis Aylin Donmez 34 PFD & Charge Pump is held when the switches are active and this charge is injected into the output nodes when the switches are turned oﬀ. When the input voltage of the switches has a transition time of ∆T while changing from logic low to high, the amount of the glitch current can be given as in Equation 3.12;

Iglitch = Cgd(VH − VL)/∆T = Cgd × S (3.12) where S is the slew rate of the input voltage during the transition. Thus this equation reveals an interesting property that the amount of glitch current gets larger with increasing Cgd capacitance and fast transitions. The amount of glitch current can be as large as the charge pump current or even larger than it but ﬂowing in the opposite direction. As a result charge injection in charge pumps is a serious problem that should be carefully taken care of.

3.2.5 Clock Feedthrough

This is due to the parasitic capacitances Cgd and Cgs. The error occurs when the fast rise and fall edges of a clock signal get coupled into the signal node via the gate to source and gate to drain overlap capacitances. This rise in signal level at times forward biases the junction diodes and leads to an injection error into the substrate leading to wrong operation if conducted by a high impedance node. However clock feed through error is signal independent and manifests itself as an output voltage.

3.2.6 Charge Sharing

This occurs when the output of a switch (for example a PMOS device) is set to high and then the switch is turned OFF. Than the cascade connected device is activated and its voltage dependent parasitic capacitances, Cgd and Cgs, are maximized. Since the gate of this device is floating, these parasitic capacitances share the gate charge and conduct it to both source and drain. This causes glitches at the output of this device, i.e the loop filter. This phenomenon occurs also in charge pumps causing glitches loop filter voltage. For High frequency high bandwidth applications of PLL, parasitic capacitances become comparable with the loop filter. This increases the charge sharing effect.

3.2.7 Charge Pump Architectures

Charge pump architectures can be classiﬁed into groups by the form of operation; single ended and diﬀerential operation.

Single-ended charge pumps

Single-ended charge pumps are widely used since they do not require complex configurations. Moreover with tri-state operation, single ended architectures offer low-power consumption compared to differential architectures. Single ended architectures typically have three types of switching locations; drain, gate and source switching.

Aylin Donmez M.Sc. thesis 3.2 Charge Pumps 35

• Drain switching ; For these architectures, switch is located at the drains of the current mirror. A very simple configuration for drain switching is given in Figure 3.23 (a). When the switch is turned OFF, drain of down current mirror is pulled to ground. When the switch is turned ON, this time drain voltage is increased to voltage level of the loop filter. During this operation, a high current peak occurs because of the voltage difference of the two series on resistors of the switch transistor and current mirror transistor, M1. For PMOS side, the same situation also occurs and the amount of these pmos or nmos current peaks vary with the output voltage. For the cases that switch is located at the drains of current mirror transistors, clock feed-through arises. Switch is directly connected to the loop filter thus high amplitude current spikes that occur at the very beginning of pump up/down action are injected directly to the loop filter.

Figure 3.23: Single ended charge pumps

• Gate switching [27]; In Figure 3.23 (b), a charge pump architecture with gate switching is given. With this topology it is guaranteed that current mirrors are always kept in saturation. Switching time is dependent on the transconductances of the mirror transistors M4 and M3. In order to meet high frequency operation speciﬁcations, charge pump current may not be scaled down since switching time is dependent on the gm’s of M4 and M3. This may set a limit for high frequency operation.

• Source switching ; The switch can also be located at the source of the current mirror satisfying that current mirrors are in saturation all the time. In contrast to gate switching, now switching time is not a function of gm’s of M4 and M3. This conﬁguration gives faster switching than gate switching since switch is connected to a node with low parasitic capacitance.

There also exist other variations of single ended charge pump architectures as given in Figure 3.24. In Figure 3.24 (a) a single ended charge pump with current steering technique is proposed [11]. Operation principle is similar to to the one given in Figure 3.23 (a) however the switching is improved by using the current switch. Thus it provides faster switching. Another single ended topology with an active ampliﬁer is given in Figure 3.24 (b). With this unity gain ampliﬁer the voltage at the drain of M1 and M2 is set to the voltage at the output

M.Sc. thesis Aylin Donmez 36 PFD & Charge Pump

Figure 3.24: Single ended charge pump architectures a)with current steering switch b)with active output buffer c)with NMOS switches only node when the switch is off to reduce the charge sharing effect when the switch is turned on. This architecture is useful when the parasitic capacitance is comparable to the value of the capacitor in the loop filter. In Figure 3.24 (c), intrinsic mismatch between NMOS and PMOS switches is avoided with NMOS only implementation of charge pump topology. Since the current does not flow in the current mirror, M6 and M7, when UP switch is turned OFF, the current mirrors still limit the performance unless large current is used. Thus the main drawback of this architecture is the lower speed due to the turning-off of the PMOS current mirror.

Diﬀerential Charge Pumps

A higher switching technique is differential switch that uses the current steering technique. This improves the switching speed however the mismatch between the PMOS and NMOS current sources. Fully differential charge-pumps are preferred in low-voltage low-jitter PLLs due to their increased supply and substrate noise rejection and higher voltage swing. On the other hand the leakage currents appear as a common mode glitch thus reducing spurious breakthrough of the reference signal. A differential charge-pump based on current steering decreases the severity of current mismatch problem. Any current mismatch between the NMOS and the PMOS transistors then appears as a common mode glitch, which is therefore suppressed by the following stages in a phase-locked loop.

3.2.8 Diﬀerential Charge Pump Design

Previous section gives a brief description of the problems that occurs with charge pump operation. The main problem is the current-mismatch, which arises as a result of the extra delay added to the reset-path of the PFD to eliminate the dead-zone. Ideally, a charge-pump PLL does not suﬀer from current-mismatch once it is locked, because the UP and DOWN

Aylin Donmez M.Sc. thesis 3.2 Charge Pumps 37 currents remain oﬀ all the time. However, in practical applications, after the additional reset- delay, the loop locks for a ﬁnite phase-error if there is a current-mismatch. The phase-error in terms of the mismatch ratio is given in Equation 3.9. As long as the reset-delay or the mismatch increases, the phase error also increases.

Figure 3.25: CPhigh speed

Figure 3.25 shows a fully differential charge-pump, which uses current steering technique. When the charge pump is not active, i.e. there is no difference between UP and DN current pulses, charge pump current is directed to a dummy branch. The advantage of this architecture is that when the output switches are turned off, the currents in transistors M9 and M11 or similarly M10 and M12 remain constant, and is just steered to the other branch. With this architecture current sources are always on and in saturation, thus charge sharing effects due to the switching are minimized. However the output common mode voltage needs to be controlled in order to satisfy that full output swing can be used.

Switch Design

Transistors M1 to M8 are simple switches processing the information received from the phase frequency detector. As to lower the on resistance of these switches, it is desirable to maximize their sizes. If the channel resistance is not suﬃciently low then there is a certain voltage drop across the switch which limits the available the output range for control voltage. When the switches are too large, another limitation reveals that their parasitic capacitances increases the slewing and slows down the switching operation. High frequency operation may not be performed when the switches are too large. Channel resistance of a MOS transistor operating

M.Sc. thesis Aylin Donmez 38 PFD & Charge Pump in triode is given as in Equation 3.13 [20];

1 1 r = = on V 2 δiD/δvDS KW DS δ L [(Vgs−VT )VDS − 2 ] δVDS L = KW (Vgs − VT ) − VDS

(3.14)

A good switch design is performed with a good compromise of channel resistance and gate drain capacitance. However channel resistance is proportional to L while the gate drain capacitance is proportional to W × L as given in Equation 3.11. Thus, for a minimum length device, there exist an optimum device width. On the other hand, switch size is critical parameter, also in noise contrubition of the charge pump. Noise voltage contribution of a switched transistor can be derived from its thermal equivalent noise resistance as [20];

2KT r e2 = 4KT r V 2/Hz = on V 2/rad/s (3.15) ron on π

Noise contribution theory also claims that on resistance of the switches should be minimized in order to reduce charge pump noise contribution.

• Simulations and Layout In Figure 3.26 noise voltage at charge pump output is given. Diﬀerent curves refers to swept switch sizes. If the switch sizes are too small, (i.e. 5u), in band noise contribution of switches can be as high as 5dB additional. However after a certain switch size, noise levels stay almost same. As a result switch sizes is chosen as 20u and switch layout is given in Figure 3.27.

Common Mode Feedback Circuit

With fully differential architectures, output common mode voltage is not well defined. Charge pump architecture used in this design is a fully differential one. When the currents flowing through each branch are not balanced, output voltages may increase or decrease. In other words, when the output switches are both OFF, output node voltages are not defined. Thus a control mechanism is required to set these voltages to a proper value. The circuit given in Figure 3.28 is used in this work for common mode signal stabilization at output. Operation of this block can be briefly expressed as follows; For the case that both OUT + and OUT − are equal to each other in magnitude but they have opposite signs, the current in M1 and M3 would be equal to each other while the current in M2 and M4 would be equal too. This relation holds as the magnitudes of the input differential voltage stays the same. As long as OUT + and OUT − are equal in magnitude but have different polarities, the current

Aylin Donmez M.Sc. thesis 3.2 Charge Pumps 39

Figure 3.26: Noise voltage at charge pump output

Figure 3.27: Switch layout

M.Sc. thesis Aylin Donmez 40 PFD & Charge Pump

Figure 3.28: Common Mode Circuit

into the diode connected transistor M7 would stay constant. It is concluded that this type of circuit does not respond to diﬀerential signals.

When the common mode voltage is not equal to VCM , for example common mode voltage at OUT + and OUT − is bigger than VCM , than the current through M2 and M3 increases the sourcing current from the diode M7. This current can be copied and added to charge pump current. Increase in charge pump current pulls down the output nodes to lower voltage, thus performing negative feedback on common mode voltage. The output currents are injected into the nodes in the charge pump shown in Figure 3.25. However, it has to be carefully designed that common mode loop always have additional poles and zeros to the system. The injection of common mode signals can cause the system become unstable thus common mode circuit has to be compensated. During the design of such a common mode loop, it is an important consideration that phase margin and step response is veriﬁed.

• Simulations and Layout Common mode feedback circuit should respond to slow changes at output nodes, however its bandwidth should still be bigger than the loop bandwidth. In Figure 3.29, its low frequency transconductance is shown as 300µ/V . Layout for common mode circuit is given in Figure 3.30(a). Transistor sizes are given in Table 3.1.

Aylin Donmez M.Sc. thesis 3.2 Charge Pumps 41

M15,M16 12u/0.2u M17,M18,M19,M20 25u/60n M21,M22 8u/0.2u

Table 3.1: UGB transistor sizes

Figure 3.29: Transconductance of common mode loop

M.Sc. thesis Aylin Donmez 42 PFD & Charge Pump

(a) CM (b) UGB

Figure 3.30: Layouts of common mode circuit and unity gain buﬀer

Aylin Donmez M.Sc. thesis 3.2 Charge Pumps 43

(a) Unity Gain Buﬀer (b) UGB Schematic

Figure 3.31: Unity gain buﬀer used in this work

Unity Gain Buﬀer Circuit

In single ended charge pump architectures charge injection of the switches can be eliminated with correct placement of the switches, (i.e. drain, gate, source switching) as mentioned in Section 3.2.4. However, with differential architectures, switches are located at the output nodes, and the topology suffers from charge injection of both the switches and common source nodes X and Y or X0 and Y 0, (nodes are shown in Figure 3.25. The charge injection from nodes X and Y is typically much greater than that of the switches, and modifications has to be made to reduce these effects.

On the other hand when the dummy branch is inactive, the nodes VDX and VDY in Figure 3.25, are not defined. Therefore a buffer is required to hold the voltage of the replica node to the same voltage as that of the output node. The advantage of this architecture is that when the output switches are turned off, the currents in transistors M9 and M11 or similarly M10 and M12 remain constant, and is just steered to the other branch. This means that the voltages at nodes X and Y or X0 and Y 0 stay approximately constant, minimizing charge sharing. The opamps used in the buffered charge pump are in a standard rail to rail input topology [28]. In a simple rail-to-rail input stage, an n-channel differential pair and a p-channel differential pair are used in parallel as shown in Figure 3.31(b). There are basically three operation regions; when the common mode voltage, VCM is near the negative power supply, Vss, or Gnd in this work, only the p-channel pair operates. For VCM , near the positive power supply, Vdd, only the n-channel pair operates. For VCM around mid-rail, both differential pairs operate. As a result, at least one of the two differential pairs will be operating for any VCM between the rails. Since there are three regions of operation for the input stage of the unity gain buffer, there are

M.Sc. thesis Aylin Donmez 44 PFD & Charge Pump

three diﬀerent regions for the total transconductance, gmT , which is given, in strong inversion, by;

p p gmT = gmn + gmp = 2KnIn + 2KpIp where Kn and Kp are the transconductance parameters of the n− and p− channel input transistors.When the current sources are implemented with a constant current sources, gmT varies depending on the operation region. This may lead to a complexity in frequency compensation, thus the loop may be driven out of stability. In Figure 3.32, AC response of the closed loop for diﬀerent common mode input is given. Minimum and maximum bandwidths are as 285.7MHz and 389.1MHz which is well above the loop bandwidth for a common mode range of 100m ∼ 1.1V and stays below the reference input not to respond to input signal. On the other hand, the noise from the CMFB circuit and unity gain buﬀer circuit is common mode to the charge pump, so it has little impact on the phase noise of the frequency synthesizer.

• Simulations and Layout Transistor sizes of the unity gain buﬀer circuit is given in Table 3.2.

M1,M2 18u/60n M3,M4 25u/60n M5 2u/0.2u M6 4.2u/0.2u M7,M8 6u/2u M9,M10,M11,M12, 16u/2u

Table 3.2: UGB transistor sizes

Layout for unity gain buﬀer circuit is given in Figure 3.30(b).

Bias Block

The complete circuit of the bias block used in charge pump design is shown in Figure 3.33. The circuit consist of wide swing current mirrors and a start up circuit. Transistors M1 to M2, form the n channel current mirror together with the diode connected bias transistor M12. Transistors M3 to M4 simply act as a current mirror. Gate voltages of these transistors are derived from the diode connected transistor M12. The current for the biasing transistor M12 is produced by the current copy transistors M13 and M14. Similar structure holds for the PMOS current mirror components. M11 is used for biasing purposes of gates of M5 and M6 and the current into this diode connected transistor is produced via M9 and M10. This bias loop has two solutions since it is a modiﬁed version of general gm bias circuit. There is a possibility for the current into the transistors to be zero. Once this occurs, the circuit stays stable in this condition forever thus it does not start up. To ensure this condition does not happen, a start up circuitry that aﬀects the bias loop only when the currents are zero, is required. M15, M16, M17 and M18 are included for this purpose. When there is no current

Aylin Donmez M.Sc. thesis 3.2 Charge Pumps 45

Figure 3.32: AC response for diﬀerent input levels of UGB

Figure 3.33: CP-Bias Block

M.Sc. thesis Aylin Donmez 46 PFD & Charge Pump

flowing in the loop, M15 is off. M16 being always on, operates as a high impedance load. It pulls the gates of M17 and M18 high. These transistors, M17 and M18, will then inject current into the bias loop via M10 and M4. This would start up the circuit. Once the circuit are biased properly M15 sinks all the current from M16 and it pulls down the gates of M17 and M18 to low thus turning them off. Once the circuit starts up, then there is no current flowing through the transistors in start-up circuit.

M1,M9,M15,M17,M18 3u/0.2u M2 12u/0.2u M3,M4,M10 3u/0.3u M5,M6,M14 6u/0.3u M7,M8,M13 6u/0.2u M11 1.2u/0.3u M12 0.6u/0.3u M16 0.6u/6u

Table 3.3: Bias Block transistor sizes

Figure 3.34: Layout for CP bias block

Glitch Suppression

High-speed glitch is mainly originated from the charge sharing effect discussed in Section 3.2.4. There are several techniques for charge injection cancellation as given in [22]. In this work transmission gates are used for charge cancellation. Charge injection effects can be partially eliminated by making use of complementary switches. The amount of charge injected to the output node have different signs, and with a good combination of the PMOS and NMOS devices, injection of charge to output node can be lowered.

Aylin Donmez M.Sc. thesis 3.2 Charge Pumps 47

Figure 3.35: Transmission gate as a switch

For fully cancellation of charge injection, ∆qN and ∆qP should be equal to each other.

∆qN = WN LN Cox(VCK − VIN1 − VTHN ) = WP LP Cox(VCK − VIN1 − VTHP ) (3.16) From this result, it can be seen that, cancellation of charge depends on the accuracy in device sizes, and the threshold voltages of PMOS and NMOS devices as in Equation 3.17. Thus totally cancellation is not possible however reduction in charge injection is expected.

WN LN (VCK − VIN1 − VTHN ) = WP LP (VCK − VIN1 − VTHP ) (3.17)

Charge pump of this work is modified as given in Figure 3.36 in order to have suppressed the high speed glitches. After adding the modified switches, the high-speed glitches are almost completely eliminated from the output current since PMOS and NMOS transistors in transmission gates are matched. In practical implementation, however, this performance will be limited by the resistance in the loop filter and any other parasitic resistance like routing resistance and gate resistance.

Figure 3.36: Modiﬁcation for Glitch Suppression

However there is an obvious drawback which is the increased complexity as compared with the standard architectures, as it is now necessary to generate and route both the primary input signals and their inverses.

M.Sc. thesis Aylin Donmez 48 PFD & Charge Pump

Total power consumption under typical operation is 2.05 mW from 1.2V power supply.

Figure 3.37: Charge pump Full Schematic

Aylin Donmez M.Sc. thesis 3.2 Charge Pumps 49

Figure 3.38: Complete Charge pump layout

M.Sc. thesis Aylin Donmez 50 PFD & Charge Pump

Aylin Donmez M.Sc. thesis Chapter 4

VCO & Divider

The VCO is the most challenging part of the PLL design, especially if the PLL reference input frequency is high. In this case, a high frequency VCO is necessary. Oscillators may seem like simple devices, until you have to design one into your system. That’s when you may discover there is much more to these critical timing devices than meets the eye. There are many requirements for the VCO in a PLL design, which conﬂict with one another. Therefore, a special care must be taken in the VCO design. Some of the most important VCO requirements and VCO terms include the following:

• Control Voltage : This is the varying voltage, which is applied to the VCO input terminal causing a change in the output frequency.

• Free-Running Frequency : FR is the output frequency of the VCO for a zero control voltage. It is sometimes referred to as center frequency.

• Tuning Range : The range of frequencies over which the VCO can operate as a result of the applied control voltage.

• Frequency Deviation : This is how far the center frequency will change as a function of the control voltage; usually speciﬁed in ± percentage or ppm. As the deviation is made larger, other stabilities such as, temperature and aging will usually degrade.

• Linearity: The generally accepted deﬁnition of linearity is the ratio between frequency error and total deviation, expressed in percent, where frequency error is the maximum frequency excursion from the best straight line drawn through a plot of output frequency versus control voltage.

• Response Slope : The slope of the frequency versus the control voltage. This is generally referred to as the VCO gain, KVCO, or the tuning performance and expressed in megahertz per volt (MHz/V).

M.Sc. thesis Aylin Donmez 52 VCO & Divider

• Transfer Function : This denotes the direction of frequency change versus control voltage and sometimes referred to as Slope Polarity. A positive transfer function denotes an increase in frequency for an increasing positive control voltage. Conversely, if the frequency decreases with a more positive control voltage, the transfer function is negative.

• Phase Stability : The output spectrum of the VCO should approximate as good as possible the theoretical Dirac-impulse of a single sine wave. It is mostly referred to as ’Spectral Purity’ and quantiﬁed by phase noise, which is expressed in terms of dBc/Hz.

• Frequency pushing : It is the dependency of the center frequency on the power supply voltage expressed in MHz/V. In this work, SVDD is used as the sensitivity parameter.

• Frequency pulling :It is the dependency of the center frequency on the output load impedance.

• Tuning Speed :This is the time required for the output frequency to settle to within 90% of its ﬁnal value with the application of a tuning-voltage step.

• Output Amplitude : It is desirable to achieve large output oscillation amplitude, thus making the waveform less sensitive to noise. The amplitude trades with power dissipation, supply voltage, and even the tuning range. Also the amplitude may vary across the tuning range, which is an undesirable eﬀect.

• Output Characteristics : This deﬁnes the output waveform of the VCO. In PLL applications, sine or square-waves are used mostly.

• Power Dissipation : As with other analog circuits, oscillators suﬀer from trade-oﬀs between speed, power dissipation, and noise.

In literature many types of oscillators can be found [19]. Depending on the application, these types are beneﬁcial or undesirable. In current application, oscillator types are discussed by their phase noise, i.e jitter, performance and their supply sensitivity. CMOS voltage controlled oscillators, VCOs, are customary designed either by using ring oscillator architectures or LC resonant circuits. Although amongst these applications, LC designs has better phase noise performance, they are undesirable due to the increased complexity and cost by addition of high quality integrated inductors. In spite of LC oscillators, ring oscillators can be built in any standard CMOS technology with much less die area. Moreover, they oﬀer multiple output phases and wide tuning ranges. In this work, main focus is on ring oscillators due to ease in integration.

4.1 Ring Oscillator VCOs

Ring oscillators are often used in PLL applications due to their simplicity and ease in IC integration. Basic oscillation principle is based on the ring of inverters in a chain. However, with single ended structures it is not possible to achieve oscillation with less then three stages and odd number of inverter stages is required [21]. In a certain technology, total delay of three inverter stages puts a limit to the maximum achievable frequency.

Aylin Donmez M.Sc. thesis 4.1 Ring Oscillator VCOs 53

4.1.1 Single Loop Ring Oscillator Design

Figure 4.1: Three-stage ring oscillator

Figure 4.1 shows a typical single-stage inverter placed in a unity-gain loop where R and C are the output equivalent node resistance and capacitance of the inverter stage, respectively. Under the assumption that all stages are identical, system has three poles located at ωp in Equation 4.1 which is the 3dB bandwidth of a single stage inverter.

1 ω = (4.1) p RC

o For three stage inverter, total phase shift of the system at ωp equals to −135 (each stage contributes −45o) and as ω = ∞ total phase shift becomes −270o. Therefore, a certain frequency exists for the system that total phase shift equals to −180o, i.e. each stage has a phase shift of 60o. Each stage also contribute a DC phase shift of −180o thus waveform at each node is −240o out of phase with respect to the previous node. Nevertheless, to meet the Berkhausen criteria, loop gain must be equal to unity at the oscillation frequency. Transfer function of each stage is given as;

A G(s) = − (4.2) 1 + s ωp Thus, transfer function for the open loop three stage oscillator is given as;

A3 H(s) = − (4.3) (1 + s )3 ωp

To meet the phase shift criteria of 180o in three stage design, single stage should have a phase shift of 60o at oscillation frequency ;

√ ωo o ∠G(s) = arctan = 60 ⇒ ωo = 3ωp (4.4) ωp

From 4.1 and 4.3 general oscillation frequency can be given as;

tan θ ω = (4.5) O RC where θ is the total phase shift of each stage individually.

M.Sc. thesis Aylin Donmez 54 VCO & Divider

To meet the loop gain criteria, magnitude of the loop gain at the oscillation frequency should be equal to or greater than unity.

A3 |H(ωo)| = 3 = 1 (4.6) r 2 1 + ωo ωp Applying 4.4 into 4.6 each stage should have a gain of A = 2 for proper oscillation. Closed loop poles can be examined to see this property clearly.

V 1 OUT = (4.7) VIN 1 − H(s) One of the three closed loop poles is real and other two are complex conjugate;

s1 = (−A − 1)ωo (4.8)

√ ! A(1 ± j 3) s = − 1 ω (4.9) 2,3 2 o

Thus the output waveform in time domain can be given as; √ ! A−2 ω t A 3 V (t) = ae( 2 p ) cos ω t (4.10) OUT 2 p

According to the Berkhausen criteria;

• If A ≺ 2, The poles are on left half plane, and output decays exponentially to 0. Thus, circuit fails to oscillate.

• If A=2, then two poles√ are on jω axis, one pole is on real axis. The output is a sinusoid at the frequency of 3ωo. Thus, steady state oscillation occurs.

• If A 2, two complex poles now have a positive real part and hence give rise to a growing sinusoid. Thus, the oscillation grow in amplitude and goes to inﬁnity. However in most practical cases, due to nonlinearity and eventually saturation of the stages oscillation amplitude is limited.

In practical conditions oscillation frequency is deﬁned based on the total delay of the inverter stages;

1 fo = (4.11) 2ntd

This oscillation frequency, fo, is obviously not equal to the frequency obtained from the small signal analysis since small signal analysis does not include the non linear behavior of active components as the oscillation amplitude grows. For the current application rail to rail switching is aimed. Small signal behavior study gives an insight on how the system operates but it does not a suﬃciently explain dynamics in rail to rail switching.

Aylin Donmez M.Sc. thesis 4.1 Ring Oscillator VCOs 55

4.1.2 Multi Loop Ring Oscillator Design

When ring oscillators are implemented in single loop inverter stages, maximum operating frequency is simply set by the total delay of the inverter stages. For a fixed technology, maximum achievable frequency relays on the minimum delay of a single stage. This restric- tion reveals a challenging requirement on maximum attainable frequency. There are many techniques that offer high frequency ring VCOs, available in literature such as sub feedback loops [16], multi feedback loops [7], dual delay paths [25] or oscillator coupling [1]. General multi loop architecture which is shown in Figure 4.2 is one of the promising techniques that operates at higher frequencies and it is the main configuration used in this work. In this architecture, inverter stages have two differential inputs P −,P + and S−,S+. Main inputs being P −,P + constitute the strongest path, the auxiliary feed forward inputs, being S−,S+, reduce the delay of the stages by speeding up the transition at output nodes. The frequency of operation is defined by the number of stages in both loops, and the fastest path sets the operation frequency.

Figure 4.2: 4 Stage Multi Loop Ring Oscillator

To understand the frequency control mechanism in multi feedback loops, even and odd number of stages are studied here.

Odd Number of Stages

Figure 4.3: 3-stage ring oscillator with multi loop architecture

In Figure 4.3, a simple conﬁguration of multi loop architecture with three stage inverters is given. Secondary feed forward loops are obtained by connection of kth outputs to nth inputs where N is the number of stages, n equals to [(k + x) modN], and (x − 1) is the number of stages that feed forward loops passover [8]. Under the assumption that each output can be modeled with a single output resistance, R and capacitance equivalent, C, small signal analysis can be applied to the 1st order model given in Figure 4.4. In this model 1st stage consist of a diﬀerential stage where the main loop is composed of inverters −GM and the auxiliary loop is formed by the inverters −gm.

M.Sc. thesis Aylin Donmez 56 VCO & Divider

Figure 4.4: 3 stage ring oscillator 1st order model

Prior to small signal behavior study, it should be strictly stated that ring oscillators are highly nonlinear, large signal systems. Their operating parameters greatly deviate from the ones obtained from small signal analysis. Since rail to rail switching is the main design goal in order to minimize phase noise requirements, it is likely that transconductance of transistors decreases with increasing signal swing. However small signal analysis is still essential to attain an insight about the circuit parameters that control frequency. In multi loop architectures main loop is intentionally designed to be stronger than the auxiliary loop, thus phase relation is determined by the main loop. For a three stage design following condition holds;

−jθ Vn+1 = Vne (4.12)

−jφ Vn+1 = Vk+1e (4.13) where the output of a single stage can be given as; R V = (−V G − V g ) (4.14) n+1 1 + jωRC n M k+1 m

jφ Output Vk+1 can be rewritten as Vn+1e . Thus; −RG −Rg V = M V + m V ejφ (4.15) n+1 1 + jωRC n 1 + jωRC n+1

Rearranging the Vn and Vn+1 terms, transfer function can be written as given in Equation 4.16. Vn RGM H(jω) = = jφ (4.16) Vn+1 1 + jωRC − Rgme or in other form, the term ejφ can be expressed in terms of its imaginary and real parts;

V RG H(jω) = n = − M (4.17) Vn+1 1 − gmR cos φ + j(ωRC − Rgm sin φ)

Aylin Donmez M.Sc. thesis 4.1 Ring Oscillator VCOs 57

Phase shift of each stage can be calculated from the phase of its transfer function.

−1 ωRC − Rgm sin φ ∠H(jω) = ±π − tan (4.18) 1 − gmR cos φ As previously mentioned, phase relation between the stages is determined by the main loop. Thus, obtained result in Equation 4.18 should be equal to the phase diﬀerence between Vn and Vn+1, θ. Thus phase shift of single stage in terms of circuit parameters can be given as;

ωRC − g R sin φ tan(θ ± π) = tan θ = m (4.19) 1 − Rgm cos φ From Equation 4.19 oscillation frequency can easily be given as;

tan θ g ω = − m [tan θ cos φ + sin φ] (4.20) o RC C

For the case gm = 0, oscillation frequency equals to the one given for single loop architectures. It is clearly stated in Equation 4.20 that frequency improvement in multiple pass architecture should be possible under the condition that tan θ cos φ+sin φ ≤ 0 is satisﬁed. Since for a ﬁxed number of inverter stages, available phases in loop is determined, connection scheme should be done to satisfy this condition. For a three stage system, total open loop gain is given as in Equation 4.21;

RG 3 G(jω) = H(jω)3 = − M (4.21) 1 − gmR cos φ + j(ωRC − Rgm sin φ)

According to the Berkhausen criteria, the magnitude of the loop gain at the oscillation frequency should be equal to unity. For a three stage ring oscillator, condition in Equation 4.23 should hold. 3 RG G(jω) = |H(jω)|3 = − M = 1 (4.22) p 2 2 (1 − gmR cos φ) + (ωRC − Rgm sin φ) For oscillation condition to be satisﬁed, condition in Equation 4.23 should hold.

p 2 2 RGM ≥ (1 − gmR cos φ) + (ωRC − gmR sin φ) (4.23)

Substituting ωRC − Rgm sin φ term from 4.19 into 4.23 one can easily conclude that required gain relation of main and auxiliary loop should satisfy the following condition;

1 − gmR cos φ RGM ≥ (4.24) cos θ Equation 4.24 is an important result that requires special attention since the gain of the loop function determines the start up conditions. On the other hand, frequency improvement is not totally controlled or in other words it is not constant for a given process since absolute improvement factor depends on process parameters that control output equivalent resistance, R and capacitance C. Thus parameters obtained from theoretical analysis may not result in desired frequency improvement.

M.Sc. thesis Aylin Donmez 58 VCO & Divider

Even Number of Stages

Multi loop architecture can also be implemented in even number of stages. However, to satisfy the Berkhausen oscillation criteria, additional π rad phase shift should be introduced to the loop. In Figure 4.5, an example of a 4 stage multiple pass ring oscillator architecture is given. For even number of inverter stages, phase relation of the auxiliary loop should be kept same as the odd number of stages. Model used given in Figure 4.4 is still can be used since internal conﬁguration of delay stages is assumed to remain same. Additional phase shift is introduced only with modiﬁcation of the connection scheme. Phase shift of π rads is assumed to be introduced to loop by reversed inputs of the 1st stage.

Figure 4.5: 4 stage multiple pass ring oscillator architecture

Transfer function of each stage can be given as in Equation 4.25. V RG H(jω) = n = − M (4.25) Vn+1 1 − gmR cos φ + j(ωRC − Rgm sin φ)

Phase information around the loop can be obtained by addition of individual phase shifts of each stages. Thus, Equation 4.26 should be the starting point to examine phase behavior in even loops.

2πk = ∠H1(jω) + ∠H2(jω) + ∠H3(jω) + ... + ∠HN (jω) (4.26)

Phase shift of all stages would be identical except from the 1st stage. Thus Equation 4.26 can be simpliﬁed as;

2πk = ∠H1(jω) − (N − 1)θ (4.27) where N is the number of stages in the loop and θ is the phase shift between the main inputs and outputs. Since ∠H1(jω) is designed to have a phase shift of −θ ± φ in order to satisfy Berkhausen oscillation condition, total phase shift can be related to θ as in Equation 4.28.

(2n − 1)π θ = (4.28) N

At the oscillation frequency, phase shift of each stage from the transfer function should be equal to −θ ± φ. ωRC − g R sin φ θ ± φ = − tan−1 m (4.29) 1 − Rgm cos φ

Aylin Donmez M.Sc. thesis 4.2 Gain Stages 59

tanθ g ω = + m [sin φ − tan θ cos φ] (4.30) o RC C This is an expected result for the operating frequency, which the same as 4.19.

RG 4 G(jω) = H(jω)4 = M (4.31) 1 − gmR cos φ + j(ωRC − Rgm sin φ)

Total loop gain of 4 stage ring oscillator, given in 4.31, has a sign inversion compared to the one given in three number of stages. Minimum gain requirement of each single stage can be obtained as the same way for odd number of stages.

p 2 2 RGM ≥ (1 − gmR cos φ) + (ωRC − gmR sin φ) (4.32)

4.1.3 Loop Architecture Decision

From the discussion in previous sections, it can be easily seen that for multi loop applications, inputs of the delay cells have to be split either by splitting the NMOS transistors or introducing additional PMOS inputs. This, in addition to other necessary components such as frequency tuning and bias current sources, increases the complexity of the oscillator. Simple mis connection in the delay cell or in the top level loop routings may lead the loop to an undesired, perfectly stable, latch up condition. However, multiple loop architectures introduce fast transitions at the output nodes thus allowing high frequency operation meanwhile reducing phase noise. With single loop architectures, it is not possible to meet high frequency with poor transitions at the outputs and also phase noise performance is worse compared to multi loop topologies. As a result, for this work multiple pass architecture is desirable for their superior phase noise performance and high frequency operation.

4.2 Gain Stages

In previous section loop structure is analyzed by means the parameters that control frequency improvement in the loop. Although, frequency range of an oscillator is an essential speciﬁcation to be met, there are other exclusive parameters to be taken into account. Constraints such as phase noise or jitter are also signiﬁcant performance parameters, and they are originally depend on the type of the delay cell used in inverter stages. When the delay cells are biased in continuous conduction, i.e. switching is not rail to rail, phase contribution of the active components increases. 1st order model given in Figure 4.1 can be used to make the an approximated noise power estimation as [24];

∆T 4kT R PNOISE = 2 (4.33) T 1 + (2πfmRC)

M.Sc. thesis Aylin Donmez 60 VCO & Divider

where T stands for the oscillation period, ∆T is the on time of transistor, fm is the offset from the carrier and RC is the approximated 1st order time constant. For differential systems power supply rejection ratio is given as the ratio of differential gain, AV (when the supply is clean), to the power supply gain, Add, when the input is 0;

AV (Vdd = 0) VOUT = Add(Vin = 0) Add Add 1 = Vdd ≈ Vdd = + Vdd 1 + AV AV PSRR

(4.35)

While it would be still possible to calculate gains Add and AV separately, differential system can be considered in unity gain configuration, and power supply rejection can be calculated directly as in Equation 4.34. For the calculation of PSRR in different delay cells of this work, they are all considered in unity gain configuration. In following sections, a brief study on gain stages is carried out.

4.2.1 CMOS Digital Inverter

An accurate estimate of the gate delay through a simple CMOS inverter gives an insight for the phase noise analysis of diﬀerent gain stages.

Figure 4.6: Simple Inverter

Throughout the literature, several studies have been performed on noise analyses of single stage inverters. Here only, results of analyses from [2] is referred in order to make comparisons with other delay cells. Propagation delay of a simple CMOS inverter is designated as the time diﬀerence between the input threshold crossing and output toggle moment [2]. This propagation delay can be given as 4.37;

V C τ = DD (4.36) inv I where C stands for the total output capacitance at output node and I is the current driven during the switching.

Aylin Donmez M.Sc. thesis 4.2 Gain Stages 61

• Phase Noise Phase noise of a single inverter is given by [19], 4kT 1 1 fO 2 Sφ = (γN + γP ) + ( ) (4.37) I Vdd − Vt Vdd f

where Vt is the threshold voltage of inverter. γN and γP are the channel noise parameters of NMOS and PMOS transistors, respectively.

• Supply Sensitivity Simple CMOS digital inverter has a low pass power supply rejection characteristic. Voltage transfer function from positive supply, VDD to output node VO has a pole approximately at − s(Cgs1+Cgs2+Cl) and a zero − Cgs2 where the zero is at higher frequencies. gm1+gm2 gm2

∂Vo gm2 + sCgs2 SVDD = ≈ (4.38) ∂Vdd gm1 + gm2 + s(Cgs1 + Cgs2 + Cl) Within the PLL loop power supply rejection of single inverter is suppressed with the amount of loop gain. However outside the loop bandwidth, supply noise rejection, PSRR, remains constant at a certain value. As a result, digital inverter exhibits extremely poor low-frequency PSRR since any power-supply noise is ampliﬁed by the small-signal gain of the inverter. This is one of the reasons why digital inverters are not frequently used in VCOs that are intended for jitter-sensitive applications.

4.2.2 Diﬀerential Pair

In contrast to single ended simple inverter stages, differential ring oscillators can be implemented with either odd or even number of stages. Differential ring oscillator buffer stage can be considered as a gain amplifier with a control input. This control input can be implemented as a current sink or current source as given in Figure 4.7.

Figure 4.7: Delay Control in Diﬀerential Gain Stages

The diﬀerential stage given in 4.7(a) exhibit small tuning range because the output capacitance and resistance is not a function of tail current and time constant is not well controlled.

M.Sc. thesis Aylin Donmez 62 VCO & Divider

For the configuration in 4.7(b), load transistors are biased in triode region. Thus their on resistance is set by the control voltage. As VCONTROL drops, time constant at the output node also drops, and on the other hand small signal gain also decreases. Eventually, this may result in a large drop of loop gain that circuit may fail to oscillate for lower VCONTROL. For the configuration 4.7(c), small signal impedance of the load transistors are adjusted via the controlled tail current and since the small signal gain is fixed gm ratios of the NMOS and PMOS transistors, gain stage is frequently used in ring oscillator applications. In general form their oscillation frequency is given as [2];

1 IT AIL fO = = (4.39) 2ln2NRC 2ln2NCVOUT where N is the number of stages, R is the equivalent output resistance, C is the equivalent output capacitance, IT AIL is the tail current per stage and ﬁnally VOUT stands for the amplitude of the output waveform.

• Phase Noise Phase noise of a diﬀerential gain stage can be given as in general form as [2];

2 2kT gmt 3gmd 1 fo Sφ = 2 γt + γd + (4.40) IT AILln(2) 2 4 R f

where γt and γd are the channel noise parameters of tail transistor and diﬀerential pair, and gmd is transconductance of diﬀerential pair and gmt stands for the transconductance of the tail current source.

• Supply Sensitivity Supply sensitivity of a diﬀerential pair can be given as in Equation 4.41 [4];

2 ∂Vo 1 + sgmrdsCP SVDD = ≈ 2 2 (4.41) ∂Vdd gmrds(CP + CO)

4.2.3 Delay Cell with push pull inverters (DC1)[12]

Another type of delay stage which is suitable for multi loop implementation is presented in [12] given Figure 4.8. For frequency improvement, secondary inputs are implemented with a push pull inverter. These inverters basically sharpens both low to high and high to low transitions.

Primary loop is implemented via transistors M3 and M9, while PMOS transistors M6 and M8 forms the load of the gain stage. In a multi loop conﬁguration, VS+ is designed to be earlier than VP +, secondary inverters starts sourcing current to the parasitics at the OUT − output node before the main inputs. In this manner, low to high transition at the output node speeds up and delay is decreased. With this conﬁguration, frequency control mechanism is implemented via load transistors M6 and M8. For an extreme case where the control voltage is too high that these loads

Aylin Donmez M.Sc. thesis 4.2 Gain Stages 63

Figure 4.8: (DC1) Delay Cell Proposed by [12]

are turned oﬀ, oscillation is maintained by grounded extra loads M4 and M10. Thus output frequency settles to a constant value for higher values of control voltage. However, since these extra loads are biased in triode, their noise contribution is continuous during the complete oscillation period. Moreover they increase the current consumption since they are biased in continuous conduction. In addition, cross coupled NMOS latch transistors ensure diﬀerential operation mode, however they limit output voltage swing.

• Phase Noise

Figure 4.9: Phase Noise of DC1 @ 5.053GHz

M.Sc. thesis Aylin Donmez 64 VCO & Divider

• Supply Sensitivity

Model used for PSRR calculation is given in Figure 4.10 and supply sensitivity of a DC1 can be given as in Equation 4.42;

Figure 4.10: Small signal equivalent model of DC1 used to calculate PSRR [12]

∂Vo gm4 + gm6 + sCgs2 SVDD = = (4.42) ∂Vdd gm1 + gm3 + gm5 + s(Cgs1 + Cgs2 + Cgs3 + Cgs5 + Co)

4.2.4 Delay Cell with feedback control (DC2)[24]

The circuit proposed in Fig. 4.11 has a diﬀerential structure in order to reduce the power supply injected noise.

Figure 4.11: (DC2) Delay Cell [24]

The tail current source, implemented simply with a MOS transistor, is removed to reduce noise. PMOS load transistors, M1 and M2 form a latch structure, and cross coupled NMOS M3 and M4 control the maximum gate voltage of this latch, thus, they limit the strength of the added latch. When VCONTROL is low, the strength of the latch becomes weak and the output current increases. When VCONTROL is high, the latch becomes stronger resisting the voltage switching of the diﬀerential cell. Therefore delay time increases. Since, positive feedback of the latch determines the transition time, output waveform keep performing full switching, although the delay time changes with control voltage.

• Phase Noise

Aylin Donmez M.Sc. thesis 4.2 Gain Stages 65

Since it is diﬃcult to analyze the noise characteristics of the saturated ring oscillator accurately, the output phase noise of the saturated-type ring oscillator is approximated by the switching operations on the thermal noise current in the MOS devices. The generated noise power can be given as in Equation 4.33.

Figure 4.12: Phase noise of DC2

• Supply Sensitivity Model used for PSRR calculation is given in Figure 4.13 and power supply rejection of delay cell in Figure 4.11 is given in Equation 4.43. Power supply noise is directly injected to the delay with transistor M7 while transistor M1 is subject to the voltage division between the Cgs of the M1 and output resistance of M4.

Figure 4.13: Small Signal Model of DC2 used to calculate PSRR in [24]

M.Sc. thesis Aylin Donmez 66 VCO & Divider

∂Vo SVDD = ∂Vdd 2 s Cgs1Cgs7 ≈ 2 s Cgs1(Cgs4 + Cgs5 + Cgs7 + Co) + sCgs1(gm4 + gm5) + gm1gm4

(4.44)

4.2.5 Delay Cell with common mode noise rejection (DC3)[15]

Delay cell proposed by [15] introduces new considerations for low phase noise and common mode noise rejection. As shown in Figure 4.14(a), each delay cell has complementary inputs and differential control terminals. Output latch is introduced in order to store logic output levels, and meanwhile they assure rail to rail switching. Input inverters are driven via the inputs. However, strength of these inverters are controlled by differentially controlled voltage V + and V − via PMOS and NMOS current sources, thus delay time is determined by the relative strength ratio between input inverters and latch inverters. As the input inverters made stronger via control voltage, delay time decreases. Generally ring oscillators have wide tuning range that it is desirable to limit this range and pull KVCO down to reasonable levels. In order to do so, current sources are biased deep into triode by biasing gate of M1 as close as possible to VDD. Thus M1 and M2 would have opposite polarities. With proper sizing of these transistors, common mode signals at VC + and VC − can be canceled. Thus, this type of delay cell offers a good rejection of common mode noise from supply and ground.

• Phase Noise Single sideband phase noise due to the additive noise can be given as in Equation 4.2.5 [15].

 2 16F kT Rωo ( ωo )2 (forV 8Vdd )  9|δυ/δt|2 ∆ω pp 3π  max L(∆ω) = 3  64F kT RVddωo ωo 2 8Vdd  3 ( ∆ω ) (forVpp 3π ) 27π|δυ/δt|max

• Supply Sensitivity Although differential circuits are well known for their improved power supply rejection at low frequencies, and they are widely used for ring oscillator circuits, there are still very few designs where the delay cell is controlled differentially. In most PLL designs, either a single-ended charge pump and loop filter have to be used, or a differential-to- single-ended converter is inserted between the loop filter and the VCO. However, in both cases, ground and supply noise couples to control voltage. Supply sensitivity for the delay cell proposed by [15] is given as in Equation 4.45;

Aylin Donmez M.Sc. thesis 4.2 Gain Stages 67

(a) Schematic (b) Block Schematic

Figure 4.14: Schematic of the DC3 [15]

Figure 4.15: Small signal model of DC3 for PSRR calculation

M.Sc. thesis Aylin Donmez 68 VCO & Divider

∂Vo gm1 + gm10 + sCgs1 SVDD = = (4.45) ∂Vdd gm1 + gm3 + s(Cgs1 + Cgs3 + Co)

4.3 Delay Cells Performance List

Each delay cell is placed in a 4 stage ring oscillator and they are designed to operate within the band of interest. Their noise performance is simulated under clean and noisy supply conditions. The 1st column in Table 4.1 shows the phase noise performance under clean supply and ground condition. In the 2nd column, noise performance under noisy supply is given. For this case, ground is assumed to be clean. In the 3rd column, noise performance under noisy ground is given and also for this case supply is assumed to be clean. And ﬁnally in the 4th column, noise performance under noisy ground and noisy supply is given. Current consumption of the delay cells are also given in Table 4.1.

Clean Supply Ground Supply- Total Cur- Freq(GHz) @1MHz @1MHz @1MHz Ground rent @1MHz DC1 [12] -84.47dBc -63.53dBc -63.53dBc -60.53dBc 22.05mA 5.053 DC2 [24] -83.04dBc -61.27dBc -60.14dBc -57.67dBc 18.54mA 5.933 This Work -83.03dBc -60.95dBc -60.82dBc -57.89dBc 7.72mA 5.503

Table 4.1: Comparison of performance metrics of delay cells

4.4 Ring Oscillator Design

An overview of the phase noise and supply noise contribution for different delay cells has been performed in previous section. In this part, the key parameters on suitable delay cell selection are discussed and design procedure for the ring oscillator is described. Main requirements of ring oscillator of the wideband PLL system are its frequency range, phase noise performance and power supply sensitivity. On the other hand, frequency control configuration is also important since the charge pump used in this work is a differential one and it has differential control voltage output. There could be two options to combine the charge pump with VCO;

• First conﬁguration could be a system where a single ended controlled VCO is used and a diﬀerential to single ended converter is inserted in between the charge pump and the VCO.

• Another solution could be a diﬀerentially controlled VCO, where the system has good noise rejection to both ground and supply.

In this work, second option is chosen in order to avoid diﬀerential to single ended converter which also introduce poor supply noise rejection.

Aylin Donmez M.Sc. thesis 4.4 Ring Oscillator Design 69

(a) Schematic (b) Block Schematic

Figure 4.16: Schematic and block schematic of the delay cell used in this work

For the configuration given in Figure 4.16(a), frequency span over the central frequency, i.e. Kvco is too high. The required tuning range is 1GHz over 5.4GHz and an additional ∓30% is required to keep the system perform over process and temperature variations. Delay cell proposed by Dai [15] is modified for multiple pass loop as given in Figure 4.16(a). Operation principle is almost similar to the one described in [15] except from the secondary input inverters, C1 and C2, in Figure ??. These secondary inputs drive a pair of inverters, C1 and C2 whose strength is controlled differentially via the current sources M13 and M14 shown in Figure ??. The delay time is determined by the strength ratio between these controlled secondary inputs and the latch inverters A1 and A2. The stronger the C1 and C2 gets, the faster the transition at output nodes occurs. This can be roughly explained as; as the C1 and C2 gets stronger, the current supplied to output nodes increases and this sharpens the transition at output. As a result delay time between the cells decreases and the operation frequency increases. Controlling the strength of these inverters determines the delay time, thus the frequency.

The current sources M13 and M14 are biased in triode region in order to improve linearity of frequency over control voltage. Thus NMOS current is controlled via V +, the control voltage that has positive polarity, and PMOS current source is controlled via V − in order to serve for the same concept. Since the Vgs voltages of these sources are relatively large, variations on supply is now less eﬀective.

On the other hand, M13 and M14 are controlled with signals that have opposite polarities. If they can be conﬁgured with a proper sizing, common mode signals at the control voltage are canceled out and only the diﬀerential operation controls the frequency. Thus common mode noise from ground an supply is rejected up to a certain extent.

• Phase Noise

M.Sc. thesis Aylin Donmez 70 VCO & Divider

Phase noise of the delay cell is given as in Equation 4.46 [5].

αF kT RV ω3 ω L(∆ω) = dd o ( o )2 (4.46) 3 ∆ω |δυ/δt|max

where L(∆ω) is the single sideband phase noise, α is the empirical constant factor, F is the excess noise factor according to the Leeson’s model [5].

Figure 4.17: Phase Noise performance of the delay cell used in this work 5GHz

• Supply Sensitivity

Model used for PSRR calculation of DC3 is given in Figure 4.18 and supply sensitivity of a DC3 can be given as in Equation 4.47;

∂Vo gm1 + gm7 + gm13 + s(Cgs1 + Cgs7) SVDD = = (4.47) ∂Vdd gm1 + gm3 + gm5 + gm7 + s(Cgs1 + Cgs3 + Cgs5 + Cgs7 + Co)

4.4.1 VCO Tuning Range

From the discussion above, it is desirable to limit the Kvco within reasonable levels. In order to lower VCO gain and still be able to cover the such a wide required frequency tuning range, input inverters are divided into 8 switchable inverters connected in parallel. With such a conﬁguration, 9 diﬀerent bands are obtained.

Aylin Donmez M.Sc. thesis 4.4 Ring Oscillator Design 71

Figure 4.18: Small Signal Equivalent to half circuit for PSRR calculation

Typical Fast-Fast Slow-Slow Fast-Slow Slow-Fast Min Max Min Max Min Max Min Max Min Max Band 0 4.010 4.455 4.793 5.332 4.060 4.377 4.026 4.772 4.141 4.755 Band 1 4.326 5.160 5.297 6.121 4.080 4.399 4.442 5.171 4.431 5.158 Band 2 4.831 5.553 5.787 6.595 4.089 4.728 4.845 5.560 4.834 5.551 Band 3 5.223 5.934 6.258 7.054 4.419 5.049 5.234 5.940 5.229 5.932 Band 4 5.605 6.305 6.717 7.500 4.741 5.362 5.612 6.305 5.610 6.305 Band 5 5.976 6.665 7.162 7.934 5.056 5.666 5.977 6.661 5.983 6.667 Band 6 6.337 7.018 7.603 8.355 5.362 5.673 6.334 7.007 6.346 7.021 Band 7 6.690 7.360 8.015 8.766 5.661 6.247 6.678 7.340 6.699 7.365 Band 8 7.034 7.695 8.425 9.165 5.952 6.543 7.014 7.669 7.045 7.704

Table 4.2: VCO Tuning Range

M.Sc. thesis Aylin Donmez 72 VCO & Divider

Figure 4.19: Schematic of VCO delay cell used in this work

Aylin Donmez M.Sc. thesis 4.5 Layout of the VCO 73

4.5 Layout of the VCO

Layout of the complete VCO is given in Figure 4.20. The delay cell is consist of switching input transistors and the main core. Transistor type used in the design is of importance from RF perspective since the operating frequency is couple of GHz. One would prefer the implementations with RF transistors since they offer better modeling for phase noise and loading effects on VCO by means of their additional substrate network, drain source diodes and capacitances, gate resistances, gate induced noise effects, etc. However, with RF transistor, introduced parasitics are relatively greater than that of normal transistors, due to the long routing and interconnection paths. Since each transistor has its own complete surrounded ring, interconnections get longer, introducing larger parasitics. At the very beginning of the layout design, the complete delay cell was drawn with RF transistors. However, it was not possible to meet the frequency range specification due to large capacitive loadings at output nodes. Primarily, estimated parasitic node capacitance was 10fF however after layout extraction with RF transistors, equivalent parasitics capacitance was 25fF which degraded the frequency. Thus, the final design was implemented with normal model transistors of IBM 65nm ´slibrary. Power consumption of the VCO cell is 9.2 mW under typical condition operating at 5.5GHz.

• VCO Top Level Layout

IBM 65nm process oﬀers a triple well option where a separate p-well can be isolated from the substrate by a buried n-implant. This buried n-implant is guarded by an n-well ring. Thus, all the n-wells within the N well ring are shorted that they are all at same potential. Each delay cell is placed in its separate deep n-well, DNW , and global ground rings are placed in between each deep n-wells. It is important for the DNW to have a low ohmic connection to the local supply. From this point, triple contact ring and wide connection metals are used for local supply and ground connections of DNW s. There exist a maximum area for DNW in order to keep eﬀectiveness of triple well high. Deep n-wells of delay cells occupy 31.6µX22.145µ of area each. Total area of the top level layout is 151.03µX24.54µ.

For Vdd and ground connections H-tree routing is used in order to keep the resistive voltage drop same for each delay cell.

4.6 Divider Performance

High speed frequency dividers are critical parts of frequency synthesizers in wireless systems. These dividers allow the output frequency from a voltage controlled oscillator to be compared with a much lower external reference frequency that is commonly used in these synthesizers. Common trade-oﬀs in high frequency dividers are speed of division, power consumption and occupied area.

M.Sc. thesis Aylin Donmez 74 VCO & Divider

Figure 4.20: VCO delay cell

Figure 4.21: VCO top level layout

Aylin Donmez M.Sc. thesis 4.6 Divider Performance 75

In this work, the most important parameters of the divider are the operating frequency, the power consumption, and the noise contribution. Since the divider noise is subject to low pass ﬁltering as explained in Subsection 2.3.2, its in band noise contribution is of importance. The operating frequency of a digital divider is decided by the propagation delay. For the divider used in this work, clock is divider by 2 in the 1st stage, and it is followed by a divide- by-3 circuit as shown in Figure 4.22. In this architecture, the maximum operating frequency is given in Equation 4.48.

1 fmax = (4.48) 2 × max(τpLH , τpHL) where τpHL, τpHL are the propagation delays of the low-to-high and high-to-low transitions respectively.

Figure 4.22: Block Schematic of the divider used in this work

Jitter performance of the divider is given in Figure 4.23.

Figure 4.23: Jitter performance of the divider

M.Sc. thesis Aylin Donmez 76 VCO & Divider

Phase noise performance of the divider is given in Figure 4.24. At 1MHz oﬀset from the carrier, the phase noise is −151.6 dBc/Hz.

Figure 4.24: Divider phase noise performance

Aylin Donmez M.Sc. thesis Chapter 5

Top Level

The ultimate goal of this research is to complete a 4.9GHz ∼ 5.9GHz Wideband PLL frequency synthesizer integrated in IBM 65nm CMOS Digital-Process without any external components or processing steps. The division ratio is fixed to 6, so the input frequency ranges from 816MHz ∼ 983MHz and the reference signal is supplied from an off chip oscillator. The required frequency range as being 4.9GHz ∼ 5.9GHz in typical conditions and with the design margins included becomes relatively large. In a wideband ring oscillator PLLs, it is easy to achieve wide tuning range. However, with wide PLL bandwidth, PLL in band noise is more important to overall jitter performance. To lower the PLL in band noise, VCO gain, charge pump, loop filter and divider noise should be reduced. Reducing the VCO gain reveals a trade of between the wide tuning range and jitter. It gets difficult to cover the required frequency range within the temperature and process variations. Reducing the charge pump and loop filter noise requires higher charge pump current, a bigger loop filter capacitance and a smaller resistance. This trade off leads to a larger die area. Simulations are verified for various design corners: temperature is swept from −20oC to 105oC, and all possible device model corners (typical, slow, fast, fastslow) are checked.

5.1 Loop Parameters

The frequency synthesizer block diagram is shown in Figure 5.1. The synthesizer is a 3rd- order type II charge pump PLL and the design consists of a phase-frequency detector, a charge-pump loop-filter, a differential VCO, an output amplifier and a frequency divider. In order to have a stable PLL synthesizer, loop bandwidth should be carefully considered. The loop-filter shown in Figure 5.2, is a differential one.

When the loop ﬁlter is only consist of C1, C1 introduces a pole to the system and together with VCO, the loop has two ideal integrators, which makes it a second-order type-two loop. However, the loop starts with a phase-shift of −180o and there is no zero in the loop. Any high frequency pole introduced by the loop components makes the loop instable. Therefore, a stabilizing zero is necessary. A resistor R1 is added in series with the C1 to introduce a zero

M.Sc. thesis Aylin Donmez 78 Top Level

Figure 5.1: Loop Components

to the loop. The zero should be placed well before the loop bandwidth to achieve sufficient phase-margin. However, the resistor introduces high frequency ripples on the control line, which are difficult to suppress. As a result, another pole is necessary to suppress these high frequency components. C2 introduces a third pole to the system, making the PLL a third- order type-two loop. This pole should be placed far from the crossover frequency not to worsen the phase-margin. As a rule of thumb [21], C2 is chosen to be 1/10th of C1. In order to perform differential mode operation, C2 is split into two separate caps and one of them is placed differentially between output nodes.

Figure 5.2: Diﬀerential loop ﬁlter used in this work

Input frequency is in the range of 816MHz ∼ 983MHz. Thus, first proposal for loop bandwidth can be 80MHz in order to keep the ratio between input frequency and loop bandwidth bigger than 10 for all input frequencies. Continuous time approximation (s domain analysis) is only valid when the loop bandwidth is narrow compared to the input frequency. As the loop bandwidth gets comparable with the input frequency, sampling effects in the loop must be analyzed. As the ratio between the loop bandwidth and the input frequency is chosen to be bigger than 10, s domain analysis given in Appendix A is still valid. Thus the relation between the loop bandwidth and cross over frequency can be given as; ω ω = 2ξω ≤ 2ξ i (5.1) c n 10 The loop filter transfer function is given as; sτ + 1 F (s) = 2 (5.2) sτ1(sτ3 + 1) where τ1 = (C1 + C2), τ2 = (C1R1), τ3 = (C1C2R/C1 + C2).

Aylin Donmez M.Sc. thesis 5.1 Loop Parameters 79

The third pole introduced by C2 is placed far from the crossover frequency, so the loop can be considered as a 2nd order system, and loop parameters such as damping factor and the natural frequency can be given as in 2nd order loops;

r KPFDKVCO ωn = (5.3) NC1

r 1 K K R2C ξ = PFD VCO 1 1 (5.4) 2 N

The zero frequency introduced by the resistance, R1 is given as;

ωn 1 ωz = = (5.5) 2ξ R1C1

The location of 3rd pole is; C1 + C2 ω3rd = (5.6) C1C2R1

The loop ﬁlter parameter should be chosen in order to satisfy Equation 5.1 within all input frequency variations, process and temperature variations for KVCO and KPFD. The worst case condition, the largest loop bandwidth, is achieved when both NMOS and PMOS devices operate at fast conditions, and the temperature is −20o and the resistor value is maximum with process variations. In this case, the loop bandwidth is set to 70.528 MHz, In typical operating conditions loop bandwidth is 54.935MHz. In Figure 5.3, loop model for frequency domain analyses in Simetrix is given.

Table 5.1: PLL Performance Summary

Technology IBM 65nm Supply Voltage 1.2V Reference Frequency Range (MHz) 816 ∼ 984 Output Frequnecy Range (GHz) 4.01 ∼ 6.543 PLL Current Consumption VCO 7.72 mA Divider 2.78 mA PFD+CP+Additional Circuitry 1.92 mA PLL Total 12.42 mA PLL Total Power Consumption 14.904mW Phase Noise -108dBc @1MHz/-119dBc @5MHz In Band Noise Floor -121.7dBc/Hz Settling Time ≺ 245ns

Bonding diagram is given in Figure 5.9. Used package is of a Quad Flats No Leads, QFN, type where the leads do not extend out from the sides of the package. It is placed on board with Surface Mount Technology, SMT. The package has 24 leads and its body area is 4mm×4mm.

M.Sc. thesis Aylin Donmez 80 Top Level

Figure 5.3: Simetrix Model of the Loop

Figure 5.4: Loop AC response in Simetrix

Aylin Donmez M.Sc. thesis 5.1 Loop Parameters 81

Figure 5.5: Noise Behaviour of the loop in Simetrix

Figure 5.6: Settling Behavior in Fast Corner

M.Sc. thesis Aylin Donmez 82 Top Level

Figure 5.7: Top level Layout - Core Only

Aylin Donmez M.Sc. thesis 5.1 Loop Parameters 83

Figure 5.8: Top level layout including the pads

M.Sc. thesis Aylin Donmez 84 Top Level

Figure 5.9: bonding diagram

Aylin Donmez M.Sc. thesis 5.2 Wideband PLL Characteristics Validation 85

5.2 Wideband PLL Characteristics Validation

5.2.1 Loop Bandwidth

Loop bandwidth measurement, can be performed using a signal source capable of generating a frequency modulated signal. This can be directly achieved by feeding a sine a wave, with a frequency fm, into a VCO. SφV CO in Figure 5.10 is, then, an FM modulated signal. Obser- vation of the distortion at the output spectrum includes information of loop bandwidth. As a result, response of PLL system to this FM modulated signal oﬀers an estimation of loop bandwidth.

Figure 5.10: Loop bandwidth measurement setup

5.2.2 Phase Noise Measurement and Other Design Metrics

Diﬀerent methods are used to measure phase noise [9]. One involves measuring phase noise L (fm) directly on a spectrum analyzer. This measurement can be done as long as the analyzer has better phase noise performance than the measured source. Other design metrics, such as; Reference Spurs, Frequency stability, can be measured easily observed with a spectrum analyzer.

• Operating frequency Tuning range Due to the time shortage, a voltage buﬀer for the VCO control voltage could not be implemented. Thus, it is not possible to perform measurements on control voltage. This is an obstacle that prevents to have an information on tuning curves thus VCO gain.

Test board of the chip was not yet complete at the time of writing this thesis. Therefore it has not been shown here.

M.Sc. thesis Aylin Donmez 86 Top Level

Aylin Donmez M.Sc. thesis Chapter 6

Conclusion and Recommendations

6.1 Conclusions

The goal of this thesis is to review the theory, design and analysis of PLL system components and complete a design of 4.9 ∼ 5.9 GHz CMOS Wideband PLL frequency synthesizer integrated in IBM 65nm CMOS Digital-Process. Therefore, to start the investigation noise phenomenon in PLL loops have been analyzed. Phase noise and jitter performance under noisy power supply conditions have been analyzed. Noise contributions of each blocks in a PLL system have been studied. Input reference frequency is in the order of 800MHz that requires a phase frequency detector which is capable of high frequency operation. A combination of phase frequency detector and charge pump that operates at high frequencies is implemented. A number of oscillator types that are configured in multipath loops have been compared on various performance metrics. A delay cell offering lower phase noise and being suitable for differential operation is used in ring VCO design. Since the VCO of the PLL is implemented with a multipath loop ring oscillator; its open loop output noise is undesirably high. Loop bandwidth, ωN , is set to be 40MHz for the validity of the continuous time (s-domain) approximation for all process and temperature corners. Wideband PLL system has been implemented with a fixed divide-by-6 divider. Entire PLL design consumes 14.9 mW under typical conditions. Total area of the PLL core is 1 mm x 800 um including the pads. Test-chip is being processed.

6.2 Future Work

The future work includes testing the PLL test-chip, and verifying the simulation results, improving phase noise performance of the PLL design. An LC VCO may be implemented to improve the phase noise performance, however, ﬁrst step is: to verify noise models, and the measurement techniques.

M.Sc. thesis Aylin Donmez 88 Conclusion and Recommendations

Aylin Donmez M.Sc. thesis Appendix A

PLL Basics

A.1 PLL Dynamics

A phase-locked loop is a feedback system that operates on the excess phase of nominally periodic signals. This is in contrast to familiar feedback circuits where voltage and current amplitudes and their rate of change are of interest. Shown in Figure A.1, a phase-locked loop contains three basic components;

1. A phase-detector (PD)

2. A loop-ﬁlter (LPF)

3. A voltage-controlled oscillator (VCO).

Figure A.1: Basic phase-locked loop block diagram

The phase-detector compares the phase of the input signal, x(t), against the phase of the VCO output signal, y(t). Output of the phase-detector is a voltage proportional to the phase difference between its two inputs. After a certain settling time, the phase remains constant with time, then the loop is considered to be constant. The difference voltage at the phase- detector output is filtered by the loop-filter. Loop-filter is a low pass filter, which suppresses the high frequency signal components and noise. Output of the loop-filter is applied to the VCO as the control voltage. This control voltage changes the frequency of the VCO in a direction that reduces the phase difference between the input signal and the local oscillator.

M.Sc. thesis Aylin Donmez 90 PLL Basics

A.1.1 Loop Order and Loop Type

In literature, there exist several applications of PLLs where different orders and types of PLLs are used. When the system’s loop filter is only consist of a single capacitance, C1, C1 introduces a pole to the system and together with VCO, the loop has two ideal integrators, which makes it a second-order type-two loop. However, when the loop filter has a stabilization zero and an additional capacitance in parallel as shown in Figure A.2 then the loop is a 3rd order loop.

Figure A.2: Loop ﬁlter with stabilization zero

The loop-ﬁlter has a pole at ω = 0 and a zero at ωz = −1/τz. A zero is necessary for stability purposes. Using this ﬁlter, open-loop transfer function becomes;

KpfdKvco(sτ2 + 1) G(s) = 2 (A.1) s τ1 and the loop gain is;

K K τ K = pfd vco 2 (A.2) τ1

Closed-loop transfer function is calculated easily as;

τ2 1 φ (s) sKpfdKvco + KpfdKvco out = τ1 τ1 2 τ2 1 φin(s) s + sK K + K K pfd vco τ1 pfd vco τ1 sK + K = τ2 s2 + sK + K τ2

(A.4)

However, the third pole introduced by C2 is placed far from the crossover frequency, so the loop can be considered as a 2nd order system, and loop parameters such as damping factor and the natural frequency can be given as in 2nd order loops. The loop ﬁlter transfer function is given as;

Aylin Donmez M.Sc. thesis A.1 PLL Dynamics 91

sτ + 1 F (s) = 2 (A.5) sτ1(sτ3 + 1) where τ1 = (C1 + C2), τ2 = (C1R1), τ3 = (C1C2R/C1 + C2). Natural frequency of the system is given as;

s KpfdKvco ωn = (A.6) NC1

Damping ratio of the system is then given by;

r 1 K K R2C ξ = pfd vco 1 1 (A.7) 2 N

The zero frequency introduced by the resistance, R1 is given as;

ωn 1 ωz = = (A.8) 2ξ R1C1

The location of 3rd pole is; C1 + C2 ω3rd = (A.9) C1C2R1

A.1.2 Loop response to a step change in phase

This situation occurs due to a phase change in the reference source or due to a sudden change in the VCO output phase. The magnitude of this change in phase, ∆φ, occurring at t = 0 can be given in Laplace domain as;

∆φ φi(s) = s

The loop response to such an input can be given as ;

2 2ξωns + ωn φo(s) = N∆φ 2 2 (A.10) s(s + 2ξωns + ωn) Corresponding transient response has diﬀerent settling behavior depending on the ξ of the system. For the case when ξ equals to 1, response in Equation A.10 can be derived in time domain as;

2 2ωns + ωn φo(s) = N∆φ 2 s(s + ωn) 1 1 ωn = N∆φ − + 2 s s + ωn (s + ωn)

M.Sc. thesis Aylin Donmez 92 PLL Basics

(A.12)

After the substitution into partial factions, Laplace transform is applied to Equation A.11.

−ωnt φo(t) = N∆φ 1 − (1 − ωnt)e (A.13)

Thus the phase error φe(t) can be given as;

φ (t) φ (t) = ∆φ − o = ∆φ(1 − ω t)e−ωnt (A.14) e N n

A.1.3 Loop response to a step change in frequency

In this work, this case occurs when the input reference signal is changed into a diﬀerent band. Thus the transient changes at loop output and also the maximum allowable frequency step should be determined. A frequency input step can be considered in Laplace form as;

φi(t) = ∆ωt

∆ω φi(s) = s2

Response of a second order system to such a step input is given as;

1 1 ωn φo(s) = N∆ω 2 − + 2 s s(s + ωn) s(s + ωn) 1 1 = N∆ω 2 − 2 s (s + ωn)

(A.16)

and with inverse Laplace transform, loop response for a frequency change can be given in time domain;

φ (t) h i o = ∆ωt 1 − e(−ωnt) (A.17) N Transient phase error at the phase detector input, then can be given as;

φo(t) −ωnt ∆ω −ωnt φerr(t) = ∆ωt − = ∆ωte = ωnte (A.18) N ωn

Peak phase error is then given by the derivative of the curve in Equation A.18 as;

Aylin Donmez M.Sc. thesis A.1 PLL Dynamics 93

δφe(t) ∆ω −ωnt −ωnt = e − ωnte = 0 (A.19) δ(ωnt) ωn

Equation in A.19 equals to 0 when ωnt = 1, and the peak phase error is given by;

∆ω φe(peak) = (A.20) eωn This reveals an important result on maximum operation frequency;

∆fo(max) = 2πeNfn (A.21)

The phase error expression given in A.19, is diﬀerentiated to obtain a time domain expression for frequency error;

δφ ω = err = ∆ω(1 − ω t)e−ωnt (A.22) e δt n In many practical cases the frequency step is much smaller than the one given by Equation A.22.

M.Sc. thesis Aylin Donmez 94 PLL Basics

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Aylin Donmez M.Sc. thesis