Analysis, Design, and Implementation of Integrated Charge Pumps with High Performance Younis Allasasmeh
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ANALYSIS, DESIGN, AND IMPLEMENTATION OF INTEGRATED CHARGE PUMPS WITH HIGH PERFORMANCE A Thesis Presented to The Faculty of Graduate Studies of The University of Guelph by YOUNIS ALLASASMEH In partial fulfilment of requirements for the degree of Master of Applied Science Guelph, Ontario, Canada c Younis Allasasmeh, August, 2011 ABSTRACT ANALYSIS, DESIGN, AND IMPLEMENTATION OF INTEGRATED CHARGE PUMPS WITH HIGH PERFORMANCE Younis Allasasmeh Advisor: University of Guelph, 2011 Professor Stefano Gregori This thesis presents the design of new integrated charge pumps with high performance. An analysis method is determined to evaluate the voltage gain, the output resistance and the conversion efficiency parameters of integrated charge pumps. An optimization method is developed to improve the performance through capacitor sizing based on area constraints. Several charge pumps structures are optimized and compared including the losses due to devices parasitics. Results show that the Dickson charge pump (voltage doubler) is the best structure for integration. Therefore, techniques to improve performance and conversion efficiency of integrated voltage doubler are proposed. Switch bootstrapping technique prevents short-circuit losses, improves driving capability, and enhances the overall efficiency. The application of charge reuse technique reduces the dynamic power losses of integrated voltage doublers and double charge pumps. A prototype of the integrated voltage dou- blers was fabricated in a 0.18-µm CMOS process with the proposed techniques. Measured results have been presented, demonstrating the improvements in performance and conversion efficiency, with a good correlation between measured and predicted results. Acknowledgements I would like to take this opportunity to express my sincere appreciation to my advisor Dr. Stefano Gregori for his support and encouragement throughout my research. Without his faith in my abilities and his consistent help, this work would not have been possible. I would also like to thank Dr. Hussein Abdullah, who never let an opportunity pass without lending me his sincere feedback, help, and advice. I deeply appreciate the support from Kapik integration, and I would like to thank Kapik team for the experience they have brought me throughout my internships. Also, I would like to thank CMC for providing the semiconductor fabrication service that made the im- plementation of my design possible. Thanks to all my friends in the analog Nano-electronics group for their technical help and feedback in the past three years. I am greatful to my relatives and friends in Jordan, Morocco, and Guelph. Thanks for the great help and kindness. Most of all, thanks are owed to my family for their countless care and sacrifice. To my father, Dr. Abdelaziz Allasasmeh. To my mother, Dr. Wafa Alami. To my sisters, Alia, Sarah, and Saja. To my love, Sara Altamimi. To them, I owe all. It was their motivation and unconditional support that guides me throughout this long journey. i Contents 1 Introduction 1 1.1 Motivation................................... 1 1.2 LiteratureReview............................... 2 1.3 Contributions ................................. 8 1.4 ThesisOrganization. .. .. .. .. .. .. .. .. 8 2 Charge Pump Analysis 10 2.1 MethodofAnalysis.............................. 10 2.2 ChargePumpGain .............................. 14 2.2.1 IdealGain............................... 14 2.2.2 GainwithParasiticCapacitances. .. 15 2.3 ChargePumpOutputResistance . 15 2.3.1 Analysis of Output Resistance with Parasitic Capacitances . 16 2.4 PowerLossesinChargePumps. 17 2.4.1 Load-DependentLosses . 17 2.4.2 Load-IndependentLosses . 18 2.5 AnalysisofSingle-SidedChargePumps . .... 19 2.5.1 OptimizationoftheOutputResistance . ... 20 2.5.2 Single-Sided Charge Pumps with Parasitic Capacitances ...... 22 2.6 AnalysisofDoubleChargePumps . 25 ii CONTENTS iii 2.6.1 Double Charge Pumps Performance with Parasitic Capacitances . 26 2.7 ChargeReuse ................................. 27 2.8 SimulationResultswithChargeReuse . .... 30 2.9 Summary ................................... 32 3 Design 34 3.1 Introduction.................................. 34 3.2 VoltageDoubler................................ 35 3.3 LossesandEfficiency............................. 37 3.3.1 Load-DependentPowerLosses. 37 3.3.2 Load-IndependentPowerLosses . 38 3.3.3 Short-CircuitPowerLosses . 39 3.4 ProposedSwitchBootstrappingTechnique . ...... 41 3.5 ChargeReuseTechnique .. .. .. .. .. .. .. .. 42 3.5.1 ChargeReuseVoltageDoublerDesign. 43 3.6 DesignConstrains............................... 43 3.6.1 MOSSwitches ............................ 44 3.6.2 BootstrappingCircuit. 45 3.6.3 DesignTrade-Offs . .. .. .. .. .. .. .. 46 3.7 TechnologyConstrains . 47 3.7.1 IntegratedCapacitors. 48 3.7.2 BulkBiasing ............................. 50 3.8 DesignofCP’sAuxiliaryCircuits . ... 51 3.8.1 ClockGenerationCircuit. 51 3.8.2 InverterDriverCircuit . 52 3.9 Summary ................................... 53 CONTENTS iv 4 Results 54 4.1 Introduction.................................. 54 4.2 SimulationResults .............................. 54 4.2.1 Steady-State ............................. 57 4.2.2 TransientAnalysisResults . 64 4.3 PrototypeImplementation . 67 4.3.1 FabricationTechnology. 67 4.3.2 ToolsandDesignFlow . 68 4.3.3 TestSetupRealization . 69 4.3.4 LayoutConsiderations . 71 4.4 ExperimentalResults . .. .. .. .. .. .. .. .. 73 4.5 Discussion of the Results and Design Considerations . ......... 81 5 Conclusion and Future Work 85 5.1 Conclusion .................................. 85 5.2 FutureWork.................................. 86 A Testing 89 A.1 ViewoftheFullChipandtheDesignedCircuits . ...... 89 A.2 CircuitsandPadsArrangementfortheDesign . ...... 92 A.3 BondingDiagramfortheDesign . 93 A.4 TestBoard................................... 94 A.4.1 PackageLayout............................ 95 A.4.2 AddingOff-ChipPassiveComponents . 95 A.4.3 ClampingthePackagetotheFixture . 96 A.5 SchematicViewofCircuits. 97 B Published Papers 104 B.1 RefereedPublications. 104 CONTENTS v Bibliography 105 List of Tables 2.1 HeapCPDesignParameters. 24 2.2 FibonacciCPDesignParameters.. ... 25 2.3 ExponentialCPDesignParameters. ... 28 4.1 Devices availablein the fabrication technology. .......... 67 5.1 ModularCPDesign. ............................. 86 A.1 Signaltypesanddescription. ... 90 vi List of Figures 1.1 FourstageconventionalDicksonCP[1]. ..... 3 1.2 FourstagebootstrappedDicksonCP[2]. ..... 4 1.3 Simplified schematic of the boosted voltage generator for DRAM word- linedriver[3].................................. 5 1.4 Doublechargepump[4]. ........................... 5 1.5 OnestagevoltagedoublerCP[5]. .. 7 2.1 Blockdiagramofagenericchargepump. ... 11 2.2 Generic2-phaseCPbuildingblock. ... 11 2.3 ProcedureforevaluatingCPgain. ... 14 2.4 Integratedcapacitormodel. ... 15 2.5 ProcedureforevaluatingCPoutputresistance. ......... 16 2.6 Schematic diagrams of conventional charge pumps with parasitic capaci- tances...................................... 21 2.7 Sketch of capacitors with optimal size of Dickson, heap, and Fibonacci CPs of equal area and gain (i.e. left A = 5, centre A = 8, right A =13). ..... 22 2.8 Normalized input conductance g of Dickson, heap, and Fibonacci CPs as a function of A, when α =0.1 and β =0.05. ................. 23 2.9 Normalized output resistance r of Dickson, heap, and Fibonacci CPs as a function of A, when α =0.1 and β =0.05. ................. 24 vii LIST OF FIGURES viii 2.10 Schematicdiagramsofdoublechargepumps. ...... 27 2.11 Sketch of capacitors with optimal size of double Dickson and double expo- nential CPs of area and gain (i.e. left A= 4, right A =8). .......... 28 2.12 Charge reuse configurationof a generic doubleCP. ........ 29 2.13 Description of charge reuse concept in double charge pumps......... 30 2.14 Schematic diagrams of double charge pumps with charge reuse (parasitic capacitancesareomittedforsimplicity). ..... 31 2.15 Normalized input conductance g versus voltage gain A for the three CP types in standard configuration and with charge reuse, when α = 0.1, and β =0.05. ................................... 32 2.16 Conversion efficiency and output characteristics of the three CP types as a function of the output current IO, when n = 4 for Dickson and heap CPs and N =3 for the Fibonacci CP, VDD =1.8 V, CT = 200 pF, f = 10 MHz, α =0.1, and β =0.05............................. 33 3.1 Conventional 2-phases cross-coupled voltage doubler stage... .. .. 36 3.2 2-phasescross-coupledvoltagedoublerstage. ......... 39 3.3 Proposed bootstrapping technique applied to a voltage doublerstage. 41 3.4 Bootstrapped voltage doubler stage with charge reuse. ........... 44 3.5 Maximum efficiency versus transistor width for a voltage doubler when N =1, VDD = 1.8 V, f = 10 MHz, CT = 250 pF, α = 0.015, and β =0.01. 46 3.6 Bootstrapping capacitor size versus the maximum efficiency. ........ 47 3.7 CVcurveofnMOScapacitor(Spectresimulation). ....... 49 3.8 EquivalentseriesresistanceofMOScapacitor. ......... 49 3.9 2-phases cross-coupled voltage doubler stage with dynamic bulk biasing forpMOSswitches[6]. .. .. .. .. .. .. .. .. 51 3.10 Nonoverlapping clock generation scheme (detailed schematic is shown in AppendixA). ................................. 52 LIST OF FIGURES ix 3.11 A CMOS inverter driver with tapering factor 4 (detailed schematic is shown inappendixA). ................................ 52 4.1 Schematic diagrams of the conventional voltage doublers........... 55 4.2 Schematic diagrams of the proposed