Analysis, Design, and Implementation of Integrated Charge Pumps with High Performance Younis Allasasmeh

ANALYSIS, DESIGN, AND IMPLEMENTATION OF INTEGRATED

CHARGE PUMPS WITH HIGH PERFORMANCE

A Thesis

Presented to The Faculty of Graduate Studies of The University of Guelph

YOUNIS ALLASASMEH

In partial fulﬁlment of requirements for the degree of Master of Applied Science

Guelph, Ontario, Canada c Younis Allasasmeh, August, 2011 ABSTRACT

ANALYSIS, DESIGN, AND IMPLEMENTATION OF INTEGRATED

CHARGE PUMPS WITH HIGH PERFORMANCE

Younis Allasasmeh Advisor:

University of Guelph, 2011 Professor Stefano Gregori

This thesis presents the design of new integrated charge pumps with high performance. An analysis method is determined to evaluate the voltage gain, the output resistance and the conversion efﬁciency parameters of integrated charge pumps. An optimization method is developed to improve the performance through capacitor sizing based on area constraints. Several charge pumps structures are optimized and compared including the losses due to devices parasitics. Results show that the

Dickson charge pump (voltage doubler) is the best structure for integration. Therefore, techniques to improve performance and conversion efficiency of integrated voltage doubler are proposed. Switch bootstrapping technique prevents short-circuit losses, improves driving capability, and enhances the overall efficiency. The application of charge reuse technique reduces the dynamic power losses of integrated voltage doublers and double charge pumps. A prototype of the integrated voltage doublers was fabricated in a 0.18-µm CMOS process with the proposed techniques. Measured results have been presented, demonstrating the improvements in performance and conversion efficiency, with a good correlation between measured and predicted results. Acknowledgements

I would like to take this opportunity to express my sincere appreciation to my advisor Dr. Stefano Gregori for his support and encouragement throughout my research. Without his faith in my abilities and his consistent help, this work would not have been possible. I would also like to thank Dr. Hussein Abdullah, who never let an opportunity pass without lending me his sincere feedback, help, and advice.

I deeply appreciate the support from Kapik integration, and I would like to thank Kapik team for the experience they have brought me throughout my internships. Also, I would like to thank CMC for providing the semiconductor fabrication service that made the implementation of my design possible.

Thanks to all my friends in the analog Nano-electronics group for their technical help and feedback in the past three years. I am greatful to my relatives and friends in Jordan, Morocco, and Guelph. Thanks for the great help and kindness. Most of all, thanks are owed to my family for their countless care and sacriﬁce. To my father, Dr. Abdelaziz Allasasmeh. To my mother, Dr. Wafa Alami. To my sisters, Alia, Sarah, and Saja. To my love, Sara Altamimi. To them, I owe all. It was their motivation and unconditional support that guides me throughout this long journey.

i Contents

1 Introduction 1 1.1 Motivation...... 1

1.2 LiteratureReview...... 2 1.3 Contributions ...... 8 1.4 ThesisOrganization...... 8

2 Charge Pump Analysis 10 2.1 MethodofAnalysis...... 10 2.2 ChargePumpGain ...... 14

2.2.1 IdealGain...... 14 2.2.2 GainwithParasiticCapacitances...... 15 2.3 ChargePumpOutputResistance ...... 15 2.3.1 Analysis of Output Resistance with Parasitic Capacitances . . . . . 16 2.4 PowerLossesinChargePumps...... 17

2.4.1 Load-DependentLosses ...... 17 2.4.2 Load-IndependentLosses ...... 18 2.5 AnalysisofSingle-SidedChargePumps ...... 19 2.5.1 OptimizationoftheOutputResistance ...... 20

2.5.2 Single-Sided Charge Pumps with Parasitic Capacitances ...... 22 2.6 AnalysisofDoubleChargePumps ...... 25

ii CONTENTS iii

2.6.1 Double Charge Pumps Performance with Parasitic Capacitances . . 26 2.7 ChargeReuse ...... 27 2.8 SimulationResultswithChargeReuse ...... 30 2.9 Summary ...... 32

3 Design 34

3.1 Introduction...... 34 3.2 VoltageDoubler...... 35 3.3 LossesandEfﬁciency...... 37 3.3.1 Load-DependentPowerLosses...... 37 3.3.2 Load-IndependentPowerLosses ...... 38

3.3.3 Short-CircuitPowerLosses ...... 39 3.4 ProposedSwitchBootstrappingTechnique ...... 41 3.5 ChargeReuseTechnique ...... 42 3.5.1 ChargeReuseVoltageDoublerDesign...... 43

3.6 DesignConstrains...... 43 3.6.1 MOSSwitches ...... 44 3.6.2 BootstrappingCircuit...... 45 3.6.3 DesignTrade-Offs ...... 46

3.7 TechnologyConstrains ...... 47 3.7.1 IntegratedCapacitors...... 48 3.7.2 BulkBiasing ...... 50 3.8 DesignofCP’sAuxiliaryCircuits ...... 51

3.8.1 ClockGenerationCircuit...... 51 3.8.2 InverterDriverCircuit ...... 52 3.9 Summary ...... 53 CONTENTS iv

4 Results 54 4.1 Introduction...... 54 4.2 SimulationResults ...... 54 4.2.1 Steady-State ...... 57

4.2.2 TransientAnalysisResults ...... 64 4.3 PrototypeImplementation ...... 67 4.3.1 FabricationTechnology...... 67 4.3.2 ToolsandDesignFlow ...... 68

4.3.3 TestSetupRealization ...... 69 4.3.4 LayoutConsiderations ...... 71 4.4 ExperimentalResults ...... 73 4.5 Discussion of the Results and Design Considerations ...... 81

5 Conclusion and Future Work 85 5.1 Conclusion ...... 85

5.2 FutureWork...... 86

A Testing 89 A.1 ViewoftheFullChipandtheDesignedCircuits ...... 89 A.2 CircuitsandPadsArrangementfortheDesign ...... 92 A.3 BondingDiagramfortheDesign ...... 93 A.4 TestBoard...... 94

A.4.1 PackageLayout...... 95 A.4.2 AddingOff-ChipPassiveComponents ...... 95 A.4.3 ClampingthePackagetotheFixture ...... 96 A.5 SchematicViewofCircuits...... 97

B Published Papers 104 B.1 RefereedPublications...... 104 CONTENTS v

Bibliography 105 List of Tables

2.1 HeapCPDesignParameters...... 24

2.2 FibonacciCPDesignParameters...... 25 2.3 ExponentialCPDesignParameters...... 28

4.1 Devices availablein the fabrication technology...... 67

5.1 ModularCPDesign...... 86

A.1 Signaltypesanddescription...... 90

vi List of Figures

1.1 FourstageconventionalDicksonCP[1]...... 3

1.2 FourstagebootstrappedDicksonCP[2]...... 4 1.3 Simpliﬁed schematic of the boosted voltage generator for DRAM word- linedriver[3]...... 5 1.4 Doublechargepump[4]...... 5

1.5 OnestagevoltagedoublerCP[5]...... 7

2.1 Blockdiagramofagenericchargepump...... 11 2.2 Generic2-phaseCPbuildingblock...... 11 2.3 ProcedureforevaluatingCPgain...... 14

2.4 Integratedcapacitormodel...... 15 2.5 ProcedureforevaluatingCPoutputresistance...... 16 2.6 Schematic diagrams of conventional charge pumps with parasitic capacitances...... 21 2.7 Sketch of capacitors with optimal size of Dickson, heap, and Fibonacci CPs

of equal area and gain (i.e. left A = 5, centre A = 8, right A =13)...... 22 2.8 Normalized input conductance g of Dickson, heap, and Fibonacci CPs as a function of A, when α =0.1 and β =0.05...... 23 2.9 Normalized output resistance r of Dickson, heap, and Fibonacci CPs as a

function of A, when α =0.1 and β =0.05...... 24

vii LIST OF FIGURES viii

2.10 Schematicdiagramsofdoublechargepumps...... 27 2.11 Sketch of capacitors with optimal size of double Dickson and double expo-

nential CPs of area and gain (i.e. left A= 4, right A =8)...... 28 2.12 Charge reuse conﬁgurationof a generic doubleCP...... 29

2.13 Description of charge reuse concept in double charge pumps...... 30 2.14 Schematic diagrams of double charge pumps with charge reuse (parasitic capacitancesareomittedforsimplicity)...... 31

2.15 Normalized input conductance g versus voltage gain A for the three CP

types in standard conﬁguration and with charge reuse, when α = 0.1, and β =0.05...... 32 2.16 Conversion efﬁciency and output characteristics of the three CP types as a

function of the output current IO, when n = 4 for Dickson and heap CPs

and N =3 for the Fibonacci CP, VDD =1.8 V, CT = 200 pF, f = 10 MHz, α =0.1, and β =0.05...... 33

3.1 Conventional 2-phases cross-coupled voltage doubler stage...... 36 3.2 2-phasescross-coupledvoltagedoublerstage...... 39

3.3 Proposed bootstrapping technique applied to a voltage doublerstage. . . . . 41 3.4 Bootstrapped voltage doubler stage with charge reuse...... 44 3.5 Maximum efﬁciency versus transistor width for a voltage doubler when

N =1, VDD = 1.8 V, f = 10 MHz, CT = 250 pF, α = 0.015, and β =0.01. . 46 3.6 Bootstrapping capacitor size versus the maximum efﬁciency...... 47

3.7 CVcurveofnMOScapacitor(Spectresimulation)...... 49 3.8 EquivalentseriesresistanceofMOScapacitor...... 49 3.9 2-phases cross-coupled voltage doubler stage with dynamic bulk biasing forpMOSswitches[6]...... 51

3.10 Nonoverlapping clock generation scheme (detailed schematic is shown in AppendixA)...... 52 LIST OF FIGURES ix

3.11 A CMOS inverter driver with tapering factor 4 (detailed schematic is shown inappendixA)...... 52

4.1 Schematic diagrams of the conventional voltage doublers...... 55 4.2 Schematic diagrams of the proposed voltage doublers...... 56

4.3 Chargepumpblockdiagram...... 57 4.4 Output characteristics, conversion efﬁciencies, and input power improvement of a one stage latched and bootstrapped voltage doublers as a function

of the output current IO, when N = 1, VDD = 1.8 V, f = 1 MHz, CT = 262.5 pF, α =0.015, and β =0.01 (Spectresimulations)...... 58 4.5 Output characteristics and conversion efﬁciencies of a one stage latched and bootstrapped voltage doublers, and savings in input power dueto switch

bootstrapping as a function of the output current IO when N = 1, VDD =

1.8 V, f = 10 MHz, CT = 262.5 pF, α = 0.015, and β = 0.01 (Spectre simulations)...... 59 4.6 Output characteristics and conversion efﬁciencies of a two stage latched and bootstrapped voltage doublers, and savings in input power dueto switch

bootstrapping as a function of the output current IO when N =1, VDD = 1.8

V, f = 1 MHz, CT = 525 pF, α =0.015, and β =0.01 (Spectre simulations). 61 4.7 Output characteristics and conversion efﬁciencies of a two stage latched and bootstrapped voltage doublers, and savings in input power dueto switch

bootstrapping as a function of the output current IO when N =1, VDD = 1.8

V, f = 10 MHz, CT = 525 pF, α =0.015, and β =0.01 (Spectre simulations). 62 4.8 Output characteristics and conversion efﬁciencies of a two stage bootstrapped voltage doubler and bootstrapped voltage doubler with charge reuse as a

function of the output current IO, when N = 2, VDD = 1.8 V, CT = 525 pF, f = 1 MHz, α =0.015, and β =0.01 (Spectresimulation)...... 63 LIST OF FIGURES x

4.9 Output characteristics and conversion efﬁciencies of a two bootstrapped voltage doubler and bootstrapped voltage doubler with charge reuse as a

function of the output current IO, when N = 2, VDD = 1.8 V, CT = 525 pF, f = 10 MHz, α =0.015, and β =0.01 (Spectresimulation)...... 64

4.10 Start-up transient with 1 nF capacitive load (two-stage charge pump, VDD = 1.8 V, and f =10MHz)(Spectresimulation)...... 65

4.11 Energy consumption versus output current (IO) of a latched and bootstrapped

voltage doublers with 1nF capacitive load (two-stage charge pump, VDD = 1.8 V, f =1MHz)(Spectresimulation)...... 65 4.12 Simulated waveforms of the current drawn from the power supply of the proposed charge reuse bootstrapped charge pump and the bootstrapped

charge pump (two-stage charge pump, VDD = 1.8 V, f = 10 MHz) (Spectre simulation)...... 66 4.13 Diagram of the analog design ﬂow used in the design (adapted from CMC). 68 4.14 Photograph of the 24-pin CFP package containing the fabricatedchip. . . . 69 4.15 Layoutofthedesignedtestboard...... 70 4.16 Blockdiagramoftheexperimentalsetup...... 71

4.17 Chipdesignlayout...... 72 4.18 Microphotograph of the design; the chip size is 1 mm × 1.5mm...... 73 4.19 A microphotograph showing circuits designed in a one stage bootstrapped voltagedoubler...... 74

4.20 Measured and simulated output characteristic and conversion efﬁciency of a fully integrated two stage bootstrapped voltage doubler as a function of

the output current IO, when VDD = 1.8 V, f =1MHz...... 75 4.21 Measured and simulated output characteristic and conversion efﬁciency of

a fully integrated two stage bootstrapped voltage doubler with charge reuse

as a function of the output current IO, when VDD = 1.8 V, f =1MHz. . . . 76 LIST OF FIGURES xi

4.22 Measured and simulated improvement in input power consumption of the two-stages bootstrapped voltage doubler with charge reuse with respect to the two-stages bootstrapped voltage doubler as a function of the output

current IO, when VDD = 1.8 V, f =1MHz...... 77 4.23 Measured and simulated output characteristics and conversion efﬁciency of a fully integrated two stage cross-coupled (latched) voltage doubler as a

function of the output current IO, when VDD = 1.8 V, f =1MHz...... 78 4.24 Measured and simulated output characteristic and conversion efﬁciency of

a fully integrated one stage bootstrapped voltage doubler as a function of

the output current IO, when VDD = 1.8 V, f =1MHz...... 79 4.25 Measured and simulated output characteristics and conversion efﬁciency of a fully integrated one stage cross-coupled (latched) voltage doubler as a

function of the output current IO, when VDD = 1.8 V, f =1MHz...... 80 4.26 Measured and simulated improvement in input power consumption of the one stage bootstrapped voltage doubler with respect to the one stage latched

voltage doubler as a function of the output current IO, when VDD = 1.8 V, f =1MHz...... 81 4.27 Measured and simulated improvement in input power consumption of the two stages bootstrapped voltage doubler with respect to the two stages

latched voltage doubler as a function of the output current IO, when VDD = 1.8 V, f =1MHz...... 81 4.28 Measured load independent power losses versus input supply voltage of two-stage voltage doublers bootstrapped, latched, and bootstrapped with

charge reuse at f =1MHz...... 82 4.29 Measured maximum efﬁciencies versus frequency of two stage voltage

doublers latched, bootstrapped, and bootstrapped with charge reuse at a

supply voltage VDD =1.8V...... 83 LIST OF FIGURES xii

4.30 Measured and calculated [7] outputresistance of the two stage bootstrapped

voltage doublers at a supply voltage VDD = 1.8 V with parasitic resistance of 120 Ω...... 84

5.1 Proposed bootstrapping technique in a modular CP stage used to build

generic double CPs (e.g. doubler-based CP, heap CP, Fibonacci CP, and exponentialCP)...... 87 5.2 Proposed bootstrapping technique in a modular CP stage used to build any two-phasedoubleCP ...... 88

A.1 Topviewofthedesignedchipschematic...... 89 A.2 Blockviewofthesixcircuits...... 91 A.3 Chiplayoutandpadsarrangement...... 92 A.4 Bondingdiagramforthedesign...... 93

A.5 Photographofthefabricatedtestboard...... 94 A.6 Technical drawing of the 24-pin CFP package (Spectrum Semiconductor, Inc)...... 95 A.7 Circuit1schematic(2stMVD)...... 97

A.8 Circuit2schematic(1stMVD)...... 98 A.9 Circuit3schematic(2stMVDDBB)...... 99 A.10Circuit4schematic(2stCSDBB)...... 100 A.11Circuit5schematic(1stCCVD)...... 101 A.12Circuit6schematic(2stCCVD)...... 102

A.13 Clockgenerationcircuitschematic...... 103 Chapter 1. Introduction

Chapter 1

Introduction

1.1 Motivation

Charge pumps (CPs) are power converters that convert the power supply voltage to higher or lower constant (DC) voltages. Charge pumps transfer charge packets from the power supply to the output terminal using only capacitors and switches to generate the required voltage level, thereby allowing integrated implementations. In microsystems, charge pumps are usually fully built on-chip, rather than off-chip, to simplify chip and board design and reduce costs. Integrated implementations of charge pumps exploit integrated capacitors as storage elements and transistors as transfer switches, where the drain and source terminals are the two switch terminals, and the gate terminal is used to control the switch state. Many MOS-based systems such as Flash memories, DRAMs, OTPs, RS-232 transceivers, and driver circuits require multiple supply voltage levels for their functional blocks and therefore are equipped with charge pumps. Integrat- ing the CP and other functional blocks on the same die is critical for footprint and cost reduction, however, it presents unique design challenges in terms of power efficiency, device reliability, driving capability, and performance. The first and most important challenge is power efficiency; charge pumps with low

1 Chapter 1. Introduction 2 power efficiency limit the benefit of power conversion on chip. It is desirable to increase charge pumps efficiency not only in battery-powered systems, but also in many applications with common supply voltages to reduce the integrated circuits packaging cost because of heat dissipation.

A second challenge involves the driving capability; for some applications, a wide range of load currents and output voltages are desirable. However, it is of particular impor- tance that charge pumps are designed to function effectively for certain steady-state operating points with minimum silicon area. In addition, the down-scaling of oxide thickness of MOS devices increases the oxide leakage currents and lessens the oxide breakdown voltage, which in turn limits the maximum voltages that can be safely handled on chip. The reliability of MOS structures is primarily determined by three threatening mechanisms namely punchthrough, oxide breakdown, and well-diffusion junction breakdown. In typ- ical CMOS design, the ﬁrst two factors happen at lower voltages than the well-substrate junction breakdown. The start-up time is an important factor in integrated charge pumps because start-up time limits the functionality and the performance of other blocks, also a faster start-up time can reduce the CP energy consumption during transients and improve the overall efﬁciency.

Finally, the output voltage ripple is a critical design speciﬁcation; larger output ripple degrades the performance of some functions. In particular, the ripple at the output of a charge pump can have a negative impact on sensitive analog circuits such as reference voltage generators, op-amps, and charge pump control circuitry.

1.2 Literature Review

The ﬁrst widely used monolithic charge pump is the Dickson charge pump [1]. This circuit, shown in Fig. 1.1, uses diode connected (N) MOS transistors and a chain of capacitors (C) driven by two complementary phases φ1 and φ2 to transfer charges from the power supply Chapter 1. Introduction 3

Figure 1.1: Four stage conventional Dickson CP [1].

at a voltage VDD to the load capacitor CL at a higher voltage. The ratio between the output voltage and the input voltage is the conversion ratio. The main drawback of this conﬁg- uration is the threshold voltage drop associated with the diode connected transistors. At higher conversion ratios, the performance is even worse because of the increased threshold voltage due to the body effect. Moreover, conversion ratios decrease at low-supply voltages since the threshold voltage shift cannot be scaled down. In the bootstrapped Dickson CP [2], limitations of the switch on resistance, low conduction, and voltage drop associated with diode connected transistors are alleviated by introducing an additional MOS switch Nb and capacitor Cb for boosting the gate voltage of the main switches N as shown in Fig. 1.2. This implementation needs devices able to withstand high voltages and the generation of four nonoverlapping clock phases (φ1, φ2, φ3, and φ4), which also prevent short-circuit currents from nodes at higher voltages to nodes at lower voltages. However, when the diode connected transistor of the output stage is for- ward biased, it causes a voltage loss equal to the diode threshold voltage. This reduction is particularly critical in the presence of low voltage power supplies. A word-line driver with a boosted voltage generator is employed to improve DRAMs performance [3]. The boosted voltage generator is conceived with cross-coupled nMOS transistors driven by the nonoverlapping phases φ1 and φ2. In this conﬁguration, shown Chapter 1. Introduction 4

Figure 1.2: Four stage bootstrapped Dickson CP [2].

in Fig. 1.3, a controlled serial switch NS is required at the output to obtain a constant DC output voltage. The output switch is controlled with a feedback technique by utilizing two additional charge pump circuits, an inverter, and two additional clock phases φ3 and φ4. To improve the performance of charge pumps, the double charge pump in Fig. 1.4 was conceived to reduce the output ripple by feeding the load in each half period using the same total capacitance [4]. The transfer capacitors of the last stage (C = C′) are alternately charged to the voltage of the previous stage (Vp) and then boosted by the same voltage level to charge the load at a higher output voltage. The clock signals of φ1 and φ2 are bootstrapped to the same level as Vp to connect the two capacitors in series. The voltage doubler of Fig. 1.5 usually consists two latched CMOS pairs in each stage [5]. The complementary voltage swings of the internal nodes are used to control the switches of opposite branches. This circuit eliminates the voltage drop at the output switches, reduces the output voltage ripple, and uses only two nonoverlapping phases. Moreover, the voltage across each transistor is never higher than the power supply voltage

VDD. At high output currents, the overdrive voltage decreases causing the output resistance to rise due to higher switch resistance, thus increasing resistive power losses and reducing power efﬁciency and driving capability. Moreover, a short-circuit loss from higher voltage Chapter 1. Introduction 5

Figure 1.3: Simpliﬁed schematic of the boosted voltage generator for DRAM word-line driver [3].

Figure 1.4: Double charge pump [4]. Chapter 1. Introduction 6 nodes to lower voltage node exists during transitions. The resulting short-circuit current reduces the charge pump efﬁciency and output voltage.

The two series pMOS transistors (P and P ′) in Fig. 1.5 act as charge-transfer devices to provide a constant output voltage at the output. If the well potential is too low, the vertical parasitic bipolar transistors create a leakage path to the substrate. As an effort to solve this issue, the pMOS well potential is kept higher than the source and drain terminals by means of a bulk biasing circuit [6]. The solution involves a switching circuit that connects the well to the highest potential. Moreover, the pMOS transistors are driven independently by an additional level shifter to improve their conductivity. However, the implementation is constrained by an input supply voltage of one third the device voltage rating speciﬁed in the process. In the conventional voltage doubler [5], the complementary voltage transitions of internal nodes occur simultaneously during switching. The resulting short-circuit currents can be reduced by exploiting two parallel stages to generate control signals of the main transfer switches [8], or by using four nonoverlapping phases and bootstrapping the pMOS switches [9]. In these implementations, at high output currents, the voltage driving the switches decreases, therefore, reducing both the driving capability and the power efﬁciency.

To overcome the limitation of the charge pump driving capability, an unconventional boosting technique to control switches is suitable for cascaded voltage doubler operating at low supply voltages [10]. The auxiliary boosting circuit generates the proper control signals from the main clock phases. The solution enhances the driving capability and allows the use of low voltage devices, but does not eleminate short-circuit losses. The maximum power efﬁciency is limited by dynamic power losses due to charging and discharging the parasitic capacitances. Reusing some of the charges that are normally wasted for charging and discharging parasitic capacitances at each cycle is a promising approach for reducing power dissipation in charge pumps [11]. This technique improves the power efﬁciency and reduces electromagnetic emission of conventional bootstrapped Chapter 1. Introduction 7

N' P' VDD

CL N P

0 C C'

f1 f2

f1 VDD

V f2 DD

Figure 1.5: One stage voltage doubler CP [5].

Dickson charge pumps. Several charge pump topologies with a voltage gain which increases at a higher rate than the number of stages have been proposed in the literature. The Fibonacci charge pump [12] achieves the highest voltage gain for a given number of capacitors [13]. Another CP structure with a high voltage gain and based on double implementation is the exponential charge pump [14] and [15], which has a voltage gain that increases exponentially with the number of stages. However, it should be pointed out that, as a result the high voltage rise per stage, the output voltage is limited only by the fabrication process and the constraint on the minimum oxide thickness of integrated devices forces the use of a high-voltage thick oxide devices. The heap charge pump represents a different topology that achieves the same ideal gain as the Dickson charge pump for a given number of stages [16]. In this topology, the transfer capacitors are alternately connected in parallel to the input supply voltage and then connected in series to charge the output terminal to a higher voltage level. The maximum voltage across any of the transfer capacitors is only equal to the input voltage, regardless Chapter 1. Introduction 8 of the number of stages, which allow the structure to use low-voltage capacitors.

1.3 Contributions

The work presented here provides analysis, design, and implementation guidelines to en- able successful on-chip integration of charge pumps. Six integrated charge pump circuits were designed and fabricated in a TSMC 0.18-µm CMOS process. The aim of this research is to develop approaches that reduce power losses with less area than existing conventional CP circuits. Design trade-offs are discussed, including a test chip design and testing. The main contributions of this thesis are summarized as:

• Determination of an analysis method for evaluating integrated charge pumps performance and optimizing their design. • Application of the charge reuse concept to effectively reduce the dynamic power losses of integrated double charge pumps.

• Development of a switch bootstrapping technique for double charge pumps. The technique prevents short-circuit losses, improves driving capability, and enables efﬁcient operation at low supply voltages.

• Implementation of six integrated circuits in a 0.18-µm digital process and comparison of experimental results.

1.4 Thesis Organization

The rest of the thesis is organized as follows: Chapter 2 introduces an analysis method to evaluate and optimize the performance of integrated single-sided charge pumps and double charge pumps, and the application of charge reuse in integrated charge pumps. Chapter

3 examines the design limitations of integrated voltage doublers and provides an overview on the design procedure of proposed integrated voltage doubler in standard CMOS process. Chapter 4 presents the implementation of the designed circuits and shows simulation and Chapter 1. Introduction 9 experimental results. The thesis concludes in chapter 5 with the discussion of the obtained results and future developments. Chapter 2. Charge Pump Analysis

Chapter 2

Charge Pump Analysis

2.1 Method of Analysis

In order to design efﬁcient on-chip charge pumps, a careful analysis must be done. The method described here is based on the pioneering work on switched-capacitor circuit analysis [17]. The method is suitable for networks containing switches, capacitors, and voltage sources as illustrated in Fig. 2.1. The circuit is described effectively by means of switching matrices, a capacitance matrix, and a voltage source matrix. The MOS switches are modelled as ideal switches with zero on resistance, capacitors as linear elements, and voltage sources as ideal sources. The analysis is done under the following assumptions. First of all, each switch changes its state (on, off) instantaneously at each switch event tk, where tk is an instant of time when at least one switch in the circuit changes state. Furthermore, slow switching conditions are assumed, where the switching period is much longer than time constants due to capacitances and resistances of integrated components and interconnects. Each switching period consists of k consecutive non-overlapping fragments known as phases, which deﬁne the state of the switches in every fragment (tk, tk+1) and, hence, the charge transfer between capacitors. Finally, the circuit is analyzed in steady-state conditions, where the capacitor voltages are periodic steady-state waveforms.

10 Chapter 2. Charge Pump Analysis 11

Figure 2.1: Block diagram of a generic charge pump.

f f 1 1 2 2 3

f2 f1 4 5 6

1 2 3 4 5 6 f1

1 2 3 4 5 6 f2

Figure 2.2: Generic 2-phase CP building block. Chapter 2. Charge Pump Analysis 12

In each phase, the nodes in the CP circuit are grouped into l separate parts, each part is either a set of nodes connected by closed switches or an isolated node as shown in Fig. 2.2.

Therefore, a k-phase CP with n nodes is described by k switching matrices Sk, with n rows and n columns, to record the CP switching activity. By assigning appropriate numbers to the nodes, the switching matrix elements are deﬁned according to their connection in the switching phase k as follows:

1 if i is the node with the lowest number in a separate part of  Sk(i, j)=  the closed switch network, and node j belongs to that separate part   0 otherwise   (2.1)  where 1 ≤ i ≤ j and 1 ≤ j ≤ n. A n×n capacitance matrix C describes the CP capacitors in terms of their values, node connections, and parasitics, and can be expressed as

total capacitance connected permanently to node i if i = j C(i, j)=  (2.2)  negative of the total capacitance between i and j if i =6 j

 The CP independent voltage source and ground (i.e. grounded switches are connected to a zero value voltage source) connections are described by an n × 2 matrix G, whose elements are deﬁned as

−1 if the h-th voltage source is connected to node i G(i, h)=  (2.3)  0 otherwise

where 1≤ i ≤ n and 1≤ h ≤ 2. The capacitance matrix and the voltage sources matrix do not change as the switches change states. The node voltages are represented by the (n × 1) vector v(tk), which deﬁnes Chapter 2. Charge Pump Analysis 13

the voltage between the i-th node and ground at switch event tk. The charges delivered by the independent voltage sources are represented by the (2×1) vector qI(tk), which denotes the charge passed through the h-th voltage source from switch event tk to switch event tk+1. In each phase, the closure of the switches imposes a set of (n − l + 2) KVL equations and l charge conservation equations, from which we ﬁnd the corresponding nodes voltage at time tk and charges delivered by the sources during the interval (tk, tk+1). For a complete solution, conservation equations can be compactly expressed as:

T vI(tk) −G 0 v(tk) = · , (2.4)    T    SkCv(tk−1) SkC + Sk − I SkG qI(tk)            

where vI(tk) is a (2 × 1) vector which represents the independent voltage sources, and

I is the n × n identity matrix. The (n + 2) × (n +2) matrix Φk in (2.4) can be rearranged to obtain a solution for the nodes voltage v(tk) and the delivered charges qI(tk) as follows:

v(tk)= AkvI(tk)+ BkSkCv(tk−1) (2.5) and

qI(tk)= RkvI(tk)+ OkSkCv(tk−1), (2.6)

where Ak and Bk are the upper-left n×2 submatrix and the upper-right n×n submatrix

−1 of Φk , respectively. Rk and Ok are the lower-left 2×2 submatrix and the lower-right 2×n

−1 submatrix of Φk , respectively. In the case of a CP operating with two phases, in steady- state v(tk−1)= v(tk+1) and v(tk)= v(tk+2), therefore the CP voltage nodes and delivered charges can be calculated. Chapter 2. Charge Pump Analysis 14

Figure 2.3: Procedure for evaluating CP gain. 2.2 Charge Pump Gain

CPs achieve capacitive voltage conversion by means of transfer capacitors and switches driven by nonoverlapping clock phases. Each transfer capacitor is charged to a certain voltage level and then it is boosted by another voltage level resulting in a voltage increase at the output terminal. Since CP circuits do not use inductors, they are well suited for integrated implementations in planar conventional technologies.

2.2.1 Ideal Gain

The voltage gain A is deﬁned as the ratio between the maximum open-circuit output voltage

VO and the input voltage VDD (assumed constant). Since no current is delivered to the load, dependencies on the switching frequency and capacitances values are eliminated. When ideal capacitors are assumed, the gain depends only on the number of capacitors N, the number of phases, and the topology, which, in turn, determines how the transfer capacitors are interconnected in each phase. The procedure for evaluating the voltage gain includes disconnecting any load at the output and ﬁnding the output voltage as shown in Fig. 2.3. Chapter 2. Charge Pump Analysis 15

C Bottom Top

aC bC

Substrate

Figure 2.4: Integrated capacitor model.

2.2.2 Gain with Parasitic Capacitances

A key reason why the gain of a real integrated CP deviates from the ideal is the unavoidable presence of parasitic capacitances, which share a portion of each charge packet transferred between transfer capacitors resulting in reduced gain. Parasitic capacitances are expressed by the technological parameters α and β, which give the stray parasitic capacitances αC (between bottom plate and substrate) and βC (between top plate and substrate) of any integrated capacitor C as shown in Fig. 2.4. The value of α and β are determined by the process and the type of the integrated capacitors used (integrated capacitors are discussed in detail in Chapter 3). To assess the impact of parasitic capacitances on the voltage gain

A, their values are included in the capacitance matrix C by modelling the total capacitance connected permanently to a node as (α + 1)C or (β + 1)C [18]. The gain with parasitic elements is lower than the ideal gain, because a portion of each charge packet transferred between stages is shared with the parasitic capacitors and wasted.

2.3 Charge Pump Output Resistance

In the case of ideal linear elements, the procedure for evaluating the output resistance involves turning off the input voltage VDD, applying an ideal source VX to the output, and calculating the ratio between the voltage and the average current of the applied source as shown in Fig. 2.5. In a two-phase CP the output resistance [19] is given by Chapter 2. Charge Pump Analysis 16

Ix = qxfs

Charge V = 0 V IN pump x

Figure 2.5: Procedure for evaluating CP output resistance.

r RO = , (2.7) f · CT

where f is the switching frequency, CT is the value of the total capacitance deﬁned as

N the sum of the capacitances of all transfer capacitors CT = i=1 Ci, and r is a constant that depends on circuit topology which can be expressed as P

N 2 r = aci, (2.8) i=1 X where N is the number of capacitors and aci = qi/qX is the charge multiplier factor, which is the ratio of the charge qi, transferred by capacitor Ci in a period, and the charge qX delivered to the load. The charge multiplier factors are calculated by applying charge conservation to the circuit in phase 1 and 2, and by considering that, in steady-state, each capacitor receives and delivers the same charge in each of the two phases.

2.3.1 Analysis of Output Resistance with Parasitic Capacitances

To evaluate the effect of parasitic elements on the output resistance, we include αCi and

βCi in the capacitance matrix, turn off VDD, connect a voltage source at the output, apply the method above one more time, and ﬁnd the charge qX delivered by the voltage source during the switching period, the corresponding current, and thus the output resistance. The output resistance with parasitic elements is lower than the ideal, because it is inversely Chapter 2. Charge Pump Analysis 17 proportional to the node capacitances that increase with the parasitics.

2.4 Power Losses in Charge Pumps

Charge pumps transfer charge packets from the power supply at a voltage VDD to an output terminal at a higher voltage VO. In this operation, CPs dissipate a portion of the input power and may reduce the benefit of scaling the supply voltage down. The energy efficiency is defined as the average power delivered to the load divided by the average of input power. Power losses arise mainly from capacitor charging and discharging losses, resistive conduction losses, and losses due to parasitic capacitances and short-circuit currents.

The highest efﬁciency is achieved in slow switching conditions. In such conditions and in steady-state, the main power losses are described by a simple model and can be divided into load dependent losses and load independent losses [20].

2.4.1 Load-Dependent Losses

Load-dependent losses are revealed when the charge pump is connected to a load and the output voltage decreases in the presence of a load current IO > 0. These losses are modelled through a non-zero equivalent output resistance RO and the corresponding power dissipation is

2 PLD = RO · IO . (2.9)

This formula indicates that lower load dependent losses can be achieved by reducing the output resistance RO given in (2.7) which is inversely proportional to the product of the switching frequency f and the total capacitance CT . Chapter 2. Charge Pump Analysis 18

2.4.2 Load-Independent Losses

Load independent losses are revealed when the CP is not connected to any load and it still dissipates power. These losses mostly arise from charging and discharging parasitic capacitances and are also called dynamic losses. They are modelled through a non-zero equivalent input conductance GI and the corresponding power dissipation is

2 PLI = GI · VDD . (2.10)

The dynamic losses of switch drivers and other auxiliary functions could be incorpo- rated in the model as well. However, for the present we focus our analysis only on the charge pump core. In this case, the input conductance is proportional to the product of the switching frequency and the total capacitance:

GI = fCT · g , (2.11) where g is a constant that depends on circuit topology and parasitic capacitances. The procedure for evaluating the input conductance involves disconnecting the output load and calculating the charge delivered by the source VDD to the CP as shown in Fig. 2.3. The output power of a charge pump (i.e. the power delivered to the load) is

PO = VO IO =(AVDD − RO IO) IO , (2.12)

Assuming the gain A> 1, the charge pump has a conversion efﬁciency given by

2 PO AVDD IO − RO IO η = = 2 , (2.13) PO + PLD + PLI AVDD IO + GI VDD Chapter 2. Charge Pump Analysis 19 which is maximum when the output current is equal to

2 GI VDD A IˆO = +1 − 1 . (2.14) A sGI RO !

In this condition, the ratio

2 PLI A 1 = · 2 , (2.15) P G R 2 LD I O A − GI RO +1 1 q is larger than one for any acceptable value of A, GI , and RO. In other words, at peak efﬁciency, load-independent losses are larger than load-dependent losses (i.e. PLI > PLD at IO = IˆO). In general, load-independent losses dominate at low currents such that

0 ≤ IO

2.5 Analysis of Single-Sided Charge Pumps

Several single-sided CP structures have been proposed in the literature, each suited to meet speciﬁc application requirements and address process constrains. Single-sided CPs transfer charge packets to the load once every switching period. Indeed, the differences between

CPs structures correspond to the configuration of their capacitors and switches in each phase. Exploring different CPs structures is motivated by choosing the appropriate structure in order to maximize the efficiency. In the Dickson CPs in Fig. 2.6(a) [2], MOS switches controlled by non-overlapping control phases eliminate the voltage drops associated with the diodes used in the classic Chapter 2. Charge Pump Analysis 20 configuration [1]. Each transfer capacitor is charged to the voltage of the preceding stage and then boosted by VDD to charge the next stage at a higher voltage. Ideally, a circuit with

2 N stages has a voltage gain A = N +1, an output resistance RO = N /(fCT ), and an input conductance GI =0.

In the heap CP in Fig. 2.6(b) [16], the voltage across each capacitor never exceeds VDD making this type of CPs attractive for implementationsin low-voltage processes. A heap CP

2 with N stages has an ideal voltage gain A = N +1, an output resistance RO = N /(fCT ), and an input conductance GI =0. The Fibonacci CP with three capacitors shown in Fig. 2.6(c) [12] has the same ideal gain as the Dickson and the heap CPs with four capacitors (Figs. 2.6(a) and 2.6(b)). This two phase CP single-sided structure has the highest attainable gain for a given number of capacitors [13]. The gain of an ideal Fibonacci CP with N stages is A = FN+1, where FN is the N-th Fibonacci number, with F0 = F1 = 1 and Fi = Fi−1 + Fi−2 for i > 1. In the case of equal transfer capacitors Ci = CT /N, the charge multiplier factors are aci = FN−i

N N 2 for to , the output resistance of this topology is − , and the i = 1 N RO = f·CT i=1(FN i) input conductance GI = 0. P

2.5.1 Optimization of the Output Resistance

To minimize the output resistance of any CP for a constant total capacitance CT , we sub- stitute C1 = CT − C2 − ... − CN in (2.7) and we set the partials with respect to capacitors

Ci equal to zero, which means

∂R 1 a2 a2 O = · ci − ci =0, (2.17) ∂C f C − C − ... − C C2 i T 2 N i for i =2 to N [18]. Since the available silicon area is a critical constraint for a designer, the CPs capacitor sizes, which are the largest portion of an integrated CP, are optimized to improve CPs per- Chapter 2. Charge Pump Analysis 21

VDD bC bC bC bC V I 1 1 2 2 1 3 2 4 1 O O

C1 C2 C3 C4 Load

a(C +C ) (C +C ) 1 3 a 2 4 0

1 2 2 1

0 VDD 0 VDD

(a) Four-stage Dickson CP.

VDD

1 1 1 1 V I 2 O O bC bC bC1 bC2 3 4 C C C C 1 2 3 4 Load 2 2 2 2

aC aC 0 1 2 aC3 aC4 1 1 1 1

0 0 0 0

(b) Four-stage heap CP.

Figure 2.6: Schematic diagrams of conventional charge pumps with parasitic capacitances. formance. Considering the three structures (i.e. the Dickson, the heap, and the Fibonacci) and the calculated charge multiplier factors for each structure, the optimal capacitor sizes are found. The optimal performance of an N-stage CP is not necessarily obtained when capacitances are equal, but when they scale as a function of the charge multiplier factor. Chapter 2. Charge Pump Analysis 22

A = 5 A = 8 A = 13

C1 C2 C3 C1 C2 C3 C4 C1 C2 C3 C4 C5

Fibonacci Fibonacci Fibonacci

C C C C C C C C C C C C C C C C C C C C C C 1 C2 3 4 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 10 11 12

Dickson Dickson Dickson

C1 C2 C3 C4 C1 C2 C3 C4 C5 C6 C7 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10C11C12

Heap Heap Heap

Figure 2.7: Sketch of capacitors with optimal size of Dickson, heap, and Fibonacci CPs of equal area and gain (i.e. left A = 5, centre A = 8, right A = 13).

For instance, the optimal performance of an N-stage Fibonacci CP is when capacitors are scaled as the Fibonacci sequence with the largest capacitor next to VDD and the smallest next to the load. When the capacitors are optimized as shown in Fig. 2.7, the three CPs have a similar performance. In this case, the trade-off between gain A and output resistance can be expressed as [18]: (A − 1)2 RO = . (2.18) fCT

2.5.2 Single-Sided Charge Pumps with Parasitic Capacitances

The design parameters for the CPs shown in Fig. 2.6 are calculated as a function of α and β. For the Dickson CP the gain is

N A = +1 , (2.19) 1+ β the output resistance is r RO = , (2.20) fCT with N 2 r = , (2.21) (1 + β) Chapter 2. Charge Pump Analysis 23

0.8 Dickson Fibonacci 0.6 Heap

g 0.4

0.2

0 1 3 5 7 9 11 Voltage Gain A

Figure 2.8: Normalized input conductance g of Dickson, heap, and Fibonacci CPs as a function of A, when α =0.1 and β =0.05.

and the input conductance is

α + β + αβ G = fC · , (2.22) I T 1+ β with α + β + αβ g = . (2.23) 1+ β

The analytical expressions for A, r, and g in the case of the optimized heap and the Fibonacci CPs are collected in Table 2.1 and 2.2. The performance comparison indicates that the Dickson CP performs the best since bottom plate parasitics α does not contribute to the gain reduction as in other structures where a signiﬁcant portion of charges delivered to the output is shared with the parasitic capacitances αCi associated with the bottom plate of the transfer capacitors. Also, the input conductance of the Dickson CP is independent of the number of stages. Accordingly, the load-independent losses of Dickson CPs depend

2 only on α and β, the total capacitance, the switching frequency, and VDD. On the other hand, the heap CP has the worst performance, exhibiting a much lower gain than other topologies at large number of stages N. Chapter 2. Charge Pump Analysis 24

16 Dickson

12 Fibonacci Heap

r 8

0 1 2 3 4 5 Voltage Gain A

Figure 2.9: Normalized output resistance r of Dickson, heap, and Fibonacci CPs as a function of A, when α =0.1 and β =0.05.

Table 2.1: Heap CP Design Parameters. N Parameters =1+ 1 1 A 1+β = 1 r 1+β = α+β+αβ g 1+β =1+ 2+β 2 A 1+α+(3+α)β+β2 = 2(2+α+β) r (1+α+(3+α)β+β2) = (5+α+2β)(α+β+αβ) g 2(1+α+(3+α)β+β2 2 = (2+α+β)(2+α+(4+α)β+β ) 3 A 1+α2(1+β)+β(2+β)(3+β)+α(3+2β(3+β)) = 3(1+α+β)(3+α+β) r (1+α2(1+β)+β(2+β)(3+β)+α(3+2β(3+β))) 2 = ((α+β+αβ)(14+α +4α(2+β)+β(14+3β))) g (3(1+α2(1+β)+β(2+β)(3+β)+α(3+2β(3+β)))) 2 2 = ((1+α+(3+α)β+β )(5+α +β(5+β)+α(5+2β))) 4 A (α3(1+β)+α(3+β)(2+3β(2+β))+α2(5+3β(3+β))+(1+β)(1+β(3+β)2)) 2 = 4(2+α+β)(2+α +2α(2+β)+β(4+β)) r (α3(1+β)+α(3+β)(2+3β(2+β))+α2(5+3β(3+β))+(1+β)(1+β(3+β)2)) 2 = ((α+β+αβ)(14+α +4α(2+β)+β(14+3β))) g (3(1+α2(1+β)+β(2+β)(3+β)+α(3+2β(3+β)))) Chapter 2. Charge Pump Analysis 25

Table 2.2: Fibonacci CP Design Parameters. N Parameters 1 1 A =1+ 1+β 1 r = 1+β α+β+αβ g = 1+β 2 2 A =1+ 1+β 4 r = 1+β α+β+αβ g = 1+β α(1+β)+(2+β)(5+2β(4+β)) 3 A = (1+β)(2+α+(5+α)β+2β2 ) 2α(1+β)+((2+β)(4+5β) r =4 (1+β)(2+α+(5+α)β+β2 (α+β+αβ)(3α(1+β)+(2+β)(7+8β)) g = 4(1+β)(2+α+(5+α)β+2β2 ) 48+α(1+β)(8+5β)+β(4+β)(35+6β(4+β)) 4 A = (3+2β)(2+3β)(1+β(3+β))+α2 (1+β)2+α(1+β)(7+β(16+7β)) 42+2α2(1+β)+α(19+3β(12+5β))+β(109+β(80+17β)) r =7 (3+2β)(2+3β)(1+β(3+β))+α2 (1+β)2+α(1+β)(7+β(16+7β)) (α+β+αβ)(108+5α2 (1+β)+α(49+92β+38β2 )+β(277+200β+42β2 )) g = (7(1+α+(3+α)β+β2 )(6+α+(13+α)β+6β2 ))

Examples of numerical values of g and r for various values of A are respectively shown in Fig. 2.8 and Fig. 2.9, where they are plotted as function of A for α = 0.1 and β = 0.05. In the Dickson CP, the normalized input conductance g does not change with the number of stages, while the voltage gain A and the output resistance does not depend on the value of α, because the circuit can be built so that the bottom plates of all capacitors are alternately connected to ground and VDD without affecting the charge transfer through the CP. For the Fibonacci and heap CPs, the normalized input conductance g depends on the number of stages because bottom plate parasitic capacitances share a portion of the charge transferred to the output and therefore affect performance.

2.6 Analysis of Double Charge Pumps

The output voltage ripple can be reduced by splittingthe CP in two parts, each part with half the total capacitance and feeding the load in a different half period [4]. This conﬁguration, called double CP, is usually implemented as a parallel connection of stages operating with opposite phases. Fig. 2.10 shows implementations of double CPs of the circuits seen in the Chapter 2. Charge Pump Analysis 26

last section. The voltage gain A, the output resistance RO, and the input conductance GI are the same as the single-sided CPs when the total capacitance is the same. On the other hand, the voltage ripple deﬁned as the peak to peak variations in the DC output voltage, is halved with respect to the single-sided charge pump and can be expressed as [21]

IO Vripple = , (2.24) 2 · f · CL

where CL is the load capacitance. Another CP structure used to achieve a high voltage gain is the exponential CP shown in Fig. 2.10(d). The gain of an ideal exponential CP with N stages is A =2N . In the case

2(N−i) of equal transfer capacitors Ci = CT /(2N), the charge multiplier factors are aci =2 for to , the output resistance is N N 2(N−i), and the input conductance i =1 N RO = f·CT i=1 2

GI = 0. The optimal performance of an exponentialP CP with N stages is obtained using (2.17), and the minimum output resistance is when capacitors are sized as

2N−i C = C . (2.25) i 2N − 1 T

A comparison between the optimal capacitors sizes of an ideal Dickson and an ideal exponential CPs with the same performance is shown in Fig. 2.11

2.6.1 Double Charge Pumps Performance with Parasitic Capacitances

The analytical expressions for A, r, and g in the case of the optimized exponential CP are collected in Table 2.3, while A, r, and g for the double Dickson, double Fibonacci, and double heap CPs are the same as those of the single-sided implementations. Comparing the performance of the exponential CP to the double Dickson, again the Dickson CP performs the better since bottom plate parasitics α does not contribute to the gain A reduction as in other structures where a signiﬁcant portion of charges delivered to the output is shared with transfer capacitances bottom plate parasitics and wasted every clock cycle. Also, the Chapter 2. Charge Pump Analysis 27

2 1 2 1 2 2 1 2 1

C' C' C' C' C' C' C' 1 2 1 V V DD I DD O IO V V 1 2 2 1 1 2 2 1 O 2 1 2 O Load Load V 0 V V V DD DD 0 DD 0 DD 0 0 0 0

1 2 1 2 1 0 1 2 1 2 0

C C C C C C C 2 1 2

2 1 1 2 2 1 1 2 1 2 1

V 0 V V DD DD 0 DD 0 VDD 0 0 0 0 (a) Four-stage double Dickson CP. (b) Three-stage double Fibonacci CP.

2 2 2 2 1

V C' C' C' C' DD 1 1 1 1 I 2 2 2 2 V O O Load 0 0 0 0

1 1 1 1 2 0

C C C C 2 2 2 2

1 1 1 1

0 0 0 0 (c) Four-stage double heap CP. (d) Three-stage double exponential CP.

Figure 2.10: Schematic diagrams of double charge pumps.

input conductance of the exponential CP depends on the number of stages. Accordingly, the load-independent losses of exponential CPs are higher, because of the voltage swings

across the parasitic capacitances larger than VDD.

2.7 ChargeReuse

At low output current, the conversion efﬁciency is largely set by parasitic capacitances. In order to reduce dynamic power losses, charge reusing [11] is investigated to mitigate

these losses. If we consider those internal nodes of a conventional charge pump (Fig. 2.6) that are connected to ground through a switch at every cycle, the parasitic capacitances associated with them are charged to a certain voltage and then discharged to 0, therefore the related charge is wasted in every cycle. We can reuse part of that charge (and therefore Chapter 2. Charge Pump Analysis 28

Figure 2.11: Sketch of capacitors with optimal size of double Dickson and double exponential CPs of area and gain (i.e. left A= 4, right A = 8).

Table 2.3: Exponential CP Design Parameters. N Parameters 2+β 1 A = 1+β 1 r = 1+β α+β+αβ g = 1+β 2.(2+β)2 2 A = (2+α+(5+α)β+2β2 ) 3(6+α+3β) r = (2+α+(5+α)β+2β2 ) 2(6+α+3β)(α+β+αβ) g = 3(2+α+(5+α)β+2β2 4.(2+β)3 3 A = α2(1+β)+(2+β)2 (1+4β)+α(2+β)(4+5β) 7(α2+6α(2+β)+7(2+β)2 ) r = (α2(1+β)+(2+β)2 (1+4β)+α(8+14β+5β2 )) 2 2 4(α+β+αβ)(α +6α(2+β)+7(2+β) )CT g = 7(α2(1+β)+(2+β)2(1+4β)+α(8+14β+5β2 )) Chapter 2. Charge Pump Analysis 29

2 Charge IN pump 2 OUT VDD VO 0 0 IO 3 3 3 1 Charge IN pump 1 OUT 0

0 0 1

3 1 2

Figure 2.12: Charge reuse conﬁguration of a generic double CP. save charges drawn from the power supply), if pairs of such nodes with complementary voltage swings (i.e. 180◦ out of phase) are equalized before each switch event. Double CPs clocked with opposite phases, have pairs of such nodes in each stage. Thus, charge reuse can be applied to all stages of any double CP [20] as shown in Fig. 2.12. Fig. 2.13 describes the charge reuse concept where an equalization switch driven by an appropriate control signal is used to bring the nodes (X and X′) to an intermediate voltage level. The time required by this operation is much smaller than the time needed for charging the transfer capacitors, because only a small fraction (e.g. α) of the capacitance is involved. Therefore, the time allocated for the equalization has a limited impact on the operating frequency. The principle of charge reuse is based on equalizing the voltages of the parasitic capacitances in each stage. The equalization switch controlled by phase 3 brings both capacitances to an intermediate voltage before each switch event, therefore the amount of charges drawn from the power supply for charging parasitic capacitances is less than the amount needed by conventional CPs. As a consequence, charge reusing reduces the load- independent losses. As design examples, we consider double Dickson CP, double Fibonacci CP, and a double heap CP. Applying charge reusing requires splitting the circuits into two Chapter 2. Charge Pump Analysis 30

(a) Circuit to describe the charge reuse.

(b) Clock phases and internal nodes voltage waveforms.

Figure 2.13: Description of charge reuse concept in double charge pumps. symmetrical parts (double CP) driven by complementary control signals and operating in parallel, as shown in Fig. 2.12. Examples of charge reuse application to the heap and Fi- bonacci CPs are shown in Fig. 2.14(a) and 2.14(b), respectively. In these cases, charge reusing not only reduces GI , it also increases A and RO.

2.8 Simulation Results with Charge Reuse

Three CP types (i.e. the Dickson, the heap, and the Fibonacci charge pumps) were designed and simulated with Spectre using MOS switches and poly-diffusion capacitors in a standard

0.18-µm technology. Fig. 2.15 shows the normalized input conductance g versus the gain

A. The reduction of g (and consequently of PLI ) for the Dickson CP is 50%. On the other Chapter 2. Charge Pump Analysis 31

(a) Three-stage double Fibonacci CP with charge reuse.

(b) Four-stage double heap CP with charge reuse.

Figure 2.14: Schematic diagrams of double charge pumps with charge reuse (parasitic capacitances are omitted for simplicity). hand, the improvement for the Fibonacci and heap CPs is less than 50% for gains larger than two and depends on the number of stages. Fig. 2.16 shows the output characteristics and the conversion efficiency η of the three CP types. The results are obtained when N =4 for Dickson and heap CPs and when N =3 for the Fibonacci CP. The output characteristics of the Dickson CP is not changed, while the open-circuit gains of the Fibonacci and heap CPs with charge reusing are improved (i.e. 1.9% and 8.7% increase, respectively), because parasitic capacitances draw less charge from the primary charge transfer path. More significantly, charge reusing substantially improves the overall conversion efficiency η in any CP type: The maximum efficiency increases from 52.5% to 63% for the Dickson CP and from Chapter 2. Charge Pump Analysis 32

1 Dickson Fibonacci 0.8 Heap Dickson-reuse Fibonacci-reuse 0.6 Heap-reuse g 0.4

0.2

0 1 3 5 7 9 11 Voltage Gain A

Figure 2.15: Normalized input conductance g versus voltage gain A for the three CP types in standard conﬁguration and with charge reuse, when α =0.1, and β =0.05.

23% to 31% for the heap CP, and from 43% to 53% for the Fibonacci CP. Reusing wasted charges reduces the current drawn from the power supply and increases the conversion efﬁciency.

2.9 Summary

In this chapter, a method of analysis for evaluating integrated charge pumps performance and optimizing their capacitor sizes is determined. The analysis allows the calculation of the voltage gain A, the output resistance RO, and the input conductance GI and consequently the major power losses (resistive and dynamic power losses) of any integrated CP can be evaluated. Moreover, charge reuse is applied to with the result of reducing the dynamic power losses and improving the overall conversion efficiency. The technique can be applied to any double CP. The application of charge reuse results in reduced dynamic power losses and a significant portion of wasted charges is recovered every clock cycle. The Dickson CP has the best performance in terms of the voltage gain and power efficiency. When charge reuse is considered the double Dickson (voltage doubler) CP has a Chapter 2. Charge Pump Analysis 33

0.8 Dickson 0.7 Fibonacci Heap 0.6 Dickson-reuse Fibonacci-reuse 0.5 Heap-reuse 0.4 0.3 0.2 Conversion Efficiency 0.1 0 0 100 200 300 400 500 600 700 800

IO (m A)

(a) Conversion efﬁciency.

10 Dickson 9 Fibonacci 8 Heap 7 Dickson-reuse Fibonacci-reuse 6 Heap-reuse O

V 5 4 3 2 1 0 0 100 200 300 400 500 600 700 800

IO (m A)

(b) Output characteristics.

Figure 2.16: Conversion efﬁciency and output characteristics of the three CP types as a function of the output current IO, when n = 4 for Dickson and heap CPs and N = 3 for the Fibonacci CP, VDD =1.8 V, CT = 200 pF, f = 10 MHz, α =0.1, and β =0.05. better performance. Chapter 3. Design

Chapter 3

Design

3.1 Introduction

The designer of integrated charge pumps has to face the constraints of the fabrication technology. Typically, integrated CMOS circuits share a single substrate, thus the chip layout geometry and the proximity of the process layers to the substrate produce parasitic capacitive couplings. The existence of such parasitics limits the charge pump performance and efficiency. Moreover, the performance of a CP depends critically on how its MOS switches are controlled. First of all, the overdrive voltage applied to turn a switch on determines its on resistance and drain-to-source voltage drop, which, in turn, affect the conversion efficiency and voltage gain. In addition, the maximum and minimum voltages applied to the switch gates affect the dynamic power losses and can be constrained by the device voltage rating. Finally, precision and adjustability in controlling the switch affect the frequency of operation (which trades off with the silicon area required for meeting design specifica- tions) and can prevent short-circuit currents from nodes at higher voltages to nodes at lower voltages during transitions (which affect efficiency). Switch bootstrapping improves conduction during the on state by connecting a given voltage between the gate and source terminals, typically by using a capacitor pre-charged

34 Chapter 3. Design 35 during the off state [22]. Moreover, reusing some of the charges that are normally wasted for charging and discharging parasitic capacitances at each cycle is a promising approach for reducing power dissipation in charge pumps [11]. In this chapter, we analyze and discuss the design aspects of integrated voltage doubler.

First, the standard voltage doubler limitations are pointed out. Second, we propose a new voltage doubler with a switch bootstrapping technique, where the voltages driving the gates of nMOS and pMOS switches can be controlled both in terms of voltage swing and timing such that limitations of standard voltage doubler are alleviated. The application of the technique is demonstrated through the design of various voltage doublers. Also, dynamic power losses due to parasitic capacitances are addressed and a method for reducing them through charge reuse is described. Simulations of the various voltage doublers conﬁrm the effectiveness of the proposed techniques which result in an improved overall performance.

Technology and design constrains are addressed as well, and design trade-offs are discussed in order to ﬁne tune the circuit components.

3.2 Voltage Doubler

In the bootstrapped Dickson CP [2], switch voltage drop, varying on resistance, and low conduction are alleviated by using four non-overlapping clock phases, which also prevent short-circuit currents from nodes at higher voltages to nodes at lower voltages. This implementation needs the generation of four appropriate clock phases and MOS switches able to withstand high voltages. The output voltage ripple can be reduced by splitting the CP in two parts each with half the total capacitance and feeding the load in a different half period [4] as depicted in (2.24). This conﬁguration, called double CP, is usually implemented as cascade connection of voltage doublers [5], [6], which need only two clock phases instead of four. As shown

′ ′ in Fig. 3.1, each modular stage is made of two latched CMOS pairs (Ni , Pi , Ni, Pi),

Chapter 3. Design 36 ( (

Figure 3.1: Conventional 2-phases cross-coupled voltage doubler stage.

′ ′ ′ two transfer capacitors (Ci, Ci), and two drivers (NDi-PDi, NDi-PDi), and does not need dedicated bootstrap drivers. Vi is the output voltage of the i-th stage and Vi is the input voltage. The transfer capacitors of each stage are alternately charged to the voltage of the previous stage and then boosted by VDD to charge the next stage at a higher voltage. The complementary voltage swings on the internal nodes are used to control the switches of opposite branches. Since the maximum voltage rise from Vi−1 to Vi is VDD, the voltage across each device is never higher than VDD and low voltage MOS switches can be used. In steady state, the operation of the voltage doubler (Fig. 3.1) is as follows; during the

′ ′ ﬁrst half cycle, φ1 = VDD and φ2 = 0, transistors Ni, NDi,Pi , and PDi are on, and transistors ′ ′ Ni , NDi,Pi, and PDi are off; transfer capacitor Ci is charged to Vi−1 through Ni and NDi, ′ ′ ′ while transfer capacitor Ci is boosted to Vi−1 +VDD through Pi and PDi. During the second ′ ′ ′ half cycle, and transistors Ni , NDi,Pi, and PDi are turned on, and transistors Ni, NDi,Pi , ′ ′ and PDi are off; transfer capacitor Ci is charged to Vi−1, while transfer capacitor Ci is boosted to charge next stage to Vi−1 + VDD. Chapter 3. Design 37 3.3 Losses and Efﬁciency

In slow-switching conditions, the main power losses of integrated charge pumps can be simply classiﬁed into load-dependent losses, load-independent losses [23], and short-circuit power losses of phase drivers and main pass transistors.

3.3.1 Load-Dependent Power Losses

When the load current IO > 0, the output voltage VO of a voltage doubler with N stages is reduced because of its non-zero equivalent output resistance RO and can be expressed as [1]

N N · I V = +1 · V − O (3.1) O 1+ β DD (1 + β) · 2 · f · C i The voltage rise per stage ∆V for a voltage doubler is

V R ∆V = DD − O · I . (3.2) 1+ β N O

From (3.1), the maximum output current (i.e. when VO =0) IOmax is limited to

N +1+ β I = · 2 · f · C · V . (3.3) Omax N i DD

In real implementations, the switches are designed with MOS transistors operating in triode region. In particular, CMOS switches are turned on with an overdrive ∆V − Vt (i.e. for simplicity pMOS and nMOS switches are assumed to have the same threshold voltage

Vt) and their on resistance RON can be approximated as

1 RON = (3.4) k · (∆V − Vt)

where k = µCoxW/L is the switch transconductance parameter. At high output currents, the overdrive voltage decreases according to (3.2) (i.e. ∆V becomes low). In these Chapter 3. Design 38

conditions the on resistance of each switch increases and if ∆V ≤ Vt the switches are off. The CP output resistance given by

N 1 R = · coth (3.5) O (1 + β) · 2 · f · C fC R i i ON

2 increases as well, thus making the load-dependent losses PLD = ROIO larger. Such losses are particularly signiﬁcant at high output currents and low VDD, the maximum output current IOmax in (3.3) is therefore reduced and a new maximum output current limit is obtained. In other words, for the MOS switch to conduct in the triode region, it must satisfy the relation

∆V ≥ Vt (3.6)

which imposes an upper bound on IO, and the maximum output current becomes

′ IOmax =(VDD − (1 + β)Vt)2fCi (3.7)

3.3.2 Load-Independent Power Losses

In integrated voltage doublers, load-independent power losses (also called dynamic or switching losses) can be calculated through the non-zero equivalent input conductance GI as explained in Chapter 2, so that the corresponding power dissipation is approximated as:

α + β + αβ P = fC V 2 (3.8) LI 1+ β T DD

Accordingly, the load-independent power losses of a voltage doubler depend only on α

2 and β, the switching frequency, the total capacitance, and VDD, and are independent from the number of stages. From the analysis in chapter 2, load-independent losses are the major power losses at Chapter 3. Design 39

Figure 3.2: 2-phases cross-coupled voltage doubler stage. low currents. Therefore, based on the design speciﬁcations, minimizing load-independent losses for voltage doublers meant to operate at maximum efﬁciency or at low currents is a critical design consideration. From (2.21), (2.22), and (2.16), a limit condition when load-independent losses in voltage doublers dominate is found and can be expressed as

fC V I ≤ α + β + αβ · T DD . (3.9) O N p 3.3.3 Short-Circuit Power Losses

In the conventional cross-coupled voltage doubler Fig. 3.2, each stage is seen as a CMOS

′ ′ latch, the gates of switches Ni , −Pi and Ni − Pi are driven by the voltage rise on nodes Bi ′ and Bi. At this point, three major cases of reversion and short-circuit losses are identiﬁed. First, in the time slot during transitions when the voltage rise across the stage is higher

′ than the overdrive of pass transistors Ni or Ni (i.e. ∆V ≥ Vi−1 + Vt), a reversion current ′ ﬂows from Ci or Ci back to node Vi−1. Second, in the time slot during transitions when the Chapter 3. Design 40

voltage rise across the stage is lower than Vi − Vt (i.e. ∆V ≤ Vi − Vt), pass transistors Pi

′ ′ or Pi are partially on, causing a reversion current from node Vi back to Ci and Ci . Third, ′ ′ the short time slot, when the CMOS pairs Ni-Pi and Ni -Pi are conducting simultaneously, generates a short-circuit current from the higher-voltage node Vi to the lower-voltage node

Vi−1. All these losses can degrade the CP efﬁciency and the output voltage [24]. The short- circuit power consumption depends mainly on the voltage rise per stage ∆V , the input

′ transition time τ, the threshold voltage Vt, and transfer capacitors (Ci,Ci) [25]

PSC = PSC (k,Vt, ∆V,τ,f,Ci). (3.10)

Short-circuit losses are particularly signiﬁcant at low output currents , when ∆V is high compared to Vt, while they are negligible when

∆V ≤ 2Vt (3.11)

A limit condition on the output current IO range where short circuit losses are signiﬁ- cant, can be obtained from (3.2) and (3.11)

IO ≤ 2 f Ci(VDD − 2(1+ β) Vt) (3.12)

The problem can be alleviated by driving pMOS switches with level shifters generating nonoverlapping control signals varying from 0 to Vi [6] or by using two parallel stages generating control signals varying from Vi−1 to Vi [8]. The problem can be solved by using four nonoverlapping clock phases and bootstrapping the pMOS pairs [9] or by adding series switches and using ﬁve phases [26]. Chapter 3. Design 41

Figure 3.3: Proposed bootstrapping technique applied to a voltage doubler stage. 3.4 Proposed Switch Bootstrapping Technique

The problem of the increased MOS on resistance (reduced driving capability) can be solved by boosting the voltage driving the main CMOS switches with a voltage swing that does not vary with IO [10], a solution that improves the driving capability at low VDD, but does not alleviate short circuit losses. In order to prevent short-circuit currents and the reduced current driving capability ob- served in the conventional voltage doubler, a new modular bootstrapping technique that allows full control on MOS switches is proposed [27] and [28]. The circuit in Fig. 3.3, provides both control on the timing of the switch transitions (therefore preventing short-circuit losses) and on the gate voltage swings (therefore improving driving capability).

Having same pass transistors, transfer capacitors, drivers, and nonoverlapping phases as the conventional one, the proposed circuit includes an nMOS cross-coupled clock booster Chapter 3. Design 42

′ ′ (Nbi, Nbi, Cni, Cni) driven by φ1 and φ2 and a pMOS cross-coupled clock booster (Pbi, ′ ′ Pbi, Cpi, Cpi) driven by φ1 and φ2. Short-circuit losses are prevented because the volt- ′ ′ ages applied between the gate and source terminals of pairs Ni - Ni and NDi - NDi have nonoverlapping transition times with both voltages low, whereas the gate-to-source volt-

′ ′ ages of pairs Pi - Pi and PDi - PDi have complementary transition times with both voltages high. The timing of switch transitions and the nonoverlapping slots can be adjusted by controlling the main clock phases. The amplitude of the gate voltage swings does not depend on output current or number of stages and is controlled by the low and high levels of the main phases, typically varying from 0 to VH = VDD. The corresponding voltage control-

′ ling Ni and Ni goes from Vi−1 (off) to Vi−1 + VH (on) and the voltage controlling Pi and ′ Pi goes from Vi − VH (on) to Vi (off). In steady state, the maximum voltage across any switch is VDD and internal voltages are within the range from 0 to the maximum CP output voltage.

3.5 Charge Reuse Technique

Since load-independent losses due to parasitic capacitances have a strong impact on conversion efﬁciency. Dynamic power losses can be reduced by reusing some of the charges wasted in charging or discharging the parasitic capacitances each cycle [11], [20]. In particular, if we consider those internal nodes of a voltage doubler that are connected to ground through a switch at every cycle and have complementary voltage swings, the parasitic capacitances associated with them are charged to a certain voltage and then discharged to

0, therefore a part of that charge can be reused (and therefore the input conductance is reduced). This can be accomplished if we redirect some of the charges wasted at falling nodes to charge parasitic capacitances at rising nodes before each switch event. To that end, switches driven by appropriate control signals are used to equalize the Chapter 3. Design 43 voltages of the parasitic capacitances. The time required by this operation is much smaller than the time needed for charging the transfer capacitors, because only a small fraction

(e.g. α, typically 1.5% to 20%) of the capacitance is involved and equalization switches are sized to complete charge reuse within each nonoverlapping time slot. Therefore, the time allocated for the equalization has a limited impact on the voltage doubler operation. Furthermore, the control signal can be generated through a NOR gate directly from the nonoverlapping control phases that are already needed to avoid short-circuit losses.

3.5.1 Charge Reuse Voltage Doubler Design

The design of a voltage doubler stage with charge reuse is shown in Fig. 3.4. The parasitic

′ capacitances αCi and αCi are alternately charged to VDD and discharged to 0. The equalization switch controlled by a NOR circuit brings both capacitances to VDD/2 before each switch event, therefore the amount of charges drawn from the power supply for charging parasitic capacitances is half the amount needed by the conventional circuit. As a consequence, charge reusing can reduce the load independent losses by a factor two. Circuit analysis conﬁrms that the input conductance of the voltage doubler CPs with charge reuse is half that of conventional voltage doubler CPs:

α + β + αβ G∗ = fC · , (3.13) I T 2(1+ β)

while the voltage gain A and the output resistance RO are unchanged.

3.6 Design Constrains

The design of efﬁcient and high performance CPs is usually associated with several design concerns that need to be addressed. Design considerations on MOS switches and bootstrapping circuits play an important role in the proper operation of the charge pump. Chapter 3. Design 44

Figure 3.4: Bootstrapped voltage doubler stage with charge reuse.

3.6.1 MOS Switches

The use of MOS transistors as switches requires that switches are designed appropriately.

MOS switches with a large aspect ratio are required mainly for three reasons. First, large switches (i.e. with low on resistances RON ) reduce resistive power losses. Second, to ensure a small time constant (i.e. fast transient) of the charge transfer paths, large switches are needed. Third, charge pumps require large switches if they have to deliver large currents. In addition, the maximum switching frequencies at which a charge pump can operate depend on the time constants of the individual stages. Each stage can be viewed as an

RC network, which needs MOS switches to have a relatively low on resistances so that capacitor voltages can settle within the clock semi-period. Therefore, a number of time constants within the half clock cycle are required for a complete charge transfer, and the following relation must hold: Chapter 3. Design 45

TON >> RON · Ci (3.14)

A frequency increase requires a reduction in the on-resistance of transfer switches, which can be obtained by increasing the transistors aspect ratios (W/L), which also requires larger drivers to maintain sharp transitions, and call for longer nonoverlapping time (due to larger gate capacitance and, hence, transition times). This increases the contributions of the switches parasitic capacitances that adds to the capacitor parasitics, and, hence, reduces the voltage gain A, increases the dynamic power losses, and reduces the efﬁciency.

3.6.2 Bootstrapping Circuit

A key design issue of the proposed circuit involves sizing the boosting capacitor adequately to bootstrap the gate of the pass transistors with the required overdrive voltage. The boosted voltage on the gate of the pass transistor is reduced because loading capacitance Cload (here we refer to MOS pass transistor capacitances and other parasitic capacitances) share a portion of the charge. The added bootstrapping circuits are not on the primary charge transfer path. However, these capacitors must be able to supply sufﬁcient voltage swing to the gate of the pass transistor and other parasitic capacitances. The boosted voltage can be expressed as

CN Vg = Vi−1 + VDD . (3.15) CN + Cload

In this design, the values of the bootstrapping capacitors CN are approximately 10 times

Cload. This ensures that corresponding voltages controlling pass transistors are within the

′ ′ required range. Furthermore, the precharge transistors (Nbi, Nbi,Pbi, Pbi) allow bootstrapping capacitors to be charged to the required voltage level. The time required for such operation (RC delay) is much less than the time required for charging transfer capacitors, because bootstrapping capacitors are small and depend mainly on the gate size of the pass Chapter 3. Design 46 transistor. Therefore, the area of precharge transistors is small as well.

3.6.3 Design Trade-Offs

To achieve satisfactory functional and performance results of the proposed design, several

Spectre simulations were performed in the 0.18-µm technology. Fine tuning of the voltage doubler components such as pass transistors and bootstrapping capacitor sizes was done to maximize efﬁciency and reduce area. Fig. 3.5 demonstrates the maximum efﬁciency of a one-stage voltage doubler as a function of the width of the pass transistors. In this design, the width of pMOS pass transistors is scaled with respect to the width of nMOS pass transistors according to the mobility ratio

µn/µp, which is about 2.5. At smaller transistors widths, the maximum efﬁciency is limited by the high on resistance of the switches. On the other hand, increasing the width of the switches gives rise to dynamic power losses due to the intrinsic parasitic capacitances of the switches.

0.85 0.8 0.75 0.7 0.65 0.6 0.55 Max Efficiency 0.5 0.45 0.4 0 20 40 60 80 100 120 140 160 180

Passtransistor width (mm)

Figure 3.5: Maximum efﬁciency versus transistor width for a voltage doubler when N =1, VDD = 1.8 V, f = 10 MHz, CT = 250 pF, α = 0.015, and β = 0.01.

Fig. 3.6 shows the maximum efficiency of a one-stage voltage doubler as a function of Chapter 3. Design 47 the bootstrapping capacitor size. As the bootstrapping capacitor size increases, the maximum efficiency increase. Further increase in the bootstrapping capacitor size will result in an increased area occupation and reduced maximum efficiency since larger drivers are required to drive these capacitors and the associated parasitics.

90 80 70 60 50 40 30 Max Efficiency 20 10 0 0.1 1 10 100 Capacitance (pF)

Figure 3.6: Bootstrapping capacitor size versus the maximum efﬁciency.

3.7 Technology Constrains

In this section, we examine issues related to design and implementation of fully integrated voltage doublers in standard CMOS process. While in off-chip implementations the critical design constraints are number of discrete components and board complexity, in on-chip realization the key cost constraint is silicon area occupation. The area allocated to integrated capacitors and switches depends on technological parameters, design speciﬁcations, and layout optimization. However, technology limitations, some of which are pointed out in this section, determine the integrated devices characteristics. Chapter 3. Design 48

3.7.1 Integrated Capacitors

In a digital CMOS technology, capacitors are made by superimposition of conductive and dielectric layers such as polysilicon, metal, or diffused layers and dielectric layers of silicon dioxide (SiO2) or silicon nitride (Si3N4). The performance of a charge pump depends critically on the properties of integrated capacitors, and in particular on parasitic capacitances (expressed by the technological parameters α and β), equivalent series resistance, and capacitance per unit area.

Metal-metal capacitors can be constructed in an interleaved configuration to maximize the capacitance utilization between available metal layers. To be more specific, capacitors constructed with metal layers have a much smaller series resistance (hence time constant) and can therefore operate at higher frequencies [29]. However, the specific capacitance of metal-metal structures in standard CMOS processes is low, because metal layers for inter- connections are separated by thick oxide layers (e.g. 1.35 µm in the considered technology) to have minimal capacitive couplings. Such constraint limits the capacitance that can be integrated in a reasonable silicon area and ultimately limits the CP driving capability. In addition, metal-metal capacitors have high parasitic coupling to the substrate with respect to the specific capacitance (up to 20%) and the parasitic capacitances αCi and βCi are particularly high when the distance between the utilized metal layers and substrate is low. MOS capacitors are constructed between a polysilicon layer and a diffused layer. These layers are separated by a thin oxide layer (e.g. 4.1 nm in the considered technology) and the capacitance per unit area is very high. The capacitance value that can be built in a specific area depends on the technological parameter Cox (the capacitance per unit area of the gate oxide) multiplied by the gate area [30]. The voltage dependence of the gate-to-channel capacitance is limited for the considered design range. The effect of the gate-to-source voltage on the gate-to-channel capacitance is shown in Fig. 3.7. The stray parasitic capacitances αCi (between doped silicon and substrate) and βCi (between the polysilicon layer and the substrate) associated with capacitor Ci are lower than other available structures. To Chapter 3. Design 49

Figure 3.7: CV curve of nMOS capacitor (Spectre simulation).

Figure 3.8: Equivalent series resistance of MOS capacitor. realize a speciﬁc capacitance value, both the length L and the width W of the polysilicon layer are scaled. As a result, the related parasitic resistance, known as equivalent series resistance, arises from both the gate sheet resistance Rg and the channel resistance Rch. The ESR of a MOS capacitor is shown in Fig. 3.8 and is given by [31]

R ESR ≈ ch + R . (3.16) 4 g

The polysilicon gate resistance can be expressed as

W R = R (3.17) g L Chapter 3. Design 50

where R is the polysilicon sheet resistance. The channel resistance can be approximated with L Rch = (3.18) µCoxW (VGS − Vth)

To this end, any large integrated capacitor is usually constructed as a set of parallel optimal units to minimize the related ESR. Given a speciﬁc capacitance area the number of required parallel devices and their geometry can be found by considering the derivative of (3.16) and setting it equal to zero. This procedure not only reduces resistive power losses, but also improves the intrinsic time constant of the MOS capacitors used in this design.

3.7.2 Bulk Biasing

Beside the higher carrier mobility, nMOS switches share the same substrate, therefore PN junctions are always reversed biased. A problem with the pMOS switches is that lower n-well potential results in a current loss injected into the substrate. The problem can be alleviated by switching the bulk of pMOS switches to the higher voltage between source and drain [6]. The voltage doubler shown in Fig. 3.9 includes an additional circuit to bias the bulk of the pMOS switches. The bulk biaser circuit is constructed with the auxiliary

′ pMOS switches PS, PS, and the capacitor CS to keep the bulk of the main pMOS switches at voltage level VS ≥ VO. This is important when a small load capacitor CL is used or a large output current is delivered, since the voltage ripple will increase according to (2.24). Also, it should be noted that minimum-sized devices are used because the biasing capacitor

CS is not connected to the load. Chapter 3. Design 51

P’S

N' P' VDD VO CS

CL RL N P 0

PS 0 0 C C'

f1 f2

Figure 3.9: 2-phases cross-coupled voltage doubler stage with dynamic bulk biasing for pMOS switches [6]. 3.8 Design of CP’s Auxiliary Circuits

3.8.1 Clock Generation Circuit

An external 50% duty-cycle reference clock cannot usually be utilized directly, but it is used as an input for a clock generator, which produces the nonoverlapping clock signals. The timing of switch transitions and the nonoverlapping slots depend on the clock generation circuit shown in Fig. 3.10. Such circuit is simple and includes only cross-coupled NAND gates, inverters, and even number of delay blocks. Each delay block is conceived by means of an inverter and a voltage-controlled RC network that consists of a transmission gate and an nMOS capacitor. Nonoverlapping time slots of the generated phases (φ1 and φ2) depend mainly on the low to high and the high to low propagation delays through the cascaded delay blocks. For this design, to ensure enough time to control the switches, a longer nonoverlapping time has been favored in order to prevent short-circuit power losses in the drivers and main pass transistors. Nonoverlapping time was also controlled via an external

DC voltage to control the resistance of the transmission gate in the RC network and the corresponding nonoverlapping time. Chapter 3. Design 52

Figure 3.10: Nonoverlapping clock generation scheme (detailed schematic is shown in Appendix A).

Figure 3.11: A CMOS inverter driver with tapering factor 4 (detailed schematic is shown in appendix A).

3.8.2 Inverter Driver Circuit

Large transfer switches and related interconnects present a large capacitive load on the clock phases path, therefore clock drivers are necessary to maintain sharp transitions and reduce short circuit losses. To increase the energy efﬁciency of a charge pump, drivers are designed so that the power dissipation in the driver chain is minimized. Designers often choose low-power tapered driver chains, which are constructed with cascaded inverter stages whose sizes increase progressively by a scaling factor S, as an example, stages are scaled with S = 4 to minimize the power delay product as shown in Fig. 3.11. In each inverter stage, pMOS transistors are scaled with respect to the nMOS transistors according to the mobility ratio [32]. As a result, the output transitions of each inverter have equal rise and fall time delay. Chapter 3. Design 53 3.9 Summary

This chapter discusses the fundamental design constraints of integrated voltage doublers. Integrated devices capabilities and associated power losses in conventional designs are addressed with focus on resistive, dynamic, and short-circuit power losses. With all these design aspects in mind, a new switch bootstrapping technique is proposed to overcome these limitations and prevent short-circuit losses, improve driving capability, and enhance the overall conversion efﬁciency. Furthermore, a charge reuse technique is applied with the result of reducing the dynamic power losses. Design and technology constrains are discussed to optimize design parameters. Chapter 4. Results

Chapter 4

Results

4.1 Introduction

This chapter presents the simulation results, prototype implementation, and experimental results of the integrated voltage doublers. First, key simulation results of the designed voltage doublers are shown and discussed at nominal process (TT), supply voltage (1.8 V) and temperature (27◦C). The clock signal applied is increased from 1 MHz to 10 MHz. This frequency range indicates a design trade-off required to meet the design speciﬁcations within a reasonable silicon area, operating at lower frequencies reduces the dynamic power losses while increasing the frequency scales up the output current that the voltage doubler can deliver. In addition, the design implementation and the test method used to characterize the design are discussed in details. Finally, the performance of the fabricated voltage doublers is presented and explained. Measured and simulated results are compared.

4.2 Simulation Results

This section presents key simulations and their results so as to provide a functional and performance reference for the fabricated chip. To verify the improvements achieved by the proposed switch bootstrapping technique and the charge reusing technique, voltage dou- 54 Chapter 4. Results 55

(a) One-stage latched voltage doubler.

(b) Two-stage latched voltage doubler.

Figure 4.1: Schematic diagrams of the conventional voltage doublers. blers with the proposed techniques (Fig. 4.2) are simulated and compared with conventional voltage doublers (Fig. 4.1). The simulated circuits are designed in 0.18-µm technology with 3.3 V devices and can be summarized as follows: Chapter 4. Results 56

(a) One-stage bootstrapped voltage doubler.

(b) Two-stage bootstrapped voltage doubler.

Figure 4.2: Schematic diagrams of the proposed voltage doublers. Chapter 4. Results 57

• One-stage latched voltage doubler (Fig. 4.1(a)).

• Two-stage latched voltage doubler (Fig. 4.1(b)).

• One-stage bootstrapped voltage doubler (Fig. 4.2(a)).

• Two-stage bootstrapped voltage doubler (Fig. 4.2(b)).

• Two-stage bootstrapped voltage doubler with charge reuse (Fig. 4.2(c)).

To have a fair comparison, all voltage doublers are designed under same speciﬁcations which include 262.5 pF stage capacitance, 1.8 V supply voltage, same clock frequency, and the same sizes of charge transfer switches. Moreover, each voltage doubler has the following building blocks as shown in Fig. 4.3:

VDD VDD VDD

f1 f1 f f V I Global Clock 1 1 Charge O O f2 Drivers f2 Clock Generation Pump f2 f2 Load

0 0 0 0

Figure 4.3: Charge pump block diagram.

• Non-overlapping clock generation circuit.

• Drivers.

• Charge pump core.

4.2.1 Steady-State

Conversion efﬁciency, output characteristics, and input power consumption are evaluated in steady-state conditions. The conversion efﬁciency is calculated as the average output power divided by the average input power including the power dissipation of the drivers and the Chapter 4. Results 58 nonoverlapping clock generation circuits. The simulated output resistance is calculated as the change in the average output voltage divided by the corresponding change in the output current.

(a) Output characteristics.

(b) Conversion efﬁciencies.

20 18 16 14 12 10 8 Input power Input power % 6 4 2 0 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 Load current (mA)

Figure 4.4: Output characteristics, conversion efﬁciencies, and input power improvement of a one stage latched and bootstrapped voltage doublers as a function of the output current IO, when N = 1, VDD = 1.8 V, f = 1 MHz, CT = 262.5 pF, α = 0.015, and β = 0.01 (Spectre simulations).

4.2.1.1 One-Stage Voltage Doublers Comparison

Performance of the one-stage bootstrapped voltage doubler (Fig. 4.2(a)) and the one-stage latched voltage doubler (Fig. 4.2(a)) is compared. Both voltage doublers are designed to achieve a voltage gain of A = 2 and to deliver an output current IO from 0 A to 2 mA. Chapter 4. Results 59

(a) Output characteristics.

(b) Conversion efﬁciencies.

Figure 4.5: Output characteristics and conversion efﬁciencies of a one stage latched and bootstrapped voltage doublers, and savings in input power due to switch bootstrapping as a function of the output current IO when N = 1, VDD = 1.8 V, f = 10 MHz, CT = 262.5 pF, α =0.015, and β =0.01 (Spectre simulations).

Fig. 4.4(a) and Fig. 4.5(a) present the simulated output characteristic at 1 MHz and 10 MHz, respectively. Simulation results show that the bootstrapped voltage doubler gives an open-circuit output voltage of 3.58 V, as compared 3.57 V provided by the latched voltage doubler because of the smaller top plate parasitic capacitance βC in the bootstrapped voltage doubler. The simulated output resistance is nearly constant (RO = 3.81 kΩ), while the output resistance of latched voltage doubler increases signiﬁcantly (because of the surge in on resistance of the pass transistors) when the load current is high enough to reduce the value of ∆V , with the output voltage dropping to zero when ∆V

4.2.1.2 Two-Stage Voltage Doublers Comparison

Two-stage bootstrapped voltage doubler (Fig. 4.2(b)) and two-stage latched voltage doubler (Fig. 4.1(b)) are designed and simulated. Both voltage doublers are designed to have a voltage gain of A = 3 and deliver an output current IO from0 A to2mA.Fig. 4.6(a)andFig.

4.7(a) compare the variation of the output voltage as function of the load current IO for the two voltage doublers. The maximum output voltage is 3.59 V for the bootstrapped voltage doubler and 3.54 V for the latched voltage doubler (indeed, the parasitic capacitances of the bootstrapped voltage doubler is slightly smaller because the gate capacitance of the pass transistors are not connected to internal nodes on the charge transfer path). It is also seen that the bootstrapped voltage doubler is able to guarantee a constant value of RO (∼ 8.51 kΩ at f = 1 MHz, and ∼ 831 Ω at f = 10 MHz) for the whole output current range, while the output resistance of the conventional voltage doubler significantly increases for higher output currents as a consequence of the increased RON of transfer switches. The efficiency as a function of the load current is shown in Fig. 4.6(b) and Fig. 4.7(b) for both voltage doublers at 1 MHz and 10 MHz, respectively. The maximum power effi- Chapter 4. Results 61

(a) Output characteristics.

(b) Conversion efﬁciencies.

Figure 4.6: Output characteristics and conversion efﬁciencies of a two stage latched and bootstrapped voltage doublers, and savings in input power due to switch bootstrapping as a function of the output current IO when N = 1, VDD = 1.8 V, f = 1 MHz, CT = 525 pF, α =0.015, and β =0.01 (Spectre simulations).

ciency of the bootstrapped voltage doubler is about 77.36% at IO = 80 µA and f = 1 MHz and 76.47% at IO = 0.8 mA and f = 10 MHz, while the maximum efﬁciency of the latched voltage doubler is 77.21% when IO = 80 µA at f = 1 MHz and 75.57% when IO = 0.7 mA at f = 10 MHz. For higher values of IO, the proposed solution guarantees a better energy efﬁciency. At low IO the input power of the proposed circuit is reduced as well, because short-circuit losses are absent as shown in Fig. 4.6(c). Chapter 4. Results 62

(a) Output characteristics.

(b) Conversion efﬁciencies.

Figure 4.7: Output characteristics and conversion efﬁciencies of a two stage latched and bootstrapped voltage doublers, and savings in input power due to switch bootstrapping as a function of the output current IO when N = 1, VDD = 1.8 V, f = 10 MHz, CT = 525 pF, α =0.015, and β =0.01 (Spectre simulations).

4.2.1.3 Voltage Doubler with Charge Reuse

To evaluate the impact of charge reuse technique, a two-stage bootstrapped voltage doubler with charge reuse was designed as shown in Fig. 4.2(c) and compared to the two stage voltage doubler in Fig. 4.2(b). The output characteristic and efﬁciency comparison for different load conditions are shown in Fig. 4.8 and Fig. 4.9 at 1 MHz and 10 MHz, respectively. The simulated output characteristics for both voltage doublers are the same, because the f · CT product and the number of stages are not changed. The simulated conversion efﬁciency of the two-stage bootstrapped voltage doubler and Chapter 4. Results 63

(a) Output characteristics.

(b) Conversion efﬁciencies.

Figure 4.8: Output characteristics and conversion efficiencies of a two stage bootstrapped voltage doubler and bootstrapped voltage doubler with charge reuse as a function of the output current IO, when N = 2, VDD = 1.8 V, CT = 525 pF, f = 1 MHz, α = 0.015, and β =0.01 (Spectre simulation). of the two-stage bootstrapped voltage doubler with charge reuse as a function of the load current is shown in and Fig. 4.8(b) and Fig. 4.9(b) for both voltage doublers at 1 MHz and 10 MHz, respectively. The efficiency of the bootstrapped voltage doubler with charge reuse is improved at low and moderate load currents. The reduction of load-independent losses for the voltage doubler with charge reuse is about 30%. Charge reusing improves the overall conversion efficiency substantially because a significant portion of the charges normally wasted through parasitic capacitances is reused. The maximum efficiency of the charge reuse voltage doubler is 80.77% at f = 1 MHz and 79.83% at f = 10 MHz. However, the overall reduction in load-independent losses is less than the theoretical 50% reduction, because there are diminishing effects caused by additional power losses from the charge reuse circuit. The short-circuit current occurs in the charge reuse path and the small amount of parasitic capacitance added by the equalization switch contribute to the overall Chapter 4. Results 64

(a) Output characteristics.

(b) Conversion efﬁciencies.

Figure 4.9: Output characteristics and conversion efﬁciencies of a two bootstrapped voltage doubler and bootstrapped voltage doubler with charge reuse as a function of the output current IO, when N = 2, VDD = 1.8 V, CT = 525 pF, f = 10 MHz, α =0.015, and β =0.01 (Spectre simulation). current consumption.

4.2.2 Transient Analysis Results

4.2.2.1 Rise Time

The start-up time of the proposed voltage doubler and the latched voltage doubler are presented with the transient analysis in Fig. 4.10, which shows the output voltage as a function of time. The start-up time is deﬁned as the time taken to boost the output terminal up to

90% of the target voltage and depends on output resistance and total capacitance of the CP, and the load capacitance. The start-up time is evaluated by setting the initial condition of all capacitors to 0 V. The comparison is made with a target voltage of 5.4 V, a supply voltage of 1.8 V, and a 1 nF capacitive load. A signiﬁcant advantage of the proposed voltage doubler is the faster rise time of the output voltage at the start-up, the simulated start-up for the Chapter 4. Results 65

Figure 4.10: Start-up transient with 1 nF capacitive load (two-stage charge pump, VDD = 1.8 V, and f = 10 MHz) (Spectre simulation). two-stage bootstrapped voltage doubler is 2.26 µs against 4.26 µs for the two-stage latched voltage doubler, i.e. the rise time of the bootstrapped doubler is reduced by 47% compared to the conventional one. The improvement in start-up time results from the smaller on resistance of the bootstrapped switches, because the switches have gate voltage swings varying from 0 to VDD.

Figure 4.11: Energy consumption versus output current (IO) of a latched and bootstrapped voltage doublers with 1nF capacitive load (two-stage charge pump, VDD = 1.8 V, f = 1 MHz) (Spectre simulation).

Energy consumption as a function of the output current IO for the proposed and the conventional voltage doublers is shown in Fig. 4.11. Here, the energy consumption is calculated as the integral of the power consumed by the charge pump during the start-up Chapter 4. Results 66 time, i.e. when capacitors are discharged and the voltage increases from 0 V to 90% of the target voltage. The energy consumption of the bootstrapped voltage doubler is independent of the load current because a given voltage is applied between the gate and source terminals of the switches, thus making their on resistance constant and the corresponding start-up time faster. Switch bootstrapping not only improves steady-state performance of voltage doublers, it also enhances their dynamic behaviour by reducing the start-up time which signiﬁcantly contribute in reducing the related energy consumption.

Figure 4.12: Simulated waveforms of the current drawn from the power supply of the proposed charge reuse bootstrapped charge pump and the bootstrapped charge pump (two- stage charge pump, VDD = 1.8 V, f = 10 MHz) (Spectre simulation).

4.2.2.2 Charge Reuse

Simulated supply current waveforms of the charge reuse bootstrapped voltage doubler and the conventional voltage doubler are shown in Fig. 4.12. A current saving is achieved by charge reuse voltage doubler, where the peak current level of the charge reuse voltage doubler is about 19 mA while it is about 27 mA for the conventional voltage doubler (i.e. here we refer to the bootstrapped voltage doubler shown in Fig. 4.2(b)). Furthermore, the time Chapter 4. Results 67

Table 4.1: Devices available in the fabrication technology. Symbol Device name Description

1.8 V nMOS transistor Minimum feature l = 0.18 µm, nominal threshold voltage Vt ≈ 0.53 V

1.8 V pMOS transistor Minimum feature l = 0.18 µm, nominal threshold voltage Vt ≈ -0.53

3.3 V nMOS transistor Minimum feature l = 0.35 µm, nominal threshold voltage Vt ≈ 0.59 V

3.3 V pMOS transistor Minimum feature l = 0.3 µm, nominal threshold voltage Vt ≈ -0.71 V

2 3.3 V nMOS capacitor Cox ≈ 5.4 fF/µm duration of the current peak is smaller in the charge reuse current waveform. As a result, the area under the current waveform which represents the average current consumption is reduced as well, therefore reducing the overall current drawn from the power supply.

4.3 Prototype Implementation

4.3.1 Fabrication Technology

The voltage doublers are designed and fabricated in a TSMC 0.18-µm CMOS process (nominal supplyvoltages are 1.8 and 3.3 volts), with a single polysilicon and 6-metal layers, including MIM capacitor and deep n-well layer options. The core area is 1.5 mm × 0.66 mm=1mm2, and the total area including bonding pads is 1.5 mm × 1mm=1.5mm2. The chip area is dominated by the area occupied by integrated capacitors. Since the circuit’s target is to generate an output voltage higher than the supply voltage, high voltage devices are needed. The technology offers a thick oxide layer that increases the breakdown voltage limit of the transistors making this technology suitable to the design. Devices used in the design of the voltage doublers are described in Table 4.1. Chapter 4. Results 68

Figure 4.13: Diagram of the analog design ﬂow used in the design (adapted from CMC).

4.3.2 Tools and Design Flow

Mathematical functional verification is performed with Mathematica software at an early stage of the design as explained in the analysis in Chapter 2. To achieve satisfactory functional and performance results, transistor level schematics are created in Cadence Com- poser and Spectre circuit simulator is used to simulate and optimize the design. The chip layout is drafted using Cadence Virtuoso. After completing the design of the layout, Men- tor’s Calibre tool is used in coordination with the layout editor for physical verifications purposes. Design rule check (DRC) is performed to avoid violations against all design rules. Layout Versus Schematic (LVS) is carried out to ensure that the netlists created by the schematic match the extracted netlist from the layout. To ensure success of the design Chapter 4. Results 69 process, the analog design flow shown in Fig. 4.13 is followed.

4.3.3 Test Setup Realization

Test issues including packaging, test ﬁxture, and equipment setup are considered during the design in order to characterize and measure the integrated voltage doublers parameters such as voltage gain, output resistance, current consumption, and energy efﬁciency.

Figure 4.14: Photograph of the 24-pin CFP package containing the fabricated chip.

4.3.3.1 Package

Since the designed circuits need to be connected to test equipment by placing the packaged chip on a test board, the decision on packaging has a strong impact on the design performance, testability, and board ﬁxturing. The die was packaged in 24-pin CFP (Ceramic Flat

Package) from Spectrum Semiconductor, Inc as shown in Fig. 4.14. The packaging choice was considered during the design process based on the number of pins that are required for the designed circuits, the area allocated for the die, and the slightly better package parasitics (i.e. about 2.5 nH) compared to the 44-pin CFP alternative which has the drawback of longer leads, larger size, and therefore worse parasitics. A technical drawing of the used Chapter 4. Results 70 package is shown in Appendix A in Fig. A.6.

Figure 4.15: Layout of the designed test board.

4.3.3.2 Test Fixture

After the selection of the appropriate package, a test ﬁxture was developed to connect the packaged chips to the test equipment. The test board was designed using EAGLE PCB-Design software considering footprints of package and off-chip components to ensure the design testability and the input and output requirements for the designed circuits (Fig. 4.15). A one layer FR4 dielectric test board with a minimum 1.34 mil trace was fabricated for the device under test. To maintain constant supply voltages, all input voltage supplies were heavily decoupled by placing large through hole capacitors (e.g. 1 µF). Moreover, 1 nF ceramic output capacitors were added to the board to create load capacitances for the designed voltage doublers. The 24-pin CFP packaged device was interfaced to SMA connectors by soldering the connectors on the test board in order to provide clock signals for the circuits. For mechanical support purpose, the packaged chip was placed in a central recess in the test board and clamped into place by using a translucent plastic clamp. Chapter 4. Results 71

Figure 4.16: Block diagram of the experimental setup.

4.3.3.3 Equipment Setup

A test setup as shown in Fig. 4.16 was used. Square wave inputs were generated using a BK Precision 4040A function generator to provide the clock signal to the chip. The output voltage of each voltage doubler was captured using a Tektronix DPO7104 digital oscilloscope, capable of capturing waveforms measurements (i.e. amplitude, rise time, mean value, etc.). An Agilent E3630A DC power supply was used to provide a reference voltage for the clock generation circuits in order to control the nonoverlapping time. A Keithley 2602 source meter was utilized because it provides both measuring and sourcing capabilities in DC with very high accuracy and has a Test Script Processor (TSP). Channel A was conﬁgured as a DC input voltage source and a current meter, while channel B was conﬁgured as a DC output current source and a voltage meter. To conduct tests, a host PC (controller), was programmed to send sequences of commands to the Keithley source meter, which, in turn, executed the commands and returned the captured data to the host

PC.

4.3.4 Layout Considerations

Layout is very important in high performance charge pumps. The analog (voltage doublers core) and digital (clock generation and drivers) power supplies were connected to their Chapter 4. Results 72

Figure 4.17: Chip design layout. own separate pads circuitry with wide metal lines. Empty areas were ﬁlled with nMOS capacitors and connected to the closest power supply to act as decoupling capacitors. The large MOS switches were laid out in an interdigitated fashion with multiple contacts to reduce parasitic capacitances and resistances. To prevent latch-up, double guard rings were placed surrounding each MOS switch. Fig. 4.17 shows the layout of the designed circuits and their pads arrangement which can be summarized as follows:

• Two-stage bootstrapped voltage doubler without bulk biasing (circuit 1).

• One-stage bootstrapped voltage doubler (circuit 2).

• Two-stage bootstrapped voltage doubler (circuit 3).

• Two-stage bootstrapped voltage doubler with charge reuse (circuit 4).

• One-stage latched voltage doubler(circuit 5).

• Two-stage latched voltage doubler (circuit 6).

Circuit 1 to circuit 6 power supplies were fed through pads VDD1 to VDD6, clock signals were fed through pads CLK1 to CLK6, and output voltages were connected to pads VO1 Chapter 4. Results 73

to VO6, each corresponding to one circuit. Pads CKP156 and CKP234 were connected as power supplies for the digital blocks of circuit 1, circuit 5, and circuit 6, and of circuit

2, circuit 3, and circuit 4. Moreover, V REF156 and V REF234 were used as a reference voltage for the clock generation blocks of circuit 1, circuit 5, and circuit 6, and of circuit 2, circuit 3, and circuit 4.

Figure 4.18: Microphotograph of the design; the chip size is 1 mm × 1.5 mm.

4.4 Experimental Results

Microphotograph of the fabricated voltage doubler is shown in Fig. 4.18. An enlarged microphotograph of the different building blocks in the one-stage bootstrapped voltage doubler (circuit 2 in Fig. 4.17) is also shown in Fig. 4.19. To validate the design and simulation results, the fabricated voltage doublers were characterized and the measured results were compared with the simulation results. All measurements were carried out with an external load capacitor of 1 nF and a clock frequency of about 1 MHz. The measured output characteristic of the two-stage bootstrapped voltage doubler at a Chapter 4. Results 74

Figure 4.19: A microphotograph showing circuits designed in a one stage bootstrapped voltage doubler.

supply voltage of VDD = 1.8 V is shown in Fig. 4.20(a). The measured output resistance is 7.49 kΩ, which is compared with a calculated value of 7.62 kΩ. The experimental results show that the two-stage bootstrapped voltage doubler gives an open-circuit output voltage of 5.395 V, very close to the output voltage of 5.388 V provided by simulation results. Moreover, the output voltage shows a linear decline with the load current because of the almost constant output resistance. The measured efﬁciency as a function of the load current is shown in Fig. 4.20(b), and as expected from simulations the maximum efﬁciency is 78.4% at IO = 90 µA. Fig. 4.21(a) shows the measured output characteristics for the two-stage bootstrapped voltage doubler with charge reuse which is equivalent to the output characteristics of the two-stage bootstrapped doubler. The open circuit output voltage at a supply voltage of

VDD = 1.8 V is 3.593 V. The measured output resistance for f = 1 MHz is about 7.46 kΩ. The measured efﬁciency is shown in Fig. 4.21(b), the maximum measured efﬁciency is 80.01% at IO = 80 µA. Improvement in input power consumption of the charge reuse bootstrapped voltage doubler with respect to the bootstrapped voltage doubler is shown in Chapter 4. Results 75

6 Simulated 5 Measured 4

(V) 3 O V 2

0 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Load current (mA)

(a) Output characteristic.

90 80 70 60 50 40

Efficiency Simulated 30 20 Measured 10 0 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Load current (mA)

(b) Efﬁciency.

Figure 4.20: Measured and simulated output characteristic and conversion efﬁciency of a fully integrated two stage bootstrapped voltage doubler as a function of the output current IO, when VDD = 1.8 V, f = 1 MHz.

Fig. 4.22. The maximum measured power savings are found to be 14% at IO = 0 A. The difference between the measured power savings and the simulated ones (i.e. a maximum power savings of 30%) is due to the short nonoverlapping time, which, in turn, affects the time required to equalize the voltages of the parasitic capacitances, and therefore results in a larger average power consumption.

On the other hand, measured output characteristics and conversion efﬁciency of the two-stage latched voltage doubler as a function of the output current IO are shown in Fig.

4.23 at a supply voltage of VDD = 1.8 V.Fig. 4.23(a) shows the output voltage as a function of the load current. The maximum output voltage is 5.372 V, the output resistance of the latched voltage doubler increases nonlinearly because of the increase in on resistance of the switches when IO is high enough to reduce the value of ∆V , with the output voltage Chapter 4. Results 76

6 Measured 5 Simulated 4

(V) 3 O V 2

0 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Load current (mA)

(a) Output characteristic.

90 80 Simulated 70 Measured 60 50 40 Efficiency 30 20 10 0 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Load current (mA)

(b) Efﬁciency.

Figure 4.21: Measured and simulated output characteristic and conversion efﬁciency of a fully integrated two stage bootstrapped voltage doubler with charge reuse as a function of the output current IO, when VDD = 1.8 V, f = 1 MHz.

dropping to zero at IOmax = 230 µA, the measured efficiency is shown in Fig. 4.23(b). The maximum measured efficiency is 77.9% at IO = 100 µA. The measured efficiency at high load current is reduced because of the increased on resistance that influences the output resistance. The measured output characteristics of the one-stage bootstrapped voltage doubler at a supply voltage VDD = 1.8 V is shown in Fig. 4.24(a). The measured output resistance is 3.67 kΩ, which is compared with a calculated value of 3.81 kΩ. The experimental results show that the one-stage bootstrapped voltage doubler gives an output voltage 3.595 V, as compared to an output voltage of 3.579 V provided by simulation results. The output voltage shows a linear decay with any load current because of the nearly constant output resistance. The measured efficiency as a function of the load current is shown in Fig. Chapter 4. Results 77

Measured % 25 Simulated 20

5 Input powerimprovement

0 0 0.0001 0.0002 0.0003 0.0004 Loadcurrent (A)

Figure 4.22: Measured and simulated improvement in input power consumption of the two-stages bootstrapped voltage doubler with charge reuse with respect to the two-stages bootstrapped voltage doubler as a function of the output current IO, when VDD = 1.8 V, f = 1 MHz.

4.24(b). The maximum efficiency is 81.76% at IO = 100 µA. Fig. 4.25 shows measured output characteristics and conversion efficiency of the one- stage latched voltage doubler at a supply voltage VDD = 1.8 V. The measured open-circuit output voltage is 3.584 V. The output voltage of the latched voltage doubler falls sharply and becomes 0 V at high load current IOmax = 240 µA because ∆V is reduced progressively due to the higher output resistance RO. The maximum measured efficiency is 81.62%, the efficiency is reduced at high currents because of the increased switches on resistance. As can be seen, there is a good agreement between the predicted and measured results. However, an additional ripple component due to capacitive coupling from the clocks causes inaccuracies in the measured output voltage. Furthermore, parasitic capacitances vary from chip to chip and in general their value cannot be predicted to a sufficiently high accuracy because of their nonlinear voltage dependence. Short-circuit power consumption as a function of the output current is also examined in the one stage voltage doublers (Fig. 4.26) and the two stage voltage doublers (Fig. 4.27).

Under no-load condition, the maximum measured improvement in the bootstrapped voltage doubler compared to the latched voltage doubler is 6% for the one stage and 7.5% for the two stage because short-circuit losses are prevented. The improvement in the two stage voltage doubler is higher because short-circuit currents are prevented in four CMOS pairs Chapter 4. Results 78

7 Simulated 6 Measured 5

4 (V) O

V 3

0 0 0.05 0.1 0.15 0.2 Load current (mA)

(a) Output characteristics.

90 80 70 60 50 40 Efficiency 30 Simulated 20 Measured 10 0 0 0.05 0.1 0.15 0.2 0.25 Load current (mA)

(b) Efﬁciency.

Figure 4.23: Measured and simulated output characteristics and conversion efﬁciency of a fully integrated two stage cross-coupled (latched) voltage doubler as a function of the output current IO, when VDD = 1.8 V, f = 1 MHz. instead of two CMOS pairs in the ﬁrst stage. At higher output currents, the overdrive voltage decreases (i.e. the voltage rise ∆V is lower), and therefore the power losses due to short-circuit currents becomes negligible.

Fig. 4.28 shows the measured load-independent power losses (PLI ) as a function of the input supply voltage for the two-stage latched voltage doubler, the two stage bootstrapped voltage doubler, and the two stage bootstrapped voltage doubler with charge reuse. The load-independent power losses are the total input power at no-load condition, and they are dominated by dynamic power losses and short-circuit power losses especially at high switching frequencies (10 MHz and higher). As expressed in (3.10), it is obvious that short-circuit power dissipation for the latched voltage doubler will depend on the voltage rise ∆V , which, in turn, scales with the in- Chapter 4. Results 79

4 3.5 3 2.5

(V) 2 O V 1.5 Simulated

1 Measured 0.5 0 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Loadcurrent (mA)

(a) Output characteristic.

90 80 70 60 50 (V)

O Simulated

V 40 30 Measured 20 10 0 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Loadcurrent (mA)

(b) Efﬁciency.

Figure 4.24: Measured and simulated output characteristic and conversion efficiency of a fully integrated one stage bootstrapped voltage doubler as a function of the output current IO, when VDD = 1.8 V, f = 1 MHz. put supply voltage. Due to the employment of the proposed bootstrapping technique, load-independent losses see noticeable improvements, because short-circuit currents are prevented. In particular, a maximum load-independent losses reduction of 11.53% is measured at 2.2 V. The bootstrapped voltage doubler with charge reuse continues to contribute a clear reduction in load-dependent losses. In addition to the short-circuit currents block- age, charge reuse reduces the dynamic power losses of the voltage doubler and improves the overall power efficiency. The measured maximum efficiencies as a function of the clock frequency of the two- stage latched voltage doubler, the two stage bootstrapped voltage doubler, and the two-stage bootstrapped voltage doubler with charge reuse are shown in Fig. 4.29. At lower frequencies (i.e. slow-switching conditions), it is obvious that the maximum power efficiency Chapter 4. Results 80

4 Simulated 3.5 Measured 3 2.5

(V) 2 O V 1.5 1 0.5 0 0 0.05 0.1 0.15 0.2 0.25 Load current (mA)

(a) Output characteristics.

90 80 70 60 50 40 Efficiency 30 Simulated 20 Measured 10 0 0 0.05 0.1 0.15 0.2 0.25 Load current (mA)

(b) Efﬁciency.

Figure 4.25: Measured and simulated output characteristics and conversion efficiency of a fully integrated one stage cross-coupled (latched) voltage doubler as a function of the output current IO, when VDD = 1.8 V, f = 1 MHz. of the bootstrapped voltage doubler is higher than the latched voltage doubler because short-circuit power losses are prevented and the parasitic capacitances are lower. The bootstrapped voltage with charge reuse has the best efficiency because of power saving due to charge reuse. At faster clock frequencies, the output resistance RO of the voltage doublers increases when the resistances associated with switches, capacitors and interconnect dominate and charges are not fully transferred due to insufficient timing while the switches are turned on. Fig. 4.30 shows the measured output resistance of the two stage bootstrapped voltage doubler as a function of the frequency. The measured results are in good agreement with the model proposed recently in [7]. Overall, as can be seen, the provided experimental results successfully verify the effectiveness of the proposed techniques and there is a good agreement between the predicted Chapter 4. Results 81

Figure 4.26: Measured and simulated improvement in input power consumption of the one stage bootstrapped voltage doubler with respect to the one stage latched voltage doubler as a function of the output current IO, when VDD = 1.8 V, f = 1 MHz.

Figure 4.27: Measured and simulated improvement in input power consumption of the two stages bootstrapped voltage doubler with respect to the two stages latched voltage doubler as a function of the output current IO, when VDD = 1.8 V, f = 1 MHz. simulated results and the measured results.

4.5 Discussion of the Results and Design Considerations

Switch bootstrapping improves the driving capability of voltage doublers and, at the same time, removes short-circuit losses. Bootstrapped voltage doublers occupy comparable silicon area (overhead < 2%) to that of latched voltage doublers. Each bootstrapping capacitor is about 1 pF. This value is a compromise between a large voltage swing (≤ VDD) on the gate of the MOS switch and silicon area. The measured output voltages of the bootstrapped Chapter 4. Results 82

120.00

110.00 Charge reuse 100.00 Bootstrapped 90.00 Latched

( 80.00

LI P 70.00 60.00 50.00 40.00 1.6 1.7 1.8 1.9 2 2.1 2.2 Input Voltage (V)

Figure 4.28: Measured load independent power losses versus input supply voltage of two- stage voltage doublers bootstrapped, latched, and bootstrapped with charge reuse at f =1 MHz. voltage doublers show a linear decay for any output current indicating that the output resistance is constant because each MOS switch has a given gate voltage swing, and therefore a constant on resistance. This results in higher efficiency when the circuit needs to deliver a higher output current, in contrast to the reduced driving capability of the latched voltage doubler, which impacts the efficiency at high output currents, especially for low voltage applications. In addition, at low output currents unwanted short-circuit losses during switch events reduce the efficiency and the output voltage of the latched voltage doubler, while the efficiency of bootstrapped voltage doubler is improved because the timing of switch events can be controlled, and therefore short-circuit currents can be prevented. The proposed bootstrapping technique is suitable for building reliable voltage doublers with high efficiency at wide range of input voltages and output currents. The charge reuse technique effectively decreases the dynamic power losses and the overall power consumption in the bootstrapped voltage doubler, especially for voltage doublers meant to operate at higher switching frequencies. Dynamic power losses due to charges wasted through parasitic capacitances can be reduced by means of a simple additional circuit and control signals easily generated from the nonoverlapping phases with no perceptible performance degradation for the voltage doubler operation. Since the charge Chapter 4. Results 83

85 Charge reuse Bootstrapped 80 Latched 75

Maxefficiency % 60

50 0 2 4 6 8 10 12 14 16 18 20 f (MHz)

Figure 4.29: Measured maximum efﬁciencies versus frequency of two stage voltage doublers latched, bootstrapped, and bootstrapped with charge reuse at a supply voltage VDD = 1.8 V. reuse path has a ﬁnite resistance and the charge reuse circuit consumes power, the maximum power savings will be limited by the the duration of the nonoverlapping time. As an example, at VDD = 1.8 V and f = 1 MHz, power savings are reduced to 14%. The trade- off between charge reuse circuit complexity, and hence associated area, and the amount of power savings should be carefully considered during the design. The charge reuse technique can be applied to voltage doublers and to any double CP with a small area overhead added by the charge reuse circuit (overhead < 0.3%). Chapter 4. Results 84

8000

7000 Calculation

6000 Measurement

5000

W () 4000 O R 3000

2000

1000

0 0 2 4 6 8 10 12 14 16 18 20 f (MHz)

Figure 4.30: Measured and calculated [7] output resistance of the two stage bootstrapped voltage doublers at a supply voltage VDD = 1.8 V with parasitic resistance of 120 Ω. Chapter 5. Conclusion and Future Work

Chapter 5

Conclusion and Future Work

5.1 Conclusion

This dissertation presented techniques to improve performance and conversion efficiency of integrated charge pumps. Switch bootstrapping reduces short-circuit power losses, improves driving capability, and enhances the overall conversion efficiency. The proposed technique uses conventional nonoverlapping phases and is suitable for building high-efficiency charge pumps without high voltage stress across the MOS switches, thereby it can be scaled to any number of stages limited only by CMOS process constrains. The application of charge reuse is shown to be highly effective in reducing dynamic power losses and improving the overall conversion efficiency. Charge reuse can be applied to bootstrapped voltage doublers and to any properly driven double charge pumps. A significant portion of the charges normally wasted through parasitic capacitances can be reused by means of small additional switches and control signals easily generated from the nonoverlapping phases used in high-efficiency bootstrapped charge pumps. A prototype of the voltage doublers with the proposed techniques was fabricated in a 0.18-µm CMOS process. The effectiveness of the proposed bootstrapping and charge reusing techniques is demonstrated through experimental results. The simulation and experimental results are in good agreement with

85 Chapter 5. Conclusion and Future Work 86

Table 5.1: Modular CP Design.

Terminal Heap Fibonacci Exponential

1 VDD Vi−1 Vi−1

2 Vi Vi Vi

3 Vi−1 Vi−2 Vi−1 the analysis. The speciﬁc research contributions of this work include the following:

1. Determination of an analysis method suitable for any integrated charge pump.

2. Modelling, optimizing, and comparing the output resistance and the conversion efﬁ-

ciency of different charge pump circuits.

3. Development of a switch bootstrapping technique for voltage doublers. The technique improves driving capability, prevents short-circuit losses, and enables efﬁcient operation at low supply voltages.

4. Application of the charge reuse concept to effectively reduce the dynamic power losses of integrated double charge pumps.

5. Prototype implementationin a 0.18-µm CMOS process and discussion of experimental results.

5.2 Future Work

An interesting development of this research will involve using ideas described in this thesis to design other double charge pumps. The proposed bootstrapping techniques can be Chapter 5. Conclusion and Future Work 87

Figure 5.1: Proposed bootstrapping technique in a modular CP stage used to build generic double CPs (e.g. doubler-based CP, heap CP, Fibonacci CP, and exponential CP). applied with similar considerations to the construction of the modular stage in Fig. 5.1. If the terminals are connected as reported in Table 5.1 (starting values being Vi=−1 = Vi=0 =

VDD), a cascade connection of stages gives rise to a double heap charge pump [33], to a double Fibonacci charge pump [12], or to a double exponential charge pump [15]. The gate voltage swings and the timing of the switch transitions are controlled as in the case of the voltage doubler (preventing short-circuit losses and improving driving capability).

The resulting charge pumps require only the conventional nonoverlapping phases, do not have extra parasitic capacitances affecting the efﬁciency, and can be scaled to any number of stages. The extension of the concept to a modular stage for generating any two-phase double charge pump is shown in Fig. 5.2. As an example, the double Cockcroft-Walton con-

ﬁguration (double ladder charge pump) is obtained with node 1 connected to Vi−1, node 2 connected to Vi, node 3 connected to Vi−1, and node 4 connected to Vi−2 (the starting values being Vi=−1 = 0, Vi=0 = VDD). This structure can operate without exceeding breakdown Chapter 5. Conclusion and Future Work 88

Figure 5.2: Proposed bootstrapping technique in a modular CP stage used to build any two-phase double CP voltages of both transfer capacitors and MOS switches [34]. In general, this stage is suitable for building adaptive charge pumps (i.e. charge pumps that change the conversion ratio under different input voltages and load currents to maintain high power efﬁciency). Future developments of the adaptive charge pump could also include automatic reconﬁguration of the required voltage conversion ratio by means of adaptive control circuitry. Appendix A. Testing

Appendix A

Testing

A.1 View of the Full Chip and the Designed Circuits

Figure A.1: Top view of the designed chip schematic.

89 Appendix A. Testing 90

Table A.1: Signal types and description. Signal Type Description VDD1 input/output input supply voltage for circuit 1 (VDD,1V,2V) VDD2 input/output input supply voltage for circuit 2 (VDD,1V,2V) VDD3 input/output input supply voltage for circuit 3 (VDD,1V,2V) VDD4 input/output input supply voltage for circuit 4 (VDD,1V,2V) VDD5 input/output input supply voltage for circuit 5 (VDD,1V,2V) VDD6 input/output input supply voltage for circuit 6 (VDD,1V,2V) CLK1 input circuit 1 input clock (freq, 1MHz, 20MHz), peak-to-peak = VDD CLK2 input circuit 2 input clock (freq, 1MHz, 20MHz), peak-to-peak = VDD CLK3 input circuit 3 input clock (freq, 1MHz, 20MHz), peak-to-peak = VDD CLK4 input circuit 4 input clock (freq, 1MHz, 20MHz), peak-to-peak = VDD CLK5 input circuit 5 input clock (freq, 1MHz, 20MHz), peak-to-peak = VDD CLK6 input circuit 6 input clock (freq, 1MHz, 20MHz), peak-to-peak = VDD

VO1 output circuit 1 output voltage, connected to the load

VO2 output circuit 2 output voltage, connected to the load

VO3 output circuit 3 output voltage, connected to the load

VO4 output circuit 4 output voltage, connected to the load

VO5 output circuit 5 output voltage, connected to the load

VO6 output circuit 6 output voltage, connected to the load V ref156 input/output clock reference (Vref, 0.8V, 2.5V); circuit 1, circuit 5, and circuit 6 V ref234 input/output clock reference (Vref, 0.8V, 2.5V); circuit 2, circuit 3, and circuit 4 CP 156 input/output clock generation supply voltage (VDD); circuit 1, circuit 5, and circuit 6 CP 234 input/output clock generation supply voltage (VDD); circuit 2, circuit 3, and circuit 4 Appendix A. Testing 91

Figure A.2: Block view of the six circuits. Appendix A. Testing 92 A.2 Circuits and Pads Arrangement for the Design

Figure A.3: Chip layout and pads arrangement. Appendix A. Testing 93 A.3 Bonding Diagram for the Design

Figure A.4: Bonding diagram for the design. Appendix A. Testing 94 A.4 TestBoard

Figure A.5: Photograph of the fabricated test board. Appendix A. Testing 95

A.4.1 Package Layout

Figure A.6: Technical drawing of the 24-pin CFP package (Spectrum Semiconductor, Inc).

A.4.2 Adding Off-Chip Passive Components

Through hole capacitors and resistors can be added to the board to create input and output ﬁlters. For instance, a parallel output capacitor and resistor can be added between (vo1 and gnd) to test for the output characteristics at certain load condition. Appendix A. Testing 96

A.4.3 Clamping the Package to the Fixture

The clamp is fastened to the board with 4-40 machine screws. In order to ensure even pressure on the IC package, care should be exercised when tightening the nuts on the clamp. Appendix A. Testing 97 A.5 Schematic View of Circuits

Figure A.7: Circuit 1 schematic (2stMVD). Appendix A. Testing 98

Figure A.8: Circuit 2 schematic (1stMVD). Appendix A. Testing 99

Figure A.9: Circuit 3 schematic (2stMVDDBB). Appendix A. Testing 100

Figure A.10: Circuit 4 schematic (2stCSDBB). Appendix A. Testing 101

Figure A.11: Circuit 5 schematic (1stCCVD). Appendix A. Testing 102

Figure A.12: Circuit 6 schematic (2stCCVD). Appendix A. Testing 103

Figure A.13: Clock generation circuit schematic. Appendix B. Published Papers

Appendix B

Published Papers

B.1 Refereed Publications

• Younis Allasasmeh and Stefano Gregori, “Switch bootstrapping technique for voltage doublers and double charge pumps,” in Proc. IEEE Int. Symp. Circuits Syst.

(ISCAS), 2011, pp. 494-497.

• Jingqi Liu, Younis Allasasmeh, and Stefano Gregori, “Fully-integrated charge pumps without oxide breakdown limitation,” in Proc. IEEE Canadian Conf. Electrical and Computer Engineering (CCECE), 2011, pp. 1474-1477.

• Younis Allasasmeh and Stefano Gregori, “Charge reusing in switched-capacitor voltage multipliers with reduced dynamic losses,” in Proc. IEEE Midwest Symp. Cir- cuits Syst. (MWSCAS), 2010, pp.1169-1172.

• Younis Allasasmeh and Stefano Gregori, “A performance comparison of Dickson

and Fibonacci charge pumps,” in Proc. European Conf. Circuit Theory Design (EC- CTD), 2009, pp. 89-92.

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