EECS 105 Fall 2003, Lecture 12
Lecture 12: MOS Transistor Models
Prof. Niknejad
Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Lecture Outline
MOS Transistors (4.3 – 4.6) – I-V curve (Square-Law Model) – Small Signal Model (Linear Model)
Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
Observed Behavior: ID-VGS
IDS
IDS VDS
VGS
VGS VT Current zero for negative gate voltage Current in transistor is very low until the gate voltage crosses the threshold voltage of device (same threshold voltage as MOS capacitor) Current increases rapidly at first and then it finally reaches a point where it simply increases linearly
Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
Observed Behavior: ID-VDS
= IkDS / VGS 4V I non-linear resistor region DS “constant” current VDS
V = 3V resistor region GS VGS
= VGS 2V
VDS
For low values of drain voltage, the device is like a resistor
As the voltage is increases, the resistance behaves non-linearly and the rate of increase of current slows Eventually the current stops growing and remains essentially constant (current source)
Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad “Linear” Region Current
> VVGS Tn G S ≈ D VDS 100mV y p+ n+ n+ x p-type Inversion layer NMOS “channel”
If the gate is biased above threshold, the surface is inverted
This inverted region forms a channel that connects the drain and gate
If a drain voltage is applied positive, electrons will flow from source to drain
Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad MOSFET: Variable Resistor
Notice that in the linear region, the current is proportional to the voltage W ICVVV=−µ ( ) DSL n ox GS Tn DS
Can define a voltage-dependent resistor
VDS 1 LL RRV== = ( ) eqµ − GS ICVVWDS n ox() GS Tn W
This is a nice variable resistor, electronically tunable!
Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
Finding ID = f (VGS, VDS)
Approximate inversion charge QN(y): drain is higher than the source less charge at drain end of channel
Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Inversion Charge at Source/Drain
≈ = + = QN (y) QN (y 0) QN (y L)
= = − − = = QN (y 0) Cox (VGS VTn ) QN (y L) − − Cox (VGD VTn )
= − GD VGS VDS
Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Average Inversion Charge
Source End Drain End
C (VVCVV−+)( − ) Qy()≈− oxGST oxGDT N 2 C (VVCVVV−+)( −− ) Qy()≈− ox GS T ox GS SD T N 2 CV(2−− 2 V ) CV V Qy()≈−ox GS T ox SD =− CV ( − V − DS ) NoxGST2 2
Charge at drain end is lower since field is lower
Simple approximation: In reality we should integrate the total charge minus the bulk depletion charge across the channel
Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Drift Velocity and Drain Current
“Long-channel” assumption: use mobility to find v
µ V vy()=−µµ Ey () ≈− ( −∆ V / ∆ y ) = n DS nn L Substituting: VV IWvQWCVV=− ≈µ DS() − − DS DNL oxGST2 W V ICVVV≈−−µ ( DS ) DoxGSTDSL 2
Inverted Parabolas
Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Square-Law Characteristics
Boundary: what is ID,SAT? TRIODE REGION
SATURATION REGION
Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad The Saturation Region
When VDS > VGS –VTn, there isn’t any inversion charge at the drain … according to our simplistic model
Why do curves flatten out?
Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Square-Law Current in Saturation
Current stays at maximum (where VDS = VGS – VTn = VDS,SAT) W V ICVVV=−−µ ( DS ) DoxGSTDSL 2 W VV− ICVVVV=−−−µ ( GS T )( ) DS, satL ox GS T2 GS T W µC IVV=−ox ( )2 DS, satL 2 GS T
Measurement: ID increases slightly with increasing VDS model with linear “fudge factor” W µC IVVV=−+ox ( )(12 λ ) DS, satL 2 GS T DS Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Pinching the MOS Transistors
> VGSTnV S G D VDS
p+ n+ n+ − VGSTnV Depletion Region p-type
NMOS Pinch-Off Point
When VDS > VDS,sat, the channel is “pinched” off at drain end (hence the name “pinch-off region”)
Drain mobile charge goes to zero (region is depleted), the remaining elecric field is dropped across this high-field depletion region
As the drain voltage is increases further, the pinch off point moves back towards source
Channel Length Modulation: The effective channel length is thus reduced higher IDS
Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Linear MOSFET Model
Channel (inversion) charge: neglect reduction at drain
Velocity saturation defines VDS,SAT =Esat L = constant
-v / µ Drain current: sat n
= − = − − − ID,SAT WvQN W (vsat )[ Cox (VGS VTn )],
4 µ |Esat| = 10 V/cm, L = 0.12 m VDS,SAT = 0.12 V! = − + λ I D,SAT vsatWCox (VGS VTn )(1 nVDS )
Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Why Find an Incremental Model?
Signals of interest in analog ICs are often of the form: =+ vtGS( )() V GS vt gs
Fixed Bias Point Small Signal
Direct substitution into iD = f(vGS, vDS) is tedious AND doesn’t include charge-storage effects … pretty rough approximation
Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Which Operating Region?
= VGS 3V TRIODE = VDS 3V
SAT
OFF
Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Changing One Variable at a Time
IkDS /
= Linear VDS 3V Triode Square Law Region Saturation = VT 1V Region
Slope of Tangent: Incremental current increase
VGS
Assumption: VDS > VDS,SAT = VGS – VTn (square law)
Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
The Transconductance gm
Defined as the change in drain current due to a change in the gate-source voltage, with everything else constant
W µC IVVV=−+ox ( )(12 λ ) DS, satL 2 GS T DS ≈ 0 ∆∂ii W gCVVV===DDµλ()(1) −+ moxGSTDS∆∂ vvGS GS L VVGS,, DS VV GS DS
W gCVV=−µ ( ) m oxL GS T Gate Bias
WW2I gC==µµDS 2 CI Drain Current Bias moxW oxDS LLC L ox µ 2I g = DS Drain Current Bias and m (V −V ) GST Gate Bias
Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
Output Resistance ro Defined as the inverse of the change in drain current due to a change in the drain-source voltage, with everything else constant
Non-Zero Slope
δ IDS
δ VDS
Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
Evaluating ro
W µC i =−+ox (VV)(12 λ V ) DGSTDSL 2 −1 ∂i r =D o ∂ vDS VVGS, DS 1 r = 0 W µC ox (VV− )2 L 2 GS T λ 1 r ≈ 0 λ IDS
Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Total Small Signal Current
=+ iDS()tI DS i ds
∂∂ii i =+DSvv DS dsgsds∂∂ vvgs ds
=+1 idsgv m gs v ds ro
Transconductance Conductance
Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Putting Together a Circuit Model
=+1 idsmgsdsgv v ro
Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Role of the Substrate Potential
Need not be the source potential, but VB < VS
Effect: changes threshold voltage, which changes the drain current … substrate acts like a “backgate”
∆i ∂i g = D = D mb ∆ ∂ vBS Q vBS Q
Q = (VGS, VDS, VBS)
Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Backgate Transconductance
=+γφφ − −− VVT TSBpp0 () V 22
∂∂ii∂Vgγ Result: g ==DDTn = m mb ∂∂∂vVv −−φ BSQQQ Tn BS 22VBS p
Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Four-Terminal Small-Signal Model
=+ +1 idsgv m gs g mb v bs v ds ro
Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad MOSFET Capacitances in Saturation
Gate-source capacitance: channel charge is not controlled by drain in saturation.
Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
Gate-Source Capacitance Cgs
Wedge-shaped charge in saturation effective area is (2/3)WL (see H&S 4.5.4 for details) = + Cgs (2/3)WLCox Cov Overlap capacitance along source edge of gate = Cov LDWCox
(Underestimate due to fringing fields)
Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
Gate-Drain Capacitance Cgd
Not due to change in inversion charge in channel
Overlap capacitance Cov between drain and source is Cgd
Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Junction Capacitances
Drain and source diffusions have (different) junction
capacitances since VSB and VDB = VSB + VDS aren’t the same Complete model (without interconnects)
Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad P-Channel MOSFET
Measurement of –IDp versus VSD, with VSG as a parameter:
Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Square-Law PMOS Characteristics
Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Small-Signal PMOS Model
Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad MOSFET SPICE Model
Many “levels”…we will use the square-law “Level 1” model See H&S 4.6 + Spice refs. on reserve for details.
Department of EECS University of California, Berkeley