MAGIC—Memristor-Aided Logic Shahar Kvatinsky, Student Member, IEEE, Dmitry Belousov, Slavik Liman, Guy Satat, Student Member, IEEE, Nimrod Wald, Eby G
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Hybrid Memristor–CMOS Implementation of Combinational Logic Based on X-MRL †
electronics Article Hybrid Memristor–CMOS Implementation of Combinational Logic Based on X-MRL † Khaled Alhaj Ali 1,* , Mostafa Rizk 1,2,3 , Amer Baghdadi 1 , Jean-Philippe Diguet 4 and Jalal Jomaah 3 1 IMT Atlantique, Lab-STICC CNRS, UMR, 29238 Brest, France; [email protected] (M.R.); [email protected] (A.B.) 2 Lebanese International University, School of Engineering, Block F 146404 Mazraa, Beirut 146404, Lebanon 3 Faculty of Sciences, Lebanese University, Beirut 6573, Lebanon; [email protected] 4 IRL CROSSING CNRS, Adelaide 5005, Australia; [email protected] * Correspondence: [email protected] † This paper is an extended version of our paper published in IEEE International Conference on Electronics, Circuits and Systems (ICECS) , 27–29 November 2019, as Ali, K.A.; Rizk, M.; Baghdadi, A.; Diguet, J.P.; Jomaah, J. “MRL Crossbar-Based Full Adder Design”. Abstract: A great deal of effort has recently been devoted to extending the usage of memristor technology from memory to computing. Memristor-based logic design is an emerging concept that targets efficient computing systems. Several logic families have evolved, each with different attributes. Memristor Ratioed Logic (MRL) has been recently introduced as a hybrid memristor–CMOS logic family. MRL requires an efficient design strategy that takes into consideration the implementation phase. This paper presents a novel MRL-based crossbar design: X-MRL. The proposed structure combines the density and scalability attributes of memristive crossbar arrays and the opportunity of their implementation at the top of CMOS layer. The evaluation of the proposed approach is performed through the design of an X-MRL-based full adder. -
CSE Yet, Please Do Well! Logical Connectives
administrivia Course web: http://www.cs.washington.edu/311 Office hours: 12 office hours each week Me/James: MW 10:30-11:30/2:30-3:30pm or by appointment TA Section: Start next week Call me: Shayan Don’t: Actually call me. Homework #1: Will be posted today, due next Friday by midnight (Oct 9th) Gradescope! (stay tuned) Extra credit: Not required to get a 4.0. Counts separately. In total, may raise grade by ~0.1 Don’t be shy (raise your hand in the back)! Do space out your participation. If you are not CSE yet, please do well! logical connectives p q p q p p T T T T F T F F F T F T F NOT F F F AND p q p q p q p q T T T T T F T F T T F T F T T F T T F F F F F F OR XOR 푝 → 푞 • “If p, then q” is a promise: p q p q F F T • Whenever p is true, then q is true F T T • Ask “has the promise been broken” T F F T T T If it’s raining, then I have my umbrella. related implications • Implication: p q • Converse: q p • Contrapositive: q p • Inverse: p q How do these relate to each other? How to see this? 푝 ↔ 푞 • p iff q • p is equivalent to q • p implies q and q implies p p q p q Let’s think about fruits A fruit is an apple only if it is either red or green and a fruit is not red and green. -
Realization of Morphing Logic Gates in a Repressilator with Quorum Sensing Feedback
Realization of Morphing Logic Gates in a Repressilator with Quorum Sensing Feedback Vidit Agarwal, Shivpal Singh Kang and Sudeshna Sinha Indian Institute of Science Education and Research (IISER) Mohali, Knowledge City, SAS Nagar, Sector 81, Manauli PO 140 306, Punjab, India Abstract We demonstrate how a genetic ring oscillator network with quorum sensing feedback can operate as a robust logic gate. Specifically we show how a range of logic functions, namely AND/NAND, OR/NOR and XOR/XNOR, can be realized by the system, thus yielding a versatile unit that can morph between different logic operations. We further demonstrate the capacity of this system to yield complementary logic operations in parallel. Our results then indicate the computing potential of this biological system, and may lead to bio-inspired computing devices. arXiv:1310.8267v1 [physics.bio-ph] 30 Oct 2013 1 I. INTRODUCTION The operation of any computing device is necessarily a physical process, and this funda- mentally determines the possibilities and limitations of the computing machine. A common thread in the history of computers is the exploitation and manipulation of different natural phenomena to obtain newer forms of computing paradigms [1]. For instance, chaos comput- ing [2], neurobiologically inspired computing, quantum computing[3], and DNA computing[4] all aim to utilize, at the basic level, some of the computational capabilities inherent in natural systems. In particular, larger understanding of biological systems has triggered the interest- ing question: what new directions do bio-systems offer for understanding and implementing computations? The broad idea then, is to create machines that benefit from natural phenomena and utilize patterns inherent in systems to encode inputs and subsequently obtain a desired output. -
Universal Gate - NOR Digital Electronics 2.2 Intro to NAND & NOR Logic
Universal Gate - NOR Digital Electronics 2.2 Intro to NAND & NOR Logic Universal Gate – NOR This presentation will demonstrate… • The basic function of the NOR gate. • How an NOR gate can be using to replace an AND gate, an OR gate or an INVERTER gate. • How a logic circuit implemented with AOI logic gates Universal Gate – NOR could be re-implemented using only NOR gates • That using a single gate type, in this case NOR, will reduce the number of integrated circuits (IC) required to implement a logic circuit. Digital Electronics AOI Logic NOR Logic 2 More ICs = More $$ Less ICs = Less $$ NOR Gate NOR Gate as an Inverter Gate X X X (Before Bubble) X Z X Y X Y X Z X Y X Y Z X Z 0 0 1 0 1 Equivalent to Inverter 0 1 0 1 0 1 0 0 1 1 0 3 4 Project Lead The Way, Inc. Copyright 2009 1 Universal Gate - NOR Digital Electronics 2.2 Intro to NAND & NOR Logic NOR Gate as an OR Gate NOR Gate as an AND Gate X X Y Y X X Z X Y X Y Y Z X Y X Y X Y Y NOR Gate “Inverter” “Inverters” NOR Gate X Y Z X Y Z 0 0 0 0 0 0 0 1 1 0 1 0 Equivalent to OR Gate Equivalent to AND Gate 1 0 1 1 0 0 1 1 1 1 1 1 5 6 NOR Gate Equivalent of AOI Gates Process for NOR Implementation 1. -
New Approaches for Memristive Logic Computations
Portland State University PDXScholar Dissertations and Theses Dissertations and Theses 6-6-2018 New Approaches for Memristive Logic Computations Muayad Jaafar Aljafar Portland State University Let us know how access to this document benefits ouy . Follow this and additional works at: https://pdxscholar.library.pdx.edu/open_access_etds Part of the Electrical and Computer Engineering Commons Recommended Citation Aljafar, Muayad Jaafar, "New Approaches for Memristive Logic Computations" (2018). Dissertations and Theses. Paper 4372. 10.15760/etd.6256 This Dissertation is brought to you for free and open access. It has been accepted for inclusion in Dissertations and Theses by an authorized administrator of PDXScholar. For more information, please contact [email protected]. New Approaches for Memristive Logic Computations by Muayad Jaafar Aljafar A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical and Computer Engineering Dissertation Committee: Marek A. Perkowski, Chair John M. Acken Xiaoyu Song Steven Bleiler Portland State University 2018 © 2018 Muayad Jaafar Aljafar Abstract Over the past five decades, exponential advances in device integration in microelectronics for memory and computation applications have been observed. These advances are closely related to miniaturization in integrated circuit technologies. However, this miniaturization is reaching the physical limit (i.e., the end of Moore’s Law). This miniaturization is also causing a dramatic problem of heat dissipation in integrated circuits. Additionally, approaching the physical limit of semiconductor devices in fabrication process increases the delay of moving data between computing and memory units hence decreasing the performance. The market requirements for faster computers with lower power consumption can be addressed by new emerging technologies such as memristors. -
A Noise-Assisted Reprogrammable Nanomechanical Logic Gate
pubs.acs.org/NanoLett A Noise-Assisted Reprogrammable Nanomechanical Logic Gate Diego N. Guerra,† Adi R. Bulsara,‡ William L. Ditto,§ Sudeshna Sinha,| K. Murali,⊥ and P. Mohanty*,† † Department of Physics, Boston University, 590 Commonwealth Avenue, Boston, Massachusetts 02215, ‡ SPAWAR Systems Center Pacific, Code 71, 53560 Hull Street, San Diego, California 92152, § School of Biological and Health Systems Engineering, Arizona State University, Tempe, Arizona 85287, | Institute of Mathematical Sciences, Taramani, Chennai 600 113, India, and ⊥ Physics Department, Anna University, Chennai 600 025, India ABSTRACT We present a nanomechanical device, operating as a reprogrammable logic gate, and performing fundamental logic functions such as AND/OR and NAND/NOR. The logic function can be programmed (e.g., from AND to OR) dynamically, by adjusting the resonator’s operating parameters. The device can access one of two stable steady states, according to a specific logic function; this operation is mediated by the noise floor which can be directly adjusted, or dynamically “tuned” via an adjustment of the underlying nonlinearity of the resonator, i.e., it is not necessary to have direct control over the noise floor. The demonstration of this reprogrammable nanomechanical logic gate affords a path to the practical realization of a new generation of mechanical computers. KEYWORDS Nanomechanical logic, nanomechanical computing, logical stochastic resonance, stochastic resonance, nanomechanical resonator practical realization of a nanomechanical logic applied as input stimuli to a two-state system, the response device, capable of performing fundamental logic can result in a specific logical output with a probability (for operations, is yet to be demonstrated despite a long- obtaining this output) controlled by the noise intensity. -
Logic Functions Realized Using Clockless Gates for Rapid Single-Flux-Quantum Circuits
R2-4 SASIMI 2021 Proceedings Logic Functions Realized Using Clockless Gates for Rapid Single-Flux-Quantum Circuits Takahiro Kawaguchi Kazuyoshi Takagi Naofumi Takagi Graduate School of Informatics Graduate School of Engineering Graduate School of Informatics Kyoto University Mie University Kyoto University Kyoto, 606-8501, Japan Mie, 514-8507, Japan Kyoto, 606-8501, Japan [email protected] [email protected] [email protected] Abstract— Superconducting rapid single-flux- and the area occupied by a clock distribution network are quantum (RSFQ) circuit is a promising candidate reduced. The reduction of the pipeline depth leads to a for circuit technology in the post-Moore era. RSFQ fewer DFFs for path-balancing and a smaller circuit area. digital circuits operate with pulse logic and are A clockless AND gate and a clockless NIMPLY gate was usually composed of clocked gates. We have proposed proposed in [10]. A NIMPLY (not-imply) gate is an AND clockless gates, which can reduce the hardware gate with one inverted input, which implements x∧¬y.A amount of a circuit drastically. In this paper, we confluence buffer [1], which merges a pulse from its inputs first discuss logic functions realizable using clockless to its output, can be used as a clockless OR gate. gates. We show that all the 0-preserving functions A clockless gate realizes only a 0-preserving logic func- can be realized using the existing clockless gates, tion, which outputs 0 from the input value of all 0s, be- i.e., AND, OR, and NIMPLY (not-imply) gates. -
Voltage Controlled Memristor Threshold Logic Gates, 2016 IEEE APCCAS, Jeju, Korea, October 25-28, 2016
A. Maan, A. P. James, Voltage Controlled Memristor Threshold Logic Gates, 2016 IEEE APCCAS, Jeju, Korea, October 25-28, 2016 Voltage Controlled Memristor Threshold Logic Gates Akshay Kumar Maan Alex Pappachen James Queensland Microelectronic Facility School of Engineering, Nazabayev University Griffith University Astana, Kazakhastan Queensland 4111, Australia Web: www.biomicrosystems.info/alex Email: [email protected] Email: [email protected] Abstract—In this paper, we present a resistive switching weights to the inputs, while the CMOS inverter behaves as memristor cell for implementing universal logic gates. The cell a threshold logic device. The weights are programmed via has a weighted control input whose resistance is set based on a the resistive switching phenomenon of the memristor device. control signal that generalizes the operational regime from NAND We show that resistive switching makes it possible to use the to NOR functionality. We further show how threshold logic in same cell architecture to work in the NAND, NOR or XOR the voltage-controlled resistive cell can be used to implement a configuration, and can be implemented in a programmable XOR logic. Building on the same principle we implement a half adder and a 4-bit CLA (Carry Look-ahead Adder) and show array architecture. We hypothesise that if such circuits are that in comparison with CMOS-only logic, the proposed system developed in silicon that can be programmed and reused to shows significant improvements in terms of device area, power generate different logic gate functionalities, we will be able to dissipation and leakage power. move a step closer towards the development of low power and large scale threshold logic applications. -
1 Novel Reconfigurable Logic Gates Using Spin Metal-Oxide
Novel Reconfigurable Logic Gates Using Spin Metal-Oxide-Semiconductor Field-Effect Transistors Satoshi Sugahara1, 2*, Tomohiro Matsuno1, and Masaaki Tanaka1,2** 1 Department of Electronic Engineering, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo, 113-8656, Japan 2 PRESTO, Japan Science and Technology Agency, 4-1-8 Honcho, Kawaguchi 332-0012, Japan We propose and numerically simulate novel reconfigurable logic gates employing spin metal-oxide-semiconductor field-effect transistors (spin MOSFETs). The output characteristics of the spin MOSFETs depend on the relative magnetization configuration of the ferromagnetic contacts for the source and drain, that is, high current-drive capability in the parallel magnetization and low current-drive capability in the antiparallel magnetization [S. Sugahara and M. Tanaka: Appl. Phys. Lett. 84 (2004) 2307]. A reconfigurable NAND/NOR logic gate can be realized by using a spin MOSFET as a driver or an active load of a complimentary MOS (CMOS) inverter with a neuron MOS input stage. Its logic function can be switched by changing the relative magnetization configuration of the ferromagnetic source and drain of the spin MOSFET. A reconfigurable logic gate for all symmetric Boolean functions can be configured using only five CMOS inverters including four spin MOSFETs. The operation of these reconfigurable logic gates was confirmed by numerical simulations using a simple device model for the spin MOSFETs. KEYWORDS: spintronics, spin transistor, spin MOSFET, reconfigurable logic, FPGA *E-mail address: [email protected] **E-mail address: [email protected] 1 1 Introduction The area of spintronics (or spin electronics) in which uses not only charge transport of electrons but also the spin degree of freedom of electrons is used has generated much interest in recent years. -
Switching Theory and Logic Design
SWITCHING THEORY AND LOGIC DESIGN LECTURE NOTES B.TECH (II YEAR – II SEM) (2018-19) Prepared by: Ms M H Bindu Reddy, Assistant Professor Department of Electrical & Electronics Engineering MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY (Autonomous Institution – UGC, Govt. of India) Recognized under 2(f) and 12 (B) of UGC ACT 1956 (Affiliated to JNTUH, Hyderabad, Approved by AICTE - Accredited by NBA & NAAC – ‘A’ Grade - ISO 9001:2015 Certified) Maisammaguda, Dhulapally (Post Via. Kompally), Secunderabad – 500100, Telangana State, India SYLLABUS UNIT -I: Number System and Gates: Number Systems, Base Conversion Methods, Complements of Numbers, Codes- Binary Codes, Binary Coded Decimal Code and its Properties, Excess-3 code, Unit Distance Code, Error Detecting and Correcting Codes, Hamming Code.Digital Logic Gates, Properties of XOR Gates, Universal Logic Gates. UNIT -II: Boolean Algebra and Minimization: Basic Theorems and Properties, Switching Functions, Canonical and Standard Forms,Multilevel NAND/NOR realizations. K- Map Method, up to Five variable K- Maps, Don’t Care Map Entries, Prime and Essential prime Implications, Quine Mc Cluskey Tabular Method UNIT -III: Combinational Circuits Design: Combinational Design, Half adder,Fulladder,Halfsubtractor,Full subtractor,Parallel binary adder/subtracor,BCD adder, Comparator, decoder, Encoder, Multiplexers, DeMultiplexers, Code Converters. UNIT -IV: Sequential Machines Fundamentals: Introduction, Basic Architectural Distinctions between Combinational and Sequential circuits, classification of sequential circuits, The binary cell, The S-R- Latch Flip-Flop The D-Latch Flip-Flop, The “Clocked T” Flip-Flop, The “ Clocked J-K” Flip-Flop, Design of a Clocked Flip-Flop, Conversion from one type of Flip-Flop to another, Timing and Triggering Consideration. UNIT -V: Sequential Circuit Design and Analysis: Introduction, State Diagram, Analysis of Synchronous Sequential Circuits, Approaches to the Design of Synchronous Sequential Finite State Machines, Design Aspects, State Reduction, Design Steps, Realization using Flip-Flops. -
Automated Synthesis of Unconventional Computing Systems
University of Central Florida STARS Electronic Theses and Dissertations, 2004-2019 2019 Automated Synthesis of Unconventional Computing Systems Amad Ul Hassen University of Central Florida Part of the Computer Engineering Commons Find similar works at: https://stars.library.ucf.edu/etd University of Central Florida Libraries http://library.ucf.edu This Doctoral Dissertation (Open Access) is brought to you for free and open access by STARS. It has been accepted for inclusion in Electronic Theses and Dissertations, 2004-2019 by an authorized administrator of STARS. For more information, please contact [email protected]. STARS Citation Ul Hassen, Amad, "Automated Synthesis of Unconventional Computing Systems" (2019). Electronic Theses and Dissertations, 2004-2019. 6500. https://stars.library.ucf.edu/etd/6500 AUTOMATED SYNTHESIS OF UNCONVENTIONAL COMPUTING SYSTEMS by AMAD UL HASSEN MSc Computer Science, University of Central Florida, 2016 MSc Electrical Engineering, University of Engineering & Technology Lahore, 2013 BSc Electrical Engineering, University of Engineering & Technology, Lahore, 2008 A Dissertation submitted in partial fulfilment of the requirements for the degree of Doctor of Philosophy in the Department of Electrical and Computer Engineering in the College of Engineering and Computer Science at the University of Central Florida Orlando, Florida Summer Term 2019 Major Professor: Sumit Kumar Jha c 2019 Amad Ul Hassen ii ABSTRACT Despite decades of advancements, modern computing systems which are based on the von Neu- mann architecture still carry its shortcomings. Moore’s law, which had substantially masked the effects of the inherent memory-processor bottleneck of the von Neumann architecture, has slowed down due to transistor dimensions nearing atomic sizes. -
Combinational Logic Circuits
CHAPTER 4 COMBINATIONAL LOGIC CIRCUITS ■ OUTLINE 4-1 Sum-of-Products Form 4-10 Troubleshooting Digital 4-2 Simplifying Logic Circuits Systems 4-3 Algebraic Simplification 4-11 Internal Digital IC Faults 4-4 Designing Combinational 4-12 External Faults Logic Circuits 4-13 Troubleshooting Prototyped 4-5 Karnaugh Map Method Circuits 4-6 Exclusive-OR and 4-14 Programmable Logic Devices Exclusive-NOR Circuits 4-15 Representing Data in HDL 4-7 Parity Generator and Checker 4-16 Truth Tables Using HDL 4-8 Enable/Disable Circuits 4-17 Decision Control Structures 4-9 Basic Characteristics of in HDL Digital ICs M04_WIDM0130_12_SE_C04.indd 136 1/8/16 8:38 PM ■ CHAPTER OUTCOMES Upon completion of this chapter, you will be able to: ■■ Convert a logic expression into a sum-of-products expression. ■■ Perform the necessary steps to reduce a sum-of-products expression to its simplest form. ■■ Use Boolean algebra and the Karnaugh map as tools to simplify and design logic circuits. ■■ Explain the operation of both exclusive-OR and exclusive-NOR circuits. ■■ Design simple logic circuits without the help of a truth table. ■■ Describe how to implement enable circuits. ■■ Cite the basic characteristics of TTL and CMOS digital ICs. ■■ Use the basic troubleshooting rules of digital systems. ■■ Deduce from observed results the faults of malfunctioning combina- tional logic circuits. ■■ Describe the fundamental idea of programmable logic devices (PLDs). ■■ Describe the steps involved in programming a PLD to perform a simple combinational logic function. ■■ Describe hierarchical design methods. ■■ Identify proper data types for single-bit, bit array, and numeric value variables.