Modeling the Short Circuit Energy Dissipation of a CMOS Inverter

Modeling the Short-circuit Energy Dissipation of a CMOS Inverter

Pinar Korkmaz

1. Introduction

The short-circuit energy dissipation results due to a direct path current flowing from the power supply to the ground during the switching of a static CMOS gate. Short-circuit energy constitutes 10-20% of the total energy dissipation of a static CMOS gate [1]. The goal of this work is to develop analytical expressions modeling the short-circuit energy dissipation of a CMOS inverter.

The first closed form expression modeling the short-circuit energy dissipation in a CMOS inverter was developed by Veendrick [2], where zero-load capacitance is assumed. The model results in pessimistic results because of the zero-load capacitance assumption. In addition, the model is based on the Shichman and Hodges square law MOSFET model [3], which ignores the short-channel effects of the submicron devices.

In [4], a more realistic short-circuit energy dissipation model was proposed. This model includes the effect of the output load capacitance. However, the short-channel effects are ignored in the derivation of the model. In [5], the model of [4] is improved by including the velocity saturation effects through use of alpha-power (α-power) law MOS model [6]. However, the contribution of the PMOS (NMOS) currents in falling (rising) output is neglected in the derivation of the model. In addition, the Miller effect of the gate-to-drain capacitance is not included. Also, it is assumed that the load transistor operates only in the saturation region during the time interval in which the short-circuit current flows.

In [7], another short-circuit energy dissipation model based on Shichman and Hodges MOSFET current model was proposed. This model considers the effect of the PMOS (NMOS) current on the short-circuit current in case of the falling (rising) edge of the output through use of two technology dependent empirical parameters. The Miller effect of the gate-to-drain capacitance is also included in the model. To include this effect, technology dependent empirical parameters are used.

In [8], the short-circuit current waveform was approximated with a piecewise linear function of the time to estimate the short-circuit energy dissipation. In this model, the energy dissipation of the reverse current due to the gate-to-drain capacitance is subtracted from the short-circuit energy dissipation. However, this reverse current is provided from the inverter input, but not from the power supply of the gate, hence this energy component can not be included in the short-circuit energy dissipation.

In [9], a short-circuit model was developed using α-power law MOS model [6]. The model takes into account the current through both transistors. The influence of the gate- to-drain capacitances of both transistors and the gate-to-source capacitance of the short circuiting transistor are included in the derivation of the model. However, the α-power law MOS model does not very well capture the short-channel effects.

Nose and Sakurai [10] derived a closed-form expression for modeling the short-circuit energy dissipation of a CMOS inverter. They used an alpha-power law MOSFET model [11] in their derivation, which is more accurate especially in the triode region [12] than the original alpha-power law model [6]. Their model includes the short-channel effects. However, the model does not include the effect of the gate-drain and gate-source capacitance of the transistors.

In this work, we improve the model in [9] by using the alpha power law MOS model of [10].

2. Modeling the Short-circuit Energy Dissipation of a CMOS Inverter

In this section, we derive the short-circuit energy dissipation in a CMOS inverter (shown in Figure 1) for the rising input. The derivation for the falling input can be carried out in a similar way.

In Figure 1, the output capacitance Co includes the drain junction capacitances of the two transistors of the inverter, the gate capacitances of the fan-out gates, and the interconnect

capacitance. CM is the Miller capacitance and is equal to the sum of the gate to drain

capacitance of both transistors. Cgsp is the gate to source capacitance of the PMOS

transistor. Ip and In are the drain to source currents of the PMOS and NMOS transistors respectively.

VDD

ICgsp

Cgsp Ip CM Vin Vout

In Co

Figure 1. The CMOS inverter

The input, Vin, is represented by Vin = VDD.(t/τ) for 0 ≤ t ≤ τ, where τ is the input rise time.

The differential equation in (1) describes the discharge of the output capacitance Co.

dV  dV dV  C out = C  in − out  + I − I (1) o dt m  dt dt  p n

To calculate the currents Ip and In, we use the α-power law MOSFET current model [10] provided below in (2). The model consists of four parameters, α, IDO, VDO and VTH. α

represents the velocity saturation index which is an empirical parameter. IDO is the drain

current at VGS = VDS = VDD. VDO is the drain to source saturation voltage at VGS = VDD. VTH

represents the threshold voltage and it is not the same as the physical threshold (Vth) of the transistor.

 <  0, VGS VTHP (cutoff region)        V  V  I = I ⋅ 2 − DS DS , V < V (linear region) (2) p Dp  V  V DS Dp   Dp  Dp    I , V < V (saturation region)   Dp DS Dp  where α  V −V  p =  GS THP  I D I DOP   p  V −V  DD THP α / 2 (3)  V −V  p V = V  GS THP  D p DOP  −   VDD VTHP 

The NMOS device current is

0, V < V (cutoff region)   GS THN    V  V  I = I ⋅2 − DS  DS , V < V (linear region) (4) n Dn  V  V DS Dn   Dn  Dn    I , V < V (saturation region)   Dn DS Dn 

where

α  −  n =  VGS VTHN  I D I DON   n V −V  DD THN α / 2 (5)  V −V  n V = V  GS THN  Dn DON  −  VDD VTHN 

To calculate the short-circuit energy dissipation; we first derive the analytical expressions of the output voltage waveforms of the CMOS inverter. Figure 2 shows the input and output voltage waveforms and the operating regions for the rising input.

In region 1 (0 ≤ t ≤ tn), the NMOS transistor is OFF and the PMOS transistor is in the linear region. Thus, the NMOS and PMOS currents are as follows

= I n 0     V −V V −V  I = I ⋅ 2 − DD out DD out , V < V (6) p Dp  V  V  DS Dp  Dp  Dp 

Then, the differential equation in (1) can be expressed as

dV out = AV 2 + BV + C (7) dt out out where

I D A = − ph ()C + C V 2 L M Dp 2I ()V −V D ph Dph DD B = − (8) ()C + C V 2 L M Dph 2 C V I D VDD 2I D VDD C = M DD − ph + ph ()C + C τ ()C + C V 2 ()C + C V L M L M Dph L M Dph

To derive (8), I and V are approximated to be constant and equal to D p D p I and V respectively. I and V correspond to the values of I and V in the D ph D ph D ph D ph D p D p middle of the interval (0 ≤ t ≤ tn) and are expressed as follows

α  − −  p = VDD VTHN / 2 VTHP  I D IDOP   ph  V −V  DD THP α / 2 (9) V −V / 2 −V  p V = V  DD THN THP  D ph DOP  −   VDD VTHP 

The differential equation (7) is a Verhulst equation [13]. It is solved using the condition

Vout (0) = VDD and the solution is described by

= + 1 Vout (t) K1 −Et A − e ()e Et −1 + (10) − E VDD K1 where

E = B2 − 4AC (11) and

E − B K = (12) 1 2A

Voltage

VDD Region 1 Region 2 Region 3

t 0 tn t1 tsatp 1-tp

Figure 2. Operating regions of the CMOS inverter during a rising input

As shown in Figure 2, there is an overshoot at the early part of the output voltage (0 ≤ t ≤ t1), that is, the output voltage is greater than the supply voltage. During the overshoot, there is no current flowing from the power supply to the ground. Hence, the short-circuit power consumption is zero during the overshoot.

In region 2 (tn ≤ t ≤ tsatp), the NMOS transistor is saturated and the PMOS transistor is in the linear region. tsatp represents the point in time when the PMOS transistor enters the saturation region. In this region, the PMOS current is approximated by a linear function of time as demonstrated in Figure 3. The approximation is shown in (13).

 V  I = I + St − THN τ  p pmin   (13)  VDD 

= VTHN τ Ipmin represents the value of the PMOS current at tn . tn is the point in time when VDD the NMOS transistor leaves the cutoff region and enters the saturation region. The value of the output voltage at tn is (using (10))

1 V ()t = K + out n 1 −Et A − e n ()e Etn −1 + (14) − E VDD K1 and Ipmin is described by (using (6))

    V −V ()t V −V ()t  I = I ⋅2 − DD out n  DD out n pmin Dp   (15) t=tn  V  V  Dp Dp t =t  t=tn  n 

Current Approximated current

t n t 0 thp tsat tp Region 2

Figure 3. Linear approximation of PMOS current in region 2

In region 2, the NMOS transistor current is given by

α  t  n  V −V  DD τ THN I = I   (16) n DON  −   VDD VTHN   

Replacing (13) and (16) for Ip and In in (1), the output voltage waveform in region 2 is calculated and found to be described by the following expression

α +   n 1 ()=  − VTHN  + 2 + + Vout t A2 t  B2t C2t K (17)  VDD  where

α I  V  N A = − DON  DD  2 ()()+ α + τ ()−  CL CM N 1  VDD VTHN  S B = 2 2()C + C L M (18) C V V I − SτV C = M DD + DD p min THN 2 ()+ τ ()+ CL CM VDD CL CM 2 SV τ C τV I K = V (t ) + THN − M V − THN p min out n ()+ 2 ()+ THN ()+ 2 CL CM VDD CL CM VDD CL CM

The slope of the PMOS current waveform, S, is calculated by equating the PMOS current τ τ = − VTHP in linear region (using (6)) to the approximated current (using (13)) at time thp . 2 2VDD = = At t tsatp , the PMOS transistor is entering the saturation region. Hence, at time t tsatp , the following saturation condition is satisfied

V = V −V out DD D p (19)

τ = τ − ()+ To find tsatp , we use a Taylor series expansion around the point t VTHP VTHN up VDD to the second order coefficient, for both V and V (in (19)). t is expressed as out D p satp

− E + E 2 − 4D F = 2 2 2 2 tsatp (20) 2D2 where = + + D5 A2 A3 B2 A4VDOP = + + E5 A2B3 VDOP B4 C2 (21) = + + − F5 A2C3 K VDOPC4 VDD with

α − α ()α + −τ ()−  n 1 = n n 1  VDD VTHP 2VTHN  A3   2  VDD  α τ()V −V − 2V  n   V −V −V  B = ()α +1  DD THP THN  1−α  DD THP THN  3 n    n  − −   VDD   VDD VTHP 2VTHN    − −    − ()α +  VDD VTHP VTHN   α +1 1 n 1   −τ()V −V 2V  n  V −V − 2V  =  DD THP THN   DD THP THN  C3    2  V α ()α +  − −   DD  + n n 1  VDD VTHP VTHN     − −    2 VDD VTHP 2VTHN   α p (22) 2 α α   V   V  2 A = p  p −1  DD   THN  4   τ   −  4  2   VTHN  VDD VTHP  α α p  α  + −  p VDD  p VTHN VTHP VDD  B = − ⋅ ()V 2 1−  −1 4 τ THN     2 VTHN   2  VTHN   α  α p V +V −V p 1− ⋅ THN THP DD +    2  2 V  =  VTHN  THN C4    2  − α α  V +V −V  VDD VTHP   p  p −   THN THP DD     1     4  2   VTHN  

Referring to Figure 2, t1 corresponds to the point in time when the output voltage = overshoot finishes. It is calculated by solving the equation Vout VDD , using the Taylor τ = 3 VTHN series expansion of Vout around the point t . Note that in [9], a Taylor series 2 VDD τ VTHN expansion around t = 2 is used. However, our HSpice simulations show that t1 is VDD τ 3 VTHN closer to t = . Then, t1 is described by 2 VDD

− E + E 2 − 4D F = 6 6 6 6 t1 (23) 2D6 where

= + D6 A2 A5 B2 = + E6 A2B5 C2 (24) = + − F6 A2C5 K VDD and

α − α ()α + τ  n 1 = n n 1  VTHN  A5   2  2VDD  α τ  n = ()α +  VTHN  ()− α B5 n 1   1 3 n (25)  2VDD  α + τ  n 1  =  VTHN  − ()α + + 9 α ()α + C5   1 3 n 1 n n 1   2VDD   2 

In region 3 (tsatp ≤ t ≤ tp), both of the transistors are saturated. Hence, the PMOS and NMOS currents are described as

α  t  p V −V −V  DD DD τ THP I = I   p DOP  −   VDD VTHP    α (26)  t  n V −V  DD τ THN I = I   n DON  −   VDD VTHN   

Note that tp corresponds to the point in time when the PMOS transistor enters the cutoff region.

Referring to Figure 1, the short-circuit current Isc (during a rising input) is expressed as

I = I − I sc p Cgsp (27)

I The current Cgsp is given by

dVin VDD I =C = C (28) Cgsp gsp dt gsp τ

[] The short-circuit energy dissipation occurs in the interval t2 ,t3 since there is a path from the power supply to the ground in this interval, and is defined as

t t3  tsat 3  r = =  +  Esc VDD ∫ I scdt VDD  ∫ Iscdt ∫ I scdt (29) t2  t2 tsat 

As shown in Figure 4, Isc is negative until t2 (when it becomes zero). In addition, t3 represents the point in time when Isc becomes zero again when the PMOS transistor enters the cutoff region.

I PMOS current

Approximated PMOS current Short- circuit current

0 t1 tp t t t 2 tsat 3

Figure 4. PMOS and short-circuit current waveforms of the inverter

In the first integral of (29), a linear approximation of the PMOS transistor current is used

= ' ()− I p S t t1 (30)

’ where S is the slope of Ip (Figure 4) and calculated by equating the PMOS current in t + t linear region (using (6)) to the approximated current (using (29)) at time t = 1 satp . 2

In the second interval of (29), the PMOS is in saturation region and Ip is given by (2).

r Then, Esc is described by

()−  2C V  r = VDD tsat t2 ()' ()+ − ' − gsp DD  Esc  S tsatp t2 2S t1  2  τ   α + α +1    p 1  V t  p V 2 C (31) VDD I DOP  VDDt3  DD satp   DD gsp −  −V  − −V − ()t − t p  τ THP  τ THP   τ 3 satp ()− α      VDD VTHP  

The value of t2 is given by

= + VDD = t2 t1 Cgsp 0 (32) S'τ

The value of t3 is calculated by the equation

α α  τ  p  V τ  p V I   t − THP  − C DD = 0 (33) DOP  ()−    gsp τ  VDD VTHP VDD   VDD 

α ()− τ p We use a Taylor series expansion of the term t VTHP / VDD around the point t τ   satp 3  VTHP  t = + 1−  up to the second coefficient to solve (33). t3 is described as follows 4 4  VDD 

− E + E2 − 4D F = 7 7 7 7 t3 (34) 2D7 where

α I A V  p = DOP 6  DD  D7 α ()− p  τ  VDD VTHP α I B   p = DOP 6 VDD  E7 α (35) ()− p  τ  VDD VTHP α I C V  p C V = DOP 6  DD  − gsp DD F6 α ()− p  τ  τ VDD VTHP with

α − α ()α −1  2  V ⋅ t −  p 2 = p p VDD  − DD satp + VDD VTHP  A6   2  τ   4τ 4  α − α V  V ⋅ t −  p 1 = − p DD − DD satp + VDD VTHP  B6   τ  4τ 4   ⋅ −1   V  VDD tsatp V −V   tsatp 3τ 3τ V  × 1− ()α −1 DD − + DD THP  − − + THP   p τ  τ      4 4   4 4 4 VDD  α  V ⋅ t −  p (36) = − DD satp + VDD VTHP  C6    4τ 4   ⋅ −1   V  VDD tsatp V −V   tsatp 3τ 3τ V   1−α DD − + DD THP  − − + THP   p τ  τ      4 4   4 4 4 VDD  ×     −2 2  α ()α −1 V 2  V ⋅ t V −V   t τ τ V   + p p  DD  − DD satp + DD THP  − satp − 3 + 3 THP   τ  τ      2    4 4   4 4 4 VDD  

The short-circuit energy consumption during the falling transition of the input can be evaluated symmetrically and is expressed as follows: ()−  2C V  f = VDD tsatn t2 ()' ()+ − ' − gsn DD  − VDD I DON × Esc  S tsatn t2 2S t1  α τ ()− n 2   VDD VTHN α + α + (31) V t  n 1 V t  n 1  V 2 C  DD 3 −  −  DD satn −   − DD gsn ()−  VTHN VTHN  t3 tsatn  τ   τ   τ

3. Model Validation

In this section, we illustrate the validity of the analytical model for the short-circuit energy dissipation of the static inverter through comparison of the analytical results to the results of circuit simulations in HSpice. The comparisons are done for a TSMC 0.25µm CMOS technology.

Figure 5 shows the comparison between the calculated and the simulated results of the short-circuit energy consumption of a TSMC 0.25µm inverter with a supply voltage value of 2.5V as a function of the input transition time τ . A capacitive load of 130fF is used for the calculations and the simulations. Table 1 shows the MOSFET model parameters used

13 in the calculations. In simulations, we use level 49 HSpice model parameters for the TSMC 0.25µm transistors. It can be observed from Figure 5 that, our results are very close to the results derived from HSpice simulations. The maximum error is 12.23 % and the average error 7.416 %.

800 HSpice 700 Analytical model 600

500

400

300

switching (fJoules) 200

100 Short-circuit energy dissipation per 0 00.511.522.533.5 Input transition time (nsec)

Figure 5. TSMC 0.25µm inverter short-circuit energy dissipation during switching as a function of the input transition time

Table I MOSFET model parameters used in the analytical model

NMOS PMOS W(µm) 3.36 6.72 L(µm) 0.25 0.25 α 1.07 1.167

IDO(mA) 1.98 1.87 |VDO| (V) 1.167 1.99 |VTH| (V) 0.67 0.63 Cgs (fF) 6 9 Cgd (fF) 7.5 12.5

Figure 6 shows the comparison between the calculated and the simulated results of the short-circuit energy consumption of a TSMC 0.25µm inverter as a function of the input transition time τ for two different values of load capacitance (200fF and 50fF). The value of the supply voltage is 2.5V. The figure shows that the short-circuit energy consumption decreases with increasing load capacitance.

1000

900 HSpice-CL=50fF 800 analytical model-CL=50fF HSpice-CL=200fF 700 analytical model-CL=200fF 600 500 400 300 switching (fJoules) 200 100

Short circuit energy dissipation per 0 00.511.522.533.5 Input transition time (nsec)

Figure 6. TSMC 0.25µm inverter short-circuit energy dissipation during switching as a function of the input transition time for load capacitance values of 50fF and 200fF

Figure 7 shows the simulation and calculated results for a TSMC 0.25µm inverter as a function of the supply voltage. In addition, the figure illustrates a comparison of our analytical model to the model developed in [9] (which we refer to as the Bisdounis model in the figure). The capacitive load is 150fF and the input transition time is 2nsec. The average error of our analytical model, 5.547% is smaller than the average error, 10.674%, of the Bisdounis model. This results from using a more accurate MOSFET current model as we discussed before in Section 1.

450

400 HSpice analytical model 350 Bisdounis model 300

250

200

150

100 switching step (fJoules)

50 Short circuit energy dissipation per 0 1.7 1.9 2.1 2.3 2.5 Vdd (Volts)

Figure 7. TSMC 0.25µm inverter short-circuit energy dissipation as a function of the supply voltage

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