Id Question is the example of ______architecture. A Princeton B Von Neumann C Rockwell D Harvard Answer A Marks 1 Unit 1

Id Question ______bus is unidirectional. A Data B Address C Control D None of these Answer B Marks 1 Unit 1

Id Question Use of ______isolates CPU form frequent accesses to main memory. A Local I/O controller B Expansion interface C structure D System bus Answer C Marks 1 Unit 1

Id Question ______buffers data transfer between system bus and I/O controllers on expansion bus. A Local I/O controller B Expansion bus interface C Cache structure D None of these Answer B Marks 1 Unit 1

Id Question ______Timing involves a clock line. A Synchronous B Asynchronous C Asymmetric D None of these Answer A Marks 1 Unit 1

Id Question -----timing takes advantage of mixture of slow and fast devices, sharing the same bus A Synchronous B asynchronous C Asymmetric D None of these Answer B Marks 1 Unit 1

Id st Question In 1 generation _____language was used to prepare programs. A Machine B Assembly C High level programming D Pseudo code Answer B Marks 1 Unit 1

Id Question The transistor was invented at ______laboratories. A AT &T B AT &Y C AM &T D AT &M Answer A Marks 1 Unit 1

Id Question ______is used to control various modules in the system A Control Bus B Data Bus C Address Bus D All of these Answer A Marks 1 Unit 1

Id Question The disadvantage of single bus structure over multi bus structure is _____ A Propagation delay B Bottle neck because of bus capacity C Both A and B D Neither A nor B Answer C Marks 1 Unit 1

Id Question _____ provide path for moving data among system modules A Control Bus B Data Bus C Address Bus D All of these Answer B Marks 1 Unit 1

Id Question is the example of _____ architecture. A Princeton B Von Neumann C Rockwell D Harvard Answer D Marks 1 Unit 1

Id Question A with more than one CPU allows instruction from different program to be executed simultaneously is called as A Microprocessor B Miniprocessor C super D multiprocessor Answer D Marks 1 Unit 1

Id Question The compact combination of CPU , memory and IO circuits in one System is called A Microcomputer B Minicomputer C Supercomputer D None of above Answer A Marks 1 Unit 1

Id Question A computer system with one CPU or microprocessor is generally referred to____ A Mainframe B Microcomputer C Large computer D None of above Answer B Marks 1 Unit 1

Id Question Performance of system and execution time of system are ___ proportional to each other. A Directly B Inversely C Equally D None of the above Answer B Marks 1 Unit 1

Id Question In pipelined processing common steps involved in instruction processing are_____overlapped

A partially B completely C Randomly D None of the above Answer A Marks 1 Unit 1

Id Question In non pipelined CPU, instructions are executed in___sequence A overlapped B any C fixed D None of the above Answer C Marks 1 Unit 1

Id Question main or primary memory M is____ A ROM B RAM C PROM D None of the above Answer B Marks 1 Unit 1

Id Question Supercomputers mainly used in scientific calculations involving large amounts of vectors and matrix calculations are some times referred as___ A super processor B C Parallel processor D Scientific processor Answer B Marks 1 Unit 1

Id Question A control signal can be ____ A Memory read B Memory write C I/ O read D All of these Answer D Marks 1

Id Question1 In Von Neumann Machine ___ feature was responsible for performance bottleneck. A Stored program B Separate memory for data and code C I/O access D None of these Answer A Marks 1 Unit 1

Id Question2 CPU Means ___ A Control Processing Unit B Control Programming Unit C D Central Programming Unit Answer C Marks 1 Unit 1

Id Question3 Key concept of stored program was introduced by____ A Safwat G. Zaky B C j. Hays D Stalling William Answer B Marks 1 Unit 1

Id Question4 Which of the following operation are involved in an ? A Opcode decoding B Instruction execution C Instruction fetching D All of these Answer D Marks 1 Unit 1

Id Question5 ___stores address of next instruction to be executed. A AR B AC C PC D IR Answer C Marks 1 Unit 1

Id Question6 ____keep track of execution of a program. A Program B Instruction Register C General Purpose Register D Answer A Marks 1 Unit 1

Id Question7 ___contains the data to be written into or read out of address location. A MAR B PC C MDR D IR Answer C Marks 1 Unit 1

Id Question8 In IAS actual word transfer take place between memory and ___ A AC B AR C DR D IR Answer C Marks 1 Unit 1

Id Question9 Data register of IAS is __wide. A 16-bit B 20-bit C 40-bit D 48-bit Answer C Marks 1 Unit 1

Id Question1 AR in IAS is ___ wide. 0 A 12-bit B 14-bit C 16-bit D 18-bit Answer A Marks 1 Unit 1

Id Question1 Program of IAS fetches ____ instruction 1 simultaneously. A Two B Three C Four D Six Answer A Marks 1 Unit 1

Id Question1 In IAS machine, IBR stores _____ instruction. 2 A Immediately executable B Later executable C Currently executing D Aborted type Answer B Marks 1 Unit 1

Id Questions In IAS machine, IR stores _____ instruction. 13 A Immediately executable B Later executable C Currently executing D Aborted type Answer A Marks 1 Unit 1

Id Question1 ______Architecture shows separate memory banks for 4 data and programs. A Princeton B Harvard C Von Neumann D Rockwell Answer B Marks 1 Unit 1

Id Question1 shows features of executing 5 instruction in ______instruction cycle than von Neumann. A More B Double C Reduced D Exactly half Answer C Marks 1 Unit 1

Id Question1 ______Architecture uses both RISC and CISC 6 architectures. A Von Neumann B Harvard C Babbage D None of these Answer A Marks 1 Unit 1

Id Question1 In IAS machine, program control unit fetches………….. 7 instructions simultaneously from memory A One B Two C Three D four Answer B Marks 1 Unit 1

Id Question1 IAS machines are designed to all bits of binary 8 numbers….. A Randomly B Simultaneously C Serially D None of the above Answer B Marks 1 Unit 1

Id Question1 In CPU of IAS computer who issues control signals to 9 data processing unit, memory and other circuits for execution of instruction? A PC B Program Control Unit PCU C Accumulator AC D Instruction Register IR Answer B Marks 1 Unit 1

Id Question2 In IAS Computer ____fetches and interprets the 0 instruction in memory and causes them to be executed. A ALU B Control Unit C Accumulator D Program counter Answer B Marks 1 Unit 1

Id Question2 In original Von Neumann Machine, memory unit consists 1 of ___ storage location of __bits each. A 2048,16 B 4096,20 C 4096,60 D 4096,40 Answer D Marks 2 Unit 1

Id Question2 In Original IAS Machine ,storage location was referred to 2 as ____ A Byte B Word C Digit D Number Answer B Marks 1 Unit 1

Id Question2 In IAS machine, data and code have _____memory. 3 A Same B Separate C Distinct D More Answer A Marks 1 Unit 1

Id Question1 The three main parts of a stored programmed computer are A CPU , memory, I/ O B Register, memory control unit C CPU, register, ALU D CPU, I/ O , control unit Answer A Marks 1 Unit 1

Id Question2 CPU takes___ time to obtain word from memory than one of its internal register A Same B longer C Lesser D Zero Answer B Marks 1 Unit 1

Id Question3 If performance of system A is 2times the performance of system B then execution times for system A is ____as of execution time for system B. A half B 2 times C same D None of above Answer A Marks 1 Unit 1

Id Question4 To enhance the speed of processor, small memory unit placed between CPU and main memory M is called______A Program memory B Stack memory C Cache memory D Dynamic memory Answer C Marks 1 Unit 1

Id Question5 Cache memory can store______A Only instructions B Instructions and data C Only data D None of the above Answer B Marks 1 Unit 1

Id Question6 Cache memory is usually___than main memory. A bigger B smaller C faster D (B) and (C) both Answer D Marks 1 Unit 1

Id Question7 Most I/O operation are ___memory operation A easier B faster C slower D None of the above Answer C Marks 1 Unit 1

Id Question8 Major component of most I/O system is set of ___memory devices A secondary B primary C cache D None of the above Answer A Marks 1 Unit 1

Id Question9 I/O devices are attached to host computer by means of___ A I/O ports B Memory slots C Control bus D None of the above Answer A Marks 1 Unit 1

Id Question1 In early supercomputer parallel processing was heavily 0 depend on___ A Sequential processing B Random processing C Pipeline processing D Nonpipeline processing Answer C Marks 1 Unit 1

Id Question Collection of data, address and control Bus is usually 1 referred as____. A Processor bus B system bus C local bus D complete bus Answer B Marks 1 Unit 1

Id Question Address bus is___. 2 A multidirectional B bidirectional C unidirectional D A and B both Answer C Marks 1 Unit 1

Id Question In a single bus structure ____can communicate with each 3 other at a time Over a single bus. A only 2 units B no unit C all the units D None of the above Answer A Marks 1 Unit 1

Id Question CPU can read data from memory and I/O And write data to 4 memory and I/O with ___data bus. A multidirectional B unidirectional C bidirectional D none of the above Answer C Marks 1 Unit 1

Id Question Performance of computer system with single bus structure 5 _____if large number of devices are connected to common System bus. A decreases B increases C remains same D none of the above Answer A Marks 1 Unit 1

Id Question When the same bus is used for more than one function at 6 different time zone it is Called as _____. A shared bus B common bus C system bus D multiplexed bus Answer D Marks 1 Unit 1

Id Question The occurrence of one event on a bus follows and depends 7 on occurrence of previous event in ___. A synchronous timing B asynchronous timing C shared timing D none of the above Answer B Marks 1 Unit 1

Id Question ______bus is used to connect major computer 8 components. A Address B Data C Control D System Answer D Marks 1 Unit 1

Id Question Data Bus is______9 A Unidirectional B Bidirectional C Unidirectional &Bidirectional D None of these Answer B Marks 1 Unit 1

Id Question ______bus width decides the number of bits transferred a 10 time A Data B Address C Control D system Answer A Marks 1 Unit 1

Id Question ______bus width decides the range of locations that can 11 be accessed A Data B Address C Control D system Answer B Marks 1 Unit 1

Id Question What is the benefit of physically dedicated bus? 12 A cheaper B less bus contention C overall system size decreases D none of these Answer B Marks 1 Unit 1

Id Question What is connected between processors bus &high speed 13 bus? A SCSI B LAN C Bridge D local bus Answer C Marks 1 Unit 1

Id Question What is the Specialty of high performance bus architecture 14 over traditional bus architecture? A Expansion bus B local bus C high speed bus D none of these Answer C Marks 1 Unit 1

Id Question What is the impact if the width of data bus is increased? 15 A reduced speed of data transfer B Greater no of bits transferred at one time C Greater range of memory location referenced D none of these Answer B Marks 1 Unit 1

Id Question What is the impact of increasing address bus width? 16 A Speedy data transfer B large no of data transfer C increased addressing capacity D decreased addressing capacity Answer C Marks 1 Unit 1

Id Question1 For unsigned 8-bit binary numbers the decimal range is______A 0 to 127 B 255 to 127 C 0 to 255 D None of these Answer C Marks 1 Unit 1

Id Question2 Forming the 2 s complement of a number involves ____ 1 to the 1's complement of the number. A multiplying B subtracting C adding D both (B) and (C) Answer C Marks 1 Unit 1

Id Question3 1's complement representation is nothing but bit-by-bit ___ operation' A OR B AND C EX-OR D NOT Answer D Marks 1 Unit 1

Id Question4 2's complement of (11001)2 is____ A (00111)2 B (00110)2 C (11000)2 D All the above Answer A Marks 1 Unit 1

Id Question5 2's complement of (11000100)2 is___ A 00111100 B 00111011 C 11001100 D 10111011 Answer A Marks 1 Unit 1

Id Question6 1's complement of (01011011)2 is____ A 10100100 B 00111000 C 10111011 D None of these Answer A Marks 1 Unit 1

Id Question7 The highest positive decimal number represented in signed binary numbers is___the highest positive decimal number for unsigned binary numbers of a fixed number of bits. A double B equal C half D triple Answer C Marks 1 Unit 1

Id Question8 The configuration of cascaded connection of n full , where the catties must Propagate through this cascade, it called____. A n-bit ripple carry adder B m-bit ripple carry adder C (n+1)-bit ripple carry adder D (m+1)- bit ripple carry adder Answer A Marks 1 Unit 1

Id Question9 LSB of a number means A Low Sequence Bit B Low Sequence Byte C Least Significant Bit D Least Significant Byte Answer C Marks 1 Unit 1

Id Question1 1's complement + ___ = 2's complement 0 A 1 B 2 C 3 D -1 Answer A Marks 1 Unit 1

Id Question1 In 1's complement subtraction when carry is generated it 1 is A ignored B added to final result C subtracted from final result D ignored and 1's complement of final result is done" Answer B Marks 1 Unit 1

Id Question1 In 2's complement subtraction when carry is generated it 2 is A ignored B added to final result C subtracted from final result D ignored and 1's complement of final result is done" Answer A Marks 1 Unit 1

Id Question1 To solve Problem of representation of negative exponent in floating Point number, _____ is added to the true exponent' A packed bias value B unpacked bias value C bias value D scaling factor Answer C Marks 2 Unit 1

Id Question2 _____bits are reserved for signed exponent in IEEE 754 standard for a double-precision representation of floating numbers. A 8 B 16 C 11 D 18 Answer C Marks 2 Unit 1

Id Question3 ______bits are reserved for mantissa in IEEE 754 standard for a single-precision presentation of floating point numbers. A 16 B 20 C 23 D 32 Answer C Marks 2 Unit 1

Id Question4 _____bits are reserved for mantissa in IEEE 754 standard for a double-precision representation of floating point numbers. A 16 B 32 C 52 D 64 Answer C Marks 2 Unit 1

Id Question5 In integer numbers, radix point is assumed to be to the _____of the right most digit. A right B left C a or b D none of these Answer A Marks 2 Unit 1

Id Question6 Floating point number system allows the representation of number having ______. A integer part B fractional part C integer and fractional part D integer or fractional part Answer C Marks 2 Unit 1

Id Question1 Booth's algorithm generates _____bit product for n-bit multiplication. A n B 2n C 3n D 4n Answer B Marks 2 Unit 1

Id Question2 What is the product of following multiplication: -13 * +11 in binary? A 11110001 B 1101110001 C 1001110001 D 1001110 Answer B Marks 2 Unit 1

Id Question3 Using bit pair recoding technique, what is the multiplier (-6)10 in bit pair recorded form A [-1 +1] B [-1 0] C [-1 -2] D [+1 -2] Answer C Marks 2 Unit 1

Id Question4 Identify worst case multiplier according to Booth's algorithm. A 10101010 B 10000000 C 10111111 D 11100000 Answer A Marks 2 Unit 1

Id Question5 Bit pair recording form for multiplication 111010 is A [0 +1 -2] B [0 -1 -2] C [0 -1 +2] D [0 +1 +2] Answer B Marks 2 Unit 1

Id Question6 In Booth’s algorithm, if Q0 = 0 and Q-1 = 0 in multiplier Q then it will perform which operation next?

A A=A-M

B A=A+M

C Arithmetic right shift of A, Q and Q-1

D A=M-A

Answer C Marks 2 Unit 1

Id Question7 In Booth’s algorithm, if Q0 =1 and Q-1 = 1 of multiplier Q then it will perform which operation next?

A A=A-M

B A=A+M

C A=M-A D Arithmetic right shift of A, Q and Q-1

Answer D Marks 2 Unit 1

Id Question8 In Booth’s algorithm, if Q0 = 1 and Q-1 = 0 of multiplier Q, then it will perform which operation next?

A A=A-M

B A=A+M

C Arithmetic right shift of A, Q and Q-1

D A=M-A

Answer A Marks 2 Unit 1

Id Question9 In Booth’s algorithm, if Q0=0 and Q-1=1 of multiplier Q then it will perform which operation next.

A A=A-M

B A=A+M

C Arithmetic right shift of A, Q and Q-1

D A=M-A

Answer B Marks 2 Unit 1

Id Question10 In Booth’s bit-pair recoding, what version of multiplicand M will be selected if consecutive multiplier bits are 001?

A 0*M

B +1*M

C -1*M

D +2*M

Answer B Marks 2 Unit 1

Id Question11 In Booth’s bit-pair recoding, what version of multiplicand M will be selected if consecutive multiplier bits are 010?

A 0*M

B +1*M

C -1*M

D +2*M

Answer B Marks 2 Unit 1

Id Question12 In Booth’s bit-pair recoding, what version of multiplicand M will be selected if consecutive multiplier bits are 011?

A 0*M

B +1*M

C -1*M D +2*M

Answer D Marks 2 Unit 1

Id Question13 In Booth’s bit-pair recoding, what version of multiplicand M will be selected if consecutive multiplier bits are 100?

A 0*M

B +1*M

C +2*M

D -2*M

Answer D Marks 2 Unit 1

Id Question14 In Booth’s bit-pair recoding, what version of multiplicand M will be selected if consecutive multiplier bits are 101?

A 0*M

B +1*M

C -1*M

D +2*M

Answer C Marks 2 Unit 1

Id Question15 In Booth’s bit-pair recoding, what version of multiplicand M will be selected if consecutive multiplier bits are 110?

A 0*M

B +1*M

C -1*M

D +2*M

Answer C Marks 2 Unit 1

Id Question16 In Booth’s bit-pair recoding, what version of multiplicand will be selected if consecutive multiplier bits are 111?

A 0*M

B +1*M

C -1*M

D +2*M

Answer A Marks 2 Unit 1

Id Question17 Using Booth's Algorithm, multiply +13 and -6. What is product?

A 1100110010

B 1110110010 C 101100111

D 110110011

Answer B Marks 2 Unit 1

Id Question18 Using Booth's Algorithm, multiply +15 and -5. What is product?

A 1100110010

B 1110110010

C 101100111

D 1110110101

Answer D Marks 2 Unit 1

Id Question19 Using Booth's Algorithm, multiply -12 and +11. What is product?

A 1001111100

B 1101111100

C 1101111101

D 101111101

Answer B Marks 2 Unit 1

Id Question20 Multiply the following numbers represented in 2's complement notation using Booth's Algorithm.

Multiplicand= 10011, Multiplier = 01011

A 1101110001

B 1101110000

C 1001110001

D 1011100010

Answer A Marks 2 Unit 1