Id Question Microprocessor is the example of _______ architecture. A Princeton B Von Neumann C Rockwell D Harvard Answer A Marks 1 Unit 1 Id Question _______ bus is unidirectional. A Data B Address C Control D None of these Answer B Marks 1 Unit 1 Id Question Use of _______isolates CPU form frequent accesses to main memory. A Local I/O controller B Expansion bus interface C Cache structure D System bus Answer C Marks 1 Unit 1 Id Question _______ buffers data transfer between system bus and I/O controllers on expansion bus. A Local I/O controller B Expansion bus interface C Cache structure D None of these Answer B Marks 1 Unit 1 Id Question ______ Timing involves a clock line. A Synchronous B Asynchronous C Asymmetric D None of these Answer A Marks 1 Unit 1 Id Question -----timing takes advantage of mixture of slow and fast devices, sharing the same bus A Synchronous B asynchronous C Asymmetric D None of these Answer B Marks 1 Unit 1 Id st Question In 1 generation _____language was used to prepare programs. A Machine B Assembly C High level programming D Pseudo code Answer B Marks 1 Unit 1 Id Question The transistor was invented at ________ laboratories. A AT &T B AT &Y C AM &T D AT &M Answer A Marks 1 Unit 1 Id Question ______is used to control various modules in the system A Control Bus B Data Bus C Address Bus D All of these Answer A Marks 1 Unit 1 Id Question The disadvantage of single bus structure over multi bus structure is _____ A Propagation delay B Bottle neck because of bus capacity C Both A and B D Neither A nor B Answer C Marks 1 Unit 1 Id Question _____ provide path for moving data among system modules A Control Bus B Data Bus C Address Bus D All of these Answer B Marks 1 Unit 1 Id Question Microcontroller is the example of _____ architecture. A Princeton B Von Neumann C Rockwell D Harvard Answer D Marks 1 Unit 1 Id Question A computer with more than one CPU allows instruction from different program to be executed simultaneously is called as A Microprocessor B Miniprocessor C super processor D multiprocessor Answer D Marks 1 Unit 1 Id Question The compact combination of CPU , memory and IO circuits in one System is called A Microcomputer B Minicomputer C Supercomputer D None of above Answer A Marks 1 Unit 1 Id Question A computer system with one CPU or microprocessor is generally referred to____ A Mainframe B Microcomputer C Large computer D None of above Answer B Marks 1 Unit 1 Id Question Performance of system and execution time of system are ___ proportional to each other. A Directly B Inversely C Equally D None of the above Answer B Marks 1 Unit 1 Id Question In pipelined processing common steps involved in instruction processing are_____overlapped A partially B completely C Randomly D None of the above Answer A Marks 1 Unit 1 Id Question In non pipelined CPU, instructions are executed in___sequence A overlapped B any C fixed D None of the above Answer C Marks 1 Unit 1 Id Question Computers main or primary memory M is____ A ROM B RAM C PROM D None of the above Answer B Marks 1 Unit 1 Id Question Supercomputers mainly used in scientific calculations involving large amounts of vectors and matrix calculations are some times referred as___ A super processor B Vector processor C Parallel processor D Scientific processor Answer B Marks 1 Unit 1 Id Question A control signal can be ____ A Memory read B Memory write C I/ O read D All of these Answer D Marks 1 Id Question1 In Von Neumann Machine ___ feature was responsible for performance bottleneck. A Stored program B Separate memory for data and code C I/O access D None of these Answer A Marks 1 Unit 1 Id Question2 CPU Means ___ A Control Processing Unit B Control Programming Unit C Central Processing Unit D Central Programming Unit Answer C Marks 1 Unit 1 Id Question3 Key concept of stored program was introduced by____ A Safwat G. Zaky B John Von Neumann C j. Hays D Stalling William Answer B Marks 1 Unit 1 Id Question4 Which of the following operation are involved in an instruction cycle? A Opcode decoding B Instruction execution C Instruction fetching D All of these Answer D Marks 1 Unit 1 Id Question5 ___stores address of next instruction to be executed. A AR B AC C PC D IR Answer C Marks 1 Unit 1 Id Question6 ____keep track of execution of a program. A Program Counter B Instruction Register C General Purpose Register D Memory Address Register Answer A Marks 1 Unit 1 Id Question7 ___contains the data to be written into or read out of address location. A MAR B PC C MDR D IR Answer C Marks 1 Unit 1 Id Question8 In IAS actual word transfer take place between memory and ___ A AC B AR C DR D IR Answer C Marks 1 Unit 1 Id Question9 Data register of IAS is __wide. A 16-bit B 20-bit C 40-bit D 48-bit Answer C Marks 1 Unit 1 Id Question1 AR in IAS is ___ wide. 0 A 12-bit B 14-bit C 16-bit D 18-bit Answer A Marks 1 Unit 1 Id Question1 Program control unit of IAS fetches ____ instruction 1 simultaneously. A Two B Three C Four D Six Answer A Marks 1 Unit 1 Id Question1 In IAS machine, IBR stores _____ instruction. 2 A Immediately executable B Later executable C Currently executing D Aborted type Answer B Marks 1 Unit 1 Id Questions In IAS machine, IR stores _____ instruction. 13 A Immediately executable B Later executable C Currently executing D Aborted type Answer A Marks 1 Unit 1 Id Question1 _______ Architecture shows separate memory banks for 4 data and programs. A Princeton B Harvard C Von Neumann D Rockwell Answer B Marks 1 Unit 1 Id Question1 Harvard architecture shows features of executing 5 instruction in _______ instruction cycle than von Neumann. A More B Double C Reduced D Exactly half Answer C Marks 1 Unit 1 Id Question1 ________ Architecture uses both RISC and CISC 6 architectures. A Von Neumann B Harvard C Babbage D None of these Answer A Marks 1 Unit 1 Id Question1 In IAS machine, program control unit fetches………….. 7 instructions simultaneously from memory A One B Two C Three D four Answer B Marks 1 Unit 1 Id Question1 IAS machines are designed to process all bits of binary 8 numbers….. A Randomly B Simultaneously C Serially D None of the above Answer B Marks 1 Unit 1 Id Question1 In CPU of IAS computer who issues control signals to 9 data processing unit, memory and other circuits for execution of instruction? A Program Counter PC B Program Control Unit PCU C Accumulator AC D Instruction Register IR Answer B Marks 1 Unit 1 Id Question2 In IAS Computer ____fetches and interprets the 0 instruction in memory and causes them to be executed. A ALU B Control Unit C Accumulator D Program counter Answer B Marks 1 Unit 1 Id Question2 In original Von Neumann Machine, memory unit consists 1 of ___ storage location of __bits each. A 2048,16 B 4096,20 C 4096,60 D 4096,40 Answer D Marks 2 Unit 1 Id Question2 In Original IAS Machine ,storage location was referred to 2 as ____ A Byte B Word C Digit D Number Answer B Marks 1 Unit 1 Id Question2 In IAS machine, data and code have _____memory. 3 A Same B Separate C Distinct D More Answer A Marks 1 Unit 1 Id Question1 The three main parts of a stored programmed computer are A CPU , memory, I/ O B Register, memory control unit C CPU, register, ALU D CPU, I/ O , control unit Answer A Marks 1 Unit 1 Id Question2 CPU takes___ time to obtain word from memory than one of its internal register A Same B longer C Lesser D Zero Answer B Marks 1 Unit 1 Id Question3 If performance of system A is 2times the performance of system B then execution times for system A is ____as of execution time for system B. A half B 2 times C same D None of above Answer A Marks 1 Unit 1 Id Question4 To enhance the speed of processor, small memory unit placed between CPU and main memory M is called_______ A Program memory B Stack memory C Cache memory D Dynamic memory Answer C Marks 1 Unit 1 Id Question5 Cache memory can store_______ A Only instructions B Instructions and data C Only data D None of the above Answer B Marks 1 Unit 1 Id Question6 Cache memory is usually___than main memory. A bigger B smaller C faster D (B) and (C) both Answer D Marks 1 Unit 1 Id Question7 Most I/O operation are ___memory operation A easier B faster C slower D None of the above Answer C Marks 1 Unit 1 Id Question8 Major component of most I/O system is set of ___memory devices A secondary B primary C cache D None of the above Answer A Marks 1 Unit 1 Id Question9 I/O devices are attached to host computer by means of___ A I/O ports B Memory slots C Control bus D None of the above Answer A Marks 1 Unit 1 Id Question1 In early supercomputer parallel processing was heavily 0 depend on___ A Sequential processing B Random processing C Pipeline processing D Nonpipeline processing Answer C Marks 1 Unit 1 Id Question Collection of data, address and control Bus is usually 1 referred as____.