Coarse Grain Reconfigurable Architectures

Reiner Hartenstein, University of Kaiserslautern, Germany [email protected] http://hartenstein.de

Enabling Technologies for Reconfigurable Computing Schedule Xputer Lab November 21, 2001, Tampere, Finland University of Kaiserslautern

time slot 08.30 – 10.00 Reconfigurable Computing (RC) Reiner Hartenstein Enabling Technologies for 10.00 – 10.30 coffee break University of 10.30 – 12.00 Stream-based Computing for RC Kaiserslautern Reconfigurable Computing 12.00 – 14.00 lunch break

14.00 – 15.30 Resources for RC Part 3: 15.30 – 16.00 coffee break Resources for RC 16.00 – 17.30 FPGAs: recent developments

>> Configware Industry Configware heading for mainstream

University of Kaiserslautern University of Kaiserslautern • Configware market taking off for mainstream • FPGA-based designs more complex, even SoC • Configware Industry • No design productivity and quality without good configware libraries (soft IP cores) from various • Terminology application areas. • Growing no. of independent configware houses • MoPL data-procedural language (soft IP core vendors) and design services • Xputer architecture and circuitry • AllianceCORE & Reference Design Alliance • Currently the top FPGA vendors are the key http://www.uni-kl.de innovators and meet most configware demand.

OS for PLDs Xilinx Alliances University of Kaiserslautern University of Kaiserslautern

• separate EDA software market, comparable • The Software • The Xilinx XtremeDSP to the compiler / OS market in computers, AllianceEDA Program Initiative (with Mentor • Cadence, Mentor, Synopsys just jumped in. • ... Xilinx Inc.'s Graphics) • < 5% Xilinx / Altera income from EDA SW Foundation... • MathWorks / Xilinx •# • free WebPACK Alliance. downloadable tool • The Wind River / Xilinx palette alliance

Enabling Technologies for System-on-Chip Development, Reconfigurable Computing Architectures November 19-20, 2001, Tampere, Finland and Methodologies for System-on-Chip; http://www.cs.tut.fi/soc/ Reiner Hartenstein, Monday, November 19, 10:15 - 11:00 hrs. Reiner Hartenstein, University of Kaiserslautern, Germany [email protected] http://hartenstein.de

The Software Alliance EDA Program The Xilinx AllianceCORE program Xputer Lab University of Kaiserslautern University of Kaiserslautern a cooperation between Xilinx and third-party provides a wide Acugen Software, IKOS Systems, core developers, to produce a broad selection selection of EDA tools Agilent Innoveda, of industry-standard solutions for use in Xilinx platforms. - Partners are: EEsof EDA, Mentor Amphion Semiconductor, Ltd. Aldec, Graphics, ARC Cores MemecCore Mentor Graphics helps leading EDA Aptix, MiroTech, CAST, Inc. vendors to integrate DELTATEC Inventra Auspy Development, Model Technoloy, NewLogic Technologies, Inc. (Europe) Xilinx Alliance software Derivation Systems, Inc. Cadence, Protel International, Dolphin Integration (Grenoble) NMI Electronics tightly into their tools Celoxica, Simucad, Eureka Technology Inc. Paxonet Communications, Inc. Perigee, LLC SynaptiCAD, Frontier Design Inc. Dolphin Integration, GV & Associates, Inc. Rapid Prototypes Inc. Elanix, Synopsys, inSilicon Corporation sci-worx GmbH (Hannover, Germany) Exemplar, Synplicity, iCODING Technology Inc. SysOnChip Loarant Corporation TILAB (Telecom Italia Lab) Flynn Systems, Translogic, Mindspeed Technologies VAutomation Hyperlynx, Virtual Computer Corporation. - A Conexant Business Virtual IP Group, Inc. (formerly Applied Telecom) | XYLON.

The Xilinx Reference Design Alliance Program The Xilinx University Program

University of Kaiserslautern University of Kaiserslautern

The Xilinx Reference Design Alliance Program helps The Xilinx University Program provides the development of multi-component reference designs that incorporate Xilinx devices and other • Xilinx Student Edition Software, semiconductors. • Professor Workshops, The designs are fully functional, but no warranties, • a Xilinx University User Group, no liability. Partners are:. • Presentation Materials and Lab Files, JK microsystems, Inc. • Course Examples, ADI Engineering LYR Technologies • Research, Innovative Integration NetLogic Microsystems • Books, etc.

Altera offers over a Altera offers over a University of Kaiserslautern hundred IP cores (1) University of Kaiserslautern hundred IP cores (2) Altera offers over a hundred IP cores like, for example: from Altera | Modelware • modulator, AMIRIX Systems, Inc. Ncomm, Inc. • controller, • synchronizer, Amphion Semiconductor, Ltd. NewLogic Technologies • UART, • DDR SDRAM controller, Arasan Chip Systems, Inc. Northwest Logic • microprocessor, • Hadamar transform, CAST, Inc. Nova Engineering, Inc. • decoder, • interrupt controller, Digital Core Design Palmchip Corporation • bus control, • Real86 16 bit microprocessor, Eureka Technology Inc. Paxonet Communications • USB controller, • floating point, HammerCores PLD Applications • PCI bus interface, • FIR filter, Innocor Sciworx • viterbi controller, • discrete cosine, Ktech Telecommunications, Inc. Simple Silicon • fast Ethernet • ATM cell processor, Lexra Computing Engines Tensilica • MAC receiver or transmitter, • and many others. Mentor Graphics - Inventra TurboConcept.

Altera IP core design services Altera Certified Design Center Xputer Lab University of Kaiserslautern University of Kaiserslautern (CDC) Program

Certified Design Center (CDC) Program:

Altera IP core design • Barco Silex services are available • El Camino GmbH from: • Excel Consultants • Plextek • Reflex Consulting • Northwest Logic • Sci-worx • Tality • Zaiq Technologies.

The Altera Consultants Devlopment boards University of Kaiserslautern Alliance Program (ACAP): University of Kaiserslautern

Devlopment boards are offered from: • Altera The Altera Consultants Alliance • El Camino GmbH Program (ACAP): lists • Gid'el Limited • Nova Engineering, Inc. •41 offices in North America and • PLD Applications •29 in the rest of the world. • Princeton Technology Group • RPA Electronics Design, LLC • Tensilica.

Consultants and services not listed Consultants and services not University of Kaiserslautern by Xilinx nor Altera (index) University of Kaiserslautern listed by Xilinx nor Altera (1)

Flexibilis, Tampere, Finland, Algotronix, Edinburgh, Reconfigurable Computing and FPL in Algotronix, Edinburgh, Geoff Bostock Designs, Wiltshire, England, software radio, communications and computer security Great River Technology, Alberquerque, NM, Andraka Consulting Group Andraka Consulting Group high performance FPGA designs for Arkham Technology, Pasadena, CA New Horizons GB Ltd, United Kingdom, DSP applications North West Logic Barco Silex, Louvain-la-Neuve, Belgium, Silicon System Solutions, Canterbury, Australia, Arkham Technology, Pasadena, low cost IP cores for Xilinx and Bottom Line Technologies, Milford, NJ Smartech, Tampere, Finland, Atmel, embedded processor, DSP, wireless communication, Codelogic, Helderberg, South Africa, COM / CORBA / DirectX, client-server database programming, Tekmosv, Austin, Texas, software internationalization, PCB design Coelacanth Engineering, Norwell, MASS The Rockland Group, Garden Valley, CA Comit Systems, Inc., Santa Clara, CA Nick Tredennick, Los Gatos, California, Barco Silex, Louvain-la-Neuve, Belgium, IP integration boards

EDTN Programmable Logic Design Center Vitesse, for ASIC and FPGA, consultancy, design, sub-contracting

Consultants and services not Consultants and services not Xputer Lab University of Kaiserslautern listed by Xilinx nor Altera (2) University of Kaiserslautern listed by Xilinx nor Altera (3)

Bottom Line Technologies, Milford, New Jersey, FPGA design, FirstPass, Castle Rock, Colorado training, designing Xilinx parts since 1985 Vitesse, ASIC design Codelogic, Helderberg, South Africa, consulting, FPGA design Flexibilis, Tampere, Finland, VHDL IP cores for Xilinx products services Geoff Bostock Designs, Wiltshire, England, FPGA design Coelacanth Engineering, Norwell, Massachusetts, design services, services test development services, in wireless communication, DSP-based Great River Technology, Alberquerque, New Mexico, FPGA instrumentation, mixed-signal ATE design services in digital video and point-to-point data transmission for aerospace, military, and commercial Comit Systems, Inc., Santa Clara, California, DSP, ASIC, broadcasters networking, embedded control in avionics -- FPGA / ASIC design New Horizons GB Ltd, United Kingdom, FPGA design and and system software training, Xilinx specialist EDTN Programmable Logic Design Center North West Logic; FPGA and embedded processor design in digital communications, digital video

Consultants and services not >> Terminology University of Kaiserslautern listed by Xilinx nor Altera (4) University of Kaiserslautern

Silicon System Solutions, Canterbury, Australia, VHDL IP cores for the ASIC and FPGA/CPLD/EPLD markets Smartech, Tampere, Finland, ASIC and FPGA design • Configware Industry Tekmosv, Austin, Texas, Multiple Designs on a Single Gate • Terminology Array, HDL synthesis, design conversions, chip debug, test generation • MoPL data-procedural language The Rockland Group, Garden Valley, California, a TeleConsulting organization about logic design for FPGAs • Xputer architecture and circuitry

Nick Tredennick, Los Gatos, California, investor and http://www.uni-kl.de consultant

Terminology Terminology & Acronyms

University of Kaiserslautern University of Kaiserslautern

• RC: reconfigurable computing Programming Paradigm Platform • RL: reconfigurable logic source • Software (SW): procedural sources* “von Neumann” Hardware Software • Configware (CW): structural sources Soft Machine (w. Coarse grain high level • Hardware (HW): hardwired platforms soft datapaths) Flexware Configware • ASIC: customizable hardwired platforms netlist level • Flexware (FW): reconfigurable platforms RL (FPGA etc.) fine grain Flexware Configware • FPGA: field-programmable gate array

• FPL: field-programmable logic *) note: firmware is SW !

Stream-based Computing (2) Confusing Terminology Xputer Lab University of Kaiserslautern University of Kaiserslautern

Computer Science and EE as well as ist R&D and applicatgion areas suffer from a babylonial confusion. terms: Communication not only between Computer Science and EE, but also • DPU: datapath unit between ist special areas, even between ist different abstrac tion levels is made difficult – mainly because of immature terminology in • DPA: datapath array relation to reconfigurable circuits and their applications. • rDPU: reconfigurable DPU Terms are rarely standardized and often used with drastically • rDPA: reconfigurable DPA different meanings – even within then same special area. Often terms have been so badly coined, that they are not self- • stream-based computing: explanatory, but mesleading. A demonstratory example is the using complex pipe network comparizon of terms used used in VHDL and Verilog. (super-systolic: Kress et al.) Ideal are "intuitive" terms. But often Intuition yields the wrong idea. Whenever a new term appears in teaching, I often have to tell the students, that the term does not mean, what he believes.

. .

[à la Ingo Kreuz] Terms (1) [à la Ingo Kreuz] Terms (2)

University of Kaiserslautern University of Kaiserslautern Term Meaning Example Term Meaning Example data objects of computing Bits, numbers, operands, Hardware hardwired Processor, ASIC “data” property results, any text (also Flexware Reconfigurable FPLA, FPGA, depends on the moment compiler input) lists, (structurally programmable) KressArray of watching graphs, tables, images, ... data stream ordered, also parallel I/O data streams for Firmware Microprogramme (rarely used IBM 360 Computer Family after introduction of RISC proc.) data word lists, systolic or other arrays obtained by scheduling Software procedural programs Word, C, OS, (sequentially executable by a CPU) Compiler, etc. programming personalisation by procedural code or loading programm code structural code: for Configware structural programs, soft for rDPA FPGA (re)configuration configuration, e. g. as a logic IP cores, personalizing CPLD, circuit, state machine, program source text or object procedural oder structural FPGA, or other Flexware datapath, function code for programming

[à la Ingo Kreuz] Terms (3) [à la Ingo Kreuz] Hardware Terms (1)

University of Kaiserslautern University of Kaiserslautern Term Meaning Example machine execution unit, driven by von Neumann Term Meaning Example deterministic sequencer machine boot program simple program to comparable to the „dataflow not a machine, since without (sleeping enable programming starter of the machine“ a deterministic sequencer research - usually saved in motor of a car (exotic concept) area) non-volatile memory CPU Instruction Set Processor ARM, Pentium booting load and execute a ("von Neumann”): program core, boot program counter (instruction sequencer) and DPU - mode of operation: deterministically instruction-driven

[à la Ingo Kreuz] Hardware Terms (2) [à la Ingo Kreuz] Terms on Parallelism (1) Xputer Lab University of Kaiserslautern University of Kaiserslautern Term Meaning Example Term Meaning Example DPU data path unit, processes ALU with parallelism several levels of parallelism parallel processes, operands - no CPU since without registers, distinguished parallelism at sequencer - no maschine multiplexers etc. instruction set level, Computer CPU with RAM and interfaces pipelines, Parallel ensemble of several Computers concurrent parallel processes run on weather prognisis, Computer different CPUs of a parallel complex simulations, computer - may occasionally etc. Xputer deterministically data-driven MoM exchange signals or data Machine, (transport-triggered) - architectures ISP (instruction several CPUs run in parallel VLIW (very long data counter(s) used instead of a (Kaiserslautern) set parallelism) by clocked synchronization instruction word) program counterm computer dataflow indeterministically data-driven (sleeping research machine (execution sequence unpredictable) area)

[à la Ingo Kreuz] Terms on Parallelism (2) [à la Ingo Kreuz] Terms on Parallelism (3)

University of Kaiserslautern University of Kaiserslautern

Term Meaning Example Term Meaning Example pipelining several uniform or different pipelined CPUs, pipe Systolic Array Pipe network with only Matrix computation, DPUs running simultaneously networks, systolic, linear (straight-on, no DSP, DNA sequencing, - connected to a pipeline by etc. branching), uniform etc. buffer registers. pipelines (all DPUs hardwired and with same chaining several uniform or different Schaltnetze, functionality) pipelines DPUs running simultaneously komplexe - connected to a pipeline arithmetische stream-based pipe network, configured image processing, DSP, without buffer registers Operatoren computing arrays before fabrication complex functions and (super-systolic arrays) algorithms Pipe network Ensemble of DPUs, also systolisc arrays, multiple pipelines, also with stream-based (coarse grain) stream-based arrays, KressArray irregular or wild structures computing arrays reconf. stream- configurable after based arrays fabrication

[à la Ingo Kreuz] Counterparts >> MoPL data-procedural language

University of Kaiserslautern University of Kaiserslautern category property counterpart programing procedural structural (synthesis, design) mode (classical) - „field-programmable“, PLA „programming“, etc. • Configware Industry machine: controlflow-driven Data-driven: Xputer machine principle of (instruction-driven): v. • Terminology operation Neumann system: instruction-flow-driven Data-stream-based (systolisc • MoPL data-procedural language principle of (parallel computer etc.) array, DPU array, KressArray) operation • Xputer architecture and circuitry

Set-up time during run time; before run time: (datapaths (instruction-driven) FPGA (at compile time) http://www.uni-kl.de switched thru) Gate Array (at fabrication)

Fundamental Ideas available (1) Fundamental Ideas available (2) Xputer Lab University of Kaiserslautern University of Kaiserslautern

• Data Sequencer Methodology

• Data-procedural Languages (Duality w. v. N.) • Programming Xputers • ... supporting memory bandwidth optimization • Similarities to programming computers • Soft Data Path Synthesis Algorithms • How not to get confused by similarities • Parallelizing Loop Transformation Methods

• Compilers supporting Soft Machines • What benefits vs. Computers ?

• SW / CW Partitioning Co-Compilers

Programming Language Paradigms Similar Programming Language Paradigms University of Kaiserslautern University of Kaiserslautern

language category Computer Languages Xputer Languages language category Computer Languages Xputer Languages both deterministic procedural sequencing: traceable, checkpointable both deterministic procedural sequencing: traceable, checkpointable read next instruction, read next data item, goto (instr. addr.), goto (data addr.), read next instruction, read next data object, operation jump (to instr. addr.), jump (to data addr.), goto (instruction addr.), goto (data addr.), sequence instr. loop, loop nesting data loop, loop nesting, jump (to instruction addr.), jump (to data addr.), driven by: no parallel loops, escapes, parallel loops, escapes, sequencing instruction loop, data loop, instruction stream branching data stream branching driven by: instruction loop nesting data loop nesting, state register program counter data counter(s) no parallel loops, parallel data loops, address massive memory computation cycle overhead overhead avoided instruction loop escapes, data loop escapes, instruction stream branching data stream branching Instruction fetch memory cycle overhead overhead avoided parallel memory bank access interleaving only no restrictions

-> Declarations goto PixMap[1,1] JPEG zigzag scan pattern >> Xputer architecture and circuitry EastScan is HalfZigZag; 4 stepUniversity by of Kaiserslautern[1,0] SouthWestScan University of Kaiserslautern end EastScan; uturn (HalfZigZag) SouthScan is step by [0,1] 1 endSouthScan; x NorthEastScan is loop 8 times until [*,1] y 2 step by [1,-1] dataHalfZigZag counter data counter • Configware Industry endloop end NorthEastScan; SouthWestScan is • Terminology loop 8 times until [1,*] 3 step by [-1,1] endloop • MoPL data-procedural language end SouthWestScan; HalfZigZag is EastScan • Xputer architecture and circuitry loop 3 times SouthWestScan

SouthScan http://www.uni-kl.de

GAG = Generic Address GAG Scheme GAG: Address Stepper Xputer Lab Generator GAG: Address Stepper University of Kaiserslautern University of Kaiserslautern

] [ | | B DA 0 L Limit Base stepVector maxStepCount GAG = B0 [ | | | | ] Generic init tag limit Address DA Generator Step L0 B0 L A D A Counter

Limit Address Base + / – =o Stepper Stepper Stepper B0 DA L [ | | | | ] Escape End Clause Detect limit A endExec GAG A Address

Generic Sequence Examples Slider Operation Demo Example University of Kaiserslautern University of Kaiserslautern

L0 DA B0

Limit Address Base address a) b) Slider Stepper Slider floor ceiling F B 0 L0 C GAG DA c) A

DB DL

y x d) e) f) g)

MoM Xputer Architecture MoM Architecture Features

University of Kaiserslautern University of Kaiserslautern

• Scan Cache Size adjustable at run time Smart memory interface • Any other shape than square supported • 2-dimensional memory space

Scan • Supports generic „scan patterns“ Multiple Window – Subject of parallel access transformations „Cache“ rDPA RAM banks – compare Francky Cathoor et al . • Supports visualization

Herz‘ MoM Xputer Architecture MoM Application Examples Xputer Lab University of Kaiserslautern University of Kaiserslautern • Image Processing smart • Grid-based design rule check [1983*] memory – 4 by 4 word scan cache interface – Pattern-matching based Multiple – Our own nMOS „DPLA“ design Scan KressArray RAM banks – design rule violation pixel map automatically Window generated from textual design rules „Cache“ – 256 M&C nMOS, 800 single metal CMOS – Speed-up > 10000 vs. Motorola 68000

*) „machine“ not yet discovered

Schedule >>> Coarse Grain

University of Kaiserslautern University of Kaiserslautern

time slot 08.30 – 10.00 Reconfigurable Computing (RC) 10.00 – 10.30 coffee break 10.30 – 12.00 Stream-based Computingfor RC 12.00 – 14.00 lunch break - END - 14.00 – 15.30 Resources for RC 15.30 – 16.00 coffee break 16.00 – 17.30 FPGAs: recent developments