Génération Automatique D'extensions De Jeux D'instructions De Processeurs

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Génération Automatique D'extensions De Jeux D'instructions De Processeurs Génération automatique d’extensions de jeux d’instructions de processeurs Kevin Martin To cite this version: Kevin Martin. Génération automatique d’extensions de jeux d’instructions de processeurs. Génie logiciel [cs.SE]. Université Rennes 1, 2010. Français. tel-00526133 HAL Id: tel-00526133 https://tel.archives-ouvertes.fr/tel-00526133 Submitted on 13 Oct 2010 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. No d’ordre : 4150 ANNEE´ 2010 THESE` / UNIVERSITE´ DE RENNES 1 sous le sceau de l’Universit´eEurop´eennede Bretagne pour le grade de DOCTEUR DE L’UNIVERSITE´ DE RENNES 1 Mention : Informatique Ecole´ doctorale MATISSE pr´esent´ee par Kevin´ MARTIN pr´epar´ee`al’unit´ede recherche UMR 6074 – Irisa Institut de Recherche en Informatique et Syst`emes Al´eatoires IFSIC Th`ese soutenue `aRennes le 7 septembre 2010 Gen´ eration´ devant le jury compos´ede : automatique Olivier DEFORGES´ Professeur INSA Rennes / pr´esident Daniel ETIEMBLE d’extensions Professeur Universit´eParis Sud 11 / rapporteur de jeux Fred´ eric´ PETROT´ Professeur ENSIMAG / rapporteur Philippe COUSSY d’instructions Maˆıtrede conf´erencesUniversit´eBretagne Sud / examinateur de processeurs Christophe WOLINSKI Professeur Universit´ede Rennes 1 / directeur de th`ese Franc¸ois CHAROT Charg´ede recherche INRIA / co-directeur de th`ese Le temps est assassin et emporte avec lui les rires des enfants Mistral Gagnant Renaud Remerciements Je remercie Olivier D´eforgesqui me fait l’honneur de pr´esiderce jury. Je remercie Daniel Etiemble et Fr´ed´ericP´etrotd’avoir accept´ela charge de rapporteur. Je remercie Philipppe Coussy qui a bien voulu juger ce travail. Je remercie bien sˆurmon directeur de th`ese,Christope Wolinski, et mon co-directeur de th`eseFran¸coisCharot. Je remercie ´egalement le professeur Kuchcinski pour sa collaboration qui a fortement contribu´e`ala r´eussitede ces travaux. Je remercie toute l’´equipe projet INRIA Cairn, en particulier Antoine Floc’h, Erwan Raffin, Steven Derrien, Florent Berthelot, Georges Adouko (en esp´erant qu’il soutienne sa th`eseun jour), Laurent Perraudeau, Charles Wagner, Patrice Quinton, Pasha et Naeem, sans oublier les lannionais Emmanuel Casseau, Daniel M´enard,Daniel Chillet, S´ebastien Pillement, Arnaud Tisserand, et le chef de projet Olivier Sentieys. Un grand merci ´egalement aux assistantes de projet qui m’ont aid´eadministrativement, C´eline,Isabelle, Elise et Nadia. Enfin, je remercie ma famille et mes amis qui m’ont toujours soutenu, mˆemesi ils ne comprenaient rien `ames travaux. Et surtout, un grand merci `ama femme Laouratou qui a mis au monde notre petit gar¸conN’ma¨ıLamine et qui s’en est largement occup´ele temps que je finisse cette th`ese. Merci `atous. Table des matieres` Introduction 1 1 Conception d’ASIP : m´ethodologies et outils 13 1.1 Conception compl`eted’ASIP . 14 1.1.1 Exemple du langage LISA . 14 1.1.2 M´ethodologie . 18 1.2 Conception partielle d’ASIP . 21 1.2.1 Exemple . 21 1.2.2 Architecture des processeurs extensibles . 24 1.2.3 M´ethodologie . 30 1.2.4 Compilation . 32 1.3 Synth`ese. 36 2 L’extension de jeu d’instructions 39 2.1 Quels sont les probl`emes `ar´esoudre? . 40 2.1.1 Motifs g´en´er´esvs motifs pr´ed´efinis . 40 2.1.2 G´en´erationd’instructions . 41 2.1.3 Limites architecturales et technologiques . 44 2.1.4 S´electiond’instructions . 46 2.1.5 Isomorphisme de graphes et de sous-graphes . 47 2.1.6 Exploitation des nouvelles instructions . 49 2.2 Quand les r´esoudre? . 50 2.2.1 A` la conception . 50 2.2.2 A` la vol´ee . 51 2.3 Comment les r´esoudre? . 51 2.3.1 Recherche Tabou . 52 2.3.2 Recuit simul´e. 52 2.3.3 Algorithme g´en´etique . 53 2.3.4 Algorithme de colonies de fourmis . 54 2.3.5 Programmation dynamique . 54 2.3.6 Algorithmes gloutons . 55 2.3.7 Heuristiques . 56 v 2.3.8 S´eparationet ´evaluation . 57 2.3.9 Programmation lin´eairepar nombres entiers . 58 2.3.10 Programmation par contraintes . 59 2.3.11 Comparaison des approches . 60 2.4 Synth`ese. 62 3 L’identification d’instructions 65 3.1 D´efinitions. 65 3.2 Algorithme de g´en´erationde motifs . 66 3.2.1 Expansion d’un motif `apartir d’un nœud graine . 66 3.2.2 Limitation du nombre de motifs : Smart filtering . 67 3.2.3 La contrainte GraphMatch ........................ 68 3.3 Contraintes technologiques et architecturales . 69 3.4 Formalisation pour la programmation par contraintes . 70 3.4.1 Contrainte de connexit´e . 70 3.4.2 Contrainte sur le nombre d’entr´eeset de sorties . 74 3.4.3 Contrainte sur le chemin critique . 76 3.4.4 Contrainte de ressources . 77 3.4.5 Contrainte d’´energie . 77 3.5 R´esultatsd’exp´erimentations . 78 3.5.1 Le processeur cible . 78 3.5.2 Environnement d’ex´ecution . 78 3.5.3 Benchmarks . 78 3.5.4 Couverture maximale . 79 3.5.5 Discussion . 80 3.6 Conclusion . 82 4 S´electiond’instructions et ordonnancement 83 4.1 S´electiond’instructions . 83 4.1.1 D´efinitiond’une occurrence . 83 4.1.2 D´efinitiondu probl`emede s´electiond’instructions . 84 4.1.3 Mod´elisationdu temps d’ex´ecutiond’une occurrence . 90 4.1.4 R´esultatsd’exp´erimentation . 93 4.2 Ordonnancement . 96 4.2.1 Placement . 97 4.2.2 Ordonnanceur . 97 4.2.3 Ordonnancement avec recalage d’instructions . 99 4.2.4 Optimisation sur les transferts de donn´ees. 101 4.2.5 R´esultatsd’exp´erimentation . 104 4.3 Conclusion . 106 5 G´en´erationd’architecture et adaptation du code 107 5.1 Architecture de l’extension . 109 5.1.1 Diff´erents types d’instructions sp´ecialis´ees . 109 5.1.2 Mod`elesd’architecture . 110 5.2 Allocation de registres . 112 5.2.1 Contrainte Diff2 .............................113 5.2.2 Allocation de registres appliqu´eeau mod`ele A . 114 5.2.3 Allocation de registres appliqu´eeau mod`ele B . 118 5.3 G´en´erationdes codes d’op´erationet de la description de l’architecture . 133 5.3.1 G´en´erationdes codes d’op´erations . 133 5.3.2 G´en´erationdu bloc logique sp´ecialis´e. 133 5.3.3 G´en´erationdu chemin de donn´eedes instructions sp´ecialis´ees . 134 5.3.4 Fusion du chemin de donn´ees . 134 5.4 G´en´erationdu code source modifi´e . 135 5.5 G´en´erationpour la simulation SystemC . 135 5.5.1 SystemC . 135 5.5.2 SoCLib . 136 5.5.3 G´en´erationdes instructions sp´ecialis´eespour le mod`eledu NiosII . 136 5.6 Conclusion . 136 6 D´eroulement du flot appliqu´e`al’algorithme GOST 139 6.1 Le flot de conception DURASE . 139 6.1.1 Gecos . 141 6.2 L’algorithme de chiffrement GOST . 143 6.3 D´eroulement du flot ´etape par ´etape appliqu´e`al’algorithme de chiffrement GOST . 143 6.3.1 Param`etresd’entr´ee . 144 6.3.2 Partie frontale . 144 6.3.3 Cr´eationd’une extension . 147 6.3.4 G´en´erationd’architecture . 158 6.3.5 Adaptation du code . 161 6.3.6 Validation par simulation avec SoCLib . 162 6.3.7 R´esum´e . 164 6.4 Proposition d’architecture . 164 6.5 Conclusion . 165 Conclusion 167 Publications 171 Bibliographie 173 Glossaire ALU Arithmetic Logic Unit ASIC Application Specific Integrated Circuit ASIP Application Specific Instruction-set Processor CDFG Control Data Flow Graph CFG Control Flow Graph CIS Composant Instruction Sp´ecialis´ee CPLD Complex Programmable Logic Device DAG Directed Acyclic Graph DFT Data Flow Tree DSP Digital Signal Processor FPGA Field Programmable Gate Array GHDC Graphe Hi´erarchis´eaux D´ependances Conditionn´ees GPP General Purpose Processor HCDG Hierarchical Conditional Dependency Graph ILP Integer Linear Programming IP Intellectual Property ISA Instruction Set Architecture LE Logic Element LUT Look-Up Table MIMD Multiple Instruction Multiple Data MISD Multiple Instruction Single Data MMU Memory Management Unit RISC Reduced Instruction Set Processor RPU Reconfigurable Processing Unit RTL Register Transfer Level SHA Secure Hash Algorithm SIMD Single Instruction Multiple Data SISD Single Instruction Single Data UAL Unit´eArithm´etiqueet Logique VHDL VHSIC Hardware Description Language VHSIC Very High Speed Integrated Circuit VLIW Very Long Instruction Word ix Introduction Les syst`emesembarqu´esont aujourd’hui envahi notre quotidien par le lot de services qu’ils apportent : t´el´ephoniemobile, navigation automobile, multim´edia(photo, vid´eo,musique), assistants ´electroniques,entre autres. Un processeur embarqu´e,simple et peu cher `amettre en œuvre, est la solution id´ealepour de tels syst`emes.Mais pour faire face aux demandes exigeantes en termes de performance, de surface de silicium et de consommation d’´energie,ces syst`emess’appuient sur des solutions mat´eriellesadapt´ees aux besoins des applications. Une strat´egietr`esr´epanduelors de leur conception consiste alors `aassocier des circuits int´egr´essp´ecialis´es`aun processeur g´en´eraliste`abas coˆut. Par exemple, de nombreux produits commerciaux associent un processeur ARM [22] avec des circuits sp´ecialis´es: t´el´ephonemobile (Nokia N97), lecteurs multim´edia(Archos 604), GPS (Mio Moov 500).
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