Coarse Grain Reconfigurable Architectures

Reiner Hartenstein, University of Kaiserslautern, Germany [email protected] http://kressarray.de

Enabling Technologies for Reconfigurable Computing Schedule Xputer Lab July 8, 2002, ENST, Paris, France University of Kaiserslautern

time slot xx.30 – xx.00 Reconfigurable Computing (RC) Reiner Hartenstein Enabling Technologies for xx.00 – xx.30 coffee break University of Reconfigurable Computing and Kaiserslautern xx.30 – xx.00 Design / Compilation Techniques Software / Configware Co-Design xx.00 – xx.00 lunch break

xx.00 – xx.30 Resources for Data-Stream-based RC Part 4: xx.30 – xx.00 Recent developments coffee break xx.00 – xx.30 FPGAs: recent developments

Opportunities by new patent laws ? >> Configware Market

University of Kaiserslautern University of Kaiserslautern

• Configware Market • FPGA Market • to clever guys being keen on patents: • Embedded Systems (Co-Design) • Hardwired IP Cores on Board • Run-Time Reconfiguration (RTR) • don‘t file for patent following details ! • Rapid Prototyping & ASIC Emulation • Evolvable Hardware (EH) • everything shown in this presentation • Academic Expertise • ASICs dead has been published years ago • Soft CPU • HLLs • Problems to be solved

Configware heading for mainstream bleeding edge designs

University of Kaiserslautern University of Kaiserslautern • Configware market taking off for mainstream • Infinite amount of gates not yet available on a chip • FPGA-based designs more complex, even SoC • 3 mio gates (10 mio in 2003 ?) far away from "infinite" • No design productivity and quality without good configware libraries (soft IP cores) from various • Bleeding edge designs only with sophisticated EDA tools application areas. • Excessive optimization needed • Growing no. of independent configware houses • Hardware epertise is inevitable for the designer. (soft IP core vendors) and design services • improve and simplify the design flow the user • AllianceCORE & Reference Design Alliance • provide rich configware libraries of soft IP cores, • Currently the top FPGA vendors are the key • control appl., networking, wireless telecommunication, data innovators and meet most configware demand. communication, embedded and consumer markets.

Enabling Technologies for Reconfigurable Computing and Software / Configware Co-Design, Part 4: ENST, Paris, 8 July 2002 Recent Developments

# Reiner Hartenstein, University of Kaiserslautern, Germany [email protected] http://kressarray.de

Configware (soft IP Products) EDA as the Key Enabler (major EDA vendors) Xputer Lab University of Kaiserslautern University of Kaiserslautern

• For libraries, creation and reuse of configware • Select EDA quality / productivity, not FPGA architectures • To search for IPs see: List of all available IP • EDA often has massive software quality problems • Customer: highest priority EDA center of excellence • The AllianceCORE program is a cooperation between Xilinx and third-party core developers – collecting EDA expertise and EDA user experience – to assemble best possible tool environments • The Xilinx Reference Design Alliance Program – for optimum support design teams • The Xilinx University Program – to cope with interoperability problems – to keep track with the EDA scene as a rapidly moving target • LogiCORE soft IP with LogiCORE PCI Interface. • being fabless, FPGA vendors spend most qualified manpower • Consultants in development of EDA, IP cores, applications , support • Xilinx and Altera are morphing into EDA companies.

OS for FPGAs EDA Software for Xilinx

University of Kaiserslautern University of Kaiserslautern

• separate EDA software market, comparable to •Full design flow from Cadence, Mentor, & Synopsys the compiler / OS market in computers, •Xilinx Software AllianceEDA Program: • Cadence, Mentor, Synopsys just jumped in. –Alliance Series Development System. • < 5% Xilinx / Altera income from EDA SW –Foundation Series Development Systems. • Changing EDA Tools Market • Major configware –Xilinx Foundation Series ISE (Integrated Synthesis Environment) EDA vendors –free WebPOWERED SW w. WebFitter & WebPACK-ISE – Altera – Cadence –StateCAD XE and HDL Bencher – Mentor Graphics –Foundation Base Express – Synopsys –Foundation ISE Base Express – Xilinx

Foundation ISE Base Express Altera EDA

University of Kaiserslautern University of Kaiserslautern • Altera was founded in June 1983 • ModelSim Xilinx Edition • JBits SDK • EDA: synthesis, place & route, and, verification (ModelSim XE) • The Xilinx XtremeDSP • Quartus II: APEX, Excalibur, Mercury, FLEX 6000 families • Forge Compiler Initiative • MAX+PLUS II: FLEX, ACEX & MAX families • Modular Design • MathWorks / Xilinx • Flow with Quartus II: Mentor Graphics, Synopsys, Synplicity deliver a design design software to support Altera SOPC solutions. • Chipscope ILA Alliance • System Generator • Mentor: only EDA vendor w. complete design environment f. APEX • The Xilinx System II incl. IP, design capture, simulation, synthesis, and h/s co- Generator • Wind River / Xilinx verification • XPower alliance • Configware: Altera offers over a hundred IP cores • Third party IP core design services and consultants

Enabling Technologies for Reconfigurable Computing and Software / Configware Co-Design, Part 4: ENST, Paris, 8 July 2002 Recent Developments

# Reiner Hartenstein, University of Kaiserslautern, Germany [email protected] http://kressarray.de

Cadence Mentor Graphics Xputer Lab University of Kaiserslautern University of Kaiserslautern

• FPGA Designer: top-down FPGA design system, • System Design and Verification. • high-level mapping, architecture-specific optimization, • Verilog,VHDL, schematic-level design entry. • PCB design and analysis: • Verilog, VHDL to Synergy (logic synthesis) and FPGA Designer • IC Design and Verification • FPGAs simulated by themselves using Cadence's Verilog- • shifts ASIC design flow to FPGAs (Altera, Xilinx) XL or Leapfrog VHDL simulators and – by FPGA Advantage with IP support • simulated w. rest of the system design w. Logic – by ModuleWare, Workbench board/system verification env‘ment. – Xilinx CORE Generator • Libraries for the leading FPGA manufacturers. – Altera MegaWizard integration,

Synopsys >> FPGA Market

University of Kaiserslautern University of Kaiserslautern

• Configware Market • FPGA Market • FPGA Compiler II • Embedded Systems (Co-Design) • Version of ASIC Design Compiler Ultra • Hardwired IP Cores on Board • Run-Time Reconfiguration (RTR) • Block Level Incremental Synthesis (BLIS) • Rapid Prototyping & ASIC Emulation • Evolvable Hardware (EH) • ASIC <-> FPGA migration • Academic Expertise • ASICs dead • Actel, Altera, Atmel, Cypress, Lattice, • Soft CPU Lucent, Quicklogic, Triscend, Xilinx • HLLs • Problems to be solved

Top 4 PLD Manufacturers 2000 FPGA market 1998 / 1999

University of Kaiserslautern University of Kaiserslautern global sales (mio $) 1999 rank Actel Source: 1998 1999 Lattice 6% Xilinx IC Insights Inc. 1 Xilinx 629 899 15% 42% Meanwhile, 2 Altera 654 837

Xilinx acquired 3 Lattice 206 410 Philips' MOS PLD 4 Actel 154 172 business, 5 Lucent 100 120 Lattice Altera $3.7 Bio purchased Vantis. 6 Cypress 41 43 37% Top 4 PLD Manufacturers 2000 . 7 Quicklogic 30 40 8 Atmel 32 38

Enabling Technologies for Reconfigurable Computing and Software / Configware Co-Design, Part 4: ENST, Paris, 8 July 2002 Recent Developments

# Reiner Hartenstein, University of Kaiserslautern, Germany [email protected] http://kressarray.de

.... into every application .... going into every type of application Xputer Lab [Gordon Bell] University of Kaiserslautern University of Kaiserslautern

• [Dataquest] PLD market > $7 billion by 2003.

• „ fastest growing segment of semiconductor market.“ • IP reuse and "pre-fabricated" components for the efficiency of design and use for PLDs

• FPGAs are going into every type of application.

Xilinx Xilinx Flexware

University of Kaiserslautern University of Kaiserslautern •fabless FPGA semi vendor, San Jose, Ca, founded 1984 • Virtex, Virtex-II, first w. 1 mio system gates. – Virtex-E series > 3 mio system gates. •key patents on FPGAs (expiring in a few years) • Virtex-EM on a copper process & addit. on chip memory f. network switch appl. • The Virtex XCV3200E > 3 million gates, 0.15-micron technology, •Fortune 2001: No. 14 Best Company to work for in (intel: • Spartan, Spartan-XL, Spartan-II no. 42, hp no. 64, TI no. 65). – for low-cost, high volume applications as ASIC replacements •DARPA grant (Nov‘99) to develop Jbits API tools for – Multiple I/O standards, on-chip block RAM, digital delay lock loops internet reconfigurable / upgradable logic (w. VT) – eliminate phase lock loops, FIFOs, I/O xlators , system bus drivers • XC4000XV, XC4000XL/XLA, CPLD: low-cost families •Less brilliant early/mid 90ies (president Curt Wozniak): – rapid development, longer system life, robust field upgradability 1995 market share from 84% down to 62% [Dataquest] – support In-System Programming (ISP), in-board debugging, •As designs get larger, Xilinx losed its advantage (bugfixes – test during manufacturing, field upgrades, full JTAG compliant interface did not require to burn new chips) • CoolRunner: low power, high speed/density, standby mode. • Military & Aerospace: QPRO high-reliability QML certified •meanwhile, weeks of expensive debug time needed • Configuration Storage Devices © 2002, [email protected] 21 http://kressarray.de © 2002, [email protected] 22 http://kressarray.de

Altera Flexware Triscend CSoC

University of Kaiserslautern University of Kaiserslautern

• Newer families: APEX 20KE, APEX 20KC, APEX II, MAX [Kean] 7000B, ACEX 1K, Excalibur, Mercury families. Configurable system logic

– Apex EP20K1500E (0.18-µ), up to 2.4 mio system gates, Digital Filter Display Interface ARM – APEX II (all-copper 0.13-µ) f. data path applications, supports Viterbi A/D Interface many I/O standards. 1-Gbps True-LVDS performance – wQ2001, an ARM-based Excalibur device CSI Socket • Altera mainstream: MAX 7000A, 3000A; FLEX 6000, Configurable System Interconnect (CSI) Bus 10KA, 10KE; APEX 20K families.

• Mature and other : Classic, MAX 7000, 7000S, 9000; Memory Other System Resources FLEX 8000, 10K families.

Enabling Technologies for Reconfigurable Computing and Software / Configware Co-Design, Part 4: ENST, Paris, 8 July 2002 Recent Developments

# Reiner Hartenstein, University of Kaiserslautern, Germany [email protected] http://kressarray.de

>> Embedded Systems (Co-Design) Goal: away from complex design flow Xputer Lab University of Kaiserslautern University of Kaiserslautern

• Configware Market

• FPGA Market Place [à la S. Guccione] Schematics/ and HDL Netlister Netlist • Embedded Systems (Co-Design) Route • Hardwired IP Cores on Board Run-Time Reconfiguration (RTR) • Bitstream • Rapid Prototyping & ASIC Emulation • Evolvable Hardware (EH) • Academic Expertise • ASICs dead • Soft CPU • HLLs HLL Compiler • Problems to be solved

Overcome traditional separate design flow Overcome traditional co-processing design University of Kaiserslautern University of Kaiserslautern separate flow -> JBits Design Flow

[à la S. Guccione] [à la S. Guccione] JBits API

HLL Compiler User Place Java Schematics/ Java Executable Netlister and Compiler HDL Netlist Code Place Route Schematics/ . Netlister and . HDL Netlist Route . . Bitstream Bitstream

User Code Compiler Executable User Compiler Executable Code

Embedded hardw. CPU & memory cores new directions in application development University of Kaiserslautern on chip. University of Kaiserslautern • new directions in application development.

HLL Compiler • aut. partitioning compilers: designer productivity • like CoDe-X (Jürgen Becker, Univ. of Karlsruhe), • supports Run-Time Reconfiguration (RTR), a key FPGA core enabler of error handling and fault correction by partial re-routing the FPGA at run time, as well as HLL Compiler remote patching for upgrading, remote debugging, CPU Memory and remote repair by reconfiguration - even over [à la S. Guccione] core core the internet.

Enabling Technologies for Reconfigurable Computing and Software / Configware Co-Design, Part 4: ENST, Paris, 8 July 2002 Recent Developments

# Reiner Hartenstein, University of Kaiserslautern, Germany [email protected] http://kressarray.de

>> Run-Time Reconfiguration (RTR) CPU use for configuration management Xputer Lab University of Kaiserslautern University of Kaiserslautern

• Configware Market • on-board microprocessor CPU is available • FPGA Market anyhow - even along with a little RTOS • Embedded Systems (Co-Design) • Hardwired IP Cores on Board • use this CPU for configuration management • Run-Time Reconfiguration (RTR) • Rapid Prototyping & ASIC Emulation • Evolvable Hardware (EH) • Academic Expertise • ASICs dead • Soft CPU RTR System Design • HLLs HLL Compiler • Problems to be solved

hard CPU & memory core on same chip Converging factors for RTR

University of Kaiserslautern University of Kaiserslautern

• Converging factors make RTR based system design viable • 1) million gate FPGA devices and co-processing with standard microprocessors are commonplace • direct implementation of complex algorithms in FPGAs. • This alone has already HLL Compiler revolutionized FPGA design. RTR System Design FPGA core JBits • 2) new tools like Xilinx Jbits API software tool suite directly

support coprocessing and RTR. User Java Compiler CPU Memory Java Executable HLL core core Compiler Code

RTR Run-time Mapping

University of Kaiserslautern University of Kaiserslautern

• divides application into a series of sequentially executed stages, each • run-time reconfigurable are: Xilinx VIRTEX FPGA family implemented as a separate execution module. • Partial RTR partitions these stages into finer-grain sub-modules to be • RAs being part of Chameleon CS2000 series systems swapped in as needed. • Using such devices changes many of the basic assumptions • Without RTR, all conf. platforms just ASIC emulators. in the HW/SW co-design process: • needs a new kind of application development environments. • host/RL interaction is dynamic, needs a tiny OS like eBIOS, • directly support development and debugging of RTR appl. also to organize RL reconfiguration under host control • essential for the advancement of configurable computing • typical goal is minimization of reconfiguration latency • will also heavily influence the future system organization (especially important in communication processors), to hide • Xilinx, VT, BYU work on run-time kernels, run-time support, RTR configuration loading latency, and, debugging tools and other associated tools. • Scheduling to find ’best’ schedule for eBIOS calls (C~side). • smaller, faster circuits, simplified hardware interfacing, fewer IOBs; smaller, cheaper packages, simplified software interfaces.

Enabling Technologies for Reconfigurable Computing and Software / Configware Co-Design, Part 4: ENST, Paris, 8 July 2002 Recent Developments

# Reiner Hartenstein, University of Kaiserslautern, Germany [email protected] http://kressarray.de

>> Rapid Prototyping & ASIC Emulation ASIC emulation: a new business model ? Xputer Lab University of Kaiserslautern University of Kaiserslautern

• Configware Market • FPGA Market • ASIC emulation / Rapid Prototyping: to replace simulation • Embedded Systems (Co-Design) • Hardwired IP Cores on Board • Quickturn (Cadence), IKOS (Synopsys), Celaro (Mentor) • Run-Time Reconfiguration (RTR) • from rack to board to chip (from other vendors, e. g. • Rapid Prototyping & ASIC Emulation Virtex and VirtexE family (emulate up to 3 million gates) • Evolvable Hardware (EH) • Academic Expertise • Easy configuration using SmartMedia FLASH cards • ASICs dead • Soft CPU • ASIC emulators will become obsolete within years • HLLs • Problems to be solved • By RTR: in-circuit execution debugging instead of emulation

>> Evolvable Hardware (EH) EH, EM, ...

University of Kaiserslautern University of Kaiserslautern

• Configware Market • "Evolvable Hardware" (EH), "Evolutionary Methods" (EM), • FPGA Market „digital DANN“, "Darwinistic Methods", and biologically inspired electronic systems • Embedded Systems (Co-Design) • Hardwired IP Cores on Board • new research area, also a new application area of FPGAs • Run-Time Reconfiguration (RTR) • revival of cybernetics or bionics: stimulated by technology • Rapid Prototyping & ASIC Emulation • Evolvable Hardware (EH) • „evolutionary“ and „DNA“ metaphor create awareness • Academic Expertise • EM sucks, also thru mushrooming funds in the EU, in • ASICs dead Japan, Korea, and the USA • Soft CPU • HLLs • EM-related international conference series are in their • Problems to be solved stormy visionary phase, like EH, ICES, EuroGP, GP, CEC, GECCO, EvoWorkshops, MAPLD, ICGA

EH, EM, ... >> Academic Expertise

University of Kaiserslautern University of Kaiserslautern

• Shake-out phenomena expected, like in the past with • Configware Market „Artificial Intelligence“ • FPGA Market • Embedded Systems (Co-Design) • should be considered as a specialized EDA scene, • Hardwired IP Cores on Board focusing on theoretical issues. • Run-Time Reconfiguration (RTR) • Genetic algorithms suck - often replacable by more • Rapid Prototyping & ASIC Emulation efficient ones from EDA • Evolvable Hardware (EH) • Academic Expertise • It is recommendable to set-up an interwoven competence • ASICs dead in both scenes, EM scene and the highly commercialized • Soft CPU EDA scene • HLLs • EH should be done by EDA people, rather than EM freaks. • Problems to be solved

Enabling Technologies for Reconfigurable Computing and Software / Configware Co-Design, Part 4: ENST, Paris, 8 July 2002 Recent Developments

# Reiner Hartenstein, University of Kaiserslautern, Germany [email protected] http://kressarray.de

BRASS (1) BRASS (2) Xputer Lab University of Kaiserslautern University of Kaiserslautern • UC Berkeley, the BRASS group: Prof. Dr. John Wawrzynek • HSRA. new FPGA (& related tools) supports pipelining, w. • The Pleiades Project, Prof. Jan Rabaey, ultra-low power high- retiming capable CLB architecture, implemented in a 0.4um performance multimedia computing through reconfiguration DRAM process supporting 250MHz operation of heterogeneous system modules, reducing energy by overhead elimination, programmability at just right • OOCG. Object Oriented Circuit-Generators in Java granularity, parallellism, pipelining, dynamic voltage scaling. • MESCAL (GSRC), the goal is: to provide a programmer's • Garp integrates processor and FPGA; dev. in parallel w. model and software development environment for efficient compiler - software compile techniques (VLIW SW implementation of an interesting set of applications onto a pipelining): simple pipelining schema f. broad class of loops. family of fully-programmable architectures / • SCORE, a stream-based computation model - a unifying microarchitectures. computational model. Fast Mapping for Datapaths: by a tree- parsing compiler tool for datapath module mapping © 2002, [email protected] 43 http://kressarray.de © 2002, [email protected] 44 http://kressarray.de

Berkeley claiming (1) Berkeley claiming (2)

University of Kaiserslautern University of Kaiserslautern

• SCORE, a stream-based computation model: the BRASS group claims having solved the problem of primary impediment to wide-spread • Remark: The DPSS (Data Path Synthesis System) using reconfigurable computing, by a unifying computational model. tree covering simultanous datapath placement and routing has been published in 1995 by Rainer Kress • Remark: clean stream-based model introduced ~1980: Systolic Array • „Chip-in-a-Da2 Bee Project. Prof. Dr. Bob Broderson‘s „radical rethink of the ASIC design flow aimed at • 1995: Rainer Kress. Introduces reconfigurable stream-based model shortening design time, relying on stream-based DPU arrays.“ [published in 2000] • Fast Mapping for Datapaths (SCORE): BRASS claims having introduced 1998 the first tree-parsing compiler tool for datapath • Remark: the KressArray, a scalable rDPU array [1995] is module mapping ." Further, it is the first work to integrate stream-based simultaneous placement with module mapping in a way that preserves linear time complexity."

.... Stream Processors - MSP-3 Berkeley: „Chip-in-a-Day“ Bee Project

University of Kaiserslautern University of Kaiserslautern

• 3rd Workshop on Media and Stream Processors (MSP-3) • Chip-in-a-Day Project. Prof. Dr. Bob Broderson, BWRD: targeting • http://www.pdcl.eng.wayne.edu/msp01 a radical rethink of the ASIC design flow aimed at shortening • in conj. w. 34th Int‘l Symp. on Microarchitecture (MICRO-34) design time. Relying on stream-based DPU arrays (not rDPU and • http://www.microarch.org/micro34 related EDA tools. Davis: „ „... 50x decrease in power requ. over • Austin, Texas, December 1-2, 2001 typical TI C64X design.“ • Topics of interest include, but are not limited to: • New design flow to break up the highly iterative EDA process, – Hardware/Compiler techniques for improving memory allowing designers to spend more time defining the device and performance of media and stream-based processing far less time implementing it in silicon. „... developers to start by – Application-specific hardware architectures for graphics, video, audio, communications, and other media and streaming creating data flow graphs rather than C code,„ applications – System-on-a-chip architectures for media & stream processors • It is stream-based computing by DPU array (hardwired DPA) – Hardware/Software Co-Design of media and stream processors • For hardwired and reconfigurable DPU array and rDPU array – and others ....

Enabling Technologies for Reconfigurable Computing and Software / Configware Co-Design, Part 4: ENST, Paris, 8 July 2002 Recent Developments

# Reiner Hartenstein, University of Kaiserslautern, Germany [email protected] http://kressarray.de

Stanford thru BYU Toronto thru Karlsruhe Xputer Lab University of Kaiserslautern University of Kaiserslautern • Stanford: Prof. Flynn went emeritus, Oskar Menzer moved to Bell Labs. • U. Toronto. Prof. J.Rose, expert in FPGA architectures and R & P alg. • no activities seen other than YAFA (yet another FPGA application) • The group has dev. Transmogrifier C, a C compiler creating netlist for • UCLA: Prof. Jason Cong, expert on FPGA architectures and R& P Xilinx XC4000 and Altera's Flex 8000 and Flex 10000 series FPGAs. algorithms. 9 projects, mult. sponsors under California MICRO Program • Prof. Majid Sarrafzadeh directs the SPS project: "versatile IPs„, a new • Founder of Right Track CAD Corporation acquired by Altera in 1999 routing architecture, architecture-aware CAD, IP-aware SPS compiler • Los Alamos National Laboratory, Los Alamos, New Mexico (Jeff • USC: Prof. Viktor Prasanna (EE dept.) works 20% on reconfigurable Arnold) – Project Streams-C: programming FPGAs from C sources. computing: MAARC project, DRIVE project and Efficient Self- • Katholic University of Leuven, and IMEC: Prof. Rudy Lauwereins, Reconfiguration. - Prof. Dubois: RPM Project, FPGA-based emulation of methods for MPEG-4 like multimedia applications on dynamically scalable multiprocessors. reconfigurable platforms, & on reconf. instruction set processors. • DEFACTO proj.: compilation - architecture-independent at all levels • MIT. MATRIX web pages removed `99. „RAW project“: a conglomerate • University of Karlsruhe. Prof. Dr.-Ing. Juergen Becker: hardware/software co-design, reconfigurable architectures & rel. • VT. Prof. Athanas: Jbits API f. internet RTR logic ($2.7 mio DARPA). w. synthesis for future mobile communication systems & synthesis w. Prof. Brad Hutchings, BYU on programming approaches for RTR Systems • BYU. Prof. Brad Hutchings works on the JHDL (JAVA Hardware • distributed internet-based CAD methods, partitioning co-compilers © Description2002, [email protected] Language) and compilation49 of JHDL sourceshttp://kressarray.de into FPGAs. © 2002, [email protected] 50 http://kressarray.de

>> ASICs dead ? (When) Will FPGAs Kill ASICs? University of Kaiserslautern University of Kaiserslautern [Jonathan Rose]

• Configware Market • FPGA Market • Embedded Systems (Co-Design) ASICs Are Already Dead • Hardwired IP Cores on Board • Run-Time Reconfiguration (RTR) • Rapid Prototyping & ASIC Emulation My Position • Evolvable Hardware (EH) [Jonathan Rose] • Academic Expertise • ASICs dead ? • Soft CPU • HLLs They Just Don’t Know It Yet! • Problems to be solved

Why? [Jonathan Rose] Making ASICs is Damn Difficult University of Kaiserslautern University of Kaiserslautern [Jonathan Rose]

• Testing 1. You have to fabricate an ASIC • Yield  Very hard, getting harder • Cross Talk • Noise

• Leakage 2. An FPGA is pre-fabricated • Clock Tree Design  A standard part • Horrible very deep submicron effects we  immense economic advantages don’t even know about yet

Enabling Technologies for Reconfigurable Computing and Software / Configware Co-Design, Part 4: ENST, Paris, 8 July 2002 Recent Developments

# Reiner Hartenstein, University of Kaiserslautern, Germany [email protected] http://kressarray.de

Did I Mention Inventory? [Jonathan Rose] [Jonathan Rose] FPGAs Give You Xputer Lab University of Kaiserslautern University of Kaiserslautern • ASIC users must predict # parts – 2 or 3 months in advance! • Instant Fabrication • Never guess the Right Amount – Get to Market Fast – Make Too Many – You Pay holding costs – Fix ‘em quick – Make Too Few – Competitor gets the Sale • Zero NRE Charges – Low Risk – Low Cost at good volume

FPGAs: “Too Pricey & Too Slow ?” What’s Wrong with This Picture? University of Kaiserslautern University of Kaiserslautern Embedded [Jonathan Rose] What About PLD FPGA Fabric • 9 Times Out of 10 Cores on ASICs ? – You make can the thing fast by breaking it into multiple parallel slower pieces 1. Still Have to Make the Chip [Jonathan Rose] • Custom IC Designer Can Make Logic 2. Need Two Sets of Software to Build It – 20x Faster, – The ASIC Flow – 20x Smaller than Programmable – The PLD Flow 3. Have No Idea What to Connect the PLD Pins to – Chances Are, You Are Going to Get It Wrong! © 2002, [email protected] 57 http://kressarray.de © 2002, [email protected] 58 http://kressarray.de

What’s Right with This Picture! >> Soft CPU

University of Kaiserslautern University of Kaiserslautern

Embedded • Configware Market CPU Serial Link, • FPGA Market Analog, “etc.” • Embedded Systems (Co-Design) • Hardwired IP Cores on Board • Run-Time Reconfiguration (RTR) • Rapid Prototyping & ASIC Emulation [Jonathan Rose] 1. Pre-Fabricated • Evolvable Hardware (EH) • Academic Expertise 2. One CAD Tool Flow! • ASICs dead • Soft CPU 3. Can Connect Anything to Anything • HLLs  PLDs are built for general connectivity • Problems to be solved

Enabling Technologies for Reconfigurable Computing and Software / Configware Co-Design, Part 4: ENST, Paris, 8 July 2002 Recent Developments

# Reiner Hartenstein, University of Kaiserslautern, Germany [email protected] http://kressarray.de

Free 32 bit processor core Processors in PLDs: Excalibur Xputer Lab University of Kaiserslautern University of Kaiserslautern

Dual-Port Single-Port ARM 922T RAM RAM Core

•High-Speed Processors Integrated General Purpose PLD with PLDs

[Jonathan Rose]

Soft CPU: new job for compilers Some soft CPU core examples

University of Kaiserslautern University of Kaiserslautern

core architecture platform core architecture platform MicroBlaze 32 bit Xilinx up to Leon SPARC 125 MHz 70 standard RISC 100 on one 25 Mhz D-MIPS 32 reg. by 32 FPGA ARM7 clone ARM LUT RAM- based reg. uP1232 8-bit CISC, 32 reg. 200 XC4000E CLBs Memory Nios 16-bit Altera FPGA core instr. set Mercury REGIS 8 bits Instr. + 2 XILINX ext. ROM 3020 LCA Nios 32-bit Altera Reliance-1 12 bit DSP Lattice 50 MHz instr. set 22 D-MIPS 4 isp30256, Nios 8 bit Altera – 4 isp1016 HLL Compiler soft FPGA Mercury CPU 1Popcorn-1 8 bit CISC Altera, Lattice, gr1040 16-bit Xilinx gr1050 32-bit Acorn-1 1 Flex 10K20 My80 i8080A FLEX10K30 YARD-1A 16-bit RISC, old Xilinx FPGA or EPF6016 2 opd. Instr. Board DSPuva16 16 bit DSP Spartan-II xr16 RISC integer C SpartanXL

Nios Architecture (Altera) free DSP or Processor Cores

University of Kaiserslautern University of Kaiserslautern

CPU core Description Language Implementation Reliance 1 12bit DSP and peripherals Schematic Viewlogic 7 Lattice CPLDs PopCorn 1 small 8 bit CISC Verilog 1 Lattice CPLD isp3256-90 Acorn 1 small 8 bit CISC VHDL Max2PlusII+ 1 Altera 10k20 16-bit DSP A 16-bit Harvard DSP with VHDL Xilinx XC4000 5 pipeline stages. Free-6502 6502 compatible core VHDL DLX Generic 32-bit RISC CPU VHDL Synopsys DLX2 Generic 32-bit RISC CPU VHDL GL85 i8085 clone VHDL AMD 2901 AMD 2901 4-bit slice VHDL AMD 2910 AMD 2910 bit slice VHDL i8051 8-bit micro-controller VHDL Synopsys i8051 another i8051 clone VHDL Mentor Graphics

Enabling Technologies for Reconfigurable Computing and Software / Configware Co-Design, Part 4: ENST, Paris, 8 July 2002 Recent Developments

# Reiner Hartenstein, University of Kaiserslautern, Germany [email protected] http://kressarray.de

FPGA CPUs in teaching and Xilinx 10Mg, 500Mt, .12 mic Xputer Lab University of Kaiserslautern academic research University of Kaiserslautern

• UCSC: 1990! • Michigan State • Märaldalen University, • Universidad de Eskilstuna, Sweden Valladolid, Spain • Chalmers University, • Virginia Tech Göteborg, Sweden • Washington • Cornell University University, St. Louis • Gray Research • New Mexico Tech • Georgia Tech • UC Riverside • Hiroshima City • Tokai University, University, Japan Japan

Soft rDPA feasible ? Array I/O examples

University of Kaiserslautern University of Kaiserslautern

data streams, or, from / to embedded memory banks Performance µProc 1000 60%/yr..

100 CPU Processor-Memory Performance Gap: (grows 50% / year) 10 DRAM DRAM 1 1980 1990 2000 7%/yr..

data streams, or,

from / to embedded memory banks [à la S. Guccione] [à la S. Guccione]

HLL 2 Soft Array HLL 2 „flex“ rDPA

University of Kaiserslautern University of Kaiserslautern

miscellanous miscellanous Memory HLL Compiler CPU HLL Compiler soft CPU Memory

[à la S. Guccione] [à la S. Guccione]

Enabling Technologies for Reconfigurable Computing and Software / Configware Co-Design, Part 4: ENST, Paris, 8 July 2002 Recent Developments

# Reiner Hartenstein, University of Kaiserslautern, Germany [email protected] http://kressarray.de

>> HLLs HLLs for Hardware Design vs. Xputer Lab University of Kaiserslautern University of Kaiserslautern System Design vs. RTR System • Configware Market Design • FPGA Market • Embedded Systems (Co-Design) • Hardwired IP Cores on Board • Run-Time Reconfiguration (RTR) HLL Compiler • Rapid Prototyping & ASIC Emulation • Evolvable Hardware (EH) System Design • Academic Expertise • ASICs dead • Soft CPU • HLLs HLL Compiler • Problems to be solved [à la S. Guccione] RTR System Design

HLLs for Hardware Design vs. CPU and memory on Chip University of Kaiserslautern System Design vs. RTR System University of Kaiserslautern Design HLL Compiler

HLL Compiler HLL Compiler

System Design RTR System Design FPGA core

Compiler CPU Memory HLL core core HLL Compiler [à la S. Guccione] RTR System Design [à la S. Guccione]

Jbit Environment HLLs for Hardware Design vs. University of Kaiserslautern University of Kaiserslautern System Design vs. RTR System RTP Core JBits Design Library API [à la S. Guccione] User Code JRoute API HLL Compiler BoardScope Debugger XHWIF

TCP/IP HLL Compiler

Device System Design Simulator [à la S. Guccione]

Enabling Technologies for Reconfigurable Computing and Software / Configware Co-Design, Part 4: ENST, Paris, 8 July 2002 Recent Developments

# Reiner Hartenstein, University of Kaiserslautern, Germany [email protected] http://kressarray.de

Embedded System Design >> Problems to be solved Xputer Lab University of Kaiserslautern University of Kaiserslautern

• Configware Market FPGA core • FPGA Market • Embedded Systems (Co-Design) HLL Compiler • Hardwired IP Cores on Board CPU Memory • Run-Time Reconfiguration (RTR) core core • Rapid Prototyping & ASIC Emulation • Evolvable Hardware (EH) Memory FPGA core • Academic Expertise • ASICs dead HLL Compiler • Soft CPU soft FPGA • HLLs CPU • Problems to be solved [à la S. Guccione]

Why Can’t Reconfig. Software Survive? >>> Coarse Grain

University of Kaiserslautern University of Kaiserslautern

• Resource constraints/sizes are exposed: – to programmer – in low-level representation (netlist) • Design revolves around device size – Algorithmic structure – Exploited parallelism - END -

Schedule Schedule

University of Kaiserslautern University of Kaiserslautern

time slot 08.30 – 10.00 Reconfigurable Computing (RC) time slot 10.00 – 10.30 coffee break 08.30 – 10.00 Reconfigurable Computing (RC) 10.30 – 12.00 Stream-based Computing for RC 10.00 – 10.30 coffee break 12.00 – 14.00 lunch break 10.30 – 12.00 Stream-based Computing for RC 14.00 – 15.30 Resources for RC 12.00 – 14.00 lunch break 15.30 – 16.00 coffee break 14.00 – 15.30 Resources for RC 16.00 – 17.30 FPGAs: recent developments 15.30 – 16.00 coffee break 17.30 end of seminar: thank you for attending 16.00 – 17.30 FPGAs: recent developments

Enabling Technologies for Reconfigurable Computing and Software / Configware Co-Design, Part 4: ENST, Paris, 8 July 2002 Recent Developments