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The Hardware Design Toolchain Approaches and State of the Art Fredo Erxleben August 27, 2014

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The Hardware Design Toolchain Approaches and State of the Art Fredo Erxleben August 27, 2014 The Hardware Design Toolchain Approaches and State of the Art Fredo Erxleben August 27, 2014 We will hate the tools (FCCM 1996 prediction for 2001) We will still hate the tools (FCCM 1998 prediction for 2003) We will merely dislike the tools (FCCM 2000 prediction for 2005) We [will] hate the tools more (FCCM 2007 prediction for 2012) 1 Motivation used for hardware design will be presented in an attempt to outline where weaknesses in the currently available tool-chains for hardware de- Since the introduction of integrated circuits, sign are found. Due to the sheer amount of hardware complexity has increased rapidly and different approaches made over the years and constantly. This complexity naturally is a hard tools that were developed with the intention of thing for humans to handle once it reaches a helping to improve the design process, it is not certain threshold. As a consequence, the need possible to look at them all or in more detail. for tools arises to enable the people involved in Instead, in the following, an overview over ap- the hardware design process to continue work- proaches made to create tool-chains for hard- ing on, advancing and improving the matter. ware design or single tools to be used in them, While this is a fact for any evolving branch of shall be given. It will also be outlined, what science and production, the speed, by which the their current state in productive use is. tools adapt varies greatly. Taking software de- velopment as a comparison, we find that there are often a lot of tools available for one task, 2 Criteria each one of them filling a niche or being tai- lored with a special use-case in mind. In ad- When reviewing tools or tool-chains there are dition, the integration between these tools be- several aspects to look at. Some of the most comes increasingly tight through the extensive essential ones are listed here, which influence 1 use of plugins and common file types . This how easily and productively humans can use allows the creation of well interlocking tool- the given software. chains with a high level of user comfort and pro- ductivity for virtually every requirement that The field of application describes which and might arise. In the following, a selection of tools how many different use-cases a tool can 1Famous examples for the first are eclipse, emacs or vim; For the second, one might think of JSON, .tex or XML 1 cover. This is often represented as points 3.1 VHDL on the extended Gajski-Kuhn-chart2 [9]. VHDL serves as standard in the world of hard- ware design and most tools support processing The design of human interaction influences or creating hardware descriptions in this lan- the way the user works with the software. guage. This is mostly due to its wide appli- It positively strongly affects the learn- cation range that allows to use VHDL for de- ing curve and productivity when using a scriptions on different abstraction levels: For tool, supporting multiple techniques for hardware interfaces, implementations as well as solving a given task, being intuitive and test benches as shown in figure1. As a trade- communicating effectively with the user. off this makes the language very diverse3, and structurally complex. Its origin is found in lan- Availability and openness are relevant for ob- guages like Ada, which makes learning it more taining a broad user base and acceptance. difficult for people more used to languages like People have very diverse premises with re- C/C++ or Java. spect to hardware and operating systems. System Behaviour Structure Being available for a lot of different se- Algorithm tups makes it easier for more users to ap- ply the tools, while available source code RTL gives interested developers the opportu- Logic nity to adapt and improve them. Circuit Tool-chain integration capabilities refer to the ability of a tool to be extended by plugins or to operate with the file for- mats used by other software. 3 Languages Used in Physical Test Hardware Design Figure 1: Green dots show the application range of VHDL Before researching tools themselves, a short overview over the hardware description lan- 3.2 Verilog guages these tools are based on is mandatory. Since virtually no hardware down to the mask An also often used HDL is Verilog. While the level is publicly available, these languages serve basic Verilog language can not cover the same as an interface typically at the register transfer range of application as VHDL, extensions like level. Everything below that is normally spe- SystemVerilog exist, that increase the amount cific to the hardware vendor who applies his of use-cases. In combination with compilers own parser and compiler. While this practice that support its features, SystemVerilog is also enables a lot of optimization for the given hard- used for the verification of hardware designs. ware by the vendor, it also binds a considerable Since Verilog and its variations are designed to amount of his development workforce. resemble C -style languages, it tends to be used 2Since testing is such an important task in the hardware design process, it is only reasonable to include it when discussing use-case coverage of tools. 3VHDL has 99 reserved keywords [16]. 4An extensive discussion about the pros and cons of teaching either VHDL or Verilog can be found at http://ask.slashdot.org/story/09/05/31/187208/vhdl-or-verilog-for-learning-fpgas. 2 like a procedural language by new users, which at all about how a specification is to be writ- contradicts the way an HDL works4. ten. There have been case studies to show that UML might be deployed to improve specifica- 3.3 The Relation between tions and reduce ambiguity compared to nearly Languages and Editing Tools pure textual variants [1]. In addition it has been tried to embed a formal specification into It could be argued that any tool, capable of VHDL and to show that this could be used for handling a given HDL also inherits the lan- automated verification [24]. guages descriptive potential. But this ignores the fact that hardware designs tend to get very complex very fast and it is in the applied editing 5 High-level synthesis tools responsibility to assist the user by provid- ing High-level synthesis usually describes the trans- formation of a hardware description given in an • Different views on the design, e. g. by of- abstract representation8 into a form which can fering schematic representations as well be synthesized directly into hardware. as textual ones or allowing certain things to be blended out. 5.1 HLS from higher level languages • Means of navigating the code easily A current trend are attempts to generate an • Aids for reading and interpreting the HDL description from other established pro- code5 gramming languages. These approaches ini- • Possible code completions tially explored functional languages like Haskell [6] because of the relative ease of translating • Shortcuts for often repeated tasks6 them into HDL [25]. Other efforts have been made to re-purpose existing software program- • Support for code refactoring ming languages like C/C++ [27], Java (espe- • Enforcement of conventions7 cially referring to JHDL [4]) or using Matlab [2]. Currently, editing tools deployed in IDEs like ISE, Quartus, Sigasi Pro or Vivado only cover a small subset of these requirements. This lack 5.2 HLS from visual representations of user support has a notable negative impact upon the hardware designers productivity [20]. Starting the design process with sketching a vi- sual representation has proven a good practice in the software world, where UML has become 4 Tools for Specifications an important tool for development. Up to now, there is no widely accepted equivalent for the Whenever a hardware design is to be made the hardware world, even though there have been first thing to be done is a specification describ- made efforts to either use UML itself for hard- ing the intended structure, behavior and limits. ware description [7] or create a visual represen- In the most cases these specifications are done tation for VHDL [21]. Still, no holistic agreed in textual form, aided by the use of tables or upon visual representation for hardware designs graphical sketches. Apart from this very gen- exist so far9 even though suggestions were made eral similarity there seems to be no consensus [11]. As a result there are nearly no tools 5Mostly associated with syntax highlighting, this also covers context based help 6Think of instantiating a component 7For example naming conventions, code formatting or required documentation 8For example, as a program written in a high-level language or a schematic representation of the structure. 9Even for the most basic elements like logic gates there exist multiple wide-spread circuit symbols 3 that employ a possibility of designing hard- 6.2.1 Example: FloPoCo ware by creating visual representations of either FloPoCo[8] is a generator for arithmetic cores, the hardware structure or behavior10. Further primarily aimed at FPGAs. It allows for the research and development regarding the topic fast generation of arithmetic operators imple- seems to have nearly ceased after the basics mentations as well as the user-provided def- have been patented [26]. Promising approaches inition of completely new operators and test have been made by HDLDesigner, Qucs and benches. Designs created with FloPoCo tend to fritzings IDE11. The latter offers the design to be very efficient with respect to hardware usage be made from a view representing either the and execution speed due to the optimization setup on a breadboard or a schematic repre- done by the generator.
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