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Using Relocatable Bitstreams for Fault Tolerance Air Force Institute of Technology AFIT Scholar Theses and Dissertations Student Graduate Works 3-2007 Using Relocatable Bitstreams for Fault Tolerance David P. Montminy Follow this and additional works at: https://scholar.afit.edu/etd Part of the Electrical and Computer Engineering Commons Recommended Citation Montminy, David P., "Using Relocatable Bitstreams for Fault Tolerance" (2007). Theses and Dissertations. 3105. https://scholar.afit.edu/etd/3105 This Thesis is brought to you for free and open access by the Student Graduate Works at AFIT Scholar. It has been accepted for inclusion in Theses and Dissertations by an authorized administrator of AFIT Scholar. For more information, please contact [email protected]. Using Relocatable Bitstreams For Fault Tolerance THESIS David P. Montminy, Captain, USAF AFIT/GCE/ENG/07-09 DEPARTMENT OF THE AIR FORCE AIR UNIVERSITY AIR FORCE INSTITUTE OF TECHNOLOGY Wright-Patterson Air Force Base, Ohio APPROVED FOR PUBLIC RELEASE; DISTRIBUTION UNLIMITED. The views expressed in this thesis are those of the author and do not reflect the official policy or position of the United States Air Force, Department of Defense, or the U.S. Government. AFIT/GCE/ENG/07-09 Using Relocatable Bitstreams For Fault Tolerance THESIS Presented to the Faculty Department of Electrical and Computer Engineering Graduate School of Engineering and Management Air Force Institute of Technology Air University Air Education and Training Command In Partial Fulfillment of the Requirements for the Degree of Master of Science in Computer Engineering David P. Montminy, B.S.E.E. Captain, USAF March 2007 APPROVED FOR PUBLIC RELEASE; DISTRIBUTION UNLIMITED. AFIT/GCE/ENG/07-09 Abstract This research develops a method for relocating reconfigurable modules on the Virtex-II (Pro) family of Field Programmable Gate Arrays (FPGAs). A bitstream translation program is developed which correctly changes the location of a partial bitstream that implements a module on the FPGA. To take advantage of relocatable modules, three fault-tolerance circuit designs are developed and tested. This circuit can operate through a fault by efficiently removing the faulty module and replacing it with a relocated module without faults. The FPGA can recover from faults at a known location, without the need for external intervention using an embedded fault recovery system. The recovery system uses an internal PowerPC to relocate the modules and reprogram the FPGA. Due to the limited architecture of the target FPGA and Xilinx tool errors, an FPGA with automatic fault recovery could not be demonstrated. However, the various components needed to do this type of recovery have been implemented and demonstrated individually. iv Acknowledgements First and foremost, without the loving support of my wife this research would not have been possible. I am very grateful to Dr. Rusty Baldwin for giving me the freedom and support to explore and develop applications for partial configuration as I conceived them while keeping me headed in the right direction. Maj Paul Williams provided a great sounding board for new ideas and helped me develop troubleshooting techniques whenever it looked like I had reached a dead end. I also like to thank the international partial reconfiguration community, especially Dr. John Williams of the University of Queensland and Xilinx Research Labs. David P. Montminy v Table of Contents Page Abstract..................................... iv Acknowledgements............................... v ListofFigures................................. ix ListofTables.................................. xi ListofAbbreviations.............................. xii I. Introduction............................. 1 1.1 Overview.......................... 1 1.2 MotivationandGoals................... 1 1.3 Organization........................ 1 II. LiteratureReview.......................... 3 2.1 Introduction......................... 3 2.1.1 Applications of Fault Tolerance . 3 2.1.2 Motivation for using FPGA reconfiguration for Fault-Tolerance.................. 3 2.2 FaultTolerance....................... 4 2.2.1 Methods for Fault Tolerance . 6 2.2.2 Reconfiguration as a Method for Fault Tolerance 9 2.3 FPGAs........................... 9 2.3.1 SRAMFPGATechnology............ 13 2.3.2 SRAMFPGAReconfiguration.......... 14 2.4 Current Research in FPGA Reconfiguration . 17 2.4.1 Methods for Partial Reconfiguration . 17 2.4.2 Hardware Bitstream Relocation . 22 2.4.3 Automatic Dynamic Active Partial Reconfigura- tionforFaultTolerance............. 23 2.5 Summary.......................... 30 III. Development of a Dynamic Reconfiguration System . 32 3.1 Introduction......................... 32 3.2 ProblemDefinition..................... 32 3.2.1 GoalsandHypothesis............... 32 3.2.2 Approach..................... 33 3.3 A Column-Based Fault Tolerant Configuration . 33 vi Page 3.3.1 Benefits...................... 34 3.3.2 RoutingandTiming............... 35 3.4 Using Relocatable Modules in TMR Designs . 35 3.4.1 Bitstream Storage Savings With Relocatable Mod- ules......................... 36 3.4.2 Routing with Relocatable Interconnect Modules 37 3.4.3 Rerouting Using Difference Based Reconfiguration 38 3.5 TheTargetFPGA..................... 40 3.6 Developing the Bitstream Translation Program . 42 3.6.1 Virtex-II Pro Bitstream Composition . 43 3.6.2 Configuration Memory Addressing . 43 3.6.3 BitstreamPacketType.............. 44 3.6.4 Software Emulation of the Packet Processor . 45 3.6.5 Virtex-II Pro Configuration Registers . 46 3.6.6 Calculating the New Major Address . 47 3.6.7 UpdatingtheCRCValue............. 49 3.6.8 Overall Organization of the BTP . 50 3.7 FPGADesignTools.................... 50 3.8 Implementing a Relocatable Partial Reconfiguration Design 53 3.8.1 ReconfigurableModules............. 53 3.8.2 BusMacros.................... 53 3.8.3 Making Reconfigurable Modules Relocatable . 55 3.9 InternalReconfiguration.................. 56 3.9.1 Using an Embedded Microprocessor to Run the BTP........................ 56 3.9.2 MicroBlazeanduClinux............. 57 3.9.3 PowerPC...................... 58 3.10Summary.......................... 59 IV. Implementation............................ 60 4.1 Introduction......................... 60 4.2 Verifying Relocation of Partial Modules . 60 4.2.1 Testing the Interconnect Module Designs . 61 4.2.2 Testing the Direct Connect Modular Design . 65 4.2.3 Implementing the LUT-based Modular Design . 66 4.3 AddingaMicroprocessortotheDesign.......... 68 4.3.1 Resources Used By Microprocessors . 68 4.3.2 ChangestoBTPforPowerPC.......... 69 4.3.3 Internal Reconfiguration using the PowerPC . 70 4.4 PreventingStaticRouting................. 71 vii Page 4.4.1 Problems Caused by Restricting Routing . 71 4.4.2 Programming of I/O Blocks . 73 4.5 Safe Locations for Relocatable Modules on the XUPV2P 75 4.6 Errors During Bitstream Generation . 75 4.7 Relocatable Module Support in 8.2 Partial Reconfigura- tionToolchain....................... 77 4.8 RelocatableModulesintheVirtex-4........... 78 4.8.1 Drawbacks of the Virtex-4 . 79 4.9 ComparisonwithREPLICA2Pro............. 80 4.10Summary.......................... 81 V. Conclusions.............................. 82 5.1 Introduction......................... 82 5.2 ProblemSummary..................... 82 5.3 ConclusionofResearch................... 82 5.4 SignificanceofResearch.................. 84 5.5 Recommendations for Future Research . 84 Appendix A. Using the PowerPC for Partial Reconfiguration . 86 A.1CreatingtheEDKProject................. 86 A.2 Adding Software, Exporting, and Integration . 89 AppendixB. BitstreamTranslationPrograms............. 90 AppendixC. ISE8.1andPlanAheadDesignFlow........... 106 C.1 ISE 8.1 Partial Reconfiguration Design Flow . 106 C.2 ISE 8.2 Partial Reconfiguration Toolchain . 109 C.3ExamplePRImplementationScript............ 109 Bibliography.................................. 113 viii List of Figures Figure Page 2.1 OneStageofaTMRCircuit................... 7 2.2 NAND Multiplexer . 8 2.3 TheBasicStructureofanFPGA................. 10 2.4 Key Elements of a Xilinx FPGA Logic Block . 11 2.5 ArchitectureoftheVirtex-IIFPGA............... 15 2.6 DesignLayoutwithTwoReconfigurableModules........ 19 2.7 TMR with Boundary Scan . 25 2.8 The Overlapping Precompiled Column Scheme. 28 3.1 BasicTMRDesign......................... 34 3.2 Modular Functions Before and After Reconfiguration . 36 3.3 Relocatable Functional and Interconnect Module Configuration 38 3.4 Relocatable Modules with LUT Selected Bus Connections System 39 3.5 LayoutoftheVirtex-IIProinPlanAhead............ 41 3.6 FrameAddressComposition................... 43 3.7 Column-Level (MJA) Configuration Memory Map . 44 3.8 BitstreamPacketType1 ..................... 45 3.9 BitstreamPacketType2 ..................... 45 3.10 DistancebetweenBRAMcolumns................ 48 3.11 V2PSerial16-bitCRCCircuity................. 49 3.12 FlowchartforProcessingaPacket................ 51 3.13 Areas with Homogenous Resource Between Columns . 54 3.14 The Layout of a Bus Macro in FPGA Editor . 55 3.15 MicroBlazeSystemBlockDiagram................ 57 3.16 PowerPCSystemBlockDiagram................. 58 4.1 Interconnect Module Layout Test Configuration . 61 ix Figure Page 4.2 Partial Reconfiguration Status Display . 61 4.3 TopLevelVHDLOrganization.................. 62 4.4 PlanAhead Layout for the Interconnect Module Configuration . 63 4.5 FPGA Editor View of NCD for Interconnect Modules Design . 64 4.6 Area Constraints Direct Connect and LUT-based Configurations 65 4.7 Top Level VHDL Organization for the Direct
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