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Reconfigurable Computing Reconfigurable computing: architectures and design methods T.J. Todman, G.A. Constantinides, S.J.E. Wilton, O. Mencer, W. Luk and P.Y.K. Cheung Abstract: Reconfigurable computing is becoming increasingly attractive for many applications. This survey covers two aspects of reconfigurable computing: architectures and design methods. The paper includes recent advances in reconfigurable architectures, such as the Alters Stratix II and Xilinx Virtex 4 FPGA devices. The authors identify major trends in general-purpose and special- purpose design methods. It is shown that reconfigurable computing designs are capable of achieving up to 500 times speedup and 70% energy savings over microprocessor implementations for specific applications. 1 Introduction Recent research suggests that it is a trend rather than a one-off for a wide variety of applications: from image Reconfigurable computing is rapidly establishing itself as a processing [3] to floating-point operations [4]. major discipline that covers various subjects of learning, Sheer speed, while important, is not the only strength of including both computing science and electronic engineer- reconfigurable computing. Another compelling advantage is ing. Reconfigurable computing involves the use of reduced energy and power consumption. In a reconfigurable reconfigurable devices, such as field programmable gate system, the circuitry is optimised for the application, such arrays (FPGAs), for computing purposes. Reconfigurable that the power consumption will tend to be much lower than computing is also known as configurable computing or that for a general-purpose processor. A recent study [5] custom computing, since many of the design techniques can reports that moving critical software loops to reconfigurable be seen as customising a computational fabric for specific hardware results in average energy savings of 35% to 70% applications [1]. with an average speedup of 3 to 7 times, depending on the Reconfigurable computing systems often have impressive particular device used. performance. Consider, as an example, the point Other advantages of reconfigurable computing include a multiplication operation in elliptic curve cryptography. reduction in size and component count (and hence cost), For a key size of 270 bits, it has been reported [2] that improved time-to-market, and improved flexibility and a point multiplication can be computed in 0.36 ms with upgradability. These advantages are especially important a reconfigurable computing design implemented in an for embedded applications. Indeed, there is evidence [6] that XC2V6000 FPGA at 66 MHz. In contrast, an optimised embedded systems developers show a growing interest in software implementation requires 196.71 ms on a dual-xeon reconfigurable computing systems, especially with the introduction of soft cores which can contain one or more computer at 2.6 GHz; so the reconfigurable computing instruction processors [7–12]. design is more than 540 times faster, while its clock speed is In this paper, we present a survey of modern reconfigur- almost 40 times slower than the Xeon processors. able system architectures and design methods. Although we This example illustrates a hardware design implemented also provide background information on notable aspects of on a reconfigurable computing platform. We regard such older technologies, our focus is on the most recent implementations as a subset of reconfigurable computing, architectures and design methods, as well as the trends which in general can involve the use of runtime reconfi- that will drive each of these areas in the near future. In other guration and soft processors. words, we intend to complement other survey papers Is this speed advantage of reconfigurable computing over [13–17] by: traditional microprocessors a one-off or a sustainable trend? (i) providing an up-to-date survey of material that appears after the publication of the papers mentioned above; q IEE, 2005 (ii) identifying explicitly the main trends in architectures IEE Proceedings online no. 20045086 and design methods for reconfigurable computing; (iii) examining reconfigurable computing from a perspec- doi: 10.1049/ip-cdt:20045086 tive different from existing surveys, for instance classifying Paper first received 14th July and in revised form 9th November 2004 design methods as special-purpose and general-purpose; T.J. Todman, O. Mencer and W. Luk are with the Department of (iv) offering various direct comparisons of technology Computing, Imperial College London, 180 Queen’s Gate, London SW7 2AZ, UK options according to a selected set of metrics from different perspectives. G.A. Constantinides and P.Y.K. Cheung are with the Department of Electrical and Electronic Engineering, Imperial College London, Exhibition Rd, South Kensington, London SW7 2BT, UK 2 Background S.J.E. Wilton is with the Department of Electrical and Computer Engineering, University of British Columbia, 2356 Main Mall, Many of today’s computationally intensive applications Vancouver, British Columbia, Canada V6T 1Z4 require more processing power than ever before. Appli- E-mail: [email protected] cations such as streaming video, image recognition IEE Proc.-Comput. Digit. Tech., Vol. 152, No. 2, March 2005 193 and processing, and highly interactive services are placing design-time inherent in an ASIC implementation. Also new demands on the computation units that implement these unlike an ASIC, the functional units implemented in the applications. At the same time, the power consumption reconfigurable fabric can change over time. This means that targets, the acceptable packaging and manufacturing costs, as the environment or usage of the embedded system and the time-to-market requirements of these computation changes, the mix of functional units can adapt to better units are all decreasing rapidly, especially in the embedded match the new environment. The reconfigurable fabric in a hand-held devices market. Meeting these performance handheld device, for instance, might implement large matrix requirements under the power, cost and time-to-market multiply operations when the device is used in one mode, constraints is becoming increasingly challenging. and large signal processing functions when the device is In the following, we describe three ways of supporting used in another mode. such processing requirements: high-performance micro- Typically, not all of the embedded system functionality processors, application-specific integrated circuits and needs to be implemented by the reconfigurable fabric. Only reconfigurable computing systems. those parts of the computation that are time-critical and High-performance microprocessors provide an off- contain a high degree of parallelism need to be mapped to the-shelf means of addressing processing requirements the reconfigurable fabric, while the remainder of the described earlier. Unfortunately for many applications, computation can be implemented by a standard instruction a single processor, even an expensive state-of-the-art processor. The interface between the processor and the processor, is not fast enough. In addition, the power fabric, as well as the interface between the memory and the consumption (100 W or more) and cost (possibly thousands fabric, are therefore of the utmost importance. Modern of dollars) state-of-the-art processors place them out of reach reconfigurable devices are large enough to implement for many embedded applications. Even if microprocessors instruction processors within the programmable fabric continue to follow Moore’s Law so that their density itself: soft processors. These can be general purpose, or doubles every 18 months, they may still be unable to keep customised to a particular application; application specific up with the requirements of some of the most aggressive instruction processors and flexible instruction processors are embedded applications. two such approaches. Section 4.3.2 deals with soft Application-specific integrated circuits (ASICs) provide processors in more detail. another means of addressing these processing requirements. Other devices show some of the flexibility of reconfigur- Unlike a software implementation, an ASIC implementation able computers. Examples include graphics processor units provides a natural mechanism for implementing the large and application specific array processors. These devices amount of parallelism found in many of these applications. perform well on their intended application, but cannot run In addition, an ASIC circuit does not need to suffer from the more general computations, unlike reconfigurable compu- serial (and often slow and power-hungry) instruction fetch, ters and microprocessors. decode and execute cycle that is at the heart of all Despite the compelling promise of reconfigurable com- microprocessors. Furthermore, ASICs consume less power puting, it has limitations of which designers should be aware. than reconfigurable devices. Finally, an ASIC can contain For instance, the flexible routing on the bit level tends to just the right mix of functional units for a particular produce large silicon area and performance overhead when application; in contrast, an off-the-shelf microprocessor compared with ASIC technology. Hence for large volume contains a fixed set of functional units which must be production of designs in applications without the need for selected to satisfy a wide variety of applications. field upgrade, ASIC technology or gate array technology can Despite the advantages of ASICs, they are often still deliver higher performance design at lower unit
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