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Reconfigurable Computing Reconfigurable Computing: A Survey of Systems and Software KATHERINE COMPTON Northwestern University AND SCOTT HAUCK University of Washington Due to its potential to greatly accelerate a wide variety of applications, reconfigurable computing has become a subject of a great deal of research. Its key feature is the ability to perform computations in hardware to increase performance, while retaining much of the flexibility of a software solution. In this survey, we explore the hardware aspects of reconfigurable computing machines, from single chip architectures to multi-chip systems, including internal structures and external coupling. We also focus on the software that targets these machines, such as compilation tools that map high-level algorithms directly to the reconfigurable substrate. Finally, we consider the issues involved in run-time reconfigurable systems, which reuse the configurable hardware during program execution. Categories and Subject Descriptors: A.1 [Introductory and Survey]; B.6.1 [Logic Design]: Design Style—logic arrays; B.6.3 [Logic Design]: Design Aids; B.7.1 [Integrated Circuits]: Types and Design Styles—gate arrays General Terms: Design, Performance Additional Key Words and Phrases: Automatic design, field-programmable, FPGA, manual design, reconfigurable architectures, reconfigurable computing, reconfigurable systems 1. INTRODUCTION of algorithms. The first is to use hard- wired technology, either an Application There are two primary methods in con- Specific Integrated Circuit (ASIC) or a ventional computing for the execution group of individual components forming a This research was supported in part by Motorola, Inc., DARPA, and NSF. K. Compton was supported by an NSF fellowship. S. Hauck was supported in part by an NSF CAREER award and a Sloan Research Fellowship. Authors’ addresses: K. Compton, Department of Electrical and Computer Engineering, Northwestern Uni- versity, 2145 Sheridan Road, Evanston, IL 60208-3118; e-mail: [email protected]; S. Hauck, De- partment of Electrical Engineering, The University of Washington, Box 352500, Seattle, WA 98195; e-mail: [email protected]. Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or direct commercial advantage and that copies show this notice on the first page or initial screen of a display along with the full citation. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any compo- nent of this work in other works requires prior specific permission and/or a fee. Permissions may be requested from Publications Dept., ACM, Inc., 1515 Broadway, New York, NY 10036 USA, fax +1 (212) 869-0481, or [email protected]. c 2002 ACM 0360-0300/02/0600-0171 $5.00 ACM Computing Surveys, Vol. 34, No. 2, June 2002, pp. 171–210. 172 K. Compton and S. Hauck board-level solution, to perform the oper- figurable hardware by computing the logic ations in hardware. ASICs are designed functions of the circuit within the logic specifically to perform a given computa- blocks, and using the configurable routing tion, and thus they are very fast and to connect the blocks together to form the efficient when executing the exact com- necessary circuit. putation for which they were designed. FPGAs and reconfigurable computing However, the circuit cannot be altered af- have been shown to accelerate a variety of ter fabrication. This forces a redesign and applications. Data encryption, for exam- refabrication of the chip if any part of its ple, is able to leverage both parallelism circuit requires modification. This is an ex- and fine-grained data manipulation. An pensive process, especially when one con- implementation of the Serpent Block siders the difficulties in replacing ASICs Cipher in the Xilinx Virtex XCV1000 in a large number of deployed systems. shows a throughput increase by a factor Board-level circuits are also somewhat in- of over 18 compared to a Pentium Pro flexible, frequently requiring a board re- PC running at 200 MHz [Elbirt and Paar design and replacement in the event of 2000]. Additionally, a reconfigurable com- changes to the application. puting implementation of sieving for fac- The second method is to use soft- toring large numbers (useful in breaking ware-programmed microprocessors—a far encryption schemes) was accelerated by a more flexible solution. Processors execute factor of 28 over a 200-MHz UltraSparc a set of instructions to perform a compu- workstation [Kim and Mangione-Smith tation. By changing the software instruc- 2000]. The Garp architecture shows a tions, the functionality of the system is comparable speed-up for DES [Hauser altered without changing the hardware. and Wawrzynek 1997], as does an However, the downside of this flexibility FPGA implementation of an elliptic curve is that the performance can suffer, if not cryptography application [Leung et al. in clock speed then in work rate, and is 2000]. far below that of an ASIC. The processor Other recent applications that have must read each instruction from memory, been shown to exhibit significant speed- decode its meaning, and only then exe- ups using reconfigurable hardware cute it. This results in a high execution include: automatic target recognition overhead for each individual operation. [Rencher and Hutchings 1997], string pat- Additionally, the set of instructions that tern matching [Weinhardt and Luk 1999], may be used by a program is determined Golomb Ruler Derivation [Dollas et al. at the fabrication time of the processor. 1998; Sotiriades et al. 2000], transitive Any other operations that are to be im- closure of dynamic graphs [Huelsbergen plemented must be built out of existing 2000], Boolean satisfiability [Zhong et al. instructions. 1998], data compression [Huang et al. Reconfigurable computing is intended to 2000], and genetic algorithms for the tra- fill the gap between hardware and soft- velling salesman problem [Graham and ware, achieving potentially much higher Nelson 1996]. performance than software, while main- In order to achieve these performance taining a higher level of flexibility than benefits, yet support a wide range of appli- hardware. Reconfigurable devices, in- cations, reconfigurable systems are usu- cluding field-programmable gate arrays ally formed with a combination of re- (FPGAs), contain an array of computa- configurable logic and a general-purpose tional elements whose functionality is de- microprocessor. The processor performs termined through multiple programmable the operations that cannot be done effi- configuration bits. These elements, some- ciently in the reconfigurable logic, such times known as logic blocks, are connected as data-dependent control and possibly using a set of routing resources that are memory accesses, while the computational also programmable. In this way, custom cores are mapped to the reconfigurable digital circuits can be mapped to the recon- hardware. This reconfigurable logic can be ACM Computing Surveys, Vol. 34, No. 2, June 2002. Reconfigurable Computing 173 composed of either commercial FPGAs or uration compression and the partial reuse custom configurable hardware. of already programmed configurations can Compilation environments for reconfig- be used to reduce this overhead. urable hardware range from tools to assist This article presents a survey of cur- a programmer in performing a hand map- rent research in hardware and software ping of a circuit to the hardware, to com- systems for reconfigurable computing, as plete automated systems that take a cir- well as techniques that specifically target cuit description in a high-level language run-time reconfigurability. We lead off this to a configuration for a reconfigurable sys- discussion by examining the technology tem. The design process involves first par- required for reconfigurable computing, fol- titioning a program into sections to be im- lowed by a more in-depth examination of plemented on hardware, and those which the various hardware structures used in are to be implemented in software on the reconfigurable systems. Next, we look at host processor. The computations destined the software required for compilation of for the reconfigurable hardware are syn- algorithms to configurable computers, and thesized into a gate level or register trans- the trade-offs between hand-mapping and fer level circuit description. This circuit is automatic compilation. Finally, we discuss mapped onto the logic blocks within the re- run-time reconfigurable systems, which configurable hardware during the technol- further utilize the intrinsic flexibility of ogy mapping phase. These mapped blocks configurable computing platforms by opti- are then placed into the specific physi- mizing the hardware not only for different cal blocks within the hardware, and the applications, but for different operations pieces of the circuit are connected using within a single application as well. the reconfigurable routing. After compi- This survey does not seek to cover ev- lation, the circuit is ready for configura- ery technique and research project in the tion onto the hardware at run-time. These area of reconfigurable computing. Instead, steps, when performed using an automatic it hopes to serve as an introduction to compilation system, require very little ef- this rapidly evolving field, bringing in- fort on the part of the programmer to terested readers
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