Reconfigurable Computing Brittany Ransbottom Benjamin Wheeler What Is Reconfigurable Computing?

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Reconfigurable Computing Brittany Ransbottom Benjamin Wheeler What is Reconfigurable Computing? A computer architecture style which tries to find a happy medium of general purpose processors and ASICs through the use of the flexibility of software, and the speed of hardware. Reconfigurable Computing von Neumann vs. Reconfigurable Fixed resources Variable resources The architecture is While the designed prior to architecture is use as a processor designed prior to use, it can be adjusted or reconfigured to use different resources Execution in SW Execution in HW Spatial vs. Temporal Hardware Software Software The Reconfigurable Computing Paradox • Migration from software to configware o speed-up factors and electricity consumption reduction of about four orders of magnitude o Clock frequency and other specifications of FPGAs are behind microprocessors by about four orders of magnitude Current State No designs merge GPP and ASIC enough to be marketable Too specialized (a glorified asic), or priced too high to benefit replacing GPPs Coarse-Grained doesn't have SW support necessary What is an FPGA? Reprogrammable Hardware Generally configured in VHDL or Verilog Can execute processes spatially as opposed to temporally The FPGA Coprocessor Option +Reprogrammable Logic -Requires pre-existing HW design -Needs to be specific processing, or have an intensive controller/compiler What is Coarse-grained computing Functional units (add, subtraction, multiplication - word-level operations) interconnected in a mesh style Coarse-Grained +Short Reconfiguration Times +Low Delay Characteristics +Low Power consumption -No Gate-level reconfigurability -Large stress for the scheduling level of a compiler (sparse connectivity, distributed register files) Coarse-Grained Architectures • Two main classes o Linear Array Very efficient for linearly pipelineable applications Struggles to support block-based applications Examples: RaPiD, PipeRench, RCP o Mesh-based Much more efficient for 2D applications Examples: KressArray, MATRIX, MorphoSys, ADRES FPGA Advances FPGAs now support dynamic partial reconfiguration Allows for sub-units, rather than reconfiguring the entire FPGA These units can be loaded with different functions Image Processing Using Partially Reconfigurable Blocks for co- processing Algorithm Image Size MicroBlaze SFU Speedup Time (s) Time (s) (6 SFUs) Sobel Smile12 120x12 23.057 1.907 12.1 Edge 0 0 Detection Kirsch Smile12 120x12 23.111 1.864 12.4 Edge 0 0 Detection Prewitt Smile12 120x12 23.051 1.908 12.1 Edge 0 0 Detection FPGA Partial Reconfiguration +Lower-level Hardware design and implementation Closer to a GPP +Significant Speed-up Closer to an ASIC -Deeper knowledge of system needs on the fly Future Potential Coarse-grained and FPGA designs are both viable Both designs require very good compilers Compilation of code and determination of design intent prior to execution appears to be the biggest delay moving forward Conclusion Reconfigurable Computing has a long way to go, but is definitely a viable option for the future. Questions?.

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Reconfigurable Computing
Reconfigurable Computing: A Survey of Systems and Software KATHERINE COMPTON Northwestern University AND SCOTT HAUCK University of Washington Due to its potential to greatly accelerate a wide variety of applications, reconfigurable computing has become a subject of a great deal of research. Its key feature is the ability to perform computations in hardware to increase performance, while retaining much of the flexibility of a software solution. In this survey, we explore the hardware aspects of reconfigurable computing machines, from single chip architectures to multi-chip systems, including internal structures and external coupling. We also focus on the software that targets these machines, such as compilation tools that map high-level algorithms directly to the reconfigurable substrate. Finally, we consider the issues involved in run-time reconfigurable systems, which reuse the configurable hardware during program execution. Categories and Subject Descriptors: A.1 [Introductory and Survey]; B.6.1 [Logic Design]: Design Style—logic arrays; B.6.3 [Logic Design]: Design Aids; B.7.1 [Integrated Circuits]: Types and Design Styles—gate arrays General Terms: Design, Performance Additional Key Words and Phrases: Automatic design, field-programmable, FPGA, manual design, reconfigurable architectures, reconfigurable computing, reconfigurable systems 1. INTRODUCTION of algorithms. The first is to use hard- wired technology, either an Application There are two primary methods in con- Specific Integrated Circuit (ASIC) or a ventional computing for the execution group of individual components forming a This research was supported in part by Motorola, Inc., DARPA, and NSF. K. Compton was supported by an NSF fellowship. S. Hauck was supported in part by an NSF CAREER award and a Sloan Research Fellowship.
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Syllabus: EEL4930/5934 Reconfigurable Computing
EEL4720/5721 Reconfigurable Computing (dual-listed course) Department of Electrical and Computer Engineering University of Florida Spring Semester 2019 Catalog Description: Prereq: EEL4712C or EEL5764 or consent of instructor. Fundamental concepts at advanced undergraduate level (EEL4720) and introductory graduate level (EEL5721) in reconfigurable computing (RC) based upon advanced technologies in field-programmable logic devices. Topics include general RC concepts, device architectures, design tools, metrics and kernels, system architectures, and application case studies. Credit Hours: 3 Prerequisites by Topic: Fundamentals of digital design including device technologies, design methodology and techniques, and design environments and tools; fundamentals of computer organization and architecture, including datapath and control structures, data formats, instruction-set principles, pipelining, instruction-level parallelism, memory hierarchy, and interconnects and interfacing. Instructor: Dr. Herman Lam Office: Benton Hall, Room 313 Office hours: TBA Telephone: (352) 392-2689 Email: [email protected] Teaching Assistant: Seyed Hashemi Office hours: TBA Email: [email protected] Class lectures: MWF 4th period, Larsen Hall 239 Required textbook: none References: . Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation, edited by Scott Hauck and Andre DeHon, Elsevier, Inc. (Morgan Kaufmann Publishers), Amsterdam, 2008. ISBN: 978-0-12-370522-8 . C. Maxfield, The Design Warrior's Guide to FPGAs, Newnes, 2004, ISBN: 978-0750676045.
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A MATLAB Compiler for Distributed, Heterogeneous, Reconfigurable
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Architecture and Programming Model Support for Reconfigurable Accelerators in Multi-Core Embedded Systems »
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Hardware Platforms for Embedded Computing Graphics: © Alexandra Nolte, Gesine Marwedel, 2003 Universität Dortmund Importance of Energy Efficiency
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Reconfigurable Computing
Reconfigurable Computing David Boland1, Chung-Kuan Cheng2, Andrew B. Kahng2, Philip H.W. Leong1 1School of Electrical and Information Engineering, The University of Sydney, Australia 2006 2Dept. of Computer Science and Engineering, University of California, La Jolla, California Abstract: Reconfigurable computing is the application of adaptable fabrics to solve computational problems, often taking advantage of the flexibility available to produce problem-specific architectures that achieve high performance because of customization. Reconfigurable computing has been successfully applied to fields as diverse as digital signal processing, cryptography, bioinformatics, logic emulation, CAD tool acceleration, scientific computing, and rapid prototyping. Although Estrin-first proposed the idea of a reconfigurable system in the form of a fixed plus variable structure computer in 1960 [1] it has only been in recent years that reconfigurable fabrics, in the form of field-programmable gate arrays (FPGAs), have reached sufficient density to make them a compelling implementation platform for high performance applications and embedded systems. In this article, intended for the non-specialist, we describe some of the basic concepts, tools and architectures associated with reconfigurable computing. Keywords: reconfigurable computing; adaptable fabrics; application integrated circuits; field programmable gate arrays (FPGAs); system architecture; runtime 1 Introduction Although reconfigurable fabrics can in principle be constructed from any type of technology, in practice, most contemporary designs are made using commercial field programmable gate arrays (FPGAs). An FPGA is an integrated circuit containing an array of logic gates in which the connections can be configured by downloading a bitstream to its memory. FPGAs can also be embedded in integrated circuits as intellectual property cores.
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A Reconfigurable Convolutional Neural Network-Accelerated
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Elements of High-Performance Reconfigurable Computing*
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Coarse-Grained Reconfigurable Computing with the Versat
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Reconfigurable Computing: Architectures and Design Methods
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Dionysios Diamantopoulos
Dionysios Diamantopoulos PHD · RESEARCH ASSOCIATE · R&D COMPUTER ENGINEER Thalwil, 8800, Zurich Canton, Switzerland (+41)-0-793339529 | [email protected] | diamantopoulos.github.io | dionysiosdiamantopoulos | dionisis.diamantopoulos | diamantopoulos Cover note: Developing innovative digital systems and design tools as well, by following a multi-facet approach is my core belief in the last years of my work experience. A strong research background gives me the analytical framework for simplifying complexity. In the past years I have actively participated in several leading multi-national projects delivering world-class digital systems with highly acknowledged contribution in the realization of reconfigurable and application specific computing. Being passionate about all things to do with silicon bring-up, I am constantly looking to deploy my expertise in world-class R&D computer engineering challenges. Education NTUA (Electrical & Computer Engineering - National Technical Univ. of Athens) Athens, Greece PH.D. IN COMPUTER SCIENCE & ENGINEERING November 2009 - July 2015 • Dissertation title: “Cross-Layer Rapid Prototyping and Synthesis of Application-Specific and Reconfigurable Many-accelerator Plat- forms”. Available in Greek (280 pages) & English (237 pages). • Advisor: Assoc. Prof. NTUA Dimitrios Soudris. • Promotion Committee: Assoc. Prof. NTUA D. Soudris, Prof. NTUA K. Pekmestzi, Assis. Prof. NTUA G. Economakos, Assis. Prof. U. Patras G. Theodoridis, Assoc. Prof. NKUA D. Reisis, Prof. RUB M. Hübner and Professor
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Power Efficiency Benchmarking of a Partially Reconfigurable, Many-Tile System Implemented on a Xilinx Virtex-6 FPGA
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