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Reconfigurable Computing: Architectures and Design Methods 1 Reconfigurable Computing: Architectures and Design Methods ∗ ∗∗ ∗∗∗ ∗ ∗ ∗∗ ∗ T.J. Todman , G.A. Constantinides , S.J.E. Wilton , O. Mencer , W. Luk and P.Y.K. Cheung Department of Computing, Imperial College London, UK ∗∗ Department of Electrical and Electronic Engineering, Imperial College London, UK ∗∗∗ Department of Electrical and Computer Engineering, University of British Columbia, Canada Abstract Reconfigurable computing is becoming increasingly attractive for many applications. This survey covers two aspects of reconfigurable computing: architectures and design methods. Our chapter includes recent advances in reconfigurable architectures, such as the Altera Stratix II and Xilinx Virtex 4 FPGA devices. We identify major trends in general-purpose and special-purpose design methods. I. INTRODUCTION Reconfigurable computing is rapidly establishing itself as a major discipline that covers various subjects of learning, including both computing science and electronic engineering. Reconfigurable computing involves the use of reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs), for computing purposes. Reconfigurable computing is also known as configurable computing or custom computing, since many of the design techniques can be seen as customising a computational fabric for specific applications [102]. Reconfigurable computing systems often have impressive performance. Consider, as an example, the point multiplication operation in Elliptic Curve cryptography. For a key size of 270 bits, it has been reported [172] that a point multiplication can be computed in 0.36 ms with a reconfigurable computing design implemented in an XC2V6000 FPGA at 66 MHz. In contrast, an optimised software implementation requires 196.71 ms on a dual-Xeon computer at 2.6 GHz; so the reconfigurable computing design is more than 540 times faster, while its clock speed is almost 40 times slower than the Xeon processors. This example illustrates a hardware design implemented on a reconfigurable computing platform. We regard such implementations as a subset of reconfigurable computing, which in general can involve the use of runtime reconfiguration and soft processors. Reconfigurable computing involves devices that can be reconfigured: their circuits can be changed after they are manufactured. This means that rather than using a single circuit for many applications, like a microprocessor, specific circuits can be generated for specific applications. How can circuits be changed after manufacture? Typically, reconfigurable devices use memory whose state switches logical elements (for example flip-flops and function generators), and the wiring between them. The state of all these memory bits is known as the configuration of the device, and determines its function (for example, image processor, network firewall). In section 3, we survey different styles of reconfigurable logical elements and wiring. New circuits for new applications can be uploaded to the reconfigurable device by writing to the configuration memory. An example of a reconfigurable device is the Xilinx Virtex 4 [116]. In this device, the configuration memory controls logical 2 elements (which include flip-flops, function generators, multiplexors and memories), and wiring, arranged in a hierarchical scheme. Designing circuits for reconfigurable devices is akin to designing application-specific integrated circuits, with the additional possibility that the design can change, perhaps in response to data received. Design methods can be general-purpose (for example, using the C programming language), or special-purpose (for example, using domain-specific tools such as MATLAB). We review such design methods in section 4. There are many commercial tools which support reconfigurable computing, including: • Xilinx's ISE [197], an example of a reconfigurable device vendor tool, which generates configurations for Xilinx's families of reconfigurable hardware from inputs such as hardware description languages. • Celoxica's DK [31] design suite, which allows descriptions based on the C programming language to be translated to configurations for reconfigurable hardware in the form of hardware description languages. • Synplicity Synplify Pro [168], which allows reconfigurable designs in hardware description languages (perhaps the output of Celoxica's DK) to be optimised and converted into a netlist, which reconfigurable device vendor tools (such as Xilinx's ISE) can then convert into a configuration. Is this speed advantage of reconfigurable computing over traditional microprocessors a one-off or a sustainable trend? Recent research suggests that it is a trend rather than a one-off for a wide variety of applications: from image processing [65] to floating-point operations [179]. Sheer speed, while important, is not the only strength of reconfigurable computing. Another compelling advantage is reduced energy and power consumption. In a reconfigurable system, the circuitry is optimized for the application, such that the power consumption will tend to be much lower than that for a general-purpose processor. A recent study [162] reports that moving critical software loops to reconfigurable hardware results in average energy savings of 35% to 70% with an average speedup of 3 to 7 times, depending on the particular device used. Other advantages of reconfigurable computing include a reduction in size and component count (and hence cost), improved time-to-market, and improved flexibility and upgradability. These advantages are especially important for embedded applications. Indeed, there is evidence [180] that embedded systems developers show a growing interest in reconfigurable computing systems, especially with the introduction of soft cores which can contain one or more instruction processors [7], [55], [100], [149], [150], [196]. In this chapter, we present a survey of modern reconfigurable system architectures and design methods. Although we also provide background information on notable aspects of older technologies, our focus is on the most recent architectures and design methods, as well as the trends that will drive each of these areas in the near future. In other words, we intend to complement other surveys [21], [36], [103], [146], [173] by: 1) providing an up-to-date survey of material that appears after the publication of the papers mentioned above; 2) identifying explicitly the main trends in architectures and design methods for reconfigurable computing; 3) examining reconfigurable computing from a perspective different from existing surveys, for instance classifying design methods as special-purpose and general-purpose; 4) offering various direct comparisons of technology options according to a selected set of metrics from different perspectives. The rest of the chapter is organised as follows. Section 2 contains background material that motivates the reconfigurable computing approach. Section 3 describes the structure of reconfigurable fabrics, showing how various researchers and vendors 3 have developed fabrics that can efficiently accelerate time-critical portions of applications. Section 4 then covers recent advances in the development of design methods that map applications to these fabrics, and distinguishes between those which employ special-purpose and general-purpose optimization methods. Finally, Section 5 concludes and summarises the main trends in architectures, design methods and applications of reconfigurable computing. II. BACKGROUND Many of today's compute-intensive applications require more processing power than ever before. Applications such as streaming video, image recognition and processing, and highly interactive services are placing new demands on the computation units that implement these applications. At the same time, the power consumption targets, the acceptable packaging and manufacturing costs, and the time-to-market requirements of these computation units are all decreasing rapidly, especially in the embedded hand-held devices market. Meeting these performance requirements under the power, cost, and time-to-market constraints is becoming increasingly challenging. In the following, we describe three ways of supporting such processing requirements: high-performance microprocessors, application-specific integrated circuits, and reconfigurable computing systems. High-performance microprocessors provide an off-the-shelf means of addressing processing requirements described earlier. Unfortunately for many applications, a single processor, even an expensive state-of-the-art processor, is not fast enough. In addition, the power consumption (100 watts or more) and cost (possibly thousands of dollars) state-of-the-art processors place them out-of-reach for many embedded applications. Even if microprocessors continue to follow Moore's Law so that their density doubles every 18 months, they may still be unable to keep up with the requirements of some of the most aggressive embedded applications. Application-specific integrated circuits (ASICs) provide another means of addressing these processing requirements. Unlike a software implementation, an ASIC implementation provides a natural mechanism for implementing the large amount of parallelism found in many of these applications. In addition, an ASIC circuit does not need to suffer from the serial (and often slow and power-hungry) instruction fetch, decode, and execute cycle that is at the heart of all microprocessors. Furthermore, ASICs consume less power than reconfigurable devices. Finally, an ASIC can contain just the right mix of functional units for a particular application;
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