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EMBEDDED ELECTRONIC SYSTEMS DRIVEN by RUN-TIME RECONFIGURABLE HARDWARE Francisco Fons Lluís DL: T

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EMBEDDED ELECTRONIC SYSTEMS DRIVEN by RUN-TIME RECONFIGURABLE HARDWARE Francisco Fons Lluís DL: T UNIVERSITAT ROVIRA I VIRGILI EMBEDDED ELECTRONIC SYSTEMS DRIVEN BY RUN-TIME RECONFIGURABLE HARDWARE Francisco Fons Lluís DL: T. 877-2012 Francisco Fons Lluís EMBEDDED ELECTRONIC SYSTEMS DRIVEN BY RUN-TIME RECONFIGURABLE HARDWARE DOCTORAL THESIS Supervised by Dr. Enrique F. Cantó Navarro Departament d’Enginyeria Electrònica, Elèctrica i Automàtica Tarragona 2012 UNIVERSITAT ROVIRA I VIRGILI EMBEDDED ELECTRONIC SYSTEMS DRIVEN BY RUN-TIME RECONFIGURABLE HARDWARE Francisco Fons Lluís DL: T. 877-2012 UNIVERSITAT ROVIRA I VIRGILI EMBEDDED ELECTRONIC SYSTEMS DRIVEN BY RUN-TIME RECONFIGURABLE HARDWARE Francisco Fons Lluís DL: T. 877-2012 ESCOLA TÈCNICA SUPERIOR D’ENGINYERIA DEPARTAMENT D’ENGINYERIA ELECTRÒNICA, ELÈCTRICA I AUTOMÀTICA Avinguda dels Països Catalans, 26 Campus Sescelades 43007 Tarragona – SPAIN Tel. + 34 977 559 610 Fax + 34 977 559 605 e-mail: [email protected] http://sauron.etse.urv.es/DEEEA/ Enrique F. Cantó Navarro, professor at the Department of Electronic, Electrical and Automatic Control Engineering of the University Rovira i Virgili, STATES: That the present thesis, entitled “Embedded electronic systems driven y run-time reconfigurable hardware”, presented by Francisco Fons Lluís for the award of the degree of Doctor, has been carried out under my supervision at the Department of Electronic, Electrical and Automatic Control Engineering of the University Rovira i Virgili. Tarragona, March 2012 Doctoral Thesis Supervisor Dr. Enrique F. Cantó Navarro UNIVERSITAT ROVIRA I VIRGILI EMBEDDED ELECTRONIC SYSTEMS DRIVEN BY RUN-TIME RECONFIGURABLE HARDWARE Francisco Fons Lluís DL: T. 877-2012 UNIVERSITAT ROVIRA I VIRGILI EMBEDDED ELECTRONIC SYSTEMS DRIVEN BY RUN-TIME RECONFIGURABLE HARDWARE Francisco Fons Lluís DL: T. 877-2012 Abstract Runtime reconfigurable hardware technology has experienced a big progress in the last decade after both academia and industry research communities have jointly got involved in this issue, bringing the necessary talent and energy to definitively put this technology to the service of the society. Many indicators confirm today that dynamic partial reconfiguration is no longer just for the avid early explorers of the recent past: improved programmable logic devices supporting this technology have been shipped; a valid method and design flow supported by acceptable EDA tools has been established; potential use cases and killer applications that can benefit from this technology have been identified; and last but not least, the first commercial products/systems driven by this technology are already being launched to the market. This PhD dissertation addresses the exploration of runtime reconfigurable hardware to implement embedded applications, exploiting its inherent strengths in flexibility and adaptability, as well as in power and system cost savings. This work does research on the conception of an open system architecture driven by a reconfiguration engine suitable for synthesizing flexible embedded electronic systems on SRAM-based FPGA/SoC devices. Thereby, it pays attention to the identification, from an application driven viewpoint, of computational tasks typically synthesized in static hardware –e.g. generalpurpose processors (MCU, DSP, GPU) or programmable logic (FPGA, SoC)– in which dynamic partial reconfiguration can be used to advantage. Several application fields like control engineering (e.g. PID and fuzzy logic controllers), digital computing (e.g. trigonometrics, 2D convolution), or full complex electronic systems (e.g. biometric recognition system, automotive electronic control unit) have been investigated from an algorithmic standpoint first and prototyped then through commercial devices –e.g., Xilinx, Atmel and Altera platforms– provided with onthe-fly reconfiguration, pioneering the use of runtime reconfigurable hardware by first time in the scientific literature in some of them. This work demonstrates that a complete run-time reconfigurable computing ecosystem provided with a high enough level of maturity for its exploitation in the industry is today already in place, making feasible –although further advances are still required, especially regarding automatic tools– the professional design and development of embedded electronic systems. Thus, in a future of digital system design increasingly parallel and programmable, many application opportunities for runtime reconfigurable hardware abound. In this sense, the future of this computing paradigm is highly promising, hoping that the intellectual effort invested in this area by the research community, the FPGA vendors and the industry in general helps to enhance the life quality of the human beings in the near future. The work conducted in this PhD dissertation aims at contributing to this goal. v UNIVERSITAT ROVIRA I VIRGILI EMBEDDED ELECTRONIC SYSTEMS DRIVEN BY RUN-TIME RECONFIGURABLE HARDWARE Francisco Fons Lluís DL: T. 877-2012 vi UNIVERSITAT ROVIRA I VIRGILI EMBEDDED ELECTRONIC SYSTEMS DRIVEN BY RUN-TIME RECONFIGURABLE HARDWARE Francisco Fons Lluís DL: T. 877-2012 Acronyms and abbreviations AFAS Automatic Fingerprint Authentication System AHB Advanced Highperformance Bus ALU Arithmetic Logic Unit AMBA Advanced Microcontroller Bus Architecture ASIC Application Specific Integrated Circuit ASIL Automotive Safety Integrity Level ASIP ApplicationSpecific Instructionset Processor ASSP Application Specific Standard Product API Application Programming Interface ARM Advanced RISC Machine AXI Advanced Extensible Interface BOM Bill Of Materials CAD Computer Aided Design CAGR Compound Annual Growth Rate CAN Controller Area Network CISC Complex Instruction Set Computing CLB Configurable Logic Block CORDIC COordinate Rotation DIgital Computer CPLD Complex Programmable Logic Device CPU Central Processing Unit CUDA Compute Unified Device Architecture DDR-SDRAM Doble Data Rate Synchronous Dynamic Random Access Memory DMA Direct Memory Access DPRAM Dual Port Random Access Memory DRAM Dynamic Random Access Memory D&D Design and Development ECU Electronic Control Unit EDA Electronic Design Automation E/E Electrical/Electronic EPP Extensible Processing Platform ESA European Space Agency FLC Fuzzy Logic Controller FPGA Field Programmable Gate Array FPSLIC Field Programmable System Level Integrated Circuit FPU Floating Point Unit FSM Finite State Machine GPGPU GeneralPurpose computation on Graphics Processing Unit GPP GeneralPurpose Processor GPS Global Positioning System GPU Graphics Processing Unit HDL Hardware Description Language HLS HighLevel Synthesis HPC HighPerformance Computing HPRC HighPerformance Reconfigurable Computing ICAP Internal Configuration Access Port ICT Information & Communication Technology IEC International Electrotechnical Commission I/O Input/Output IP Intellectual Property ISA Instruction Set Architecture ISO International Organization for Standardization vii UNIVERSITAT ROVIRA I VIRGILI EMBEDDED ELECTRONIC SYSTEMS DRIVEN BY RUN-TIME RECONFIGURABLE HARDWARE Francisco Fons Lluís DL: T. 877-2012 JTAG Joint Test Action Group LCD Liquid Crystal Display LUT Look-Up Table MAC Multiplier-Accumulator MCU Microcontroller Unit MCyT Spanish Ministry of Science and Technology MMU Memory Management Unit MPMC Multi-Port Memory Controller NASA National Aeronautics and Space Administration NoC Network-onChip NPI Native Port Interface NRE NonRecurring Engineering NVM NonVolatile Memory OEM Original Equipment Manufacturer OS Operating System OTP One-Time Programmable PAL Programmable Array Logic PC Personal Computer PCB Printed Circuit Board PID Proportional Integral Derivative PIN Personal Identification Number PLA Programmable Logic Arrays PLB Peripheral Local Bus PLD Programmable Logic Device PR Partial Reconfiguration PROM Programmable Read-Only Memory PRM Partially Reconfigurable Module PRR Partially Reconfigurable Region PSoC Programmable System-on-Chip RAM Random Access Memory RC Reconfigurable Computing RISC Reduced Instruction Set Computing ROM Read Only Memory RTL Register Transfer Level SDRAM Synchronous Dynamic Random Access Memory SEU Single Event Upset SME Small and Medium Enterprises SoC System-on-Chip SoPC System-on-Programmable-Chip SRAM Static Random Access Memory SWaP Size, Weight and Power UART Universal Asynchronous Receiver Transmitter VHDL Very High Speed Integrated Circuit Hardware Description Language VLIW Very Long Instruction Word V&V Verification and Validation XCL Xilinx CacheLink viii UNIVERSITAT ROVIRA I VIRGILI EMBEDDED ELECTRONIC SYSTEMS DRIVEN BY RUN-TIME RECONFIGURABLE HARDWARE Francisco Fons Lluís DL: T. 877-2012 List of figures Figure 1.1 Milestones of the roadmap towards runtime reconfigurable computing Figure 1.2 Use of FPGA devices Figure 1.3 Recent achievements in runtime reconfigurable computing Figure 1.4 DES horizontal (design technology) and vertical (embedded apps) disciplines Figure 2.1 Antifuse programming technology Figure 2.2 SRAM programming technology Figure 2.3 MRAM programming technology Figure 2.4 SRAM-based FPGA conceptual view Figure 2.5 SRAM-based FPGA logic cell Figure 4.1 Embedded system components breakdown into host CPU, reconfiguration engine, external memory and I/O Figure 4.2 High level model of the FPGA embedded system split in physical devices Figure 4.3 Dynamic partial self-reconfigurable FPGA high level model Figure 4.4 Minimalist system architecture based on one PR partition and one repository Figure 4.5 Embedded system architecture based on two PR partitions and one repository Figure 4.6 Embedded system architecture composed of two PR partitions and two sytem repositories
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