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Architectures Des Accélérateurs De Traitement Flexibles Pour Les Systèmes Sur Puce Pascal Benoit

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Architectures Des Accélérateurs De Traitement Flexibles Pour Les Systèmes Sur Puce Pascal Benoit Architectures des Accélérateurs de Traitement Flexibles pour les Systèmes sur Puce Pascal Benoit To cite this version: Pascal Benoit. Architectures des Accélérateurs de Traitement Flexibles pour les Systèmes sur Puce. Micro et nanotechnologies/Microélectronique. Université Montpellier II - Sciences et Techniques du Languedoc, 2004. Français. tel-00007352 HAL Id: tel-00007352 https://tel.archives-ouvertes.fr/tel-00007352 Submitted on 9 Nov 2004 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. ACADEMIE DE MONTPELLIER UNIVERSITE MONTPELLIER II - SCIENCES ET TECHNIQUES DU LANGUEDOC - THESE pour obtenir le grade de DOCTEUR DE L ‘U NIVERSITE MONTPELLIER II Discipline : Génie Informatique, Automatique et Traitement du Signal Formation Doctorale : Systèmes Automatiques et Microélectroniques Ecole Doctorale : Information, Structures, Systèmes présentée et soutenue publiquement par Pascal BENOIT Le lundi 11 octobre 2004 ARCHITECTURES DES ACCELERATEURS DE TRAITEMENT FLEXIBLES POUR LES SYSTEMES SUR PUCE JURY CAMBON Gaston Professeur, LIRMM, Université Montpellier II Président du jury ROBERT Michel Professeur, LIRMM, Université Montpellier II Directeur de thèse DEMIGNY Didier Professeur, R2D2, Université Rennes I Rapporteur GARDA Patrick Professeur, LISIF, Université Pierre et Marie Curie Paris VI Rapporteur SENTIEYS Olivier Professeur, R2D2, Université Rennes I Examinateur SASSATELLI Gilles Chargé de Recherche CNRS, LIRMM, Université Montpellier II Examinateur TORRES Lionel Maître de Conférences, LIRMM, Université Montpellier II Membre invité Le progrès a encore des progrès à faire » P. Meyer i REMERCIEMENTS Ce document présente les travaux que j‘ai effectués durant trois années au LIRMM et je tiens à remercier en tout premier lieu M. Michel Habib, directeur du laboratoire, ainsi que tout le personnel administratif et technique, pour m‘avoir permis de réaliser cette thèse dans d‘excellentes conditions. Je remercie également les permanents du département microélectronique et leurs représentants, M. Michel Renovell et M. Pascal Nouet, notamment pour la bonne ambiance de travail qui règne au sein de cette unité de recherche. Je remercie M. Didier Demigny et M. Patrick Garda d‘avoir accepté d‘être les rapporteurs de cette thèse, ainsi que M. Olivier Sentieys pour sa participation au jury. Je remercie mon directeur de thèse M. Michel Robert, pour la confiance qu‘il m‘a accordée depuis le début. Merci également à M. Gaston Cambon qui a participé à l‘encadrement de ces travaux. Je tiens à remercier chaleureusement mon encadrant Lionel Torres, pour sa disponibilité, son écoute et sa bonne humeur. Aussi, je remercie sincèrement Gilles Sassatelli pour sa participation active à ce projet et sans qui ce sujet de thèse n‘aurait vu le jour. Merci également à Thierry Gil pour son aide sur la carte de prototypage. Je tiens également à remercier M. Juergen Becker, ainsi que l‘ensemble du personnel de son laboratoire, à l‘Université de Karlsruhe, d‘avoir accepté de m‘accueillir pour mon stage post-doctoral. Je voudrais adresser toute ma sympathie aux collègues que j'ai eu le plaisir de côtoyer au cours de ces quatre années, la promo Olivier (rendez-vous en Allemagne!), Régis, Alain, les mélomanes Laurent, Serge, Mariane, Ben et Wence, les colocataires du box David, Jean- Denis, Daniel et Alex, les sportifs (Foot, Baby-foot et autres …) Arnaud, Abou, Norbert, Seb, Fabrice, Luigi, Julien, ainsi que tous les anciens et nouveaux qui se reconnaîtront ! Enfin, un grand merci à toutes les personnes qui partagent ma vie personnelle, qui m‘ont encouragé et soutenu durant ces trois années. Je pense évidement à Sylvie, à mes parents, ma sŒur, ma famille proche et mes amis, montpelliérains, nîmois, lillois, niçois et parisiens… ii iii RESUME Les systèmes sur puce intègrent sur un même substrat de silicium l‘ensemble des organes nécessaires à la prise en charge des différentes fonctionnalités du système. Pour la partie dédiée aux traitements numériques, le microprocesseur central est souvent déchargé des applications critiques (traitement du signal et des images en général) par un accélérateur de traitement. C‘est par rapport à l‘architecture du coprocesseur que se pose la problématique de cette thèse. En effet, de nombreuses approches sont possibles pour ce dernier, et vouloir les comparer s‘avère être une tâche complexe. Après avoir fait un état de l‘art des différentes solutions architecturales de traitement flexibles, nous proposons un ensemble de métriques dans une optique de caractérisation. Nous illustrons alors notre méthode par la caractérisation et la comparaison d‘architectures représentatives de l‘état de l‘art. Nous montrons que c‘est par une exploitation efficace du parallélisme que les coprocesseurs peuvent améliorer significativement leurs performances. Or, malgré de réelles aptitudes, les accélérateurs ne sont pas toujours capables de tirer parti de ce potentiel. C‘est pour cela que nous proposons une méthode générale de multiplexage matériel, qui permet d‘améliorer les performances par l‘exploitation dynamique du parallélisme (boucle et tâches). Par son application à un cas concret, un système baptisé Saturne, nous prouvons que par l‘adjonction d‘un contrôleur dédié au multiplexage matériel, les performances de l‘accélérateur sont quasiment doublées, et ce avec un faible surcoût matériel. iv GGLOSSAIRE AAA Adéquation Algorithme Architecture ALU Arithmetic-Logic Unit ARM Advanced RISC Machine ASIC Application-Specific Integrated Circuit CAO Conception Assistée par Ordinateur CDFG Control Data Flow Graph CDMA Code Division Multiple Access CISC Complex-Instruction-Set computer CMOS Complementary Metal-Oxide Semiconductor CFB Configurable Functional Block CLB Configurable Logic Block CPLD Complex Programmable-Logic Device CPU Central Processing Unit CW ConfigWare DCT Discrete Cosine Transform DFG Data Flow Graph DMA Direct-Memory Access DRAM Dynamic Random-Access Memory DSP Digital Signal Processor (ou Processing) EDGE Enhanced Data GSM Environment F Farad FFT Fast Fourier Transform FIFO First-In, First-Out FIR Finite Impulse Response FPGA Field-Programmable Gate Array FPU Floating-Point Unit FSM Finite State Machine GOPS Giga-Operations Per Second GPP General Purpose Processor GPRS General Packet Radio Service GSM Global System for Mobile communications HCDFG Hierarchical Control Data Flow Graph HDL Hardware Description Language HW HardWare I/O Input/Output ILP Instruction Level Parallelism IIR Infinite Impulse Response IP Intellectual Property JPEG Joint Photographic Experts Group LLP Loop Level Parallelism LUT Look Up Table MAC Multiplication-ACcumulation MEF Machine à Etats Finis MIMD Multiple-Instruction, Multiple-Data vi MIPS Million Instructions Per Second MOPS Million Operations Per Second MPEG Moving Picture Experts Group NOC Network On Chip OS Operating System PC Personal Computer PDA Personal Digital Assistant RAM Random Access Memory RISC Reduced-Instruction-Set Computer RTL Register Transfer Level RTOS Real-Time Operating System SDRAM Synchronous DRAM SIMD Single-Instruction, Multiple-Data (array) SIP System In a Package SMT Simultaneous Multi-Thread SPARC Scalable Processor ARChitecture SOC System On a Chip SRAM Static RAM SW SoftWare TDMA Time-Division Multiple Access (communications) TSI Traitement du Signal et des Images UAL Unité Arithmétique et Logique UMTS Universal Mobile Telecommunication System VGA Video Graphics Adapter VHDL VHSIC (Very High Speed Integrated Circuits) HDL VLIW Very Long Instruction Word VLSI Very-Large-Scale Integration vii SSOMMAIRE viii Sommaire ix Introduction générale..................................................................................... 1 Chapitre 1 : Systèmes sur puce et architectures de traitement....................... 7 1. Les systèmes sur puce...........................................................................................9 1.1. Intégration des systèmes sur Puce .....................................................................................................9 1.2.Les critères de performance des systèmes........................................................................................11 2. Les architectures de traitement .......................................................................... 14 2.1. Familles d’architectures de traitement .............................................................................................14 2.2. Modèles de traitement .......................................................................................................................14 2.3.Architectures mixtes............................................................................................................................15 3. Contributions ...................................................................................................... 17 3.1. Etat de l’art des architectures de traitement flexibles....................................................................18 3.2. Métriques de caractérisation .............................................................................................................20
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