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A Multicore Computing Platform for Benchmarking

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A Multicore Computing Platform for Benchmarking A MULTICORE COMPUTING PLATFORM FOR BENCHMARKING DYNAMIC PARTIAL RECONFIGURATION BASED DESIGNS by DAVID A. THORNDIKE Submitted in partial fulfillment of the requirements For the degree of Master of Science Thesis Advisor: Dr. Christos A. Papachristou Department of Electrical Engineering and Computer Science CASE WESTERN RESERVE UNIVERSITY August, 2012 CASE WESTERN RESERVE UNIVERSITY SCHOOL OF GRADUATE STUDIES We hereby approve the thesis/dissertation of David A. Thorndike candidate for the Master of Science degree *. (signed) Christos A.Papachristou (chair of the committee) Francis L. Merat Francis G. Wolff (date) June 1, 2012 *We also certify that written approval has been obtained for any proprietary material contained therein. Table of Contents List of Figures ................................................................................................................... iii List of Tables .................................................................................................................... iv Abstract .............................................................................................................................. v 1. Introduction .................................................................................................................. 1 1.1 Motivation .......................................................................................................... 1 1.2 Contributions ...................................................................................................... 2 1.3 Thesis Outline .................................................................................................... 2 2. Background .................................................................................................................. 3 2.1 Multicore Computing ......................................................................................... 3 2.2 Reconfigurable Computing ................................................................................ 6 2.3 Dynamic Partial Reconfigurability ................................................................... 10 2.4 Related Work .................................................................................................... 12 3. Platform Development Process .................................................................................. 15 3.1 OpenSPARC ..................................................................................................... 16 3.2 LEON3 ............................................................................................................. 19 3.3 Xilinx Virtex-5 ................................................................................................. 22 3.4 GNU Tools / GRLIB ........................................................................................ 24 3.5 Xilinx ISE ......................................................................................................... 25 3.6 SnapGear Linux (for SMP) .............................................................................. 26 3.7 Benchmarking Applications ............................................................................. 27 4. General Implementation Flow ................................................................................... 31 4.1 Hardware and Software Tools .......................................................................... 31 i 4.2 Board Functional Verification .......................................................................... 32 4.3 Hardware Development .................................................................................... 34 4.4 Software Development ..................................................................................... 37 5. Results ........................................................................................................................ 41 6. Summary .................................................................................................................... 50 6.1 Conclusion ........................................................................................................ 50 6.2 Future Work ..................................................................................................... 50 Appendix A ...................................................................................................................... 51 Bibliography .................................................................................................................... 83 ii List of Figures Figure 1. IBM's Cell Processor ...........................................................................................6 Figure 2. DPR for Functional Modification and Size Reduction .....................................11 Figure 3. Leon3 SMP with reconfigurable coprocessors .................................................13 Figure 4. Xilinx XUPV5-LX110T development board (ML509) ...................................15 Figure 5. Virtex-5 FPGA ML50x Evaluation Platform Block Diagram .........................18 Figure 6. Block diagram of configurable LEON3 processor ............................................21 Figure 7. Example LEON3 multicore SoC with other GRLIB IP cores ..........................22 Figure 8. Linear speedup of OpenMPBench's BasicMath ...............................................29 Figure 9. LEON3 Xilinx ML509 Template Design from leon3mp.vhd ..........................35 Figure 10. LEON3 processor core configurability ..........................................................36 iii List of Tables Table 1. Soft-core CPUs suitable for FPGA implementation ..........................................20 Table 2. Xilinx Virtex-5 LX50T and LX110T Comparison ............................................33 Table 3. Single Core Synthesis Results ...........................................................................41 Table 4. Multicore Synthesis Results...............................................................................44 Table 5. Benchmark Performance Results .......................................................................48 iv A Multicore Computing Platform for Benchmarking Dynamic Partial Reconfiguration Based Designs Abstract by DAVID ANDREW THORNDIKE With the increasing application of multiple processor cores (multicores) within embedded system applications, as well as the pervasive utilization of the field- programmable gate array (FPGA), the embedded system development community has been exploring the advantages of the dynamically reconfigurable nature of FPGAs. Given size and power limitations, a primary motivation for this interest is to enable dynamic customization of hardware to optimize system performance for the various algorithms that a system encounters. This work presents a hardware based platform for studying dynamic reconfiguration of FPGAs in the context of multicore embedded systems. It also presents a methodology for developing the hardware and software for these systems. An important aspect of this work was to maximize the utilization of open source hardware and software intellectual property (IP). An example of the basic implementation flow is also provided, along with some benchmarking results. v 1. Introduction 1.1 Motivation Over the past few decades, since the commercial introduction of the Field Programmable Gate Arrays (FPGA) by Xilinx, the configurable nature of FPGAs brought them to the center of attention for many in the field of computing. Though recent advances by Actel have introduced the first commercially available FPGAs with configurable analog blocks (Morris, 2005), FPGAs have primarily occupied the realm of digital logic and microprocessor functionality. When the density of these devices got sufficiently large, designers were able to implement multiple microprocessor cores within a single FPGA in order to achieve the performance and power advantages that brought multicore architectures to general-purpose CPUs and ASIC platforms. With the advancement of dynamic partial reconfiguration capabilities provided by Xilinx tools and devices, new opportunities have unfolded to explore dynamic reconfigurability of multicore systems. The intent of this work is to develop a hardware platform on which the capabilities of this powerful and flexible technology can be explored. Since reconfigurable computing has found wide ranging applicability throughout the field of computing, the primary focus of this work will be on its application to embedded systems. These are microprocessor based systems with customized software for the sole purpose of performing or controlling a set of specific functions, often involving real-time operations. The end-user may be provided options or choices in the operation of the system, but unlike that of a personal computer, the user is generally not provided the ability to program or change the software of an embedded system (Heath, 2003). 1 1.2 Contributions In this work, a reconfigurable multicore computing platform is presented. A method is demonstrated to create such a platform through the application of an open source soft- core processor and open source development tools along with Xilinx tools and a Virtex-5 evaluation board, also referred to as XUPV5 or ML509. 1.3 Thesis Outline This thesis is organized as follows: • Chapter 2: Presents background information on multicore computing and reconfigurable computing, including dynamic partial reconfiguration (DPR). Related work in the area of DPR design on the ML509 is also described. • Chapter 3: Describes components
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