Reiner Hartenstein, University of Kaiserslautern, Germany [email protected] http://kressarray.de Enabling Technologies for Reconfigurable Computing Schedule Xputer Lab July 8, 2002, ENST, Paris, France University of Kaiserslautern time slot xx.30 – xx.00 Reconfigurable Computing (RC) Reiner Hartenstein Enabling Technologies for xx.00 – xx.30 coffee break University of Reconfigurable Computing and Kaiserslautern xx.30 – xx.00 Design / Compilation Techniques Software / Configware Co-Design xx.00 – xx.00 lunch break xx.00 – xx.30 Resources for Data-Stream-based RC Part 4: xx.30 – xx.00 Recent developments coffee break xx.00 – xx.30 FPGAs: recent developments -. © 2002, [email protected] 2 http://kressarray.de Opportunities by new patent laws ? >> Configware Market University of Kaiserslautern University of Kaiserslautern • Configware Market • FPGA Market • to clever guys being keen on patents: • Embedded Systems (Co-Design) • Hardwired IP Cores on Board • Run-Time Reconfiguration (RTR) • don‘t file for patent following details ! • Rapid Prototyping & ASIC Emulation • Evolvable Hardware (EH) • everything shown in this presentation • Academic Expertise • ASICs dead has been published years ago • Soft CPU • HLLs • Problems to be solved © 2002, [email protected] 3 http://kressarray.de © 2002, [email protected] 4 http://kressarray.de Configware heading for mainstream bleeding edge designs University of Kaiserslautern University of Kaiserslautern • Configware market taking off for mainstream • Infinite amount of gates not yet available on a chip • FPGA-based designs more complex, even SoC • 3 mio gates (10 mio in 2003 ?) far away from "infinite" • No design productivity and quality without good configware libraries (soft IP cores) from various • Bleeding edge designs only with sophisticated EDA tools application areas. • Excessive optimization needed • Growing no. of independent configware houses • Hardware epertise is inevitable for the designer. (soft IP core vendors) and design services • improve and simplify the design flow the user • AllianceCORE & Reference Design Alliance • provide rich configware libraries of soft IP cores, • Currently the top FPGA vendors are the key • control appl., networking, wireless telecommunication, data innovators and meet most configware demand. communication, embedded and consumer markets. © 2002, [email protected] 5 http://kressarray.de © 2002, [email protected] 6 http://kressarray.de Enabling Technologies for Reconfigurable Computing and Software / Configware Co-Design, Part 4: ENST, Paris, 8 July 2002 Recent Developments # Reiner Hartenstein, University of Kaiserslautern, Germany [email protected] http://kressarray.de Configware (soft IP Products) EDA as the Key Enabler (major EDA vendors) Xputer Lab University of Kaiserslautern University of Kaiserslautern • For libraries, creation and reuse of configware • Select EDA quality / productivity, not FPGA architectures • To search for IPs see: List of all available IP • EDA often has massive software quality problems • Customer: highest priority EDA center of excellence • The AllianceCORE program is a cooperation between Xilinx and third-party core developers – collecting EDA expertise and EDA user experience – to assemble best possible tool environments • The Xilinx Reference Design Alliance Program – for optimum support design teams • The Xilinx University Program – to cope with interoperability problems – to keep track with the EDA scene as a rapidly moving target • LogiCORE soft IP with LogiCORE PCI Interface. • being fabless, FPGA vendors spend most qualified manpower • Consultants in development of EDA, IP cores, applications , support • Xilinx and Altera are morphing into EDA companies. © 2002, [email protected] 7 http://kressarray.de © 2002, [email protected] 8 http://kressarray.de OS for FPGAs EDA Software for Xilinx University of Kaiserslautern University of Kaiserslautern • separate EDA software market, comparable to •Full design flow from Cadence, Mentor, & Synopsys the compiler / OS market in computers, •Xilinx Software AllianceEDA Program: • Cadence, Mentor, Synopsys just jumped in. –Alliance Series Development System. • < 5% Xilinx / Altera income from EDA SW –Foundation Series Development Systems. • Changing EDA Tools Market • Major configware –Xilinx Foundation Series ISE (Integrated Synthesis Environment) EDA vendors –free WebPOWERED SW w. WebFitter & WebPACK-ISE – Altera – Cadence –StateCAD XE and HDL Bencher – Mentor Graphics –Foundation Base Express – Synopsys –Foundation ISE Base Express – Xilinx © 2002, [email protected] 9 http://kressarray.de © 2002, [email protected] 10 http://kressarray.de Foundation ISE Base Express Altera EDA University of Kaiserslautern University of Kaiserslautern • Altera was founded in June 1983 • ModelSim Xilinx Edition • JBits SDK • EDA: synthesis, place & route, and, verification (ModelSim XE) • The Xilinx XtremeDSP • Quartus II: APEX, Excalibur, Mercury, FLEX 6000 families • Forge Compiler Initiative • MAX+PLUS II: FLEX, ACEX & MAX families • Modular Design • MathWorks / Xilinx • Flow with Quartus II: Mentor Graphics, Synopsys, Synplicity deliver a design design software to support Altera SOPC solutions. • Chipscope ILA Alliance • System Generator • Mentor: only EDA vendor w. complete design environment f. APEX • The Xilinx System II incl. IP, design capture, simulation, synthesis, and h/s co- Generator • Wind River / Xilinx verification • XPower alliance • Configware: Altera offers over a hundred IP cores • Third party IP core design services and consultants © 2002, [email protected] 11 http://kressarray.de © 2002, [email protected] 12 http://kressarray.de Enabling Technologies for Reconfigurable Computing and Software / Configware Co-Design, Part 4: ENST, Paris, 8 July 2002 Recent Developments # Reiner Hartenstein, University of Kaiserslautern, Germany [email protected] http://kressarray.de Cadence Mentor Graphics Xputer Lab University of Kaiserslautern University of Kaiserslautern • FPGA Designer: top-down FPGA design system, • System Design and Verification. • high-level mapping, architecture-specific optimization, • Verilog,VHDL, schematic-level design entry. • PCB design and analysis: • Verilog, VHDL to Synergy (logic synthesis) and FPGA Designer • IC Design and Verification • FPGAs simulated by themselves using Cadence's Verilog- • shifts ASIC design flow to FPGAs (Altera, Xilinx) XL or Leapfrog VHDL simulators and – by FPGA Advantage with IP support • simulated w. rest of the system design w. Logic – by ModuleWare, Workbench board/system verification env‘ment. – Xilinx CORE Generator • Libraries for the leading FPGA manufacturers. – Altera MegaWizard integration, © 2002, [email protected] 13 http://kressarray.de © 2002, [email protected] 14 http://kressarray.de Synopsys >> FPGA Market University of Kaiserslautern University of Kaiserslautern • Configware Market • FPGA Market • FPGA Compiler II • Embedded Systems (Co-Design) • Version of ASIC Design Compiler Ultra • Hardwired IP Cores on Board • Run-Time Reconfiguration (RTR) • Block Level Incremental Synthesis (BLIS) • Rapid Prototyping & ASIC Emulation • Evolvable Hardware (EH) • ASIC <-> FPGA migration • Academic Expertise • ASICs dead • Actel, Altera, Atmel, Cypress, Lattice, • Soft CPU Lucent, Quicklogic, Triscend, Xilinx • HLLs • Problems to be solved © 2002, [email protected] 15 http://kressarray.de © 2002, [email protected] 16 http://kressarray.de Top 4 PLD Manufacturers 2000 FPGA market 1998 / 1999 University of Kaiserslautern University of Kaiserslautern global sales (mio $) 1999 rank Actel Source: 1998 1999 Lattice 6% Xilinx IC Insights Inc. 1 Xilinx 629 899 15% 42% Meanwhile, 2 Altera 654 837 Xilinx acquired 3 Lattice 206 410 Philips' MOS PLD 4 Actel 154 172 business, 5 Lucent 100 120 Lattice Altera $3.7 Bio purchased Vantis. 6 Cypress 41 43 37% Top 4 PLD Manufacturers 2000 . 7 Quicklogic 30 40 8 Atmel 32 38 © 2002, [email protected] 17 http://kressarray.de © 2002, [email protected] 18 http://kressarray.de Enabling Technologies for Reconfigurable Computing and Software / Configware Co-Design, Part 4: ENST, Paris, 8 July 2002 Recent Developments # Reiner Hartenstein, University of Kaiserslautern, Germany [email protected] http://kressarray.de .... into every application .... going into every type of application Xputer Lab [Gordon Bell] University of Kaiserslautern University of Kaiserslautern • [Dataquest] PLD market > $7 billion by 2003. • „ fastest growing segment of semiconductor market.“ • IP reuse and "pre-fabricated" components for the efficiency of design and use for PLDs • FPGAs are going into every type of application. © 2002, [email protected] 19 http://kressarray.de © 2002, [email protected] 20 http://kressarray.de Xilinx Xilinx Flexware University of Kaiserslautern University of Kaiserslautern •fabless FPGA semi vendor, San Jose, Ca, founded 1984 • Virtex, Virtex-II, first w. 1 mio system gates. – Virtex-E series > 3 mio system gates. •key patents on FPGAs (expiring in a few years) • Virtex-EM on a copper process & addit. on chip memory f. network switch appl. • The Virtex XCV3200E > 3 million gates, 0.15-micron technology, •Fortune 2001: No. 14 Best Company to work for in (intel: • Spartan, Spartan-XL, Spartan-II no. 42, hp no. 64, TI no. 65). – for low-cost, high volume applications as ASIC replacements •DARPA grant (Nov‘99) to develop Jbits API tools for – Multiple I/O standards, on-chip block RAM, digital delay lock