Coarse Grain Reconfigurable Architectures

Coarse Grain Reconfigurable Architectures

Reiner Hartenstein, University of Kaiserslautern, Germany [email protected] http://hartenstein.de Enabling Technologies for Reconfigurable Computing Schedule Xputer Lab November 21, 2001, Tampere, Finland University of Kaiserslautern time slot 08.30 – 10.00 Reconfigurable Computing (RC) Reiner Hartenstein Enabling Technologies for 10.00 – 10.30 coffee break University of 10.30 – 12.00 Stream-based Computing for RC Kaiserslautern Reconfigurable Computing 12.00 – 14.00 lunch break 14.00 – 15.30 Resources for RC Part 3: 15.30 – 16.00 coffee break Resources for RC 16.00 – 17.30 FPGAs: recent developments Wednesday, November 21, 14.00 – 15.30 hrs. © 2001, [email protected] 2 http://www.fpl.uni-kl.de >> Configware Industry Configware heading for mainstream University of Kaiserslautern University of Kaiserslautern • Configware market taking off for mainstream • FPGA-based designs more complex, even SoC • Configware Industry • No design productivity and quality without good configware libraries (soft IP cores) from various • Terminology application areas. • Growing no. of independent configware houses • MoPL data-procedural language (soft IP core vendors) and design services • Xputer architecture and circuitry • AllianceCORE & Reference Design Alliance • Currently the top FPGA vendors are the key http://www.uni-kl.de innovators and meet most configware demand. © 2001, [email protected] 3 http://www.fpl.uni-kl.de © 2001, [email protected] 4 http://www.fpl.uni-kl.de OS for PLDs Xilinx Alliances University of Kaiserslautern University of Kaiserslautern • separate EDA software market, comparable • The Software • The Xilinx XtremeDSP to the compiler / OS market in computers, AllianceEDA Program Initiative (with Mentor • Cadence, Mentor, Synopsys just jumped in. • ... Xilinx Inc.'s Graphics) • < 5% Xilinx / Altera income from EDA SW Foundation... • MathWorks / Xilinx •# • free WebPACK Alliance. downloadable tool • The Wind River / Xilinx palette alliance © 2001, [email protected] 5 http://www.fpl.uni-kl.de © 2001, [email protected] 6 http://www.fpl.uni-kl.de Enabling Technologies for System-on-Chip Development, Reconfigurable Computing Architectures November 19-20, 2001, Tampere, Finland and Methodologies for System-on-Chip; http://www.cs.tut.fi/soc/ Reiner Hartenstein, Monday, November 19, 10:15 - 11:00 hrs. Reiner Hartenstein, University of Kaiserslautern, Germany [email protected] http://hartenstein.de The Software Alliance EDA Program The Xilinx AllianceCORE program Xputer Lab University of Kaiserslautern University of Kaiserslautern a cooperation between Xilinx and third-party provides a wide Acugen Software, IKOS Systems, core developers, to produce a broad selection selection of EDA tools Agilent Innoveda, of industry-standard solutions for use in Xilinx platforms. - Partners are: EEsof EDA, Mentor Amphion Semiconductor, Ltd. Aldec, Graphics, ARC Cores MemecCore Mentor Graphics helps leading EDA Aptix, MiroTech, CAST, Inc. vendors to integrate DELTATEC Inventra Auspy Development, Model Technoloy, NewLogic Technologies, Inc. (Europe) Xilinx Alliance software Derivation Systems, Inc. Cadence, Protel International, Dolphin Integration (Grenoble) NMI Electronics tightly into their tools Celoxica, Simucad, Eureka Technology Inc. Paxonet Communications, Inc. Perigee, LLC SynaptiCAD, Frontier Design Inc. Dolphin Integration, GV & Associates, Inc. Rapid Prototypes Inc. Elanix, Synopsys, inSilicon Corporation sci-worx GmbH (Hannover, Germany) Exemplar, Synplicity, iCODING Technology Inc. SysOnChip Loarant Corporation TILAB (Telecom Italia Lab) Flynn Systems, Translogic, Mindspeed Technologies VAutomation Hyperlynx, Virtual Computer Corporation. - A Conexant Business Virtual IP Group, Inc. (formerly Applied Telecom) | XYLON. © 2001, [email protected] 7 http://www.fpl.uni-kl.de © 2001, [email protected] 8 http://www.fpl.uni-kl.de The Xilinx Reference Design Alliance Program The Xilinx University Program University of Kaiserslautern University of Kaiserslautern The Xilinx Reference Design Alliance Program helps The Xilinx University Program provides the development of multi-component reference designs that incorporate Xilinx devices and other • Xilinx Student Edition Software, semiconductors. • Professor Workshops, The designs are fully functional, but no warranties, • a Xilinx University User Group, no liability. Partners are:. • Presentation Materials and Lab Files, JK microsystems, Inc. • Course Examples, ADI Engineering LYR Technologies • Research, Innovative Integration NetLogic Microsystems • Books, etc. © 2001, [email protected] 9 http://www.fpl.uni-kl.de © 2001, [email protected] 10 http://www.fpl.uni-kl.de Altera offers over a Altera offers over a University of Kaiserslautern hundred IP cores (1) University of Kaiserslautern hundred IP cores (2) Altera offers over a hundred IP cores like, for example: from Altera | Modelware • modulator, AMIRIX Systems, Inc. Ncomm, Inc. • controller, • synchronizer, Amphion Semiconductor, Ltd. NewLogic Technologies • UART, • DDR SDRAM controller, Arasan Chip Systems, Inc. Northwest Logic • microprocessor, • Hadamar transform, CAST, Inc. Nova Engineering, Inc. • decoder, • interrupt controller, Digital Core Design Palmchip Corporation • bus control, • Real86 16 bit microprocessor, Eureka Technology Inc. Paxonet Communications • USB controller, • floating point, HammerCores PLD Applications • PCI bus interface, • FIR filter, Innocor Sciworx • viterbi controller, • discrete cosine, Ktech Telecommunications, Inc. Simple Silicon • fast Ethernet • ATM cell processor, Lexra Computing Engines Tensilica • MAC receiver or transmitter, • and many others. Mentor Graphics - Inventra TurboConcept. © 2001, [email protected] 11 http://www.fpl.uni-kl.de © 2001, [email protected] 12 http://www.fpl.uni-kl.de Enabling Technologies for System-on-Chip Development, Reconfigurable Computing Architectures November 19-20, 2001, Tampere, Finland and Methodologies for System-on-Chip; http://www.cs.tut.fi/soc/ Reiner Hartenstein, Monday, November 19, 10:15 - 11:00 hrs. Reiner Hartenstein, University of Kaiserslautern, Germany [email protected] http://hartenstein.de Altera IP core design services Altera Certified Design Center Xputer Lab University of Kaiserslautern University of Kaiserslautern (CDC) Program Certified Design Center (CDC) Program: Altera IP core design • Barco Silex services are available • El Camino GmbH from: • Excel Consultants • Plextek • Reflex Consulting • Northwest Logic • Sci-worx • Tality • Zaiq Technologies. © 2001, [email protected] 13 http://www.fpl.uni-kl.de © 2001, [email protected] 14 http://www.fpl.uni-kl.de The Altera Consultants Devlopment boards University of Kaiserslautern Alliance Program (ACAP): University of Kaiserslautern Devlopment boards are offered from: • Altera The Altera Consultants Alliance • El Camino GmbH Program (ACAP): lists • Gid'el Limited • Nova Engineering, Inc. •41 offices in North America and • PLD Applications •29 in the rest of the world. • Princeton Technology Group • RPA Electronics Design, LLC • Tensilica. © 2001, [email protected] 15 http://www.fpl.uni-kl.de © 2001, [email protected] 16 http://www.fpl.uni-kl.de Consultants and services not listed Consultants and services not University of Kaiserslautern by Xilinx nor Altera (index) University of Kaiserslautern listed by Xilinx nor Altera (1) Flexibilis, Tampere, Finland, Algotronix, Edinburgh, Reconfigurable Computing and FPL in Algotronix, Edinburgh, Geoff Bostock Designs, Wiltshire, England, software radio, communications and computer security Great River Technology, Alberquerque, NM, Andraka Consulting Group Andraka Consulting Group high performance FPGA designs for Arkham Technology, Pasadena, CA New Horizons GB Ltd, United Kingdom, DSP applications North West Logic Barco Silex, Louvain-la-Neuve, Belgium, Silicon System Solutions, Canterbury, Australia, Arkham Technology, Pasadena, low cost IP cores for Xilinx and Bottom Line Technologies, Milford, NJ Smartech, Tampere, Finland, Atmel, embedded processor, DSP, wireless communication, Codelogic, Helderberg, South Africa, COM / CORBA / DirectX, client-server database programming, Tekmosv, Austin, Texas, software internationalization, PCB design Coelacanth Engineering, Norwell, MASS The Rockland Group, Garden Valley, CA Comit Systems, Inc., Santa Clara, CA Nick Tredennick, Los Gatos, California, Barco Silex, Louvain-la-Neuve, Belgium, IP integration boards EDTN Programmable Logic Design Center Vitesse, for ASIC and FPGA, consultancy, design, sub-contracting © 2001, [email protected] 17 http://www.fpl.uni-kl.de © 2001, [email protected] 18 http://www.fpl.uni-kl.de Enabling Technologies for System-on-Chip Development, Reconfigurable Computing Architectures November 19-20, 2001, Tampere, Finland and Methodologies for System-on-Chip; http://www.cs.tut.fi/soc/ Reiner Hartenstein, Monday, November 19, 10:15 - 11:00 hrs. Reiner Hartenstein, University of Kaiserslautern, Germany [email protected] http://hartenstein.de Consultants and services not Consultants and services not Xputer Lab University of Kaiserslautern listed by Xilinx nor Altera (2) University of Kaiserslautern listed by Xilinx nor Altera (3) Bottom Line Technologies, Milford, New Jersey, FPGA design, FirstPass, Castle Rock, Colorado training, designing Xilinx parts since 1985 Vitesse, ASIC design Codelogic, Helderberg, South Africa, consulting, FPGA design Flexibilis, Tampere, Finland, VHDL IP cores for Xilinx products services

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