IBM Z13s Frequently Asked Questions
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IBM Z Systems Introduction May 2017
IBM z Systems Introduction May 2017 IBM z13s and IBM z13 Frequently Asked Questions Worldwide ZSQ03076-USEN-15 Table of Contents z13s Hardware .......................................................................................................................................................................... 3 z13 Hardware ........................................................................................................................................................................... 11 Performance ............................................................................................................................................................................ 19 z13 Warranty ............................................................................................................................................................................ 23 Hardware Management Console (HMC) ..................................................................................................................... 24 Power requirements (including High Voltage DC Power option) ..................................................................... 28 Overhead Cabling and Power ..........................................................................................................................................30 z13 Water cooling option .................................................................................................................................................... 31 Secure Service Container ................................................................................................................................................. -
IBM Elastic Storage System 3000: Service Guide Chapter 1
IBM Elastic Storage System 3000 6.0.2 Service Guide IBM SC28-3187-03 Note Before using this information and the product it supports, read the information in “Notices” on page 63. This edition applies to Version 6 release 0 modification 2 of the following product and to all subsequent releases and modifications until otherwise indicated in new editions: • IBM Spectrum® Scale Data Management Edition for IBM® ESS (product number 5765-DME) • IBM Spectrum Scale Data Access Edition for IBM ESS (product number 5765-DAE) IBM welcomes your comments; see the topic “How to submit your comments” on page xiii. When you send information to IBM, you grant IBM a nonexclusive right to use or distribute the information in any way it believes appropriate without incurring any obligation to you. © Copyright International Business Machines Corporation 2019, 2021. US Government Users Restricted Rights – Use, duplication or disclosure restricted by GSA ADP Schedule Contract with IBM Corp. Contents Figures.................................................................................................................. v Tables................................................................................................................. vii About this information.......................................................................................... ix Who should read this information...............................................................................................................ix IBM Elastic Storage System information units.......................................................................................... -
Vitex-II Pro: the Platfom for Programmable Systems
The Platform for Programmable Systems Developing high-performance systems with embedded pro- cessors and fast I/O is quite a challenge. To be successful, you Industry’s Fastest must solve the difficult technical FPGA Fabric problems of hardware and Up to 4 IBM PowerPC™ Processors immersed in FPGA Fabric software development, I/O Up to 24 Embedded Rocket I/O™ Multi-Gigabit Transceivers interfacing, and third-party IP Up to 12 Digital Clock Managers integration; you must rigorously XCITE Digitally Controlled Impedance Technology simulate, test, and verify your Up to 556 18x18 Multipliers design; and you must meet Over 10 Mb Embedded Block RAM increasingly difficult deadlines with a cost-effective product that can adapt as industry standards Virtex-II Pro Platform FPGA Family quickly evolve. Benefits are Overwhelming The revolutionary Virtex-II Pro™ Because all of the critical system components (such as microprocessors, memory, IP peripherals, programmable logic, and high-performance I/O) are located on one family, based on the highly successful programmable logic device, you gain a significant performance and productivity Virtex-II architecture, provides a advantage. The Virtex-II Pro FPGA family, along with the Wind River Systems embedded tools and Xilinx ISE development environment, is the fastest, easiest, and unique platform for developing most cost effective method for developing your next generation high-performance high-performance microprocessor- programmable systems. and I/O-intensive applications. With Virtex-II Pro FPGAs, you get: Virtex-II Pro FPGAs provide up to • On-Chip IBM PowerPC Processors – You get maximum performance and ease of use because these are hard cores, operating at peak efficiency, tightly coupled with ™ four embedded 32-bit IBM PowerPC all memory and programmable logic resources. -
Design and Implementation of Clocked Open Core Protocol Interfaces for Intellectual Property Cores and On-Chip Network Fabric
DESIGN AND IMPLEMENTATION OF CLOCKED OPEN CORE PROTOCOL INTERFACES FOR INTELLECTUAL PROPERTY CORES AND ON-CHIP NETWORK FABRIC by Raghu Prasad Gudla A thesis submitted to the faculty of The University of Utah in partial fulfillment of the requirements for the degree of Master of Science Department of Electrical and Computer Engineering The University of Utah May 2011 Copyright c Raghu Prasad Gudla 2011 All Rights Reserved The University of Utah Graduate School STATEMENT OF THESIS APPROVAL This thesis of Raghu Prasad Gudla has been approved by the following supervisory committee members: Kenneth S. Stevens , Chair 01/14/2011 Date Approved Alan L. Davis , Member 01/14/2011 Date Approved Erik L. Brunvand , Member 01/14/2011 Date Approved and by Gianluca Lazzi , Chair of the Department of Electrical and Computer Engineering and by Charles A. Wight, Dean of the Graduate School. ABSTRACT This thesis designs, implements, and evaluates modular Open Core Protocol (OCP) interfaces for Intellectual Property (IP) cores and Network-on-Chip (NoC) that re- duces System-On-Chip (SoC) design time and enables research on different archi- tectural sequencing control methods. To utilize the NoCs design time optimization feature at the boundaries, a standardized industry socket was required, which can address the SoC shorter time-to-market requirements, design issues, and also the subsequent reuse of developed IP cores. OCP is an open industry standard socket interface specification used in this research to enable the IP cores reusability across multiple SoC designs. This research work designs and implements clocked OCP interfaces between IP cores and On-Chip Network Fabric (NoC), in single- and multi- frequency clocked domains. -
New Virtex™-II Pro Family Extends Platform FPGA Capability with Multi
Virtex-II Pro Platform FPGA Family Product Backgrounder The Virtex-II Pro Platform FPGA solution is arguably the most technically sophisticated silicon and software product in the programmable logic industry. The goal in developing the Virtex-II Pro FPGA was to revolutionize system architecture “from the ground up.” To achieve that objective, circuit engineers and system architects from IBM, Mindspeed, and Xilinx co- developed this advanced Platform FPGA. Engineering teams from top embedded systems companies, including Wind River Systems and Celoxica, worked together with Xilinx software teams to develop the systems software and IP solutions that enable new system architecture. The result is the first Platform FPGA solution capable of implementing ultra-high bandwidth SoC (system-on-a-chip) designs that were previously the exclusive domain of custom ASICs, yet with the flexibility and low development cost of programmable logic. This new solution is expected to usher a new era of leading-edge system architectures in networking applications, embedded systems, and digital signal processing systems. Virtex-II Pro Family Features • Five family members with 3,168 to 50,832 logic cells and 216 to 3,888 Kbits of Block RAM • Based upon Virtex-II IP-Immersion architecture • Multi-gigabit (3.125 Gb/s) serial transceiver blocks, up to 16 per device • PowerPC embedded processor cores, up to four per device Virtex-II Pro Family Key Value Proposition • Platform for Programmable Systems • Enables architectural synthesis • Delivers next generation connectivity standards • Enables a new development paradigm • Delivers leading edge price/performance value Virtex-II Pro Family Highlights The Virtex-II Pro family consists of five members, each with four to 16 RocketIO™ multi- gigabit transceivers based on the Mindspeed SkyRail™ technology. -
IBM Z13 Server Technology
Introducing the IBM® z13™ Server Platform Structure and Performance Monte Bauman Enterprise Server Technical Support IBM Columbus [email protected] January 2015 IBM z Systems Agenda § Design Imperatives § The IBM z Systems z13 Server § The z13 Big Data Server 2 © 2015 IBM Corporation IBM z Systems Design Imperatives IBM z Systems Business Imperatives The Mobile Moment The Odds are High … Business Management is interested in... Enterprise § Promoting High Retention Rates and Capturing Class Competitive share through mobile interactions Cloud § Driving integrated/smart transactions that improve the Client Experience (e.g. Next Best Action) Business- Critical § Growing and Improving the IT services consumer Analytics experience within Existing Environmental Envelope Smart Transactions 4 © 2015 IBM Corporation IBM z Systems IBM z13 Design Primitives The IBM z13 Server was developed with the intent to: § Capture transaction growth through mobile enablement of existing systems § Drive integrated analytics at the time of the transaction § Deliver higher levels of Capacity and Performance within the Existing Environmental Envelope Enclave-Encapsulated Systems of Engagement Systems of Record Systems of Insight 5 © 2015 IBM Corporation IBM z Systems The IBM z13 Server 6 © 2015 IBM Corporation IBMIBM z Systems z13 platform positioning Platform Core Capabilities: Transaction Processing • The world’s premier transaction and data engine now enabled for Data Serving the mobile generation Mixed Workloads Operational Efficiency • The integrated transaction -
XC2VP30-6FFG896C Xilinx Inc. IC FPGA 556 I/O 896FCBGA
XC2VP30-6FFG896C Xilinx Inc. IC FPGA 556 I/O 896FCBGA https://www.fpgamall.com/ Product Not Recommended For New Designs XC2VP30-6FFG896C Xilinx Inc. IC FPGA 556 I/O 896FCBGA 1 R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Complete Data Sheet DS083 (v5.0) June 21, 2011 0 Product Specification Module 1: Module 3: Introduction and Overview DC and Switching Characteristics 10 pages 59 pages • Summary of Features • Electrical Characteristics • General Description • Performance Characteristics • Architecture • Switching Characteristics • IP Core and Reference Support • Pin-to-Pin Output Parameter Guidelines • Device/Package Combinations and Maximum I/O • Pin-to-Pin Input Parameter Guidelines • Ordering Information • DCM Timing Parameters • Source-Synchronous Switching Characteristics Module 2: Functional Description Module 4: 60 pages Pinout Information • Functional Description: RocketIO™ X Multi-Gigabit 302 pages Transceiver • Pin Definitions • Functional Description: RocketIO Multi-Gigabit •Pinout Tables Transceiver - FG256/FGG256 Wire-Bond Fine-Pitch BGA Package • Functional Description: Processor Block - FG456/FGG456 Wire-Bond Fine-Pitch BGA Package • Functional Description: PowerPC™ 405 Core - FG676/FGG676 Wire-Bond Fine-Pitch BGA Package • Functional Description: FPGA - FF672 Flip-Chip Fine-Pitch BGA Package - FF896 Flip-Chip Fine-Pitch BGA Package - Input/Output Blocks (IOBs) - FF1148 Flip-Chip Fine-Pitch BGA Package - Digitally Controlled Impedance (DCI) - FF1152 Flip-Chip Fine-Pitch BGA Package - On-Chip Differential Termination - FF1517 Flip-Chip Fine-Pitch BGA Package - Configurable Logic Blocks (CLBs) - FF1696 Flip-Chip Fine-Pitch BGA Package - 3-State Buffers - FF1704 Flip-Chip Fine-Pitch BGA Package - CLB/Slice Configurations - 18-Kb Block SelectRAM™ Resources - 18-Bit x 18-Bit Multipliers - Global Clock Multiplexer Buffers - Digital Clock Manager (DCM) •Routing • Configuration IMPORTANT NOTE: Page, figure, and table numbers begin at 1 for each module, and each module has its own Revision History at the end. -
Linux on IBM Z13:Performance Aspects of New Technology And
Linux on IBM z13: Performance Aspects of New Technology and Features Mario Held ([email protected]) Linux on z Systems Performance Analyst IBM Corporation Session 17772 August 13, 2015 Trademarks The following are trademarks of the International Business Machines Corporation in the United States and/or other countries. BlueMix ECKD IBM* Maximo* Smarter Cities* WebSphere* z Systems BigInsights FICON* Ibm.com MQSeries* Smarter Analytics XIV* z/VSE* Cognos* FileNet* IBM (logo)* Performance Toolkit for VM SPSS* z13 z/VM* DB2* FlashSystem IMS POWER* Storwize* zEnterprise* DB2 Connect GDPS* Informix* Quickr* System Storage* z/OS* Domino* GPFS InfoSphere Rational* Tivoli* DS8000* Sametime* * Registered trademarks of IBM Corporation The following are trademarks or registered trademarks of other companies. Adobe, the Adobe logo, PostScript, and the PostScript logo are either registered trademarks or trademarks of Adobe Systems Incorporated in the United States, and/or other countries. IT Infrastructure Library is a registered trademark of the Central Computer and Telecommunications Agency which is now part of the Office of Government Commerce. Intel, Intel logo, Intel Inside, Intel Inside logo, Intel Centrino, Intel Centrino logo, Celeron, Intel Xeon, Intel SpeedStep, Itanium, and Pentium are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. Linux is a registered trademark of Linus Torvalds in the United States, other countries, or both. Microsoft, Windows, Windows NT, and the Windows logo are trademarks of Microsoft Corporation in the United States, other countries, or both. Windows Server and the Windows logo are trademarks of the Microsoft group of countries. ITIL is a registered trademark, and a registered community trademark of the Office of Government Commerce, and is registered in the U.S. -
SIMD Processing on IBM Z14, Z13 and Z13s
with current compilers. String and character array processing, traditional loop and array SIMD Processing on IBM z14, z13 and z13s Background Companies want to quickly and efficiently processing with integer and floating point data process huge amounts of information for can all be accelerated using SIMD. Complex analytics, mobile applications, data serving and mathematical processing, algorithmic-intensive more. To cost-effectively achieve these programs, image processing applications, and efficiencies new innovative technologies are other applications can be efficiently processed needed. Vector processing and SIMD optimize with SIMD. SIMD also enables processing of a performance by processing data in parallel on new class of applications on IBM Z using ® IBM Z . analytics, mathematical optimization without requiring an offload to specialized processors. What is SIMD? Standard SIMD math and linear algebra libraries SIMD stands for Single Instruction Multiple Data. enable easier porting from X86 platforms. Unlike instructions which performs a single operation on a single data point, SIMD instructions Compilers can perform the same operation on multiple data SIMD helps you achieve efficiencies using IBM points at once. z/OS® XL C/C++ V2.1.1, IBM Enterprise COBOL 5.2 and IBM Enterprise PL/I for z/OS V4.5, for SIMD is an innovation that was delivered with applications with character or integer IBM z13® (z13) and IBM z13s™ (z13s). With SIMD manipulation. IBM z/OS XL C/C++ V2.1.1 entire arrays of data can be processed by a compilers offer new capabilities, such as single instruction enabling more efficient architecture sections, inline assembly, and high processing of data. -
IBM Storage and the NVM Express Revolution
Front cover IBM Storage and the NVM Express Revolution Ioannis Koltsidas IBM Research Staff, Technical Leader for Flash and SDS Vincent Hsu IBM Systems, IBM Fellow and CTO for Storage and SDE In partnership with IBM Academy of Technology Point-of-View The need for a standardized and efficient protocol for storage access Efficient access to solid state storage is becoming increasingly Highlights important as data volumes increase and as data-hungry workloads become more critical to the success of businesses The industry recognizes the need for and organizations. With the introduction of IBM® FlashSystem standardized and efficient protocols and all-flash arrays, IBM pioneered efficient, high-performance interfaces that are optimized for access to flash-based storage. This method uses a system low-latency, performance-dense storage architecture that minimizes software interactions in the data path media (such as flash) and non-volatile and that builds on efficient interfaces to access memory technologies. This paper purpose-engineered dense flash modules with consistently low provides the following highlights: latency and high throughput. Purpose-built hardware helps to The NVM Express (NVMe) satisfy the most demanding enterprise workload requirements technology enables storage and to translate raw storage performance into application-level accesses with low latency, high benefits that can unlock new use cases and business value. efficiency, and high scalability. With the increasing maturity and wider adoption of flash-based The NVMe technology can make storage in data centers, the broader industry has recognized the server-based SDS higher performing need for standardized, efficient protocols and interfaces that are and more efficient. -
Themis PPC64 / TPPC64 Datasheet (Pdf)
Full-service, independent repair center -~ ARTISAN® with experienced engineers and technicians on staff. TECHNOLOGY GROUP ~I We buy your excess, underutilized, and idle equipment along with credit for buybacks and trade-ins. Custom engineering Your definitive source so your equipment works exactly as you specify. for quality pre-owned • Critical and expedited services • Leasing / Rentals/ Demos equipment. • In stock/ Ready-to-ship • !TAR-certified secure asset solutions Expert team I Trust guarantee I 100% satisfaction Artisan Technology Group (217) 352-9330 | [email protected] | artisantg.com All trademarks, brand names, and brands appearing herein are the property o f their respective owners. Find the Mercury Computer Systems / Themis PPC64 / TPPC64 at our website: Click HERE Themis TPPC64 High-Performance Multiprocessing VME Computer New IBM PowerPC 970FX - based Dual- New PowerPC®-based DuPralo-Prcessocessor VoMr VEMbuEsbu Cos mCoputmputersers The Themis TPPC64™ is a single board VMEbus computer, based on the IBM® PowerPC ® 970FX processor. It is available in both a single slot uniprocessor configuration, as well as a two slot, dual Symmetric Multiprocessing (SMP) configuration. I/O extension and graphics boards can be added to either single or dual processor configurations and occupy additional VMEbus slots. The TPPC64 supports up to 4 GB of DDR400 SDRAM. The Themis TPPC64 includes two Gb Ethernet ports and a Single Ultra320 SCSI channel. PMC I/O can be expanded to four slots with two different PMC carrier boards. Themis TPPC64 -
IBM Z Systems Hardware - 2016 Technical Overview
IBM z Systems Hardware - 2016 Technical Overview Session B01 / C15 Walter Kläy, IMS SWAT Team [email protected] with support from Kevin Hite (SVL) and Silvia Mueller (BOB) © 2016 IBM Corporation Innovation never stops. …2016… Internet of things GA2 Cloud SMT MobileIMS Rockhopper z13s Mainframe Mainframe IBM SIMD Internet of things IBM IBMEmperor LinuxOne Cloud CloudInternet of things z13 Mobile Mobile 2 Digital Revolution Transform interactions World becoming smarter Personalized everything In the moment right now What is happening? 16 billion connected devices Infrastructure of the company 75 billion devices by 2020 Infrastructure of the city 7 billion smart phones Infrastructure of the world Respect and protect security and privacy 3 The market is moving, forcing businesses to transform Explosion in Analytics is Hybrid cloud is the transaction growth moving to real time new standard driven by mobility to capture new for delivering service, and the Internet of opportunities at the agility, trust and Things point of impact efficiency 4 z13 Overview © 2016 IBM Corporation IBM z Systems Evolution New Brand: LinuxOne 6 z13(s) Functions and Features (DGA Driver Level 22) System, Processor, Memory I/O Subsystem, Parallel Sysplex, STP, Security Five hardware models New PCIe Gen3 I/O fanouts with 16 GBps Buses Eight core 22nm PU SCM LCSS increased from 4 to 6 Up to 141 processors configurable as CPs, zIIPs, IFLs, ICFs, or optional SAPs 4th Subchannel Set per LCSS Increased Uni processor capacity z13 Maximum number of I/O Devices (subchannels)