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R Virtex-II Pro™ X Platform FPGAs: Introduction and Overview

DS110-1 (v1.1) March 5, 2004 00Advance Product Specification Summary of Virtex-II Pro X Features • High-Performance Platform FPGA Solution Including - Active Interconnect™ technology - Up to twenty RocketIO™ X embedded multi-gigabit - SelectRAM™ memory hierarchy transceiver blocks - Dedicated 18-bit x 18-bit multiplier blocks - Up to two IBM® PowerPC ® RISC processor blocks - High-performance clock Management circuitry • Based on Virtex-II Pro™ Platform FPGA Technology - SelectI/O™-Ultra technology - Flexible logic resources - Digitally Controlled Impedance (DCI) I/O - SRAM-based in-system configuration

The Virtex-II Pro X™ family members and resources are shown in Table 1. Table 1: Virtex-II Pro X FPGA Family Members CLB (1 = 4 slices = max 128 bits) Block SelectRAM RocketIO X PowerPC 18 X 18 Bit Maximum Transceiver Processor Logic Max Distr Multiplier 18 Kb Max Block User Device Blocks Blocks Cells(1) Slices RAM (Kb) Blocks Blocks RAM (Kb) DCMs I/O Pads XC2VPX20 8 1 22,032 9,792 306 88 88 1,584 8 552 XC2VPX70 20 2 74,448 33,088 1,034 308 308 5,544 8 992

Notes: 1. Logic Cell = (1) 4-input LUT + (1)FF + Carry Logic. 2. See Table 3 for package configurations.

RocketIO X Features • Variable speed full-duplex transceiver, allowing • Programmable pre-emphasis levels 0 to 500% 2.488 Gb/s to 10.3125 Gb/s baud transfer rates. • Telecom/Datacom support modes with "x8" and "x10" Includes specific baud rates used by various clocking/data paths, and 64B/66B clocking support standards, as listed in Table 1, Module 2. • Receiver equalization • Between eight and twenty transceiver modules on an • AC and DC coupling FPGA, depending upon device • On-chip termination of 50Ω (eliminating the need for • Monolithic clock synthesis and clock recovery system external termination resistors) eliminates the need for external components • Pre- and post-driver serial and parallel TX-to-RX • Automatic lock-to-reference function internal loopback modes for testing operability • Programmable serial output differential swing (200 mV • Programmable comma detection allows for any to 1600 mV, peak-peak) allows compatibility with other protocol and detection of any 10-bit character serial system voltage levels • 8B/10B and 64B/66B encoding blocks

PowerPC RISC Core Features • Embedded 300+ MHz Harvard architecture core • Memory Management Unit (MMU) • Low power consumption: 0.9 mW/MHz • 64-entry unified Translation Look-aside Buffers (TLB) • Five-stage data path pipeline • Variable page sizes (1 KB to 16 MB) • Hardware multiply/divide unit • Dedicated on-chip memory (OCM) interface • Thirty-two 32-bit general purpose registers • Supports IBM CoreConnect™ bus architecture • 16 KB two-way set-associative instruction cache • Debug and trace support • 16 KB two-way set-associative data cache • Timer facilities © 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS110-1 (v1.1) March 5, 2004 www.xilinx.com 1 Advance Product Specification 1-800-255-7778 R Virtex-II Pro™ X Platform FPGAs: Introduction and Overview

Virtex-II Pro X Platform FPGA Technology - PCI support(1) - Differential signaling • SelectRAM memory hierarchy · 840 Mb/s Low-Voltage Differential Signaling I/O - Up to 5.5 Mb of True Dual-Port RAM in 18 Kb block (LVDS) with current mode drivers SelectRAM resources · Bus LVDS I/O - Up to 1,034 Kb of distributed SelectRAM resources · HyperTransport (LDT) I/O with current driver - High-performance interfaces to external memory buffers • Arithmetic functions · Built-in DDR input and output registers - Dedicated 18-bit x 18-bit multiplier blocks - Proprietary high-performance SelectLink - Fast look-ahead carry logic chains technology for communications between Xilinx • Flexible logic resources devices - Up to 66,176 internal registers/latches with Clock · High-bandwidth data path Enable · Double Data Rate (DDR) link · Web-based HDL generation methodology - Up to 66,176 look-up tables (LUTs) or cascadable variable (1 to 16 bits) shift registers • SRAM-based in-system configuration - Fast SelectMAP™ configuration - Wide multiplexers and wide-input function support - Horizontal cascade chain and Sum-of-Products - Triple Data Encryption Standard (DES) security support option (bitstream encryption) - IEEE1532 support - Internal 3-state busing - Partial reconfiguration • High-performance clock management circuitry - Unlimited reprogrammability - Up to eight Digital Clock Manager (DCM) modules · Precise clock de-skew - Readback capability · Flexible frequency synthesis • Supported by Xilinx Foundation™ and Alliance™ · High-resolution phase shifting series development systems - Sixteen global clock multiplexer buffers in all parts - Integrated VHDL and Verilog design flows • Active Interconnect technology - ChipScope™ Integrated Logic Analyzer - Fourth-generation segmented routing structure • 0.13-µm, nine-layer copper process with 90 nm - Fast, predictable routing delay, independent of high-speed transistors fanout •1.5V (VCCINT) core power supply, dedicated 2.5V - Deep sub-micron noise immunity benefits VCCAUX auxiliary and VCCO I/O power supplies • SelectI/O-Ultra technology • IEEE 1149.1 compatible boundary-scan logic support - Up to 992 user I/Os • Flip-Chip Ball Grid Array (BGA) packages in standard - Twenty-two single-ended standards and 1.00 mm pitch six differential standards • Each device 100% factory tested - Programmable LVCMOS sink/source current (2 mA to 24 mA) per I/O - Digitally Controlled Impedance (DCI) I/O 1. Refer to XAPP653 for more information.

General Description Architecture The Virtex-II Pro X family is a platform FPGA for designs Virtex-II Pro X Array Overview that are based on IP cores and customized modules. The Virtex-II Pro X devices are user-programmable gate arrays family incorporates multi-gigabit transceivers and PowerPC with various configurable elements and embedded cores CPU cores in Virtex-II Pro X Series FPGA architecture. It optimized for high-density and high-performance system empowers complete solutions for telecommunication, wire- designs. Virtex-II Pro X devices implement the following less, networking, video, and DSP applications. functionality: The leading-edge 0.13 µm CMOS nine-layer copper pro- cess and the Virtex-II Pro X architecture are optimized for • Data baud rate up to 10.3125 Gb/s per channel high-performance designs in a wide range of densities. • Embedded IBM PowerPC 405 RISC CPU cores Combining a wide variety of flexible features and IP cores, provide performance of 300+ MHz the Virtex-II Pro X family enhances programmable logic • SelectI/O-Ultra blocks provide the interface between design capabilities and is a powerful alternative to package pins and the internal configurable logic. Most mask-programmed gate arrays. popular and leading-edge I/O standards are supported by the programmable IOBs.

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• Configurable Logic Blocks (CLBs) provide functional • Receiver clock recovery tolerance of up to elements for combinatorial and synchronous logic, 75 non-transitioning bits including basic storage elements. BUFTs (3-state •50Ω on-chip transmit and receive terminations buffers) associated with each CLB element drive • Programmable comma detection and word alignment dedicated segmentable horizontal routing resources. • Rate matching via insertion/deletion characters • Block SelectRAM memory modules provide large • Automatic lock-to-reference function 18 Kb storage elements of True Dual-Port RAM. • Programmable pre-emphasis support • Embedded multiplier blocks are 18-bit x 18-bit dedicated multipliers. • Per-channel serial and parallel transmitter-to-receiver internal loopback modes • Digital Clock Manager (DCM) blocks provide self-calibrating, fully digital solutions for clock PowerPC 405 Processor Block distribution delay compensation, clock multiplication The PPC405 RISC CPU can execute instructions at a sus- and division, and coarse- and fine-grained clock phase tained rate of one instruction per cycle. On-chip instruction shifting. and data cache reduce design complexity and improve sys- A new generation of programmable routing resources called tem throughput. Active Interconnect Technology interconnects all of these The PPC405 features include: elements. The general routing matrix (GRM) is an array of routing switches. Each programmable element is tied to a • PowerPC RISC CPU switch matrix, allowing multiple connections to the general - Implements the PowerPC User Instruction Set routing matrix. The overall programmable interconnection is Architecture (UISA) and extensions for embedded hierarchical and designed to support high-speed designs. applications All programmable elements, including the routing - Thirty-two 32-bit general purpose registers (GPRs) resources, are controlled by values stored in static memory - Static branch prediction cells. These values are loaded in the memory cells during - Five-stage pipeline with single-cycle execution of configuration and can be reloaded to change the functions most instructions, including loads/stores of the programmable elements. - Unaligned and aligned load/store support to cache, Virtex-II Pro X Features main memory, and on-chip memory This section briefly describes Virtex-II Pro X features. - Hardware multiply/divide for faster integer arithmetic (4-cycle multiply, 35-cycle divide) RocketIO X Multi-Gigabit Transceiver Cores - Enhanced string and multiple-word handling The RocketIO X Multi-Gigabit Transceiver core is a flexible - Big/little endian operation support parallel-to-serial and serial-to-parallel transceiver embed- • Storage Control ded core used for high-bandwidth interconnection between - Separate instruction and data cache units, both buses, backplanes, or other subsystems. two-way set-associative and non-blocking Multiple user instantiations in an FPGA are possible, provid- - Eight words (32 bytes) per cache line ing up to 412.5 Gb/s of full-duplex aggregate baud rate. - 16 KB array Instruction Cache Unit (ICU), 16 KB Each channel can be operated at a maximum baud rate of array Data Cache Unit (DCU) 10.3125 Gb/s. -Operand forwarding during instruction cache line fill Each RocketIO X core implements the following functionality: - Copy-back or write-through DCU strategy • Serializer and deserializer (SERDES) - Doubleword instruction fetch from cache improves • Monolithic clock synthesis and clock recovery (CDR) branch latency • 10 Gigabit Attachment Unit Interface (XAUI) and • Virtual mode memory management unit (MMU) 10GBase-R Ethernet, Fibre Channel (3.1875 Gb/s - Translation of the 4 gigabit logical address space XAUI), Infiniband, PCI Express, Aurora, SXI-5 into physical addresses (SFI-5,/SPI-5), OC-48, and OC-192 compatibility - Software control of page replacement strategy • 8-, 16-, 32-, or 64-bit selectable FPGA interface - Supports multiple simultaneous page sizes ranging • 8B/10B and 64b/66b encoder and decoder, with from 1 KB to 16 MB bypassing option on each channel • OCM controllers provide dedicated interfaces between • Channel bonding support (two to twenty channels) block Select RAM memory and processor core - Elastic buffers for inter-chip deskewing and instruction and data paths for high-speed access channel-to-channel alignment

DS110-1 (v1.1) March 5, 2004 www.xilinx.com 3 Advance Product Specification 1-800-255-7778 R Virtex-II Pro™ X Platform FPGAs: Introduction and Overview

• PowerPC timer facilities Configurable Logic Blocks (CLBs) - 64-bit time base CLB resources include four slices and two 3-state buffers. - Programmable interval timer (PIT) Each slice is equivalent and contains: - Fixed interval timer (FIT) • Two function generators (F & G) - Watchdog timer (WDT) • Two storage elements • Debug Support • Arithmetic logic gates - Internal debug mode • Large multiplexers - External debug mode - Debug Wait mode • Wide function capability - Real Time Trace debug mode • Fast carry look-ahead chain - Enhanced debug support with logical operators • Horizontal cascade chain (OR gate) - Instruction trace and trace-back support The function generators F & G are configurable as 4-input - Forward or backward trace look-up tables (LUTs), as 16-bit shift registers, or as 16-bit • Two hardware interrupt levels support distributed SelectRAM memory. • Advanced power management support In addition, the two storage elements are either edge-triggered D-type flip-flops or level-sensitive latches. Input/Output Blocks (IOBs) Each CLB has internal fast interconnect and connects to a IOBs are programmable and can be categorized as follows: switch matrix to access general routing resources. • Input block with an optional single data rate (SDR) or double data rate (DDR) register Block SelectRAM Memory • Output block with an optional SDR or DDR register and The block SelectRAM memory resources are 18 Kb of True an optional 3-state buffer to be driven directly or Dual-Port RAM, programmable from 16K x 1 bit to 512 x 36 through an SDR or DDR register bit, in various depth and width configurations. Each port is • Bidirectional block (any combination of input and output totally synchronous and independent, offering three configurations) “read-during-write” modes. Block SelectRAM memory is cascadable to implement large embedded storage blocks. These registers are either edge-triggered D-type flip-flops Supported memory configurations for dual-port and sin- or level-sensitive latches. gle-port modes are shown in Table 2. IOBs support the following single-ended I/O standards: • LVTTL, LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V) Table 2: Dual-Port and Single-Port Configurations • PCI-X compatible (133 MHz and 66 MHz) at 3.3V(1) 16K x 1 bit 4K x 4 bits 1K x 18 bits • PCI compliant (66 MHz and 33 MHz) at 3.3V(1) 8K x 2 bits 2K x 9 bits 512 x 36 bits • GTL and GTLP • HSTL (1.5V and 1.8V, Class I, II, III, and IV) 18 X 18 Bit Multipliers • SSTL (1.8V and 2.5V, Class I and II) A multiplier block is associated with each SelectRAM mem- The DCI I/O feature automatically provides on-chip termina- ory block. The multiplier block is a dedicated 18 x 18-bit 2s tion for each single-ended I/O standard. complement signed multiplier and is optimized for opera- The IOB elements also support the following differential sig- tions based on the block SelectRAM content on one port. naling I/O standards: The 18 x 18 multiplier can be used independently of the block SelectRAM resource. Read/multiply/accumulate oper- • LVDS and Extended LVDS (2.5V only) ations and DSP filter structures are extremely efficient. • BLVDS (Bus LVDS) Both the SelectRAM memory and the multiplier resource •ULVDS are connected to four switch matrices to access the general •LDT routing resources. • LVPECL (2.5V) Global Clocking Two adjacent pads are used for each differential pair. Two or four IOB blocks connect to one switch matrix to access the The DCM and global clock multiplexer buffers provide a routing resources. complete solution for designing high-speed clock schemes. Up to eight DCM blocks are available. To generate deskewed internal or external clocks, each DCM can be used to eliminate clock distribution delay. The DCM also 1. Refer to XAPP653 for more information.

DS110-1 (v1.1) March 5, 2004 www.xilinx.com 4 Advance Product Specification 1-800-255-7778 R Virtex-II Pro™ X Platform FPGAs: Introduction and Overview provides 90-, 180-, and 270-degree phase-shifted versions • Slave-serial mode of its output clocks. Fine-grained phase shifting offers • Master-serial mode 1 high-resolution phase adjustments in increments of /256 of • Slave SelectMAP mode the clock period. Very flexible frequency synthesis provides • Master SelectMAP mode a clock output frequency equal to a fractional or integer mul- • Boundary-Scan mode (IEEE 1532) tiple of the input clock frequency. For exact timing parame- A Data Encryption Standard (DES) decryptor is available ters, see Virtex-II Pro X™ Platform FPGAs: DC and on-chip to secure the bitstreams. One or two triple-DES key Switching Characteristics (Module 3). sets can be used to optionally encrypt the configuration data. Virtex-II Pro X devices have 16 global clock MUX buffers, with up to eight clock nets per quadrant. Each clock MUX The Xilinx System Advanced Configuration Environment buffer can select one of the two clock inputs and switch (System ACE™) family offers high-capacity and flexible glitch-free from one clock to the other. Each DCM can send solution for FPGA configuration as well as program/data up to four of its clock outputs to global clock buffers on the storage for the processor. See DS080, System ACE Com- same edge. Any global clock pin can drive any DCM on the pactFlash Solution for more information. same edge. Readback and Integrated Logic Analyzer Routing Resources Configuration data stored in Virtex-II Pro X configuration The IOB, CLB, block SelectRAM, multiplier, and DCM ele- memory can be read back for verification. Along with the ments all use the same interconnect scheme and the same configuration data, the contents of all flip-flops/latches, dis- access to the global routing matrix. Timing models are tributed SelectRAM, and block SelectRAM memory shared, greatly improving the predictability of the perfor- resources can be read back. This capability is useful for mance of high-speed designs. real-time debugging. The Xilinx ChipScope™ Integrated Logic Analyzer (ILA) There are a total of 16 global clock lines, with eight available cores and Integrated Bus Analyzer (IBA) cores, along with per quadrant. In addition, 24 vertical and horizontal long the ChipScope Pro Analyzer software, provide a complete lines per row or column, as well as massive secondary and solution for accessing and verifying user designs within local routing resources, provide fast interconnect. Virtex-II Pro X devices. Virtex-II Pro X buffered interconnects are relatively unaf- fected by net fanout, and the interconnect layout is designed IP Core and Reference Support to minimize crosstalk. Intellectual Property is part of the Platform FPGA solution. Horizontal and vertical routing resources for each row or In addition to the existing FPGA fabric cores, the list below column include: shows some of the currently available hardware and soft- • 24 long lines ware intellectual properties specially developed for • 120 hex lines Virtex-II Pro X by Xilinx. Each IP core is modular, portable, • 40 double lines Real-Time Operating System (RTOS) independent, and • 16 direct connect lines (total in all four directions) CoreConnect compatible for ease of design migration. Refer to www.xilinx.com for the latest and most complete Boundary Scan list of cores. Boundary-scan instructions and associated data registers support a standard methodology for accessing and config- Hardware Cores uring Virtex-II Pro X devices, complying with IEEE stan- • Bus Infrastructure cores (arbiters, bridges, and more) dards 1149.1 and 1532. A system mode and a test mode • Memory cores (DDR, Flash, and more) are implemented. In system mode, a Virtex-II Pro X device • Peripheral cores (UART, IIC, and more) will continue to function while executing non-test bound- • Networking cores (ATM, Ethernet, and more) ary-scan instructions. In test mode, boundary-scan test instructions control the I/O pins for testing purposes. The Software Cores Virtex-II Pro X Test Access Port (TAP) supports BYPASS, • Boot code PRELOAD, SAMPLE, IDCODE, and USERCODE non-test • Test code instructions. The EXTEST, INTEST, and HIGHZ test instruc- • Device drivers tions are also supported. • Protocol stacks Configuration • RTOS integration • Customized board support package Virtex-II Pro X devices are configured by loading the bit- stream into internal configuration memory using one of the following modes:

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Virtex-II Pro X Device/Package Combinations and Maximum I/Os Offerings include ball grid array (BGA) packages with PWRDWN_B, TCK, TDI, TDO, TMS, HSWAP_EN, DXN, 1.0 mm pitch. Flip-chip interconnect is used in the BGA DXP, and RSVD), VBATT, and RocketIO X transceiver pins. offerings. The use of flip-chip interconnect offers more I/Os than are possible in wire-bond versions of the similar pack- Table 3: Virtex-II Pro X Device/Package Combinations ages. Flip-chip construction offers the combination of high and Maximum Number of Available I/Os pin count and excellent power dissipation. Available The Virtex-II Pro X device/package combination table I/Os / Transceivers (Table 3) details the maximum number of I/Os for each Pitch Size device and package using flip-chip technology. Package (mm) (mm) XC2VPX20 XC2VPX70 • FF denotes flip-chip fine-pitch BGA (1.00 mm pitch). FF896 1.00 31 x 31 552 / 8 The I/O per package count includes all user I/Os except the FF1704 1.00 42.5 x 42.5 992 / 20 15 control pins (CCLK, DONE, M0, M1, M2, PROG_B, Maximum Performance Maximum RocketIO X transceiver and PowerPC processor block performance varies depending on the package style and speed grade. See Table 4 for details. Virtex-II Pro X™ Platform FPGAs: DC and Switching Characteristics (Module 3) contains the rest of the FPGA fabric performance parameters.

Table 4: Maximum RocketIO X Transceiver and PowerPC Processor Block Performance Speed Grade Package -7 -6 -5 Units RocketIO X Transceiver 10.3125 6.4 4.3 Gb/s PowerPC Processor Block 400 350 300 MHz

Virtex-II Pro X Ordering Information Virtex-II Pro X ordering information is shown in Figure 1.

Example: XC2VPX20 -7 FF 896 C

Device Type Temperature Range: Speed Grade C = Commercial (Tj = 0ûC to +85ûC) (-6, -7) I = Industrial (Tj = 40ûC to +100ûC) Number of Pins Package Type (Flip-Chip Only = FF)

DS110_01_110603 Figure 1: Virtex-II Pro X Ordering Information

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Revision History This section records the change history for this module of the data sheet.

Date Version Revision 11/17/03 1.0 Initial Xilinx release. 03/05/04 1.1 Changed number of User I/Os in Table 1, Table 3, and Virtex-II Pro X Platform FPGA Technology, page 2

Virtex-II Pro X Data Sheet The Virtex-II Pro X Data Sheet contains the following modules: • Virtex-II Pro™ X Platform FPGAs: Introduction and • Virtex-II Pro™ X Platform FPGAs: DC and Switching Overview (Module 1) Characteristics (Module 3) • Virtex-II Pro™ X Platform FPGAs: Functional • Virtex-II Pro™ X Platform FPGAs: Pinout Information Description (Module 2) (Module 4)

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