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Datasheet Search Engine 0 R Virtex-II Pro™ X Platform FPGAs: Introduction and Overview DS110-1 (v1.1) March 5, 2004 00Advance Product Specification Summary of Virtex-II Pro X Features • High-Performance Platform FPGA Solution Including - Active Interconnect™ technology - Up to twenty RocketIO™ X embedded multi-gigabit - SelectRAM™ memory hierarchy transceiver blocks - Dedicated 18-bit x 18-bit multiplier blocks - Up to two IBM® PowerPC ® RISC processor blocks - High-performance clock Management circuitry • Based on Virtex-II Pro™ Platform FPGA Technology - SelectI/O™-Ultra technology - Flexible logic resources - Digitally Controlled Impedance (DCI) I/O - SRAM-based in-system configuration The Virtex-II Pro X™ family members and resources are shown in Table 1. Table 1: Virtex-II Pro X FPGA Family Members CLB (1 = 4 slices = max 128 bits) Block SelectRAM RocketIO X PowerPC 18 X 18 Bit Maximum Transceiver Processor Logic Max Distr Multiplier 18 Kb Max Block User Device Blocks Blocks Cells(1) Slices RAM (Kb) Blocks Blocks RAM (Kb) DCMs I/O Pads XC2VPX20 8 1 22,032 9,792 306 88 88 1,584 8 552 XC2VPX70 20 2 74,448 33,088 1,034 308 308 5,544 8 992 Notes: 1. Logic Cell = (1) 4-input LUT + (1)FF + Carry Logic. 2. See Table 3 for package configurations. RocketIO X Features • Variable speed full-duplex transceiver, allowing • Programmable pre-emphasis levels 0 to 500% 2.488 Gb/s to 10.3125 Gb/s baud transfer rates. • Telecom/Datacom support modes with "x8" and "x10" Includes specific baud rates used by various clocking/data paths, and 64B/66B clocking support standards, as listed in Table 1, Module 2. • Receiver equalization • Between eight and twenty transceiver modules on an • AC and DC coupling FPGA, depending upon device • On-chip termination of 50Ω (eliminating the need for • Monolithic clock synthesis and clock recovery system external termination resistors) eliminates the need for external components • Pre- and post-driver serial and parallel TX-to-RX • Automatic lock-to-reference function internal loopback modes for testing operability • Programmable serial output differential swing (200 mV • Programmable comma detection allows for any to 1600 mV, peak-peak) allows compatibility with other protocol and detection of any 10-bit character serial system voltage levels • 8B/10B and 64B/66B encoding blocks PowerPC RISC Core Features • Embedded 300+ MHz Harvard architecture core • Memory Management Unit (MMU) • Low power consumption: 0.9 mW/MHz • 64-entry unified Translation Look-aside Buffers (TLB) • Five-stage data path pipeline • Variable page sizes (1 KB to 16 MB) • Hardware multiply/divide unit • Dedicated on-chip memory (OCM) interface • Thirty-two 32-bit general purpose registers • Supports IBM CoreConnect™ bus architecture • 16 KB two-way set-associative instruction cache • Debug and trace support • 16 KB two-way set-associative data cache • Timer facilities © 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS110-1 (v1.1) March 5, 2004 www.xilinx.com 1 Advance Product Specification 1-800-255-7778 R Virtex-II Pro™ X Platform FPGAs: Introduction and Overview Virtex-II Pro X Platform FPGA Technology - PCI support(1) - Differential signaling • SelectRAM memory hierarchy · 840 Mb/s Low-Voltage Differential Signaling I/O - Up to 5.5 Mb of True Dual-Port RAM in 18 Kb block (LVDS) with current mode drivers SelectRAM resources · Bus LVDS I/O - Up to 1,034 Kb of distributed SelectRAM resources · HyperTransport (LDT) I/O with current driver - High-performance interfaces to external memory buffers • Arithmetic functions · Built-in DDR input and output registers - Dedicated 18-bit x 18-bit multiplier blocks - Proprietary high-performance SelectLink - Fast look-ahead carry logic chains technology for communications between Xilinx • Flexible logic resources devices - Up to 66,176 internal registers/latches with Clock · High-bandwidth data path Enable · Double Data Rate (DDR) link · Web-based HDL generation methodology - Up to 66,176 look-up tables (LUTs) or cascadable variable (1 to 16 bits) shift registers • SRAM-based in-system configuration - Fast SelectMAP™ configuration - Wide multiplexers and wide-input function support - Horizontal cascade chain and Sum-of-Products - Triple Data Encryption Standard (DES) security support option (bitstream encryption) - IEEE1532 support - Internal 3-state busing - Partial reconfiguration • High-performance clock management circuitry - Unlimited reprogrammability - Up to eight Digital Clock Manager (DCM) modules · Precise clock de-skew - Readback capability · Flexible frequency synthesis • Supported by Xilinx Foundation™ and Alliance™ · High-resolution phase shifting series development systems - Sixteen global clock multiplexer buffers in all parts - Integrated VHDL and Verilog design flows • Active Interconnect technology - ChipScope™ Integrated Logic Analyzer - Fourth-generation segmented routing structure • 0.13-µm, nine-layer copper process with 90 nm - Fast, predictable routing delay, independent of high-speed transistors fanout •1.5V (VCCINT) core power supply, dedicated 2.5V - Deep sub-micron noise immunity benefits VCCAUX auxiliary and VCCO I/O power supplies • SelectI/O-Ultra technology • IEEE 1149.1 compatible boundary-scan logic support - Up to 992 user I/Os • Flip-Chip Ball Grid Array (BGA) packages in standard - Twenty-two single-ended standards and 1.00 mm pitch six differential standards • Each device 100% factory tested - Programmable LVCMOS sink/source current (2 mA to 24 mA) per I/O - Digitally Controlled Impedance (DCI) I/O 1. Refer to XAPP653 for more information. General Description Architecture The Virtex-II Pro X family is a platform FPGA for designs Virtex-II Pro X Array Overview that are based on IP cores and customized modules. The Virtex-II Pro X devices are user-programmable gate arrays family incorporates multi-gigabit transceivers and PowerPC with various configurable elements and embedded cores CPU cores in Virtex-II Pro X Series FPGA architecture. It optimized for high-density and high-performance system empowers complete solutions for telecommunication, wire- designs. Virtex-II Pro X devices implement the following less, networking, video, and DSP applications. functionality: The leading-edge 0.13 µm CMOS nine-layer copper pro- cess and the Virtex-II Pro X architecture are optimized for • Data baud rate up to 10.3125 Gb/s per channel high-performance designs in a wide range of densities. • Embedded IBM PowerPC 405 RISC CPU cores Combining a wide variety of flexible features and IP cores, provide performance of 300+ MHz the Virtex-II Pro X family enhances programmable logic • SelectI/O-Ultra blocks provide the interface between design capabilities and is a powerful alternative to package pins and the internal configurable logic. Most mask-programmed gate arrays. popular and leading-edge I/O standards are supported by the programmable IOBs. DS110-1 (v1.1) March 5, 2004 www.xilinx.com 2 Advance Product Specification 1-800-255-7778 R Virtex-II Pro™ X Platform FPGAs: Introduction and Overview • Configurable Logic Blocks (CLBs) provide functional • Receiver clock recovery tolerance of up to elements for combinatorial and synchronous logic, 75 non-transitioning bits including basic storage elements. BUFTs (3-state •50Ω on-chip transmit and receive terminations buffers) associated with each CLB element drive • Programmable comma detection and word alignment dedicated segmentable horizontal routing resources. • Rate matching via insertion/deletion characters • Block SelectRAM memory modules provide large • Automatic lock-to-reference function 18 Kb storage elements of True Dual-Port RAM. • Programmable pre-emphasis support • Embedded multiplier blocks are 18-bit x 18-bit dedicated multipliers. • Per-channel serial and parallel transmitter-to-receiver internal loopback modes • Digital Clock Manager (DCM) blocks provide self-calibrating, fully digital solutions for clock PowerPC 405 Processor Block distribution delay compensation, clock multiplication The PPC405 RISC CPU can execute instructions at a sus- and division, and coarse- and fine-grained clock phase tained rate of one instruction per cycle. On-chip instruction shifting. and data cache reduce design complexity and improve sys- A new generation of programmable routing resources called tem throughput. Active Interconnect Technology interconnects all of these The PPC405 features include: elements. The general routing matrix (GRM) is an array of routing switches. Each programmable element is tied to a • PowerPC RISC CPU switch matrix, allowing multiple connections to the general - Implements the PowerPC User Instruction Set routing matrix. The overall programmable interconnection is Architecture (UISA) and extensions for embedded hierarchical and designed to support high-speed designs. applications All programmable elements, including the routing - Thirty-two 32-bit general purpose registers (GPRs) resources, are controlled by values stored in static memory - Static branch prediction cells. These values are loaded in the memory cells during - Five-stage pipeline with single-cycle execution of configuration and can be reloaded to change the functions most instructions, including loads/stores of the programmable elements. - Unaligned and aligned load/store support to cache, Virtex-II
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