POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor Dieter F
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 1, JANUARY 2011 145 POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor Dieter F. Wendel, Member, IEEE, Ron Kalla, James Warnock, Senior Member, IEEE, Robert Cargnoni, Member, IEEE, Sam G. Chu, Joachim G. Clabes, Daniel Dreps, Member, IEEE, David Hrusecky, Josh Friedrich, Saiful Islam, Jim Kahle, Jens Leenstra, Gaurav Mittal, Jose Paredes, Juergen Pille, Member, IEEE, Phillip J. Restle, Member, IEEE, Balaram Sinharoy, Fellow, IEEE, George Smith, Senior Member, IEEE, William J. Starke, Scott Taylor, Member, IEEE, A. James Van Norstrand, Jr., Stephen Weitzel, Member, IEEE, Phillip G. Williams, and Victor Zyuban, Member, IEEE Abstract—This paper gives an overview of the latest member TABLE I of the POWER™ processor family, POWER7™. Eight quad- THE 11 LEVEL METAL STACK threaded cores, operating at frequencies up to 4.14 GHz, are integrated together with two memory controllers and high speed system links on a 567 mmP die, employing 1.2B transistors in a 45 nm CMOS SOI technology with 11 layers of low-k copper wiring. The technology features deep trench capacitors which are used to build a 32 MB embedded DRAM L3 based on a 0.067 mP DRAM cell. The functionally equivalent chip transistor count would have been over 2.7B if the L3 had been implemented with a conventional 6 transistor SRAM cell. (A detailed paper about the eDRAM implementation will be given in a separate paper of this Journal). Deep trench capacitors are also used to reduce on-chip voltage island supply noise. This paper describes the organiza- tion of the design and the features of the processor core, before moving on to discuss the circuits used for analog elements, clock generation and distribution, and I/O designs.
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