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PCI Express® Base Specification Revision 2.0

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PCI Express® Base Specification Revision 2.0 PCI Express® Base Specification Revision 2.0 December 20, 2006 Revision Revision History DATE 1.0 Initial release. 07/22/02 1.0a Incorporated Errata C1-C66 and E1-E4.17. 04/15/03 1.1 Incorporated approved Errata and ECNs. 03/28/05 2.0 Added 5.0 GT/s data rate and incorporated approved Errata 12/20/06 and ECNs. PCI-SIG® disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does PCI-SIG make a commitment to update the information contained herein. Contact the PCI-SIG office to obtain the latest revision of this specification. Questions regarding the PCI Express Base Specification or membership in PCI-SIG may be forwarded to: Membership Services www.pcisig.com E-mail: [email protected] Phone: 503-619-0569 Fax: 503-644-6708 Technical Support [email protected] DISCLAIMER This PCI Express Base Specification is provided “as is” with no warranties whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample. PCI-SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. PCI, PCI Express, PCIe, and PCI-SIG are trademarks or registered trademarks of PCI-SIG. All other product names are trademarks, registered trademarks, or servicemarks of their respective owners. Copyright © 2002-2006 PCI-SIG 2 PCI EXPRESS BASE SPECIFICATION, REV. 2.0 Contents OBJECTIVE OF THE SPECIFICATION.................................................................................... 21 DOCUMENT ORGANIZATION ................................................................................................ 21 DOCUMENTATION CONVENTIONS...................................................................................... 22 TERMS AND ACRONYMS........................................................................................................ 23 REFERENCE DOCUMENTS...................................................................................................... 29 1. INTRODUCTION ................................................................................................................ 31 1.1. A THIRD GENERATION I/O INTERCONNECT ................................................................... 31 1.2. PCI EXPRESS LINK......................................................................................................... 33 1.3. PCI EXPRESS FABRIC TOPOLOGY .................................................................................. 35 1.3.1. Root Complex........................................................................................................ 35 1.3.2. Endpoints .............................................................................................................. 36 1.3.3. Switch.................................................................................................................... 39 1.3.4. Root Complex Event Collector.............................................................................. 40 1.3.5. PCI Express to PCI/PCI-X Bridge........................................................................ 40 1.4. PCI EXPRESS FABRIC TOPOLOGY CONFIGURATION ....................................................... 40 1.5. PCI EXPRESS LAYERING OVERVIEW.............................................................................. 41 1.5.1. Transaction Layer................................................................................................. 42 1.5.2. Data Link Layer .................................................................................................... 42 1.5.3. Physical Layer ...................................................................................................... 43 1.5.4. Layer Functions and Services............................................................................... 43 2. TRANSACTION LAYER SPECIFICATION ..................................................................... 47 2.1. TRANSACTION LAYER OVERVIEW.................................................................................. 47 2.1.1. Address Spaces, Transaction Types, and Usage................................................... 48 2.1.2. Packet Format Overview ...................................................................................... 50 2.2. TRANSACTION LAYER PROTOCOL - PACKET DEFINITION............................................... 51 2.2.1. Common Packet Header Fields ............................................................................ 51 2.2.2. TLPs with Data Payloads - Rules ......................................................................... 54 2.2.3. TLP Digest Rules .................................................................................................. 56 2.2.4. Routing and Addressing Rules.............................................................................. 56 2.2.5. First/Last DW Byte Enables Rules........................................................................ 59 2.2.6. Transaction Descriptor......................................................................................... 61 2.2.7. Memory, I/O, and Configuration Request Rules................................................... 66 2.2.8. Message Request Rules......................................................................................... 69 2.2.9. Completion Rules.................................................................................................. 80 2.3. HANDLING OF RECEIVED TLPS...................................................................................... 82 2.3.1. Request Handling Rules........................................................................................ 85 3 PCI EXPRESS BASE SPECIFICATION, REV. 2.0 2.3.2. Completion Handling Rules.................................................................................. 98 2.4. TRANSACTION ORDERING............................................................................................ 100 2.4.1. Transaction Ordering Rules ............................................................................... 100 2.4.2. Update Ordering and Granularity Observed by a Read Transaction ................ 104 2.4.3. Update Ordering and Granularity Provided by a Write Transaction ................ 105 2.5. VIRTUAL CHANNEL (VC) MECHANISM........................................................................ 105 2.5.1. Virtual Channel Identification (VC ID) .............................................................. 108 2.5.2. TC to VC Mapping.............................................................................................. 109 2.5.3. VC and TC Rules................................................................................................. 110 2.6. ORDERING AND RECEIVE BUFFER FLOW CONTROL ..................................................... 111 2.6.1. Flow Control Rules............................................................................................. 112 2.7. DATA INTEGRITY ......................................................................................................... 122 2.7.1. ECRC Rules ........................................................................................................ 123 2.7.2. Error Forwarding ............................................................................................... 127 2.8. COMPLETION TIMEOUT MECHANISM ........................................................................... 129 2.9. LINK STATUS DEPENDENCIES ...................................................................................... 130 2.9.1. Transaction Layer Behavior in DL_Down Status............................................... 130 2.9.2. Transaction Layer Behavior in DL_Up Status ................................................... 131 3. DATA LINK LAYER SPECIFICATION.......................................................................... 133 3.1. DATA LINK LAYER OVERVIEW .................................................................................... 133 3.2. DATA LINK CONTROL AND MANAGEMENT STATE MACHINE ...................................... 135 3.2.1. Data Link Control and Management State Machine Rules ................................ 136 3.3. FLOW CONTROL INITIALIZATION PROTOCOL ............................................................... 138 3.3.1. Flow Control Initialization State Machine Rules ............................................... 138 3.4. DATA LINK LAYER PACKETS (DLLPS)........................................................................ 142 3.4.1. Data Link Layer Packet Rules ............................................................................ 142 3.5. DATA INTEGRITY ......................................................................................................... 147 3.5.1. Introduction......................................................................................................... 147 3.5.2. LCRC, Sequence Number, and Retry Management (TLP Transmitter).............. 147 3.5.3. LCRC and Sequence Number (TLP Receiver).................................................... 159 4. PHYSICAL LAYER SPECIFICATION ............................................................................ 167 4.1. INTRODUCTION ...........................................................................................................
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