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L 60 E9 L L 49 50 I US006085274A Ulllted States Patent [19] [11] Patent Number: 6,085,274 Seeman [45] Date 0f Patent: Jul. 4, 200() [54] COMPUTER SYSTEM WITH BRIDGES 5,613,075 3/1997 Wade et al. ........................... .. 395/287 HAVING POSTED MEMORY WRITE 5,636,374 6/1997 Rodgers et al. 395/384 BUFFERS 5,678,064 10/1997 Kulik et al. .. 395/309 5,684,997 11/1997 Kau et al. 395/309 . 5,941,970 8/1999 Lange .................................... .. 710/129 [75] Inventor' Thomas R’ Seeman’ Tombau’ TeX' 6,012,120 1/2000 Duncan etal. ....................... .. 710/129 [73] Assignee: Compaq Computer Corporation 6,021,451 2/2000 Bell et al. ............................. .. 710/128 Primary Examiner-Paul R. Myers [21] Appl' No* 09/260’962 Attorney, Agent, 0r Firm-Sharp, Comfort & Merrett, P.C. [22] Filed: Mar. 2, 1999 [57] ABSTRACT Related U.S. Application Data A computer system using posted memory Write buffers in a bridge can implement the system management mode Without COIIÍÍIllliitÍOIl 0f application N0. 08/775,129, DCC. 31, 1996. faulty Operation. The System management interrupt [51] Int. CI.7 .................................................... .. G06F 13/00 eeknewledge Signed is Pested in bridge buffers Se that any [52] U S C] ,n0/129. 37o/402 previously posted memory Write commands currently held l. ........................................... .. ., in a posted memory Write buffer in the bridge execute prior [58] Fleld of Search ........................... .. 370/470126/55/112386 to the appearance of the posted System management íntep ’ rupt acknowledge signal. In this Way, devices on a down [56] References Cited stream bus Will not be confused by the occurrence of posted memory Write transactions into mistaking such transactions U.S. PATENT DOCUMENTS for system management mode operations. In this Way, both 5 5 d l bridges having posted Write buffers and the system manage S’Ègg’gîl SÉ; met; ' """""""""""""" " ment mode may be utilized in efficient joint operation. 5ï586ï270 12/1996 Rnner et n1. .. 395/282 5,594,882 1/1997 Bell .................................. .. 395/421.02 17 Claims, 8 Drawing Sheets r- ­ ­ ­ - ­ ­ ­ ­ _ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ * ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­­ ­­ 1 1 8 l f- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _l Id _ _ _ n _ _ t _ _ _ _ _ _ _ _ _ u _ _' _I I \} ' §47 l l 57 ‘ g A I _9 I I ,I 5 I ~ I 34 I I (7- : I I I USDCO _t I I I DSDCO I) lI : \ I I / ‘ 75 : I 58 : I 48 I l I I 05000 { } 05000 I 15\ : RAM l I RAM i f2@ l 60 E9 l l 49 50 i I \ I I / I I P6 UsPwo } { 0sPwo PCI I BPUSS C@I INTERFACE4_3 6I |} l{ 5I INTERFACEß c@I l \ I I / : I USPwo i i DSPwO I i RAM | | RAM I _ I I _ l e2 I I 52 1 I \ : l / I l l l USDRO <`,__î '| lI Úîù DSDRO l E 75 I i 72 l g 65 i•l‘t\64_ _ 45j| ,N46 54f _ _ ` 55 }| « lI \ ARBITER \63 l| l 53f ARBITER / lI e I L _____________ _ 959315 _ J I. _ _DSQELÄ ____________ _ _ _l I U.S. Patent Jul. 4,2000 Sheet 2 0f 8 6,085,274 ___îää_lâ@m@ENI___1||||||||||||||||||||||||| LUn_ _l_A„,____,_ __ L_ |||__ll||l _ _„id _ _lI|.ILl|_Í.IILV| _ l|||.I__||l _ _ __ _A_IIIIVogm:_rONEm@ ` 1 _ \_/_ __‘_ä@a 03am:o_âm@_ A r __f\__ _A` _:ë _ Wwwm_____ _ _8%@80S A1 _ww@m_o@8 mäSm _03am:05am@_ __N@S __ \f _\_ _y8cm@8cm: _ _y_É___ê /2@N\_ _ä_äAAuïvAAHV_ÉÈEf_QÈÉ _m_m_b_ -lQQ n@mm_ fr\__\5„_Èœë„E_É l\2B/ _„_/___\__Ãï„___ïm _ _/œ_@NUI_È U.S. Patent Jul. 4,2000 Sheet 3 0f8 6,085,274 FIG. 3b U.S. Patent Jul. 4,2000 Sheet 4 0f 8 6,085,274 NFL„VL; Llw/XIM/ïj ïm/XljXJ/ßn„ 3|/UAXlï/ @IlX«IlTÍXT-„dT--TmNv_ @[email protected]@l.. omUX@ î/LJLÄLJLJLJLWÍWÍî/LWÍ @ÉXNÍXNXNÍÍXFXFTlí!{i} X U.S. Patent Jul. 4,2000 Sheet s 0f 8 6,085,274 ï.;Äy PL„Í; laElï.;ÄßN w3n; FLLÍ/>\ TT@iTTLfr*ÍT; @ÉTÉNîîîîîTlllli-- „a„ääë- .UhmBm, ÍÍÄÃÃIQÃÍQÍ JLJÈÜLJLJLJLÈJLÈJLJEL / ÈI ï: :338% ÈE ïœ@ 23a@- §95 EN@ U.S. Patent Jul. 4,2000 Sheet 6 0f 8 6,085,274 H HJ / //// / nopmœNÉNFv@_ï mm,65m. // /// / // zocäwzë@EEma@ä 7h j“ lilll *m2 @338% ÈI *Ef ÈÈ Èä 205mm ïœ@ §85 "Ewa U.S. Patent Jul. 4,2000 Sheet 7 0f 8 6,085,274 VA VA _llll ||||||||1 DATA PCI BUS READ FIG. 3f U.S. Patent Jul. 4,2000 Sheet 8 0f 8 6,085,274 .Illlllllll PCI BUS WRITE FIG. 3g 6,085,274 1 2 COMPUTER SYSTEM WITH BRIDGES the burst can be negotiated betvveen initiator and target HAVING POSTED MEMORY WRITE devices, and can be any length. BUFFERS System and component manufacturers have implemented PCI bus interfaces in various Ways. For eXample, Intel This is a continuation of application Ser. No. 08/775,129 Corporation manufactures and sells a PCI Bridge device filed Dec. 31, 1996. under the part number 82450GX, Which is a single-chip host-to-PCI bridge, allovving CPU-to-PCI and PCI-to-CPU FIELD OF THE INVENTION transactions, and permitting up to four P6 processors and This invention relates generally to computer systems With tvvo PCI bridges to be operated on a system bus. Another posted memory Write buffers used, for example, in bus to bus 10 eXample, offered by VLSI Technology, Inc., is a PCI chipset bridges. under the part number VL82C59X SuperCore, providing logic for designing a Pentium based system that uses both BACKGROUND OF THE INVENTION PCI and ISA buses. The chipset includes a bridge betvveen Computer systems of the PC type usually employ a the host bus and the PCI bus, a bridge betvveen the PCI bus 15 and the ISA bus, and a PCI bus arbiter. Posted memory Write so-called eXpansion bus to handle various data transfers and buffers are provided in both bridges, and provision is made transactions related to I/O and disk access. The eXpansion for Pentium’s pipelined bus cycles and burst transactions. bus is separate from the system bus or from the bus to Which the processor is connected, but is coupled to the system bus The “Pentium Pro” processor, commercially available from Intel Corporation uses a processor bus structure as by a bridge circuit. 20 For some time, all PC’s employed the ISA (Industry defined in the specification for this device, particularly as set forth in the publication “Pentium Pro Family Developer’s Standard Architecture) eXpansion bus, Which Was an 8-MhZ, 16-bit device (actually clocked at 8.33 Mhz). Using tvvo Manual” Vols. 1-3, Intel Corp., 1996, available from cycles of the bus clock to complete a transfer, the theoretical McGraw-Hill, and incorporated herein by reference; this maXimum transfer rate Was 8.33 Mbytes/sec. NeXt, the EISA manual is also available from Intel by accessing <http:// 25 WWW.intel.com>. (Extension to ISA) bus Was Widely used, this being a 32-bit bus clocked at 8-MhZ, allovving burst transfers at one per A CPU operates at a much faster clock rate and data clock cycle, so the theoretical maXimum Was increased to 33 access rate than most of the resources it accesses via a bus. Mbytes/sec. As performance requirements increased, With In earlier processors, such as those commonly available When the ISA bus and EISA bus Were designed, this delay faster processors and memory, and increased video band 30 Width needs, a high performance bus standard Was a neces in reading data from a resource on the bus Was handled by sity. Several standards Were proposed, including a Micro Wait states. When a processor requested data that Was not Channel architecture Which Was a 10-MhZ, 32-bit bus, immediately available due to a slovv memory or disk access, allovving 40 MByte/sec, as Well as an enhanced Micro then the processor merely marked time using Wait states, Channel using a 64-bit data Width and 64-bit data streaming, 35 doing no useful Work, until the data finally became avail theoretically permitting 80-to-160 Mbyte/sec transfer. The able. In order to make use of this delay time, a processor requirements imposed by the use of video and graphics such as the P6 provides a pipelined bus that allovvs multiple transfer on networks, hovvever, necessitate even faster trans transactions to be pending on the bus at one time, rather than fer rates. One approach Was the VESA (Video Electronics requiring one transaction to be finished before starting Standards Association) bus Which Was a 33 Mhz, 32-bit local 40 another. Also, the P6 bus allovvs split transactions, i.e., a bus standard specifically for a 486 processor, providing a request for data may be separated from the delivery of the theoretical maXimum transfer rate of 132 Mbyte/sec for data by other transactions on the bus. The P6 processor uses burst, or 66 Mbyte/sec for non-burst; the 486 had limited a technique referred to as a “deferred transaction” to accom burst transfer capability. The VESA bus Was a short-term plish the split on the bus. In a deferred transaction, a processor sends out a read request, for eXample, and the solution as higher-performance processors, e.g., the Intel P5 45 and P6 or Pentium and Pentium Pro processors, became the target sends back a “defer” response, meaning that the target standard.
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