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USB 3380-AA/AB Data Book, V1.3

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USB 3380-AA/AB Data Book, V1.3 USB 3380-AA/AB PCI Express Gen 2 to USB 3.0 SuperSpeed Peripheral Controller Data Book Version 1.3 July 2012 Website www.plxtech.com Technical Support www.plxtech.com/support Phone 800 759-3735 408 774-9060 FAX 408 774-2169 Copyright © 2012 by PLX Technology, Inc. All Rights Reserved – v1.3 July, 2012 Data Book PLX Technology, Inc. Revision History Version Date Description of Changes 1.0 January, 2012 Production release, Silicon Revision AA. Production update, Silicon Revision AA. Corrected function of pin 34 to be VAUX_IO. Previous versions of this data book incorrectly labeled this pin as VDD_IO. Designs that power VAUX_IO and VDD_IO 1.2 March, 2012 supplies separately are impacted by this change. Designs that connect VAUX_IO and VDD_IO supplies together are not affected. Added note to USB_VBUS pin regarding possible leakage current. Applied miscellaneous corrections throughout the data book. Production release, Silicon Revision AB. Production update, Silicon Revision AA. Cleaned up PM D-state references. Significantly updated Chapter 8, “USB Controller Functional Description.” 1.3 July, 2012 Changed register offset 31Ch to reserved. Corrected the SETUPDW0 register Setup Byte 0 field (USB Controller, offset 98h[7:0]). Applied miscellaneous corrections and enhancements throughout the data book. Copyright Information Copyright © 2012 PLX Technology, Inc. All Rights Reserved. The information in this document is proprietary and confidential to PLX Technology. No part of this document may be reproduced in any form or by any means or used to make any derivative work (such as translation, transformation, or adaptation) without written permission from PLX Technology. PLX Technology provides this documentation without warranty, term or condition of any kind, either express or implied, including, but not limited to, express and implied warranties of merchantability, fitness for a particular purpose, and non-infringement. While the information contained herein is believed to be accurate, such information is preliminary, and no representations or warranties of accuracy or completeness are made. In no event will PLX Technology be liable for damages arising directly or indirectly from any use of or reliance upon the information contained in this document. PLX Technology may make improvements or changes in the product(s) and/or the program(s) described in this documentation at any time. PLX Technology retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX Technology assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX Technology products. PLX Technology, USB Duet, and the PLX logo are registered trademarks and NETCHIP is a trademark of PLX Technology, Inc. PCI Express is a trademark of the PCI Special Interest Group (PCI-SIG). All product names are trademarks, registered trademarks, or service marks of their respective owners. Document Number: 3380-AA/AB-SIL-DB-P1-1.3 USB 3380-AA/AB PCI Express Gen 2 to USB 3.0 SuperSpeed Peripheral Controller Data Book, v1.3 ii Copyright © 2012 by PLX Technology, Inc. All Rights Reserved July, 2012 Preface Preface The information in this data book is subject to change without notice. This PLX data book to be updated periodically as new information is made available. Audience This data book provides functional details of PLX Technology’s USB 3380-AA/AB PCI Express Gen 2 to USB 3.0 SuperSpeed Peripheral Controller, for hardware designers and software/firmware engineers. The information provided pertains to both Silicon Revisions (AA and AB), unless specified otherwise. Supplemental Documentation This data book assumes that the reader is familiar with the following documents: • PLX Technology, Inc., www.plxtech.com The PLX USB 3380 Toolbox includes this data book and other supporting documentation, such as errata, and design and application notes. • Intel Corporation, www.intel.com – PHY Interface for the PCI Express Architecture, Version 2.00 • PCI Special Interest Group (PCI-SIG), www.pcisig.com – PCI Local Bus Specification, Revision 3.0 – PCI Bus Power Management Interface Specification, Revision 1.2 – PCI Code and ID Assignment Specification, Revision 1.2 – PCI to PCI Bridge Architecture Specification, Revision 1.2 – PCI Express Base Specification, Revision 1.1 – PCI Express Base Specification, Revision 2.0 – PCI Express Base Specification, Revision 2.0 Errata – PCI Express Base Specification, Revision 2.1 – PCI Express Card Electromechanical Specification, Revision 2.0 – PCI Express Mini Card Electromechanical Specification, Revision 1.1 – PCI Express Architecture PCI Express Jitter and BER White Paper, Revision 1.0 • Personal Computer Memory Card International Association (PCMCIA), www.pcmcia.org – ExpressCard Standard Release 1.0 • PXI System Alliance (PXI), www.pxisa.org – PXI-5 PXI Express Hardware Specification, Revision 1.0 • USB Implementers Forum, www.usb.org – Universal Serial Bus Specification Revision 2.0 – Universal Serial Bus Specification Revision 3.0 USB 3380-AA/AB PCI Express Gen 2 to USB 3.0 SuperSpeed Peripheral Controller Data Book, v1.3 Copyright © 2012 by PLX Technology, Inc. All Rights Reserved iii Supplemental Documentation PLX Technology, Inc. Note: In this data book, shortened titles are associated with the previously listed documents. The following table lists these abbreviations. Abbreviation Document PCI r3.0 PCI Local Bus Specification, Revision 3.0 PCI Power Mgmt. r1.2 PCI Bus Power Management Interface Specification, Revision 1.2 PCI-to-PCI Bridge r1.2 PCI to PCI Bridge Architecture Specification, Revision 1.2 PCI Express Base r1.0a PCI Express Base Specification, Revision 1.0a PCI Express Base r1.1 PCI Express Base Specification, Revision 1.1 PCI Express Base r2.0 PCI Express Base Specification, Revision 2.0 PCI Express Base r2.1 PCI Express Base Specification, Revision 2.1 PCI ExpressCard CEM r2.0 PCI Express Card Electromechanical Specification, Revision 2.0 PCI ExpressCard Mini CEM r1.1 PCI Express Mini Card Electromechanical Specification, Revision 1.1 USB r2.0 Universal Serial Bus Specification r2.0 USB r3.0 Universal Serial Bus Specification r3.0 USB 3380-AA/AB PCI Express Gen 2 to USB 3.0 SuperSpeed Peripheral Controller Data Book, v1.3 iv Copyright © 2012 by PLX Technology, Inc. All Rights Reserved July, 2012 Terms and Abbreviations Terms and Abbreviations The following tables list common terms and abbreviations used in this data book. Most terms and abbreviations defined in the PCI Express Base r2.1 and/or USB r3.0 are generally not included in this table. Terms and Definitions Abbreviations Data-encoding scheme used on data transferred across a Link that is operating at either 8b/10b Gen 1 or Gen 2 Link speed (2.5 or 5.0 GT/s, respectively). Acknowledge Control Packet. A Control packet used by a destination to acknowledge ACK Data packet receipt. A signal that acknowledges signal receipt. AEC Auto-Enumerate Controller. Agent Entity that operates on the PCI Express interface. ARI Alternative Routing-ID Interpretation. ARP Address Resolution Protocol. BAR Base Address register. Big Endian Most significant byte in a scalar is located at Address 0. BER Bit error rate. BIST Built-In Self Test. CDR Clock/Data Recovery circuit. Clock cycle One period of the PCI Express interface clock. Configurable Available for general Data transfers between the USB Host and PCI Express interface. Endpoint Support configuration/command/status type communication to Endpoint 0 (EP 0) CSR Control Transfer Handler, Interrupts, Messages, and Serial EEPROM Handler. CRC Cyclic Redundancy Check. CSR Configuration Space register. Dedicated Used for a pre-defined task within the USB 3380. Endpoint A uniquely addressable portion of a USB device that is the source or sink of information Device Endpoint in a communication flow between the Host and USB 3380. The USB 3380 has six Dedicated endpoints, and up to eight general-purpose endpoints. DLL Data Link Layer. DMA Direct Memory Access. The direction of data flow that moves away from the Host. The USB 3380 always connects Downstream to a downstream Port. Downstream Device that is connected to a downstream Port. Device Port that is used to communicate with a device below it in the system hierarchy. Downstream Port A bridge can have one or more downstream Ports. USB 3380-AA/AB PCI Express Gen 2 to USB 3.0 SuperSpeed Peripheral Controller Data Book, v1.3 Copyright © 2012 by PLX Technology, Inc. All Rights Reserved v Terms and Abbreviations PLX Technology, Inc. Terms and Definitions Abbreviations ECC Error-Correcting Code. EIES Electrical Idle Exit Sequence. EIOS Electrical Idle Ordered-Set. Electrical Idle Transmitter is in a High-Impedance state (+ and - are both at common mode voltage). EOP End of Packet. EP Endpoint. FC Flow Control. Field Multiple register bits that are combined for a single function. Frame 1-μs timebase established on Full-Speed Buses. FTS Fast Training Sequence. Function USB device that provides a capability to the Host. Gbps Gigabits per second. Gen 1 PCI Express Base r1.1 and below. Link transfer rate of 2.5 GT/s. Gen 2 PCI Express Base r2.0 and PCI Express Base r2.1. Link transfer rate of 5.0 GT/s. GPIO General-Purpose Input/Output. GT/s Giga-Transfers per second. Handshake Packet Packet that acknowledges or rejects a specific condition. High Bandwidth High-Speed device endpoint that transfers more than 1,024 bytes and less than Endpoint 3,073 bytes, per microframe. The Host computer system in which the USB Host Controller is installed. This includes Host the Host hardware platform and operating system in use. HCSL High-Speed Current Steering Logic. HCSLOUT HCSL Output clocks. INCH Ingress Credit Handler. InitFC Initialization Flow Control. IRAM Internal Random Access Memory (IRAM). Isochronous Data A stream of data whose timing is implied by its delivery rate. Isochronous Provide periodic continuous communication between Host and device.
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