PCI Local Bus Specification
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PCI Local Bus Specification Revision 2.2 December 18, 1998 Revision 2.2 REVISION REVISION HISTORY DATE 1.0 Original issue 6/22/92 2.0 Incorporated connector and expansion board specification 4/30/93 2.1 Incorporated clarifications and added 66 MHz chapter 6/1/95 2.2 Incorporated ECNs and improved readability 12/18/98 7KH3&,6SHFLDO,QWHUHVW*URXSGLVFODLPVDOOZDUUDQWLHVDQGOLDELOLW\IRUWKHXVHRIWKLVGRFXPHQW DQGWKHLQIRUPDWLRQFRQWDLQHGKHUHLQDQGDVVXPHVQRUHVSRQVLELOLW\IRUDQ\HUURUVWKDWPD\DSSHDU LQ WKLV GRFXPHQW QRU GRHV WKH 3&, 6SHFLDO ,QWHUHVW *URXS PDNH D FRPPLWPHQW WR XSGDWH WKH LQIRUPDWLRQFRQWDLQHGKHUHLQ &RQWDFWWKH3&,6SHFLDO,QWHUHVW*URXSRIILFHWRREWDLQWKHODWHVWUHYLVLRQRIWKHVSHFLILFDWLRQ 4XHVWLRQVUHJDUGLQJWKH3&,VSHFLILFDWLRQRUPHPEHUVKLSLQWKH3&,6SHFLDO,QWHUHVW*URXSPD\EH IRUZDUGHGWR 3&,6SHFLDO,QWHUHVW*URXS 1(.DWKU\Q +LOOVERUR2UHJRQ 3KRQH ,QVLGHWKH86 2XWVLGHWKH86 )D[ HPDLO SFLVLJ#SFLVLJFRP http://www.pcisig.com ',6&/$,0(5 7KLV3&,/RFDO%XV6SHFLILFDWLRQLVSURYLGHGDVLVZLWKQRZDUUDQWLHVZKDWVRHYHU LQFOXGLQJDQ\ZDUUDQW\RIPHUFKDQWDELOLW\QRQLQIULQJHPHQWILWQHVVIRUDQ\SDUWLFXODU SXUSRVHRUDQ\ZDUUDQW\RWKHUZLVHDULVLQJRXWRIDQ\SURSRVDOVSHFLILFDWLRQRUVDPSOH 7KH3&,6,*GLVFODLPVDOOOLDELOLW\IRULQIULQJHPHQWRISURSULHWDU\ULJKWVUHODWLQJWRXVH RILQIRUPDWLRQLQWKLVVSHFLILFDWLRQ1ROLFHQVHH[SUHVVRULPSOLHGE\HVWRSSHORU RWKHUZLVHWRDQ\LQWHOOHFWXDOSURSHUW\ULJKWVLVJUDQWHGKHUHLQ $/3+$LVDUHJLVWHUHGWUDGHPDUNRI'LJLWDO(TXLSPHQW&RUSRUDWLRQ )LUH:LUHLVDWUDGHPDUNRI$SSOH&RPSXWHU,QF 7RNHQ5LQJDQG9*$DUHWUDGHPDUNVDQG36,%00LFUR&KDQQHO26DQG3&$7DUHUHJLVWHUHG WUDGHPDUNVRI,%0&RUSRUDWLRQ :LQGRZV06'26DQG0LFURVRIWDUHUHJLVWHUHGWUDGHPDUNVRI0LFURVRIW&RUSRUDWLRQ 7ULVWDWHLVDUHJLVWHUHGWUDGHPDUNRI1DWLRQDO6HPLFRQGXFWRU 1X%XVLVDWUDGHPDUNRI7H[DV,QVWUXPHQWV (WKHUQHWLVDUHJLVWHUHGWUDGHPDUNRI;HUR[&RUSRUDWLRQ $OORWKHUSURGXFWQDPHVDUHWUDGHPDUNVUHJLVWHUHGWUDGHPDUNVRUVHUYLFHPDUNVRIWKHLUUHVSHFWLYHRZQHUV Copyright © 1992, 1993, 1995, 1998 PCI Special Interest Group ii Revision 2.2 Contents Chapter 1 Introduction 1.1. Specification Contents............................................................................................................ 1 1.2. Motivation .............................................................................................................................. 1 1.3. PCI Local Bus Applications ................................................................................................... 2 1.4. PCI Local Bus Overview........................................................................................................ 3 1.5. PCI Local Bus Features and Benefits..................................................................................... 4 1.6. Administration........................................................................................................................ 6 Chapter 2 Signal Definition 2.1. Signal Type Definition ........................................................................................................... 8 2.2. Pin Functional Groups............................................................................................................ 8 2.2.1. System Pins ..................................................................................................................... 8 2.2.2. Address and Data Pins..................................................................................................... 9 2.2.3. Interface Control Pins.................................................................................................... 10 2.2.4. Arbitration Pins (Bus Masters Only)............................................................................. 11 2.2.5. Error Reporting Pins...................................................................................................... 12 2.2.6. Interrupt Pins (Optional) ............................................................................................... 13 2.2.7. Additional Signals ......................................................................................................... 15 2.2.8. 64-Bit Bus Extension Pins (Optional) ........................................................................... 17 2.2.9. JTAG/Boundary Scan Pins (Optional) .......................................................................... 18 2.3. Sideband Signals .................................................................................................................. 19 2.4. Central Resource Functions.................................................................................................. 19 iii Revision 2.2 Chapter 3 Bus Operation 3.1. Bus Commands..................................................................................................................... 21 3.1.1. Command Definition .....................................................................................................21 3.1.2. Command Usage Rules ................................................................................................. 23 3.2. PCI Protocol Fundamentals.................................................................................................. 26 3.2.1. Basic Transfer Control .................................................................................................. 26 3.2.2. Addressing..................................................................................................................... 27 3.2.2.1. I/O Space Decoding................................................................................................ 28 3.2.2.2. Memory Space Decoding ....................................................................................... 28 3.2.2.3. Configuration Space Decoding............................................................................... 30 3.2.3. Byte Lane and Byte Enable Usage ................................................................................ 38 3.2.4. Bus Driving and Turnaround......................................................................................... 39 3.2.5. Transaction Ordering and Posting ................................................................................. 40 3.2.5.1. Transaction Ordering and Posting for Simple Devices .......................................... 41 3.2.5.2. Transaction Ordering and Posting for Bridges ....................................................... 42 3.2.6. Combining, Merging, and Collapsing ........................................................................... 44 3.3. Bus Transactions .................................................................................................................. 46 3.3.1. Read Transaction ........................................................................................................... 47 3.3.2. Write Transaction .......................................................................................................... 48 3.3.3. Transaction Termination ............................................................................................... 49 3.3.3.1. Master Initiated Termination .................................................................................. 49 3.3.3.2. Target Initiated Termination .................................................................................. 52 3.3.3.3. Delayed Transactions ............................................................................................. 61 3.4. Arbitration ............................................................................................................................ 68 3.4.1. Arbitration Signaling Protocol ...................................................................................... 70 3.4.2. Fast Back-to-Back Transactions.................................................................................... 72 3.4.3. Arbitration Parking........................................................................................................ 74 3.5. Latency ................................................................................................................................. 75 3.5.1. Target Latency............................................................................................................... 75 3.5.1.1. Target Initial Latency ............................................................................................. 75 3.5.1.2. Target Subsequent Latency .................................................................................... 77 iv Revision 2.2 3.5.2. Master Data Latency...................................................................................................... 78 3.5.3. Memory Write Maximum Completion Time Limit ...................................................... 78 3.5.4. Arbitration Latency ....................................................................................................... 79 3.5.4.1. Bandwidth and Latency Considerations................................................................. 80 3.5.4.2. Determining Arbitration Latency ........................................................................... 82 3.5.4.3. Determining Buffer Requirements ......................................................................... 87 3.6. Other Bus Operations ........................................................................................................... 88 3.6.1. Device Selection............................................................................................................ 88 3.6.2. Special Cycle ................................................................................................................. 90 3.6.3. Address/Data Stepping