PCI Local Bus Specification
Revision 2.2 December 18, 1998 Revision 2.2
REVISION REVISION HISTORY DATE 1.0 Original issue 6/22/92 2.0 Incorporated connector and expansion board specification 4/30/93 2.1 Incorporated clarifications and added 66 MHz chapter 6/1/95 2.2 Incorporated ECNs and improved readability 12/18/98
7KH3&,6SHFLDO,QWHUHVW*URXSGLVFODLPVDOOZDUUDQWLHVDQGOLDELOLW\IRUWKHXVHRIWKLVGRFXPHQW DQGWKHLQIRUPDWLRQFRQWDLQHGKHUHLQDQGDVVXPHVQRUHVSRQVLELOLW\IRUDQ\HUURUVWKDWPD\DSSHDU LQ WKLV GRFXPHQW QRU GRHV WKH 3&, 6SHFLDO ,QWHUHVW *URXS PDNH D FRPPLWPHQW WR XSGDWH WKH LQIRUPDWLRQFRQWDLQHGKHUHLQ &RQWDFWWKH3&,6SHFLDO,QWHUHVW*URXSRIILFHWRREWDLQWKHODWHVWUHYLVLRQRIWKHVSHFLILFDWLRQ 4XHVWLRQVUHJDUGLQJWKH3&,VSHFLILFDWLRQRUPHPEHUVKLSLQWKH3&,6SHFLDO,QWHUHVW*URXSPD\EH IRUZDUGHGWR 3&,6SHFLDO,QWHUHVW*URXS 1(.DWKU\Q +LOOVERUR2UHJRQ 3KRQH ,QVLGHWKH86 2XWVLGHWKH86 )D[ HPDLO SFLVLJ#SFLVLJFRP http://www.pcisig.com
',6&/$,0(5 7KLV3&,/RFDO%XV6SHFLILFDWLRQLVSURYLGHGDVLVZLWKQRZDUUDQWLHVZKDWVRHYHU LQFOXGLQJDQ\ZDUUDQW\RIPHUFKDQWDELOLW\QRQLQIULQJHPHQWILWQHVVIRUDQ\SDUWLFXODU SXUSRVHRUDQ\ZDUUDQW\RWKHUZLVHDULVLQJRXWRIDQ\SURSRVDOVSHFLILFDWLRQRUVDPSOH 7KH3&,6,*GLVFODLPVDOOOLDELOLW\IRULQIULQJHPHQWRISURSULHWDU\ULJKWVUHODWLQJWRXVH RILQIRUPDWLRQLQWKLVVSHFLILFDWLRQ1ROLFHQVHH[SUHVVRULPSOLHGE\HVWRSSHORU RWKHUZLVHWRDQ\LQWHOOHFWXDOSURSHUW\ULJKWVLVJUDQWHGKHUHLQ
$/3+$LVDUHJLVWHUHGWUDGHPDUNRI'LJLWDO(TXLSPHQW&RUSRUDWLRQ )LUH:LUHLVDWUDGHPDUNRI$SSOH&RPSXWHU,QF 7RNHQ5LQJDQG9*$DUHWUDGHPDUNVDQG36,%00LFUR&KDQQHO26DQG3&$7DUHUHJLVWHUHG WUDGHPDUNVRI,%0&RUSRUDWLRQ :LQGRZV06'26DQG0LFURVRIWDUHUHJLVWHUHGWUDGHPDUNVRI0LFURVRIW&RUSRUDWLRQ 7ULVWDWHLVDUHJLVWHUHGWUDGHPDUNRI1DWLRQDO6HPLFRQGXFWRU 1X%XVLVDWUDGHPDUNRI7H[DV,QVWUXPHQWV (WKHUQHWLVDUHJLVWHUHGWUDGHPDUNRI;HUR[&RUSRUDWLRQ $OORWKHUSURGXFWQDPHVDUHWUDGHPDUNVUHJLVWHUHGWUDGHPDUNVRUVHUYLFHPDUNVRIWKHLUUHVSHFWLYHRZQHUV
Copyright © 1992, 1993, 1995, 1998 PCI Special Interest Group
ii Revision 2.2
Contents
Chapter 1 Introduction
1.1. Specification Contents...... 1
1.2. Motivation ...... 1
1.3. PCI Local Bus Applications ...... 2
1.4. PCI Local Bus Overview...... 3
1.5. PCI Local Bus Features and Benefits...... 4
1.6. Administration...... 6
Chapter 2 Signal Definition
2.1. Signal Type Definition ...... 8
2.2. Pin Functional Groups...... 8
2.2.1. System Pins ...... 8
2.2.2. Address and Data Pins...... 9
2.2.3. Interface Control Pins...... 10
2.2.4. Arbitration Pins (Bus Masters Only)...... 11
2.2.5. Error Reporting Pins...... 12
2.2.6. Interrupt Pins (Optional) ...... 13
2.2.7. Additional Signals ...... 15
2.2.8. 64-Bit Bus Extension Pins (Optional) ...... 17
2.2.9. JTAG/Boundary Scan Pins (Optional) ...... 18
2.3. Sideband Signals ...... 19
2.4. Central Resource Functions...... 19
iii Revision 2.2
Chapter 3 Bus Operation
3.1. Bus Commands...... 21
3.1.1. Command Definition ...... 21
3.1.2. Command Usage Rules ...... 23
3.2. PCI Protocol Fundamentals...... 26
3.2.1. Basic Transfer Control ...... 26
3.2.2. Addressing...... 27 3.2.2.1. I/O Space Decoding...... 28 3.2.2.2. Memory Space Decoding ...... 28 3.2.2.3. Configuration Space Decoding...... 30
3.2.3. Byte Lane and Byte Enable Usage ...... 38
3.2.4. Bus Driving and Turnaround...... 39
3.2.5. Transaction Ordering and Posting ...... 40 3.2.5.1. Transaction Ordering and Posting for Simple Devices ...... 41 3.2.5.2. Transaction Ordering and Posting for Bridges ...... 42
3.2.6. Combining, Merging, and Collapsing ...... 44
3.3. Bus Transactions ...... 46
3.3.1. Read Transaction ...... 47
3.3.2. Write Transaction ...... 48
3.3.3. Transaction Termination ...... 49 3.3.3.1. Master Initiated Termination ...... 49 3.3.3.2. Target Initiated Termination ...... 52 3.3.3.3. Delayed Transactions ...... 61
3.4. Arbitration ...... 68
3.4.1. Arbitration Signaling Protocol ...... 70
3.4.2. Fast Back-to-Back Transactions...... 72
3.4.3. Arbitration Parking...... 74
3.5. Latency ...... 75
3.5.1. Target Latency...... 75 3.5.1.1. Target Initial Latency ...... 75 3.5.1.2. Target Subsequent Latency ...... 77 iv Revision 2.2
3.5.2. Master Data Latency...... 78
3.5.3. Memory Write Maximum Completion Time Limit ...... 78
3.5.4. Arbitration Latency ...... 79 3.5.4.1. Bandwidth and Latency Considerations...... 80 3.5.4.2. Determining Arbitration Latency ...... 82 3.5.4.3. Determining Buffer Requirements ...... 87
3.6. Other Bus Operations ...... 88
3.6.1. Device Selection...... 88
3.6.2. Special Cycle ...... 90
3.6.3. Address/Data Stepping ...... 91
3.6.4. Interrupt Acknowledge...... 93
3.7. Error Functions...... 93
3.7.1. Parity Generation...... 94
3.7.2. Parity Checking ...... 95
3.7.3. Address Parity Errors ...... 95
3.7.4. Error Reporting...... 95 3.7.4.1. Data Parity Error Signaling on PERR# ...... 96 3.7.4.2. Other Error Signaling on SERR# ...... 97 3.7.4.3. Master Data Parity Error Status Bit...... 98 3.7.4.4. Detected Parity Error Status Bit ...... 98
3.7.5. Delayed Transactions and Data Parity Errors ...... 98
3.7.6. Error Recovery ...... 99
3.8. 64-Bit Bus Extension...... 100
3.8.1. Determining Bus Width During System Initialization ...... 104
3.9. 64-bit Addressing ...... 105
3.10. Special Design Considerations ...... 108
v Revision 2.2
Chapter 4 Electrical Specification
4.1. Overview ...... 113
4.1.1. 5V to 3.3V Transition Road Map ...... 113
4.1.2. Dynamic vs. Static Drive Specification ...... 115
4.2. Component Specification ...... 115
4.2.1. 5V Signaling Environment ...... 117 4.2.1.1. DC Specifications ...... 117 4.2.1.2. AC Specifications ...... 118 4.2.1.3. Maximum AC Ratings and Device Protection ...... 120
4.2.2. 3.3V Signaling Environment ...... 122 4.2.2.1. DC Specifications ...... 122 4.2.2.2. AC Specifications ...... 123 4.2.2.3. Maximum AC Ratings and Device Protection ...... 125
4.2.3. Timing Specification ...... 126 4.2.3.1. Clock Specification ...... 126 4.2.3.2. Timing Parameters...... 128 4.2.3.3. Measurement and Test Conditions ...... 129
4.2.4. Indeterminate Inputs and Metastability ...... 130
4.2.5. Vendor Provided Specification...... 131
4.2.6. Pinout Recommendation ...... 131
4.3. System (Motherboard) Specification...... 132
4.3.1. Clock Skew...... 132
4.3.2. Reset ...... 133
4.3.3. Pull-ups...... 136
4.3.4. Power...... 137 4.3.4.1. Power Requirements...... 137 4.3.4.2. Sequencing...... 137 4.3.4.3. Decoupling...... 138
4.3.5. System Timing Budget ...... 138
4.3.6. Physical Requirements ...... 141 4.3.6.1. Routing and Layout Recommendations for Four-Layer Motherboards ...... 141 4.3.6.2. Motherboard Impedance...... 141
vi Revision 2.2
4.3.7. Connector Pin Assignments ...... 142
4.4. Expansion Board Specification ...... 146
4.4.1. Board Pin Assignment...... 146
4.4.2. Power Requirements...... 150 4.4.2.1. Decoupling...... 150 4.4.2.2. Power Consumption ...... 150
4.4.3. Physical Requirements ...... 151 4.4.3.1. Trace Length Limits ...... 151 4.4.3.2. Routing Recommendations for Four-Layer Expansion Boards ...... 152 4.4.3.3. Impedance...... 152 4.4.3.4. Signal Loading...... 152
Chapter 5 Mechanical Specification
5.1. Overview ...... 153
5.2. Expansion Card Physical Dimensions and Tolerances ...... 154
5.2.1. Connector Physical Description ...... 168 5.2.1.1. Connector Physical Requirements...... 176 5.2.1.2. Connector Performance Specification...... 177
5.2.2. Planar Implementation ...... 178
Chapter 6 Configuration Space
6.1. Configuration Space Organization ...... 190
6.2. Configuration Space Functions ...... 192
6.2.1. Device Identification ...... 192
6.2.2. Device Control...... 193
6.2.3. Device Status ...... 196
6.2.4. Miscellaneous Registers ...... 198
6.2.5. Base Addresses...... 201 6.2.5.1. Address Maps ...... 201 6.2.5.2. Expansion ROM Base Address Register...... 204
6.3. PCI Expansion ROMs ...... 205
6.3.1. PCI Expansion ROM Contents...... 206
vii Revision 2.2
6.3.1.1. PCI Expansion ROM Header Format...... 206 6.3.1.2. PCI Data Structure Format ...... 207
6.3.2. Power-on Self Test (POST) Code ...... 209
6.3.3. PC-compatible Expansion ROMs...... 209 6.3.3.1. ROM Header Extensions ...... 209
6.4. Vital Product Data ...... 212
6.5. Device Drivers...... 212
6.6. System Reset ...... 213
6.7. Capabilities List...... 213
6.8. Message Signaled Interrupts ...... 214
6.8.1. Message Capability Structure...... 214 6.8.1.1. Capability ID ...... 215 6.8.1.2. Next Pointer...... 215 6.8.1.3. Message Control ...... 215 6.8.1.4. Message Address ...... 217 6.8.1.5. Message Upper Address (Optional) ...... 217 6.8.1.6. Message Data...... 218
6.8.2. MSI Operation ...... 218 6.8.2.1. MSI Transaction Termination ...... 220 6.8.2.2. MSI Transaction Reception and Ordering Requirements ...... 220
Chapter 7 66 Mhz PCI Specification
7.1. Introduction ...... 221
7.2. Scope ...... 221
7.3. Device Implementation Considerations ...... 222
7.3.1. Configuration Space ...... 222
7.4. Agent Architecture ...... 222
7.5. Protocol...... 222
7.5.1. 66MHZ_ENABLE (M66EN) Pin Definition ...... 222
7.5.2. Latency ...... 223
viii Revision 2.2
7.6. Electrical Specification...... 223
7.6.1. Overview ...... 223
7.6.2. Transition Roadmap to 66 MHz PCI...... 224
7.6.3. Signaling Environment...... 224 7.6.3.1. DC Specifications...... 225 7.6.3.2. AC Specifications...... 225 7.6.3.3. Maximum AC Ratings and Device Protection ...... 226
7.6.4. Timing Specification ...... 226 7.6.4.1. Clock Specification ...... 226 7.6.4.2. Timing Parameters...... 228 7.6.4.3. Measurement and Test Conditions ...... 229
7.6.5. Vendor Provided Specification ...... 231
7.6.6. Recommendations ...... 231 7.6.6.1. Pinout Recommendations...... 231 7.6.6.2. Clocking Recommendations...... 231
7.7. System (Planar) Specification ...... 232
7.7.1. Clock Uncertainty...... 232
7.7.2. Reset ...... 233
7.7.3. Pullups ...... 233
7.7.4. Power...... 233 7.7.4.1. Power Requirements...... 233 7.7.4.2. Sequencing...... 233 7.7.4.3. Decoupling...... 233
7.7.5. System Timing Budget ...... 233
7.7.6. Physical Requirements ...... 236 7.7.6.1. Routing and Layout Recommendations for Four-Layer Boards ...... 236 7.7.6.2. Planar Impedance ...... 236
7.7.7. Connector Pin Assignments ...... 236
7.8. Expansion Board Specifications...... 237
ix Revision 2.2
Appendix A Special Cycle Messages ...... 239
Appendix B State Machines ...... 241
Appendix C Operating Rules...... 251
Appendix D Class Codes...... 257
Appendix E System Transaction Ordering...... 267
Appendix F Exclusive Accesses...... 279
Appendix G I/O Space Address Decoding for Legacy Devices ...... 285
Appendix H Capability IDs...... 287
Appendix I Vital Product Data ...... 289
Glossary ...... 297
x Revision 2.2 Figures
Figure 1-1: PCI Local Bus Applications ...... 2
Figure 1-2: PCI System Block Diagram...... 3
Figure 2-1: PCI Pin List ...... 7
Figure 3-1: Address Phase Formats of Configuration Transactions ...... 31
Figure 3-2: Layout of CONFIG_ADDRESS Register ...... 32
Figure 3-3: Host Bridge Translation for Type 0 Configuration Transactions Address Phase...... 33
Figure 3-4: Configuration Read ...... 38
Figure 3-5: Basic Read Operation ...... 47
Figure 3-6: Basic Write Operation ...... 48
Figure 3-7: Master Initiated Termination ...... 50
Figure 3-8: Master-Abort Termination ...... 51
Figure 3-9: Retry ...... 55
Figure 3-10: Disconnect With Data...... 56
Figure 3-11: Master Completion Termination ...... 57
Figure 3-12: Disconnect-1 Without Data Termination ...... 58
Figure 3-13: Disconnect-2 Without Data Termination ...... 58
Figure 3-14: Target-Abort ...... 59
Figure 3-15: Basic Arbitration ...... 70
Figure 3-16: Arbitration for Back-to-Back Access ...... 74
Figure 3-17: DEVSEL# Assertion...... 89
Figure 3-18: Address Stepping...... 92
Figure 3-19: Interrupt Acknowledge Cycle...... 93
Figure 3-20: Parity Operation...... 94
Figure 3-21: 64-bit Read Request With 64-bit Transfer ...... 103
Figure 3-22: 64-bit Write Request With 32-bit Transfer ...... 104
xi Revision 2.2
Figure 3-23. 64-Bit Dual Address Read Cycle...... 107
Figure 4-1: PCI Board Connectors ...... 114
Figure 4-2: V/I Curves for 5V Signaling...... 120
Figure 4-3: Maximum AC Waveforms for 5V Signaling ...... 121
Figure 4-4: V/I Curves for 3.3V Signaling...... 124
Figure 4-5: Maximum AC Waveforms for 3.3V Signaling ...... 125
Figure 4-6: Clock Waveforms ...... 126
Figure 4-7: Output Timing Measurement Conditions ...... 129
Figure 4-8: Input Timing Measurement Conditions ...... 129
Figure 4-9: Suggested Pinout for PQFP PCI Component ...... 132
Figure 4-10: Clock Skew Diagram...... 133
Figure 4-11: Reset Timing...... 135
Figure 4-12: Measurement of Tprop, 5 Volt Signaling...... 140 Figure 5-1: PCI Raw Card (5V) ...... 155
Figure 5-2: PCI Raw Card (3.3V and Universal) ...... 155
Figure 5-3: PCI Raw Variable Height Short Card (5V, 32-bit) ...... 156
Figure 5-4: PCI Raw Variable Height Short Card (3.3V, 32-bit) ...... 156
Figure 5-5: PCI Raw Variable Height Short Card (5V, 64-bit) ...... 157
Figure 5-6: PCI Raw Variable Height Short Card (3.3V, 64-bit) ...... 158
Figure 5-7: PCI Card Edge Connector Bevel ...... 159
Figure 5-8: ISA Assembly (5V) ...... 160
Figure 5-9: ISA Assembly (3.3V and Universal)...... 160
Figure 5-10: MC Assembly (5V) ...... 161
Figure 5-11: MC Assembly (3.3V) ...... 161
Figure 5-12: ISA Bracket ...... 162
Figure 5-13: ISA Retainer ...... 163
Figure 5-14: I/O Window Height ...... 164
xii Revision 2.2
Figure 5-15: Adapter Installation With Large I/O Connector ...... 165
Figure 5-16: MC Bracket Brace ...... 166
Figure 5-17: MC Bracket...... 167
Figure 5-18: MC Bracket Details ...... 168
Figure 5-19: 32-bit Connector ...... 169
Figure 5-20: 5V/32-bit Connector Layout Recommendation ...... 169
Figure 5-21: 3.3V/32-bit Connector Layout Recommendation ...... 170
Figure 5-22: 5V/64-bit Connector ...... 170
Figure 5-23: 5V/64-bit Connector Layout Recommendation ...... 170
Figure 5-24: 3.3V/64-bit Connector ...... 171
Figure 5-25: 3.3V/64-bit Connector Layout Recommendation ...... 171
Figure 5-26: 5V/32-bit Card Edge Connector Dimensions and Tolerances ...... 172
Figure 5-27: 5V/64-bit Card Edge Connector Dimensions and Tolerances ...... 172
Figure 5-28: 3.3V/32-bit Card Edge Connector Dimensions and Tolerances ...... 173
Figure 5-29: 3.3V/64-bit Card Edge Connector Dimensions and Tolerances ...... 173
Figure 5-30: Universal 32-bit Card Edge Connector Dimensions and Tolerances ...... 174
Figure 5-31: Universal 64-bit Card Edge Connector Dimensions and Tolerances ...... 175
Figure 5-32: PCI Card Edge Connector Contacts ...... 176
Figure 5-33: PCI Connector Location on Planar Relative to Datum on the ISA Connector ...... 179
Figure 5-34: PCI Connector Location on Planar Relative to Datum on the EISA Connector...... 179
Figure 5-35: PCI Connector Location on Planar Relative to Datum on the MC Connector ...... 180
Figure 5-36: 32-bit PCI Riser Connector ...... 181
Figure 5-37: 32-bit/5V Riser Connector Footprint ...... 182
Figure 5-38: 32-bit/3.3V Riser Connector Footprint ...... 183
Figure 5-39: 64-bit/5V Riser Connector ...... 184
Figure 5-40: 64-bit/5V Riser Connector Footprint ...... 185
xiii Revision 2.2
Figure 5-41: 64-bit/3.3V Riser Connector ...... 186
Figure 5-42: 64-bit/3.3V Riser Connector Footprint...... 187
Figure 6-1: Type 00h Configuration Space Header ...... 191
Figure 6-2: Command Register Layout...... 193
Figure 6-3: Status Register Layout...... 196
Figure 6-4: BIST Register Layout...... 199
Figure 6-5: Base Address Register for Memory ...... 202
Figure 6-6: Base Address Register for I/O ...... 202
Figure 6-7: Expansion ROM Base Address Register Layout...... 205
Figure 6-8: PCI Expansion ROM Structure ...... 206
Figure 6-9: Typical Image Layout...... 211
Figure 6-10: Example Capabilities List...... 213
Figure 6-11: Message Signaled Interrupt Capability Structure...... 214
Figure 7-1: 33 MHz PCI vs. 66 MHz PCI Timing ...... 224
Figure 7-2: 3.3V Clock Waveform...... 226
Figure 7-3: Output Timing Measurement Conditions ...... 229
Figure 7-4: Input Timing Measurement Conditions ...... 229
Figure 7-5: Tval(max) Rising Edge...... 230
Figure 7-6: Tval(max) Falling Edge...... 230
Figure 7-7: Tval (min) and Slew Rate...... 231
Figure 7-8: Recommended Clock Routing...... 232
Figure 7-9: Clock Skew Diagram...... 233
Figure 7-10: Measurement of Tprop ...... 235
Figure D-1: Programming Interface Byte Layout for IDE Controller Class Code ...... 258
Figure E-1: Example Producer - Consumer Model...... 269
Figure E-2: Example System with PCI-to-PCI Bridges ...... 276
Figure F-1: Starting an Exclusive Access ...... 282
xiv Revision 2.2
Figure F-2: Continuing an Exclusive Access ...... 283
Figure F-3: Accessing a Locked Agent ...... 284
Figure I-1: VPD Capability Structure ...... 289
Figure I-2: Small Resource Data Type Tag Bit Definitions...... 290
Figure I-3: Large Resource Data Type Tag Bit Definitions...... 291
Figure I-4: Resource Data Type Flags for a Typical VPD...... 291
Figure I-5: VPD Format ...... 292
xv Revision 2.2
xvi Revision 2.2
Preface
Specification Supersedes Earlier Documents 7KLVGRFXPHQWFRQWDLQVWKHIRUPDOVSHFLILFDWLRQVRIWKHSURWRFROHOHFWULFDODQG PHFKDQLFDOIHDWXUHVRIWKH3&,/RFDO%XV6SHFLILFDWLRQ5HYLVLRQDVWKHSURGXFWLRQ YHUVLRQHIIHFWLYH'HFHPEHU 7KH3&,/RFDO%XV6SHFLILFDWLRQ5HYLVLRQ LVVXHG-XQH LVVXSHUVHGHGE\WKLVVSHFLILFDWLRQ )ROORZLQJSXEOLFDWLRQRIWKH3&,/RFDO%XV6SHFLILFDWLRQ5HYLVLRQWKHUHPD\EH IXWXUHDSSURYHGHUUDWDDQGRUDSSURYHGFKDQJHVWRWKHVSHFLILFDWLRQSULRUWRWKHLVVXDQFH RIDQRWKHUIRUPDOUHYLVLRQ7RDVVXUHGHVLJQVPHHWWKHODWHVWOHYHOUHTXLUHPHQWV GHVLJQHUVRI3&,GHYLFHVPXVWUHIHUWRWKH3&,6,*KRPHSDJHDWKWWS ZZZSFLVLJFRP LQWKHPHPEHUVRQO\VHFWLRQIRUDQ\DSSURYHGFKDQJHV
Incorporation of Engineering Change Requests (ECRs) 7KHIROORZLQJ(&5VKDYHEHHQLQFRUSRUDWHGLQWRWKLVSURGXFWLRQYHUVLRQRIWKH VSHFLILFDWLRQ
ECR Description New Capabilities Changes to configuration structure to define additional capabilities of a PCI function Sub ID Subsystem vendor configuration space changed from optional to required for most classes of devices PME# Describes wake-up function and assigns (previously reserved) pin on PCI bus MECH ECN# 1 Bracket mounting for EMI reduction MECH ECN# 2 Increase size of I/O window to enable new connectors MECH ECN# 3 I/O connector volume to enable add-in card insertion MECH ECN# 4 Riser connector-add-in card interface
xvii Revision 2.2
ECR Description MECH ECN# 5 Tighten critical tolerance to improve add-in card seating MECH ECN# 6 Mechanical errata (wrong datum ref), components free areas Posted Memory Clarified requirements for posted memory writes to prevent Writes situations which may lead to a deadlock Tprop Clarifies measurement and determination of Tprop times for 33/66 MHz RST# TIMING New timing requirements between RST# and the first transaction on the bus and the first access to a device VPD (Revised) Provides alternate access method to vital product data 3.3 V Aux Specifies a standard source of power for power management wake event logic Max Retry Time Devices cannot Retry a memory write request for longer than 10 µs Msg Interrupt Method by which an I/O controller can deliver message based interrupt Spread Spectrum Adds spread spectrum clocking (SSC) to the specification Clocking
xviii Revision 2.2
Document Conventions 7KHIROORZLQJQDPHDQGXVDJHFRQYHQWLRQVDUHXVHGLQWKLVGRFXPHQW asserted, deasserted The terms asserted and deasserted refer to the globally visible state of the signal on the clock edge, not to signal transitions. edge, clock edge The terms edge and clock edge refer to the rising edge of the clock. On the rising edge of the clock is the only time signals have any significance on the PCI bus. # A # symbol at the end of a signal name indicates that the signal's asserted state occurs when it is at a low voltage. The absence of a # symbol indicates that the signal is asserted at a high voltage. reserved The contents or undefined states or information are not defined at this time. Using any reserved area in the PCI specification is not permitted. All areas of the PCI specification can only be changed according to the by-laws of the PCI Special Interest Group. Any use of the reserved areas of the PCI specification will result in a product that is not PCI-compliant. The functionality of any such product cannot be guaranteed in this or any future revision of the PCI specification. signal names Signal names are indicated with this bold font. signal range A signal name followed by a range enclosed in brackets, for example AD[31::00], represents a range of logically related signals. The first number in the range indicates the most significant bit (msb) and the last number indicates the least significant bit (lsb). implementation notes Implementation notes are enclosed in a box. They are not part of the PCI specification and are included for clarification and illustration only.
xix Revision 2.2
xx Revision 2.2
Chapter 1 Introduction
1.1. Specification Contents 7KH3&,/RFDO%XVLVDKLJKSHUIRUPDQFHELWRUELWEXVZLWKPXOWLSOH[HGDGGUHVV DQGGDWDOLQHV7KHEXVLVLQWHQGHGIRUXVHDVDQLQWHUFRQQHFWPHFKDQLVPEHWZHHQKLJKO\ LQWHJUDWHGSHULSKHUDOFRQWUROOHUFRPSRQHQWVSHULSKHUDODGGLQERDUGVDQG SURFHVVRUPHPRU\V\VWHPV 7KH3&,/RFDO%XV6SHFLILFDWLRQ5HYLQFOXGHVWKHSURWRFROHOHFWULFDOPHFKDQLFDO DQGFRQILJXUDWLRQVSHFLILFDWLRQIRU3&,/RFDO%XVFRPSRQHQWVDQGH[SDQVLRQERDUGV 7KHHOHFWULFDOGHILQLWLRQSURYLGHVIRU9DQG9VLJQDOLQJHQYLURQPHQWV 7KH3&,/RFDO%XV6SHFLILFDWLRQGHILQHVWKH3&,KDUGZDUHHQYLURQPHQW&RQWDFWWKH 3&,6,*IRUPRUHLQIRUPDWLRQRQWKHDYDLODEOH3&,GHVLJQJXLGHVDQGWKH3&,%,26 6SHFLILFDWLRQ)RULQIRUPDWLRQRQKRZWRMRLQWKH3&,6,*RUWRREWDLQWKHVHGRFXPHQWV UHIHUWR6HFWLRQ
1.2. Motivation :KHQWKH3&,/RFDO%XV6SHFLILFDWLRQZDVRULJLQDOO\GHYHORSHGLQ JUDSKLFV RULHQWHGRSHUDWLQJV\VWHPVVXFKDV:LQGRZVDQG26KDGFUHDWHGDGDWDERWWOHQHFN EHWZHHQWKHSURFHVVRUDQGLWVGLVSOD\SHULSKHUDOVLQVWDQGDUG3&,2DUFKLWHFWXUHV 0RYLQJSHULSKHUDOIXQFWLRQVZLWKKLJKEDQGZLGWKUHTXLUHPHQWVFORVHUWRWKHV\VWHP V SURFHVVRUEXVFDQHOLPLQDWHWKLVERWWOHQHFN6XEVWDQWLDOSHUIRUPDQFHJDLQVDUHVHHQZLWK JUDSKLFDOXVHULQWHUIDFHV *8,V DQGRWKHUKLJKEDQGZLGWKIXQFWLRQV LHIXOOPRWLRQ YLGHR6&6,/$1VHWF ZKHQDORFDOEXVGHVLJQLVXVHG 3&,VXFFHVVIXOO\PHWWKHVHGHPDQGVRIWKHLQGXVWU\DQGLVQRZWKHPRVWZLGHO\DFFHSWHG DQGLPSOHPHQWHGH[SDQVLRQVWDQGDUGLQWKHZRUOG
1 Revision 2.2
1.3. PCI Local Bus Applications 7KH3&,/RFDO%XVKDVEHHQGHILQHGZLWKWKHSULPDU\JRDORIHVWDEOLVKLQJDQLQGXVWU\ VWDQGDUGKLJKSHUIRUPDQFHORFDOEXVDUFKLWHFWXUHWKDWRIIHUVORZFRVWDQGDOORZV GLIIHUHQWLDWLRQ:KLOHWKHSULPDU\IRFXVLVRQHQDEOLQJQHZSULFHSHUIRUPDQFHSRLQWVLQ WRGD\ VV\VWHPVLWLVLPSRUWDQWWKDWDQHZVWDQGDUGDOVRDFFRPPRGDWHVIXWXUHV\VWHP UHTXLUHPHQWVDQGEHDSSOLFDEOHDFURVVPXOWLSOHSODWIRUPVDQGDUFKLWHFWXUHV)LJXUH VKRZVWKHPXOWLSOHGLPHQVLRQVRIWKH3&,/RFDO%XV 6HUYHUV 9
+LJK(QG $XWR 64-bit Upgrade 'HVNWRSV 9 &RQILJXUDWLRQ Path
/RZ0LG 70 5DQJH ; $OSKD$;3 )XWXUH 'HVNWRS $UFKLWHFWXUH 3URFHVVRU &38V 3URFHVVRU )DPLOLHV 0RELOH )DPLOLHV
)LJXUH 3&,/RFDO%XV$SSOLFDWLRQV
:KLOHWKHLQLWLDOIRFXVRIORFDOEXVDSSOLFDWLRQVKDVEHHQRQORZWRKLJKHQGGHVNWRS V\VWHPVWKH3&,/RFDO%XVDOVRFRPSUHKHQGVWKHUHTXLUHPHQWVIURPPRELOHDSSOLFDWLRQV XSWKURXJKGHSDUWPHQWDOVHUYHUV7KHYROWUHTXLUHPHQWVRIWKHPRELOHHQYLURQPHQW DQGWKHLPPLQHQWPRYHIURPYROWVWRYROWVLQGHVNWRSDSSOLFDWLRQVPXVWEH DFFRXQWHGIRULQDQHZVWDQGDUG7KH3&,/RFDO%XVVSHFLILHVERWKYROWDJHVDQG GHVFULEHVDFOHDUPLJUDWLRQSDWKEHWZHHQWKHP 7KH3&,FRPSRQHQWDQGDGGLQFDUGLQWHUIDFHLVSURFHVVRULQGHSHQGHQWHQDEOLQJDQ HIILFLHQWWUDQVLWLRQWRIXWXUHSURFHVVRUJHQHUDWLRQVDQGXVHZLWKPXOWLSOHSURFHVVRU DUFKLWHFWXUHV3URFHVVRULQGHSHQGHQFHDOORZVWKH3&,/RFDO%XVWREHRSWLPL]HGIRU,2 IXQFWLRQVHQDEOHVFRQFXUUHQWRSHUDWLRQRIWKHORFDOEXVZLWKWKHSURFHVVRUPHPRU\ VXEV\VWHPDQGDFFRPPRGDWHVPXOWLSOHKLJKSHUIRUPDQFHSHULSKHUDOVLQDGGLWLRQWR JUDSKLFV PRWLRQYLGHR/$16&6,)'',KDUGGLVNGULYHVHWF 0RYHPHQWWR HQKDQFHGYLGHRDQGPXOWLPHGLDGLVSOD\V LH+'79DQG'JUDSKLFV DQGRWKHUKLJK EDQGZLGWK,2ZLOOFRQWLQXHWRLQFUHDVHORFDOEXVEDQGZLGWKUHTXLUHPHQWV$ WUDQVSDUHQWELWH[WHQVLRQRIWKHELWGDWDDQGDGGUHVVEXVHVLVGHILQHGGRXEOLQJWKH EXVEDQGZLGWKDQGRIIHULQJIRUZDUGDQGEDFNZDUGFRPSDWLELOLW\RIELWDQGELW3&, /RFDO%XVSHULSKHUDOV$IRUZDUGDQGEDFNZDUGFRPSDWLEOH0+]VSHFLILFDWLRQLV DOVRGHILQHGGRXEOLQJWKHEDQGZLGWKFDSDELOLWLHVRIWKH0+]GHILQLWLRQ 7KH3&,/RFDO%XVVWDQGDUGRIIHUVDGGLWLRQDOEHQHILWVWRWKHXVHUVRI3&,EDVHGV\VWHPV &RQILJXUDWLRQUHJLVWHUVDUHVSHFLILHGIRU3&,FRPSRQHQWVDQGDGGLQFDUGV$V\VWHP ZLWKHPEHGGHGDXWRFRQILJXUDWLRQVRIWZDUHRIIHUVWUXHHDVHRIXVHIRUWKHV\VWHPXVHUE\ DXWRPDWLFDOO\FRQILJXULQJ3&,DGGLQFDUGVDWSRZHURQ
2 Revision 2.2
1.4. PCI Local Bus Overview 7KHEORFNGLDJUDP )LJXUH VKRZVDW\SLFDO3&,/RFDO%XVV\VWHPDUFKLWHFWXUH7KLV H[DPSOHLVQRWLQWHQGHGWRLPSO\DQ\VSHFLILFDUFKLWHFWXUDOOLPLWV,QWKLVH[DPSOHWKH SURFHVVRUFDFKHPHPRU\VXEV\VWHPLVFRQQHFWHGWR3&,WKURXJKD3&,EULGJH7KLV EULGJHSURYLGHVDORZODWHQF\SDWKWKURXJKZKLFKWKHSURFHVVRUPD\GLUHFWO\DFFHVV3&, GHYLFHVPDSSHGDQ\ZKHUHLQWKHPHPRU\RU,2DGGUHVVVSDFHV,WDOVRSURYLGHVDKLJK EDQGZLGWKSDWKDOORZLQJ3&,PDVWHUVGLUHFWDFFHVVWRPDLQPHPRU\7KHEULGJHPD\ RSWLRQDOO\LQFOXGHVXFKIXQFWLRQVDVGDWDEXIIHULQJSRVWLQJDQG3&,FHQWUDOIXQFWLRQV HJDUELWUDWLRQ
3URFHVVRU
&DFKH %ULGJH 0RWLRQ $XGLR 0HPRU\ 9LGHR '5$0 &RQWUROOHU
3&,/RFDO%XV
([S%XV *UDSKLFV /$1 6&6, ;IDFH
%DVH,2 )XQFWLRQV
,6$(,6$ÃÃÃÃ0LFUR&KDQQHO
)LJXUH 3&,6\VWHP%ORFN'LDJUDP
7\SLFDO3&,/RFDO%XVLPSOHPHQWDWLRQVZLOOVXSSRUWXSWRIRXUDGGLQERDUGFRQQHFWRUV DOWKRXJKH[SDQVLRQFDSDELOLW\LVQRWUHTXLUHG7KH3&,DGGLQERDUGFRQQHFWRULVD 0LFUR&KDQQHO 0& VW\OHFRQQHFWRU7KHVDPH3&,H[SDQVLRQERDUGFDQEHXVHGLQ ,6$(,6$DQG0&EDVHGV\VWHPV3&,H[SDQVLRQFDUGVXVHDQHGJHFRQQHFWRUDQG PRWKHUERDUGVWKDWDOORZDIHPDOHFRQQHFWRUWREHPRXQWHGSDUDOOHOWRWKHV\VWHPEXV FRQQHFWRUV7RSURYLGHDTXLFNDQGHDV\WUDQVLWLRQIURP9WR9FRPSRQHQW WHFKQRORJ\3&,GHILQHVWZRDGGLQERDUGFRQQHFWRUV RQHIRUWKH9VLJQDOLQJ HQYLURQPHQWDQGRQHIRUWKH9VLJQDOLQJHQYLURQPHQW 7KUHHVL]HVRI3&,DGGLQERDUGVDUHGHILQHG ORQJVKRUWDQGYDULDEOHVKRUWOHQJWK 6\VWHPVDUHQRWUHTXLUHGWRVXSSRUWDOOERDUGW\SHV7KHORQJERDUGVLQFOXGHDQ ,6$(,6$H[WHQGHUWRHQDEOHWKHPWRXVH,6$(,6$FDUGJXLGHVLQ,6$(,6$V\VWHPV 7RDFFRPPRGDWHWKH9DQG9VLJQDOLQJHQYLURQPHQWVDQGWRIDFLOLWDWHDVPRRWK PLJUDWLRQSDWKEHWZHHQWKHYROWDJHVWKUHHDGGLQERDUGHOHFWULFDOW\SHVDUHVSHFLILHG D YROWERDUGZKLFKSOXJVLQWRRQO\WKH9FRQQHFWRUDXQLYHUVDOERDUGZKLFKSOXJV LQWRERWK9DQG9FRQQHFWRUVDQGDYROWERDUGZKLFKSOXJVLQWRRQO\WKH9 FRQQHFWRU 7ZRW\SHVRI3&,EDFNSODWHVDUHFXUUHQWO\GHILQHG ,6$(,6$DQG0&FRPSDWLEOH 7KHLQWHUFKDQJHDEOHEDFNSODWHVVKRXOGERWKEHVXSSOLHGZLWKHDFK3&,/RFDO%XVDGGLQ ERDUGVKLSSHGWRDFFRPPRGDWHXVDJHRIWKHERDUGLQDOOWKUHHV\VWHPW\SHV
3 Revision 2.2
1.5. PCI Local Bus Features and Benefits 7KH3&,/RFDO%XVZDVVSHFLILHGWRHVWDEOLVKDKLJKSHUIRUPDQFHORFDOEXVVWDQGDUGIRU VHYHUDOJHQHUDWLRQVRISURGXFWV7KH3&,VSHFLILFDWLRQSURYLGHVDVHOHFWLRQRIIHDWXUHV WKDWFDQDFKLHYHPXOWLSOHSULFHSHUIRUPDQFHSRLQWVDQGFDQHQDEOHIXQFWLRQVWKDWDOORZ GLIIHUHQWLDWLRQDWWKHV\VWHPDQGFRPSRQHQWOHYHO)HDWXUHVDUHFDWHJRUL]HGE\EHQHILWDV IROORZV
High Performance • Transparent upgrade from 32-bit data path at 33 MHz (132 MB/s peak) to 64-bit data path at 33 MHz (264 MB/s peak) and from 32-bit data path at 66 MHz (264 MB/s peak) to 64-bit data path at 66 MHz (528 MB/s peak). • Variable length linear and cacheline wrap mode bursting for both read and writes improves write dependent graphics performance. • Low latency random accesses (60-ns write access latency for 33 MHz PCI or 30-ns for 66 MHz PCI to slave registers from master parked on bus). • Capable of full concurrency with processor/memory subsystem. • Synchronous bus with operation up to 33 MHz or 66 MHz. • Hidden (overlapped) central arbitration. Low Cost • Optimized for direct silicon (component) interconnection; i.e., no glue logic. Electrical/driver (i.e., total load) and frequency specifications are met with standard ASIC technologies and other typical processes. • Multiplexed architecture reduces pin count (47 signals for target; 49 for master) and package size of PCI components or provides for additional functions to be built into a particular package size. • Single PCI add-in card works in ISA-, EISA-, or MC-based systems (with minimal change to existing chassis designs), reducing inventory cost and end user confusion. Ease of Use • Enables full auto configuration support of PCI Local Bus add-in boards and components. PCI devices contain registers with the device information required for configuration. Longevity • Processor independent. Supports multiple families of processors as well as future generations of processors (by bridges or by direct integration). • Support for 64-bit addressing. • Both 5-volt and 3.3-volt signaling environments are specified. Voltage migration path enables smooth industry transition from 5 volts to 3.3 volts.
4 Revision 2.2
Interoperability/ • Small form factor add-in boards. Reliability • Present signals allow power supplies to be optimized for the expected system usage by monitoring add-in boards that could surpass the maximum power budgeted by the system. • Over 2000 hours of electrical SPICE simulation with hardware model validation. • Forward and backward compatibility of 32-bit and 64-bit add-in boards and components. • Forward and backward compatibility with 33 MHz and 66 MHz add-in boards and components. • Increased reliability and interoperability of add-in cards by comprehending the loading and frequency requirements of the local bus at the component level, eliminating buffers and glue logic. • MC-style expansion connectors. Flexibility • Full multi-master capability allowing any PCI master peer- to-peer access to any PCI master/target. • A shared slot accommodates either a standard ISA, EISA, or MC board or a PCI add-in board (refer to Chapter 5, "Mechanical Specification" for connector layout details). Data Integrity • Provides parity on both data and address and allows implementation of robust client platforms. Software • PCI components can be fully compatible with existing Compatibility driver and applications software. Device drivers can be portable across various classes of platforms.
5 Revision 2.2
1.6. Administration 7KLVGRFXPHQWLVPDLQWDLQHGE\WKH3&,6,*7KH3&,6,*DQXQLQFRUSRUDWHG DVVRFLDWLRQRIPHPEHUVRIWKHPLFURFRPSXWHULQGXVWU\ZDVHVWDEOLVKHGWRPRQLWRUDQG HQKDQFHWKHGHYHORSPHQWRIWKH3&,/RFDO%XVLQWKUHHZD\V7KH3&,6,*LVFKDUWHUHG WR • 0DLQWDLQWKHIRUZDUGFRPSDWLELOLW\RIDOO3&,/RFDO%XVUHYLVLRQVRUDGGHQGD • 0DLQWDLQWKH3&,/RFDO%XVVSHFLILFDWLRQDVDVLPSOHHDV\WRLPSOHPHQWVWDEOH WHFKQRORJ\LQWKHVSLULWRILWVGHVLJQ • &RQWULEXWHWRWKHHVWDEOLVKPHQWRIWKH3&,/RFDO%XVDVDQLQGXVWU\ZLGHVWDQGDUG DQGWRWKHWHFKQLFDOORQJHYLW\RIWKH3&,/RFDO%XVDUFKLWHFWXUH 6,*PHPEHUVKLSLVDYDLODEOHWRDOODSSOLFDQWVZLWKLQWKHPLFURFRPSXWHULQGXVWU\ %HQHILWVRIPHPEHUVKLSLQFOXGH • $ELOLW\WRVXEPLWVSHFLILFDWLRQUHYLVLRQVDQGDGGHQGXPSURSRVDOV • 3DUWLFLSDWLRQLQVSHFLILFDWLRQUHYLVLRQVDQGDGGHQGXPSURSRVDOV • $XWRPDWLFDOO\UHFHLYHUHYLVLRQVDQGDGGHQGD • 9RWLQJULJKWVWRGHWHUPLQHWKH6WHHULQJ&RPPLWWHHPHPEHUVKLS • 9HQGRU,'QXPEHUDVVLJQPHQW • 3&,WHFKQLFDOVXSSRUW • 3&,VXSSRUWGRFXPHQWDWLRQDQGPDWHULDOV • 3DUWLFLSDWLRQLQ6,*VSRQVRUHGWUDGHVKRZVXLWHVDQGHYHQWVFRQIHUHQFHVDQGRWKHU 3&,/RFDO%XVSURPRWLRQDODFWLYLWLHV • 3DUWLFLSDWLRQLQWKHFRPSOLDQFHSURJUDPLQFOXGLQJSDUWLFLSDWLRQDWWKH³3&, &RPSOLDQFH:RUNVKRSV´DQGWKHRSSRUWXQLW\WREHLQFOXGHGLQWKH³3&,,QWHJUDWRU¶V /LVW´ $QDQQXDO3&,6SHFLDO,QWHUHVW*URXSPHPEHUVKLSFRVWV867KLVPHPEHUVKLS IHHVXSSRUWVWKHDFWLYLWLHVRIWKH3&,6,*LQFOXGLQJWKHFRPSOLDQFHSURJUDP3&,6,* DGPLQLVWUDWLRQDQGYHQGRU,'LVVXLQJDQGDGPLQLVWUDWLRQ
)RULQIRUPDWLRQRQKRZWREHFRPHD6,*PHPEHURURQREWDLQLQJ3&,/RFDO%XV GRFXPHQWDWLRQSOHDVHFRQWDFW 3&,6SHFLDO,QWHUHVW*URXS 1(.DWKU\Q +LOOVERUR2UHJRQ 3KRQH ,QVLGHWKH86 2XWVLGHWKH86 )D[ HPDLO SFLVLJ#SFLVLJFRP http://www.pcisig.com
6 Revision 2.2
Chapter 2 Signal Definition
7KH3&,LQWHUIDFHUHTXLUHVDPLQLPXP RISLQVIRUDWDUJHWRQO\GHYLFHDQG SLQV IRUDPDVWHUWRKDQGOHGDWDDQGDGGUHVVLQJLQWHUIDFHFRQWURODUELWUDWLRQDQGV\VWHP IXQFWLRQV)LJXUHVKRZVWKHSLQVLQIXQFWLRQDOJURXSVZLWKUHTXLUHGSLQVRQWKHOHIW VLGHDQGRSWLRQDOSLQVRQWKHULJKWVLGH7KHGLUHFWLRQLQGLFDWLRQRQVLJQDOVLQ)LJXUH DVVXPHVDFRPELQDWLRQPDVWHUWDUJHWGHYLFH Required Pins Optional Pins
AD[31::00] AD[63::32] Address & Data C/BE[3::0]# C/BE[7::4]# 64-Bit Extension PAR PAR64 REQ64# FRAME# ACK64# TRDY# PCI Interface IRDY# COMPLIANT LOCK# Interface Control STOP# DEVICE Control DEVSEL# INTA# INTB# IDSEL INTC# Interrupts INTD# Error PERR# Reporting SERR#
REQ# Arbitration TDI GNT# (masters only) TDO TCK JTAG CLK TMS (IEEE 1149.1) System RST# TRST#
)LJXUH 3&,3LQ/LVW
1 The minimum number of pins for a planar-only device is 45 for a target-only and 47 for a master (PERR# and SERR# are optional for planar-only applications). Systems must support all signals defined for the connector. This includes individual REQ# and GNT# signals for each connector. The PRSNT[1::2]# pins are not device signals and, therefore, are not included in Figure 2-1, but are required to be connected on add-in cards.
7 Revision 2.2
2.1. Signal Type Definition 7KHIROORZLQJVLJQDOW\SHGHILQLWLRQVDUHIURPWKHYLHZSRLQWRIDOOGHYLFHVRWKHUWKDQ WKHDUELWHURUFHQWUDOUHVRXUFH)RUWKHDUELWHUREQ#LVDQLQSXWGNT#LVDQRXWSXW DQGRWKHU3&,VLJQDOVIRUWKHDUELWHUKDYHWKHVDPHGLUHFWLRQDVDPDVWHURUWDUJHW7KH FHQWUDOUHVRXUFHLVD³ORJLFDO´GHYLFHZKHUHDOOV\VWHPW\SHIXQFWLRQVDUHORFDWHG UHIHUWR 6HFWLRQIRUPRUHGHWDLOV
in Input is a standard input-only signal. out Totem Pole Output is a standard active driver. t/s Tri-State is a bi-directional, tri-state input/output pin. s/t/s Sustained Tri-State is an active low tri-state signal owned and driven by one and only one agent at a time. The agent that drives an s/t/s pin low must drive it high for at least one clock before letting it float. A new agent cannot start driving a s/t/s signal any sooner than one clock after the previous owner tri-states it. A pullup is required to sustain the inactive state until another agent drives it and must be provided by the central resource. o/d Open Drain allows multiple devices to share as a wire-OR. A pull-up is required to sustain the inactive state until another agent drives it and must be provided by the central resource.
2.2. Pin Functional Groups 7KH3&,SLQGHILQLWLRQVDUHRUJDQL]HGLQWKHIXQFWLRQDOJURXSVVKRZQLQ)LJXUH$ V\PERODWWKHHQGRIDVLJQDOQDPHLQGLFDWHVWKDWWKHDVVHUWHGVWDWHRFFXUVZKHQWKH VLJQDOLVDWDORZYROWDJH:KHQWKHV\PEROLVDEVHQWWKHVLJQDOLVDVVHUWHGDWDKLJK YROWDJH7KHVLJQDOLQJPHWKRGXVHGRQHDFKSLQLVVKRZQIROORZLQJWKHVLJQDOQDPH
2.2.1. System Pins
CLK in Clock provides timing for all transactions on PCI and is an input to every PCI device. All other PCI signals, except RST#, INTA#, INTB#, INTC#, and INTD#, are sampled on the rising edge of CLK and all other timing parameters are defined with respect to this edge. PCI operates up to 33 MHz (refer to Chapter 4) or 66 MHz (refer to Chapter 7) and, in general, the minimum frequency is DC (0 Hz); however, component-specific permissions are described in Chapter 4 (refer to Section 4.2.3.1.).
8 Revision 2.2
RST# in Reset is used to bring PCI-specific registers, sequencers, and signals to a consistent state. What effect RST# has on a device beyond the PCI sequencer is beyond the scope of this specification, except for reset states of required PCI configuration registers. A device that can wake the system while in a powered down bus state has additional requirements related to RST#. Refer to the PCI Power Management Interface Specification for details. Anytime RST# is asserted, all PCI output signals must be driven to their benign state. In general, this means they must be asynchronously tri-stated. REQ# and GNT# must both be tri- stated (they cannot be driven low or high during reset). To prevent AD, C/BE#, and PAR signals from floating during reset, the central resource may drive these lines during reset (bus parking) but only to a logic low level; they may not be driven high. Refer to Section 3.8.1. for special requirements for AD[63::32], C/BE[7::4]#, and PAR64 when they are not connected (as in a 64-bit card installed in a 32-bit connector). RST# may be asynchronous to CLK when asserted or deasserted. Although asynchronous, deassertion is guaranteed to be a clean, bounce-free edge. Except for configuration accesses, only devices that are required to boot the system will respond after reset.
2.2.2. Address and Data Pins
AD[31::00] t/s Address and Data are multiplexed on the same PCI pins. A bus transaction consists of an address2 phase followed by one or more data phases. PCI supports both read and write bursts. The address phase is the first clock cycle in which FRAME# is asserted. During the address phase, AD[31::00] contain a physical address (32 bits). For I/O, this is a byte address; for configuration and memory, it is a DWORD address. During data phases, AD[07::00] contain the least significant byte (lsb) and AD[31::24] contain the most significant byte (msb). Write data is stable and valid when IRDY# is asserted; read data is stable and valid when TRDY# is asserted. Data is transferred during those clocks where both IRDY# and TRDY# are asserted.
2 The DAC uses two address phases to transfer a 64-bit address.
9 Revision 2.2
C/BE[3::0]# t/s Bus Command and Byte Enables are multiplexed on the same PCI pins. During the address phase of a transaction, C/BE[3::0]# define the bus command (refer to Section 3.1. for bus command definitions). During the data phase, C/BE[3::0]# are used as Byte Enables. The Byte Enables are valid for the entire data phase and determine which byte lanes carry meaningful data. C/BE[0]# applies to byte 0 (lsb) and C/BE[3]# applies to byte 3 (msb). PAR t/s Parity is even3 parity across AD[31::00] and C/BE[3::0]#. Parity generation is required by all PCI agents. PAR is stable and valid one clock after each address phase. For data phases, PAR is stable and valid one clock after either IRDY# is asserted on a write transaction or TRDY# is asserted on a read transaction. Once PAR is valid, it remains valid until one clock after the completion of the current data phase. (PAR has the same timing as AD[31::00], but it is delayed by one clock.) The master drives PAR for address and write data phases; the target drives PAR for read data phases.
2.2.3. Interface Control Pins
FRAME# s/t/s Cycle Frame is driven by the current master to indicate the beginning and duration of an access. FRAME# is asserted to indicate a bus transaction is beginning. While FRAME# is asserted, data transfers continue. When FRAME# is deasserted, the transaction is in the final data phase or has completed. IRDY# s/t/s Initiator Ready indicates the initiating agent's (bus master's) ability to complete the current data phase of the transaction. IRDY# is used in conjunction with TRDY#. A data phase is completed on any clock both IRDY# and TRDY# are asserted. During a write, IRDY# indicates that valid data is present on AD[31::00]. During a read, it indicates the master is prepared to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. TRDY# s/t/s Target Ready indicates the target agent's (selected device's) ability to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is completed on any clock both TRDY# and IRDY# are asserted. During a read, TRDY# indicates that valid data is present on AD[31::00]. During a write, it indicates the target is prepared to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. STOP# s/t/s Stop indicates the current target is requesting the master to stop the current transaction.
3 The number of "1"s on AD[31::00], C/BE[3::0]#, and PAR equals an even number.
10 Revision 2.2
LOCK# s/t/s Lock indicates an atomic operation to a bridge that may require multiple transactions to complete. When LOCK# is asserted, non-exclusive transactions may proceed to a bridge that is not currently locked. A grant to start a transaction on PCI does not guarantee control of LOCK#. Control of LOCK# is obtained under its own protocol in conjunction with GNT#. It is possible for different agents to use PCI while a single master retains ownership of LOCK#. Locked transactions may be initiated only by host bridges, PCI-to-PCI bridges, and expansion bus bridges. Refer to Appendix F for details on the requirements of LOCK#. IDSEL in Initialization Device Select is used as a chip select during configuration read and write transactions. DEVSEL# s/t/s Device Select, when actively driven, indicates the driving device has decoded its address as the target of the current access. As an input, DEVSEL# indicates whether any device on the bus has been selected.
2.2.4. Arbitration Pins (Bus Masters Only)
REQ# t/s Request indicates to the arbiter that this agent desires use of the bus. This is a point-to-point signal. Every master has its own REQ# which must be tri-stated while RST# is asserted. GNT# t/s Grant indicates to the agent that access to the bus has been granted. This is a point-to-point signal. Every master has its own GNT# which must be ignored while RST# is asserted.
:KLOHRST#LVDVVHUWHGWKHDUELWHUPXVWLJQRUHDOOREQ# OLQHVVLQFHWKH\DUHWULVWDWHG DQGGRQRWFRQWDLQDYDOLGUHTXHVW7KHDUELWHUFDQRQO\SHUIRUPDUELWUDWLRQDIWHURST# LVGHDVVHUWHG$PDVWHUPXVWLJQRUHLWVGNT#ZKLOHRST#LVDVVHUWHGREQ#DQG GNT#DUHWULVWDWHVLJQDOVGXHWRSRZHUVHTXHQFLQJUHTXLUHPHQWVLQWKHFDVHZKHUHWKH EXVDUELWHULVSRZHUHGE\DGLIIHUHQWVXSSO\YROWDJHWKDQWKHEXVPDVWHUGHYLFH
4 REQ# is an input to the arbiter, and GNT# is an output.
11 Revision 2.2
2.2.5. Error Reporting Pins
7KHHUURUUHSRUWLQJSLQVDUHUHTXLUHG E\DOOGHYLFHVDQGPD\EHDVVHUWHGZKHQHQDEOHG PERR# s/t/s Parity Error is only for the reporting of data parity errors during all PCI transactions except a Special Cycle. The PERR# pin is sustained tri-state and must be driven active by the agent receiving data (when enabled) two clocks following the data when a data parity error is detected. The minimum duration of PERR# is one clock for each data phase that a data parity error is detected. (If sequential data phases each have a data parity error, the PERR# signal will be asserted for more than a single clock.) PERR# must be driven high for one clock before being tri-stated as with all sustained tri-state signals. Refer to Section 3.7.4.1. for more details. SERR# o/d System Error is for reporting address parity errors, data parity errors on the Special Cycle command, or any other system error where the result will be catastrophic. If an agent does not want a non-maskable interrupt (NMI) to be generated, a different reporting mechanism is required. SERR# is pure open drain and is actively driven for a single PCI clock by the agent reporting the error. The assertion of SERR# is synchronous to the clock and meets the setup and hold times of all bused signals. However, the restoring of SERR# to the deasserted state is accomplished by a weak pullup (same value as used for s/t/s) which is provided by the central resource not by the signaling agent. This pullup may take two to three clock periods to fully restore SERR#. The agent that reports SERR# to the operating system does so anytime SERR# is asserted.
5 Some planar devices are granted exceptions (refer to Section 3.7.2. for details).
12 Revision 2.2
2.2.6. Interrupt Pins (Optional)
,QWHUUXSWVRQ3&,DUHRSWLRQDODQGGHILQHGDVOHYHOVHQVLWLYHDVVHUWHGORZ QHJDWLYH WUXH XVLQJRSHQGUDLQRXWSXWGULYHUV7KHDVVHUWLRQDQGGHDVVHUWLRQRIINTx#LV DV\QFKURQRXVWRCLK$GHYLFHDVVHUWVLWVINTx#OLQHZKHQUHTXHVWLQJDWWHQWLRQIURP LWVGHYLFHGULYHUXQOHVVWKHGHYLFHLVHQDEOHGWRXVHPHVVDJHVLJQDOHGLQWHUUXSWV 06, UHIHUWR6HFWLRQIRUPRUHLQIRUPDWLRQ 2QFHWKHINTx#VLJQDOLVDVVHUWHGLW UHPDLQVDVVHUWHGXQWLOWKHGHYLFHGULYHUFOHDUVWKHSHQGLQJUHTXHVW:KHQWKHUHTXHVWLV FOHDUHGWKHGHYLFHGHDVVHUWVLWVINTx#VLJQDO3&,GHILQHVRQHLQWHUUXSWOLQHIRUDVLQJOH IXQFWLRQGHYLFHDQGXSWRIRXULQWHUUXSWOLQHVIRUDPXOWLIXQFWLRQ GHYLFHRUFRQQHFWRU )RUDVLQJOHIXQFWLRQGHYLFHRQO\INTA#PD\EHXVHGZKLOHWKHRWKHUWKUHHLQWHUUXSW OLQHVKDYHQRPHDQLQJ INTA# o/d Interrupt A is used to request an interrupt. INTB# o/d Interrupt B is used to request an interrupt and only has meaning on a multi-function device. INTC# o/d Interrupt C is used to request an interrupt and only has meaning on a multi-function device. INTD# o/d Interrupt D is used to request an interrupt and only has meaning on a multi-function device.
$Q\IXQFWLRQRQDPXOWLIXQFWLRQGHYLFHFDQEHFRQQHFWHGWRDQ\RIWKHINTx#OLQHV 7KH,QWHUUXSW3LQUHJLVWHU UHIHUWR6HFWLRQIRUGHWDLOV GHILQHVZKLFKINTx#OLQH WKHIXQFWLRQXVHVWRUHTXHVWDQLQWHUUXSW,IDGHYLFHLPSOHPHQWVDVLQJOHINTx#OLQHLWLV FDOOHGINTA# LILWLPSOHPHQWVWZROLQHVWKH\DUHFDOOHGINTA#DQGINTB# DQGVR IRUWK)RUDPXOWLIXQFWLRQGHYLFHDOOIXQFWLRQVPD\XVHWKHVDPHINTx#OLQHRUHDFK PD\KDYHLWVRZQ XSWRDPD[LPXPRIIRXUIXQFWLRQV RUDQ\FRPELQDWLRQWKHUHRI$ VLQJOHIXQFWLRQFDQQHYHUJHQHUDWHDQLQWHUUXSWUHTXHVWRQPRUHWKDQRQHINTx#OLQH 7KHV\VWHPYHQGRULVIUHHWRFRPELQHWKHYDULRXVINTx#VLJQDOVIURPWKH3&, FRQQHFWRU V LQDQ\ZD\WRFRQQHFWWKHPWRWKHLQWHUUXSWFRQWUROOHU7KH\PD\EHZLUH 25HGRUHOHFWURQLFDOO\VZLWFKHGXQGHUSURJUDPFRQWURORUDQ\FRPELQDWLRQWKHUHRI 7KHV\VWHPGHVLJQHUPXVWLQVXUHWKDWHDFKINTx#VLJQDOIURPHDFKFRQQHFWRULV FRQQHFWHGWRDQLQSXWRQWKHLQWHUUXSWFRQWUROOHU7KLVPHDQVWKHGHYLFHGULYHUPD\QRW PDNHDQ\DVVXPSWLRQVDERXWLQWHUUXSWVKDULQJ$OO3&,GHYLFHGULYHUVPXVWEHDEOHWR VKDUHDQLQWHUUXSW FKDLQLQJ ZLWKDQ\RWKHUORJLFDOGHYLFHLQFOXGLQJGHYLFHVLQWKHVDPH PXOWLIXQFWLRQSDFNDJH
6 When several independent functions are integrated into a single device, it will be referred to as a multi- function device. Each function on a multi-function device has its own configuration space.
13 Revision 2.2
Implementation Note: Interrupt Routing +RZLQWHUUXSWVDUHURXWHGRQWKHPRWKHUERDUGLVV\VWHPVSHFLILF+RZHYHUWKH IROORZLQJH[DPSOHPD\EHXVHGZKHQDQRWKHURSWLRQLVQRWUHTXLUHGDQGWKHLQWHUUXSW FRQWUROOHUKDVIRXURSHQLQWHUUXSWUHTXHVWOLQHVDYDLODEOH6LQFHPRVWGHYLFHVDUHVLQJOH IXQFWLRQDQGWKHUHIRUHFDQRQO\XVHINTA#RQWKHGHYLFHWKLVPHFKDQLVPGLVWULEXWHV WKHLQWHUUXSWVHYHQO\DPRQJWKHLQWHUUXSWFRQWUROOHU VLQSXWSLQV INTA#RI'HYLFH1XPEHULVFRQQHFWHGWRIRQWRQWKHPRWKHUERDUG 'HYLFH 1XPEHUKDVQRVLJQLILFDQFHUHJDUGLQJEHLQJORFDWHGRQWKHPRWKHUERDUGRULQD FRQQHFWRU INTA#RI'HYLFH1XPEHULVFRQQHFWHGWRIRQXRQWKHPRWKHUERDUG INTA# RI'HYLFH1XPEHULVFRQQHFWHGWRIRQYRQWKHPRWKHUERDUGINTA#RI 'HYLFH1XPEHULVFRQQHFWHGWRIRQZRQWKHPRWKHUERDUG7KHWDEOHEHORZGHVFULEHV KRZHDFKDJHQW¶VINTx#OLQHVDUHFRQQHFWHGWRWKHPRWKHUERDUGLQWHUUXSWOLQHV7KH IROORZLQJHTXDWLRQFDQEHXVHGWRGHWHUPLQHWRZKLFKINTx#VLJQDORQWKHPRWKHUERDUG DJLYHQGHYLFH¶VINTx#OLQH V LVFRQQHFWHG 0% ', 02' 0% 0RWKHUERDUG,QWHUUXSW IRQW IRQX IRQY DQGIRQZ ' 'HYLFH1XPEHU , ,QWHUUXSW1XPEHU INTA# INTB# INTC# DQGINTD#
Device Number Interrupt Pin on Interrupt Pin on on Motherboard Device Motherboard
0, 4, 8, 12, INTA# IRQW 16, 20, 24, 28 INTB# IRQX INTC# IRQY INTD# IRQZ
1, 5, 9, 13, INTA# IRQX 17, 21, 25, 29 INTB# IRQY INTC# IRQZ INTD# IRQW
2, 6, 10, 14, INTA# IRQY 18, 22, 26, 30 INTB# IRQZ INTC# IRQW INTD# IRQX
3, 7, 11, 15, INTA# IRQZ 19, 23, 27, 31 INTB# IRQW INTC# IRQX INTD# IRQY
14 Revision 2.2
2.2.7. Additional Signals
PRSNT[1:2]# in The Present signals are not signals for a device, but are provided by an add-in board. The Present signals indicate to the motherboard whether an add-in board is physically present in the slot and, if one is present, the total power requirements of the board. These signals are required for add-in boards but are optional for motherboards. Refer to Section 4.4.1. for more details. Implementation Note: PRSNT# Pins
$WDPLQLPXPWKHDGGLQERDUGPXVWJURXQGRQHRIWKHWZRPRSNT[1:2]#SLQVWR LQGLFDWHWRWKHPRWKHUERDUGWKDWDERDUGLVSK\VLFDOO\LQWKHFRQQHFWRU7KHVLJQDOOHYHO RIPRSNT1#DQGPRSNT2#LQIRUPWKHPRWKHUERDUGRIWKHSRZHUUHTXLUHPHQWVRIWKH DGGLQERDUG7KHDGGLQERDUGPD\VLPSO\WLHPRSNT1#DQGRUPRSNT2#WRJURXQG WRVLJQDOWKHDSSURSULDWHSRZHUUHTXLUHPHQWVRIWKHERDUG 5HIHUWR6HFWLRQIRU GHWDLOV 7KHPRWKHUERDUGSURYLGHVSXOOXSVRQWKHVHVLJQDOVWRLQGLFDWHZKHQQRERDUG LVFXUUHQWO\SUHVHQW CLKRUN# in, o/d, Clock running is an optional signal used as an input for a s/t/s device to determine the status of CLK and an open drain output used by the device to request starting or speeding up CLK. CLKRUN# is a sustained tri-state signal used by the central resource to request permission to stop or slow CLK. The central resource is responsible for maintaining CLKRUN# in the asserted state when CLK is running and deasserts CLKRUN# to request permission to stop or slow CLK. The central resource must provide the pullup for CLKRUN#.
Implementation Note: CLKRUN#
CLKRUN#LVDQRSWLRQDOVLJQDOXVHGLQWKH3&,PRELOHHQYLURQPHQWDQGQRWGHILQHGIRU WKHFRQQHFWRU'HWDLOVRIWKHCLKRUN#SURWRFRODQGRWKHUPRELOHGHVLJQ FRQVLGHUDWLRQVDUHGLVFXVVHGLQWKH3&,0RELOH'HVLJQ*XLGH
15 Revision 2.2
M66EN in The 66MHZ_ENABLE pin indicates to a device whether the bus segment is operating at 66 or 33 MHz. Refer to Section 7.5.1. for details of this signal's operation. PME# o/d The Power Management Event signal is an optional signal that can be used by a device to request a change in the device or system power state. The assertion and deassertion of PME# is asynchronous to CLK. This signal has additional electrical requirements over and above standard open drain signals that allow it to be shared between devices which are powered off and those which are powered on. In general, this signal is bused between all PCI connectors in a system, although certain implementations may choose to pass separate buffered copies of the signal to the system logic. Devices must be enabled by software before asserting this signal. Once asserted, the device must continue to drive the signal low until software explicitly clears the condition in the device. The use of this pin is specified in the PCI Bus Power Management Interface Specification. The system vendor must provide a pull-up on this signal, if it allows the signal to be used. System vendors that do not use this signal are not required to bus it between connectors or provide pull- ups on those pins. 3.3Vaux in An optional 3.3 volt auxiliary power source delivers power to the PCI add-in card for generation of power management events when the main power to the card has been turned off by software. The use of this pin is specified in the PCI Bus Power Management Interface Specification. A system or add-in card that does not support PCI bus power management must treat the 3.3Vaux pin as reserved.
Implementation Note: PME# and 3.3Vaux
PME# DQG3.3VauxDUHRSWLRQDOVLJQDOVGHILQHGE\WKH3&,%XV3RZHU0DQDJHPHQW ,QWHUIDFH6SHFLILFDWLRQ'HWDLOVRIWKHVHVLJQDOVFDQEHIRXQGLQWKDWGRFXPHQW
16 Revision 2.2
2.2.8. 64-Bit Bus Extension Pins (Optional)
7KHELWH[WHQVLRQSLQVDUHFROOHFWLYHO\RSWLRQDO7KDWLVLIWKHELWH[WHQVLRQLV XVHGDOOWKHSLQVLQWKLVVHFWLRQDUHUHTXLUHG AD[63::32] t/s Address and Data are multiplexed on the same pins and provide 32 additional bits. During an address phase (when using the DAC command and when REQ64# is asserted), the upper 32-bits of a 64-bit address are transferred; otherwise, these bits are reserved7 but are stable and indeterminate. During a data phase, an additional 32-bits of data are transferred when a 64-bit transaction has been negotiated by the assertion of REQ64# and ACK64#. C/BE[7::4]# t/s Bus Command and Byte Enables are multiplexed on the same pins. During an address phase (when using the DAC command and when REQ64# is asserted), the actual bus command is transferred on C/BE[7::4]#; otherwise, these bits are reserved and indeterminate. During a data phase, C/BE[7::4]# are Byte Enables indicating which byte lanes carry meaningful data when a 64-bit transaction has been negotiated by the assertion of REQ64# and ACK64#. C/BE[4]# applies to byte 4 and C/BE[7]# applies to byte 7. REQ64# s/t/s Request 64-bit Transfer, when asserted by the current bus master, indicates it desires to transfer data using 64 bits. REQ64# also has the same timing as FRAME#. REQ64# also has meaning at the end of reset as described in Section 3.8.1. ACK64# s/t/s Acknowledge 64-bit Transfer, when actively driven by the device that has positively decoded its address as the target of the current access, indicates the target is willing to transfer data using 64 bits. ACK64# has the same timing as DEVSEL#. PAR64 t/s Parity Upper DWORD is the even8 parity bit that protects AD[63::32] and C/BE[7::4]#. PAR64 must be valid one clock after each address phase on any transaction in which REQ64# is asserted. PAR64 is stable and valid for 64-bit data phases one clock after either IRDY# is asserted on a write transaction or TRDY# is asserted on a read transaction. (PAR64 has the same timing as AD[63::32] but delayed by one clock.) The master drives PAR64 for address and write data phases; the target drives PAR64 for read data phases.
7 Reserved means reserved for future use by the PCI SIG Steering Committee. Reserved bits must not be used by any device. 8 The number of “1”s on AD[63::32], C/BE[7::4]#, and PAR64 equals an even number.
17 Revision 2.2
2.2.9. JTAG/Boundary Scan Pins (Optional)
7KH,(((6WDQGDUG 7HVW$FFHVV3RUWDQG%RXQGDU\6FDQ$UFKLWHFWXUHLV LQFOXGHGDVDQRSWLRQDOLQWHUIDFHIRU3&,GHYLFHV,(((6WDQGDUG VSHFLILHVWKH UXOHVDQGSHUPLVVLRQVIRUGHVLJQLQJDQ FRPSOLDQW,&,QFOXVLRQRID7HVW$FFHVV 3RUW 7$3 RQDGHYLFHDOORZVERXQGDU\VFDQWREHXVHGIRUWHVWLQJRIWKHGHYLFHDQGWKH ERDUGRQZKLFKLWLVLQVWDOOHG7KH7$3LVFRPSULVHGRIIRXUSLQV RSWLRQDOO\ILYH WKDW DUHXVHGWRLQWHUIDFHVHULDOO\ZLWKD7$3FRQWUROOHUZLWKLQWKH3&,GHYLFH TCK in Test Clock is used to clock state information and test data into and out of the device during operation of the TAP. TDI in Test Data Input is used to serially shift test data and test instructions into the device during TAP operation. TDO out Test Output is used to serially shift test data and test instructions out of the device during TAP operation. TMS in Test Mode Select is used to control the state of the TAP controller in the device. TRST# in Test Reset provides an asynchronous initialization of the TAP controller. This signal is optional in IEEE Standard 1149.1. 7KHVH7$3SLQVRSHUDWHLQWKHVDPHHOHFWULFDOHQYLURQPHQW 9RU9 DVWKH,2 EXIIHUVRIWKHGHYLFH V3&,LQWHUIDFH7KHGULYHVWUHQJWKRIWKHTDOSLQLVQRWUHTXLUHG WREHWKHVDPHDVVWDQGDUG3&,EXVSLQVTDOGULYHVWUHQJWKVKRXOGEHVSHFLILHGLQWKH GHYLFH VGDWDVKHHW 7KHV\VWHPYHQGRULVUHVSRQVLEOHIRUWKHGHVLJQDQGRSHUDWLRQRIWKH VHULDOFKDLQV ULQJV UHTXLUHGLQWKHV\VWHP7KHVLJQDOVDUHVXSSOHPHQWDU\WRWKH3&,EXVDQGDUH QRWRSHUDWHGLQDPXOWLGURSIDVKLRQ7\SLFDOO\DQ ULQJLVFUHDWHGE\FRQQHFWLQJ RQHGHYLFH VTDOSLQWRDQRWKHUGHYLFH VTDISLQWRFUHDWHDVHULDOFKDLQRIGHYLFHV,Q WKLVDSSOLFDWLRQWKH,& VUHFHLYHWKHVDPHTCKTMSDQGRSWLRQDOTRST#VLJQDOV7KH HQWLUH ULQJ RUULQJV LV DUH FRQQHFWHGHLWKHUWRDPRWKHUERDUGWHVWFRQQHFWRUIRU WHVWSXUSRVHVRUWRDUHVLGHQW &RQWUROOHU,& 7KH3&,VSHFLILFDWLRQVXSSRUWVH[SDQVLRQERDUGVZLWKDFRQQHFWRUWKDWLQFOXGHV %RXQGDU\6FDQVLJQDOV0HWKRGVRIFRQQHFWLQJDQGXVLQJWKH WHVWULQJVLQD V\VWHPZLWKH[SDQVLRQERDUGVLQFOXGH • 2QO\XVHWKH ULQJRQWKHH[SDQVLRQERDUGGXULQJPDQXIDFWXULQJWHVWRIWKH H[SDQVLRQERDUG,QWKLVFDVHWKH ULQJRQWKHPRWKHUERDUGZRXOGQRWEH FRQQHFWHGWRWKH VLJQDOVIRUWKHH[SDQVLRQERDUGV7KHPRWKHUERDUGZRXOG EHWHVWHGE\LWVHOIGXULQJPDQXIDFWXULQJ • )RUHDFKH[SDQVLRQERDUGFRQQHFWRULQDV\VWHPFUHDWHDVHSDUDWH ULQJRQWKH PRWKHUERDUG)RUH[DPSOHZLWKWZRH[SDQVLRQERDUGFRQQHFWRUVWKHUHZRXOGEH WKUHH ULQJVRQWKHPRWKHUERDUG • 8WLOL]HDQ,&WKDWDOORZVIRUKLHUDUFKLFDO PXOWLGURSDGGUHVVDELOLW\7KHVH ,& VZRXOGEHDEOHWRKDQGOHWKHPXOWLSOH ULQJVDQGDOORZPXOWLGURS DGGUHVVDELOLW\DQGRSHUDWLRQ ([SDQVLRQERDUGVWKDWGRQRWVXSSRUWWKH,(((6WDQGDUG LQWHUIDFHPXVWKDUGZLUH WKHERDUG VTDISLQWRLWVTDOSLQ
18 Revision 2.2
2.3. Sideband Signals 3&,SURYLGHVDOOEDVLFWUDQVIHUPHFKDQLVPVH[SHFWHGRIDJHQHUDOSXUSRVHPXOWLPDVWHU ,2EXV+RZHYHULWGRHVQRWSUHFOXGHWKHRSSRUWXQLW\IRUSURGXFWVSHFLILF IXQFWLRQSHUIRUPDQFHHQKDQFHPHQWVYLDVLGHEDQGVLJQDOV$VLGHEDQGVLJQDOLVORRVHO\ GHILQHGDVDQ\VLJQDOQRWSDUWRIWKH3&,VSHFLILFDWLRQWKDWFRQQHFWVWZRRUPRUH3&, FRPSOLDQWDJHQWVDQGKDVPHDQLQJRQO\WRWKHVHDJHQWV6LGHEDQGVLJQDOVDUHSHUPLWWHG IRUWZRRUPRUHGHYLFHVWRFRPPXQLFDWHVRPHDVSHFWRIWKHLUGHYLFHVSHFLILFVWDWHLQ RUGHUWRLPSURYHWKHRYHUDOOHIIHFWLYHQHVVRI3&,XWLOL]DWLRQRUV\VWHPRSHUDWLRQ 1RSLQVDUHDOORZHGLQWKH3&,FRQQHFWRUIRUVLGHEDQGVLJQDOV7KHUHIRUHVLGHEDQG VLJQDOVPXVWEHOLPLWHGWRWKHSODQDUHQYLURQPHQW)XUWKHUPRUHVLGHEDQGVLJQDOVPD\ QHYHUYLRODWHWKHVSHFLILHGSURWRFRORQGHILQHG3&,VLJQDOVRUFDXVHWKHVSHFLILHG SURWRFROWREHYLRODWHG
2.4. Central Resource Functions 7KURXJKRXWWKLVVSHFLILFDWLRQWKHWHUPFHQWUDOUHVRXUFHLVXVHGWRGHVFULEHEXVVXSSRUW IXQFWLRQVVXSSOLHGE\WKHKRVWV\VWHPW\SLFDOO\LQD3&,FRPSOLDQWEULGJHRUVWDQGDUG FKLSVHW7KHVHIXQFWLRQVLQFOXGHEXWDUHQRWOLPLWHGWRWKHIROORZLQJ • &HQWUDO$UELWUDWLRQ REQ#LVDQLQSXWDQGGNT#LVDQRXWSXW • 5HTXLUHGVLJQDOSXOOXSVDVGHVFULEHGLQ6HFWLRQDQGNHHSHUVDVGHVFULEHGLQ 6HFWLRQ • 6XEWUDFWLYH'HFRGH2QO\RQHDJHQWRQD3&,EXVFDQXVHVXEWUDFWLYHGHFRGHDQG ZRXOGW\SLFDOO\EHDEULGJHWRDVWDQGDUGH[SDQVLRQEXV UHIHUWR6HFWLRQ • &RQYHUWSURFHVVRUWUDQVDFWLRQLQWRDFRQILJXUDWLRQWUDQVDFWLRQ • *HQHUDWLRQRIWKHLQGLYLGXDOIDSELVLJQDOVWRHDFKGHYLFHIRUV\VWHPFRQILJXUDWLRQ • 'ULYLQJREQ64#GXULQJUHVHW
19 Revision 2.2
20 Revision 2.2
Chapter 3 Bus Operation
3.1. Bus Commands %XVFRPPDQGVLQGLFDWHWRWKHWDUJHWWKHW\SHRIWUDQVDFWLRQWKHPDVWHULVUHTXHVWLQJ%XV FRPPDQGVDUHHQFRGHGRQWKHC/BE[3::0]#OLQHVGXULQJWKHDGGUHVVSKDVH
3.1.1. Command Definition
3&,EXVFRPPDQGHQFRGLQJVDQGW\SHVDUHOLVWHGEHORZIROORZHGE\DEULHIGHVFULSWLRQ RIHDFK1RWH 7KHFRPPDQGHQFRGLQJVDUHDVYLHZHGRQWKHEXVZKHUHDLQGLFDWHV DKLJKYROWDJHDQGLVDORZYROWDJH%\WHHQDEOHVDUHDVVHUWHGZKHQ
C/BE[3::0]# Command Type 0000 Interrupt Acknowledge 0001 Special Cycle 0010 I/O Read 0011 I/O Write 0100 Reserved 0101 Reserved 0110 Memory Read 0111 Memory Write 1000 Reserved 1001 Reserved 1010 Configuration Read 1011 Configuration Write 1100 Memory Read Multiple 1101 Dual Address Cycle 1110 Memory Read Line 1111 Memory Write and Invalidate
7KH,QWHUUXSW$FNQRZOHGJHFRPPDQGLVDUHDGLPSOLFLWO\DGGUHVVHGWRWKHV\VWHP LQWHUUXSWFRQWUROOHU7KHDGGUHVVELWVDUHORJLFDOGRQ WFDUHVGXULQJWKHDGGUHVVSKDVHDQG WKHE\WHHQDEOHVLQGLFDWHWKHVL]HRIWKHYHFWRUWREHUHWXUQHG
21 Revision 2.2
7KH6SHFLDO&\FOHFRPPDQGSURYLGHVDVLPSOHPHVVDJHEURDGFDVWPHFKDQLVPRQ3&,,W LVGHVLJQHGWREHXVHGDVDQDOWHUQDWLYHWRSK\VLFDOVLJQDOVZKHQVLGHEDQG FRPPXQLFDWLRQLVQHFHVVDU\7KLVPHFKDQLVPLVIXOO\GHVFULEHGLQ6HFWLRQ 7KH,25HDGFRPPDQGLVXVHGWRUHDGGDWDIURPDQDJHQWPDSSHGLQ,2$GGUHVV6SDFH AD[31::00]SURYLGHDE\WHDGGUHVV$OOELWVPXVWEHGHFRGHG7KHE\WHHQDEOHV LQGLFDWHWKHVL]HRIWKHWUDQVIHUDQGPXVWEHFRQVLVWHQWZLWKWKHE\WHDGGUHVV 7KH,2:ULWHFRPPDQGLVXVHGWRZULWHGDWDWRDQDJHQWPDSSHGLQ,2$GGUHVV6SDFH $OOELWVPXVWEHGHFRGHG7KHE\WHHQDEOHVLQGLFDWHWKHVL]HRIWKHWUDQVIHUDQGPXVW EHFRQVLVWHQWZLWKWKHE\WHDGGUHVV 5HVHUYHGFRPPDQGHQFRGLQJVDUHUHVHUYHGIRUIXWXUHXVH3&,WDUJHWVPXVWQRWDOLDV UHVHUYHGFRPPDQGVZLWKRWKHUFRPPDQGV7DUJHWVPXVWQRWUHVSRQGWRUHVHUYHG HQFRGLQJV,IDUHVHUYHGHQFRGLQJLVXVHGRQWKHLQWHUIDFHWKHDFFHVVW\SLFDOO\ZLOOEH WHUPLQDWHGZLWK0DVWHU$ERUW 7KH0HPRU\5HDGFRPPDQGLVXVHGWRUHDGGDWDIURPDQDJHQWPDSSHGLQWKH0HPRU\ $GGUHVV6SDFH7KHWDUJHWLVIUHHWRGRDQDQWLFLSDWRU\UHDGIRUWKLVFRPPDQGRQO\LILW FDQJXDUDQWHHWKDWVXFKDUHDGZLOOKDYHQRVLGHHIIHFWV)XUWKHUPRUHWKHWDUJHWPXVW HQVXUHWKHFRKHUHQF\ ZKLFKLQFOXGHVRUGHULQJ RIDQ\GDWDUHWDLQHGLQWHPSRUDU\EXIIHUV DIWHUWKLV3&,WUDQVDFWLRQLVFRPSOHWHG6XFKEXIIHUVPXVWEHLQYDOLGDWHGEHIRUHDQ\ V\QFKURQL]DWLRQHYHQWV HJXSGDWLQJDQ,2VWDWXVUHJLVWHURUPHPRU\IODJ DUHSDVVHG WKURXJKWKLVDFFHVVSDWK 7KH0HPRU\:ULWHFRPPDQGLVXVHGWRZULWHGDWDWRDQDJHQWPDSSHGLQWKH0HPRU\ $GGUHVV6SDFH:KHQWKHWDUJHWUHWXUQVUHDG\LWKDVDVVXPHGUHVSRQVLELOLW\IRUWKH FRKHUHQF\ ZKLFKLQFOXGHVRUGHULQJ RIWKHVXEMHFWGDWD7KLVFDQEHGRQHHLWKHUE\ LPSOHPHQWLQJWKLVFRPPDQGLQDIXOO\V\QFKURQRXVPDQQHURUE\LQVXULQJDQ\VRIWZDUH WUDQVSDUHQWSRVWLQJEXIIHUZLOOEHIOXVKHGEHIRUHV\QFKURQL]DWLRQHYHQWV HJXSGDWLQJ DQ,2VWDWXVUHJLVWHURUPHPRU\IODJ DUHSDVVHGWKURXJKWKLVDFFHVVSDWK7KLVLPSOLHV WKDWWKHPDVWHULVIUHHWRFUHDWHDV\QFKURQL]DWLRQHYHQWLPPHGLDWHO\DIWHUXVLQJWKLV FRPPDQG 7KH&RQILJXUDWLRQ5HDGFRPPDQGLVXVHGWRUHDGWKH&RQILJXUDWLRQ6SDFHRIHDFKDJHQW $QDJHQWLVVHOHFWHGGXULQJDFRQILJXUDWLRQDFFHVVZKHQLWVIDSELVLJQDOLVDVVHUWHGDQG AD[1::0]DUH'XULQJWKHDGGUHVVSKDVHRIDFRQILJXUDWLRQWUDQVDFWLRQAD[7::2] DGGUHVVRQHRIWKH':25'UHJLVWHUV ZKHUHE\WHHQDEOHVDGGUHVVWKHE\WH V ZLWKLQ HDFK':25' LQ&RQILJXUDWLRQ6SDFHRIHDFKGHYLFHDQGAD[31::11]DUHORJLFDOGRQ W FDUHVWRWKHVHOHFWHGDJHQW UHIHUWR6HFWLRQ AD[10::08]LQGLFDWHZKLFKGHYLFH RIDPXOWLIXQFWLRQDJHQWLVEHLQJDGGUHVVHG 7KH&RQILJXUDWLRQ:ULWHFRPPDQGLVXVHGWRWUDQVIHUGDWDWRWKH&RQILJXUDWLRQ6SDFHRI HDFKDJHQW$GGUHVVLQJIRUFRQILJXUDWLRQZULWHWUDQVDFWLRQVLVWKHVDPHDVIRU FRQILJXUDWLRQUHDGWUDQVDFWLRQV 7KH0HPRU\5HDG0XOWLSOHFRPPDQGLVVHPDQWLFDOO\LGHQWLFDOWRWKH0HPRU\5HDG FRPPDQGH[FHSWWKDWLWDGGLWLRQDOO\LQGLFDWHVWKDWWKHPDVWHUPD\LQWHQGWRIHWFKPRUH WKDQRQHFDFKHOLQHEHIRUHGLVFRQQHFWLQJ7KHPHPRU\FRQWUROOHUFRQWLQXHVSLSHOLQLQJ PHPRU\UHTXHVWVDVORQJDVFRAME#LVDVVHUWHG7KLVFRPPDQGLVLQWHQGHGWREHXVHG ZLWKEXONVHTXHQWLDOGDWDWUDQVIHUVZKHUHWKHPHPRU\V\VWHP DQGWKHUHTXHVWLQJPDVWHU PLJKWJDLQVRPHSHUIRUPDQFHDGYDQWDJHE\VHTXHQWLDOO\UHDGLQJDKHDGRQHRUPRUH DGGLWLRQDOFDFKHOLQH V ZKHQDVRIWZDUHWUDQVSDUHQWEXIIHULVDYDLODEOHIRUWHPSRUDU\ VWRUDJH 7KH'XDO$GGUHVV&\FOH '$& FRPPDQGLVXVHGWRWUDQVIHUDELWDGGUHVVWRGHYLFHV WKDWVXSSRUWELWDGGUHVVLQJZKHQWKHDGGUHVVLVQRWLQWKHORZ*%DGGUHVVVSDFH
22 Revision 2.2
7DUJHWVWKDWVXSSRUWRQO\ELWDGGUHVVHVPXVWWUHDWWKLVFRPPDQGDVUHVHUYHGDQGQRW UHVSRQGWRWKHFXUUHQWWUDQVDFWLRQLQDQ\ZD\ 7KH0HPRU\5HDG/LQHFRPPDQGLVVHPDQWLFDOO\LGHQWLFDOWRWKH0HPRU\5HDG FRPPDQGH[FHSWWKDWLWDGGLWLRQDOO\LQGLFDWHVWKDWWKHPDVWHULQWHQGVWRIHWFKDFRPSOHWH FDFKHOLQH7KLVFRPPDQGLVLQWHQGHGWREHXVHGZLWKEXONVHTXHQWLDOGDWDWUDQVIHUV ZKHUHWKHPHPRU\V\VWHP DQGWKHUHTXHVWLQJPDVWHU PLJKWJDLQVRPHSHUIRUPDQFH DGYDQWDJHE\UHDGLQJXSWRDFDFKHOLQHERXQGDU\LQUHVSRQVHWRWKHUHTXHVWUDWKHUWKDQD VLQJOHPHPRU\F\FOH$VZLWKWKH0HPRU\5HDGFRPPDQGSUHIHWFKHGEXIIHUVPXVWEH LQYDOLGDWHGEHIRUHDQ\V\QFKURQL]DWLRQHYHQWVDUHSDVVHGWKURXJKWKLVDFFHVVSDWK 7KH0HPRU\:ULWHDQG,QYDOLGDWHFRPPDQGLVVHPDQWLFDOO\LGHQWLFDOWRWKH0HPRU\ :ULWHFRPPDQGH[FHSWWKDWLWDGGLWLRQDOO\JXDUDQWHHVDPLQLPXPWUDQVIHURIRQH FRPSOHWHFDFKHOLQH LHWKHPDVWHULQWHQGVWRZULWHDOOE\WHVZLWKLQWKHDGGUHVVHG FDFKHOLQHLQDVLQJOH3&,WUDQVDFWLRQXQOHVVLQWHUUXSWHGE\WKHWDUJHW1RWH $OOE\WH HQDEOHVPXVWEHDVVHUWHGGXULQJHDFKGDWDSKDVHIRUWKLVFRPPDQG7KHPDVWHUPD\ DOORZWKHWUDQVDFWLRQWRFURVVDFDFKHOLQHERXQGDU\RQO\LILWLQWHQGVWRWUDQVIHUWKHHQWLUH QH[WOLQHDOVR7KLVFRPPDQGUHTXLUHVLPSOHPHQWDWLRQRIDFRQILJXUDWLRQUHJLVWHULQWKH PDVWHULQGLFDWLQJWKHFDFKHOLQHVL]H UHIHUWR6HFWLRQIRUPRUHLQIRUPDWLRQ DQG PD\RQO\EHXVHGZLWK/LQHDU%XUVW2UGHULQJ UHIHUWR6HFWLRQ ,WDOORZVD PHPRU\SHUIRUPDQFHRSWLPL]DWLRQE\LQYDOLGDWLQJDGLUW\OLQHLQDZULWHEDFNFDFKH ZLWKRXWUHTXLULQJWKHDFWXDOZULWHEDFNF\FOHWKXVVKRUWHQLQJDFFHVVWLPH
3.1.2. Command Usage Rules
$OO3&,GHYLFHV H[FHSWKRVWEXVEULGJHV DUHUHTXLUHGWRUHVSRQGDVDWDUJHWWR FRQILJXUDWLRQ UHDGDQGZULWH FRPPDQGV$OORWKHUFRPPDQGVDUHRSWLRQDO $PDVWHUPD\LPSOHPHQWWKHRSWLRQDOFRPPDQGVDVQHHGHG$WDUJHWPD\DOVR LPSOHPHQWWKHRSWLRQDOFRPPDQGVDVQHHGHGEXWLILWLPSOHPHQWVEDVLFPHPRU\ FRPPDQGVLWPXVWVXSSRUWDOOWKHPHPRU\FRPPDQGVLQFOXGLQJ0HPRU\:ULWHDQG ,QYDOLGDWH0HPRU\5HDG/LQHDQG0HPRU\5HDG0XOWLSOH,IQRWIXOO\LPSOHPHQWHG WKHVHSHUIRUPDQFHRSWLPL]LQJFRPPDQGVPXVWEHDOLDVHGWRWKHEDVLFPHPRU\ FRPPDQGV)RUH[DPSOHDWDUJHWPD\QRWLPSOHPHQWWKH0HPRU\5HDG/LQHFRPPDQG KRZHYHULWPXVWDFFHSWWKHUHTXHVW LIWKHDGGUHVVLVGHFRGHGIRUDPHPRU\DFFHVV DQG WUHDWLWDVD0HPRU\5HDGFRPPDQG6LPLODUO\DWDUJHWPD\QRWLPSOHPHQWWKH0HPRU\ :ULWHDQG,QYDOLGDWHFRPPDQGEXWPXVWDFFHSWWKHUHTXHVW LIWKHDGGUHVVLVGHFRGHGIRU DPHPRU\DFFHVV DQGWUHDWLWDVD0HPRU\:ULWHFRPPDQG )RUEORFNGDWDWUDQVIHUVWRIURPV\VWHPPHPRU\0HPRU\:ULWHDQG,QYDOLGDWH0HPRU\ 5HDG/LQHDQG0HPRU\5HDG0XOWLSOHDUHWKHUHFRPPHQGHGFRPPDQGVIRUPDVWHUV FDSDEOHRIVXSSRUWLQJWKHP7KH0HPRU\5HDGRU0HPRU\:ULWHFRPPDQGVFDQEH XVHGLIIRUVRPHUHDVRQWKHPDVWHULVQRWFDSDEOHRIXVLQJWKHSHUIRUPDQFHRSWLPL]LQJ FRPPDQGV)RUPDVWHUVXVLQJWKHPHPRU\UHDGFRPPDQGVDQ\OHQJWKDFFHVVZLOOZRUN IRUDOOFRPPDQGV KRZHYHUWKHSUHIHUUHGXVHLVVKRZQEHORZ :KLOH0HPRU\:ULWHDQG,QYDOLGDWHLVWKHRQO\FRPPDQGWKDWUHTXLUHVLPSOHPHQWDWLRQ RIWKH&DFKHOLQH6L]HUHJLVWHULWLVVWURQJO\VXJJHVWHGWKHPHPRU\UHDGFRPPDQGVXVHLW DVZHOO$EULGJHWKDWSUHIHWFKHVLVUHVSRQVLEOHIRUDQ\ODWHQWGDWDQRWFRQVXPHGE\WKH PDVWHU 0HPRU\FRPPDQGUHFRPPHQGDWLRQVYDU\GHSHQGLQJRQWKHFKDUDFWHULVWLFVRIWKH PHPRU\ORFDWLRQDQGWKHDPRXQWRIGDWDEHLQJUHDG0HPRU\ORFDWLRQVDUHFKDUDFWHUL]HG DVHLWKHUSUHIHWFKDEOHRUQRQSUHIHWFKDEOH3UHIHWFKDEOHPHPRU\KDVWKHIROORZLQJ FKDUDFWHULVWLFV
23 Revision 2.2
• 7KHUHDUHQRVLGHHIIHFWVRIDUHDGRSHUDWLRQ7KHUHDGRSHUDWLRQFDQQRWEH GHVWUXFWLYHWRHLWKHUWKHGDWDRUDQ\RWKHUVWDWHLQIRUPDWLRQ)RUH[DPSOHD),)2 WKDWDGYDQFHVWRWKHQH[WGDWDZKHQUHDGZRXOGQRWEHSUHIHWFKDEOH6LPLODUO\D ORFDWLRQWKDWFOHDUHGDVWDWXVELWZKHQUHDGZRXOGQRWEHSUHIHWFKDEOH • :KHQUHDGWKHGHYLFHLVUHTXLUHGWRUHWXUQDOOE\WHVUHJDUGOHVVRIWKHE\WHHQDEOHV IRXURUHLJKWGHSHQGLQJXSRQWKHZLGWKRIWKHGDWDWUDQVIHU UHIHUWR6HFWLRQ • %ULGJHVDUHSHUPLWWHGWRPHUJHZULWHVLQWRWKLVUDQJH UHIHUWR6HFWLRQ $OORWKHUPHPRU\LVFRQVLGHUHGWREHQRQSUHIHWFKDEOH 7KHSUHIHUUHGXVHRIWKHUHDGFRPPDQGVLV 0HPRU\5HDG :KHQUHDGLQJGDWDLQDQDGGUHVVUDQJHWKDWKDVVLGH HIIHFWV QRWSUHIHWFKDEOH RUUHDGLQJDVLQJOH':25' 0HPRU\5HDG/LQH 5HDGLQJPRUHWKDQD':25'XSWRWKHQH[WFDFKHOLQH ERXQGDU\LQDSUHIHWFKDEOHDGGUHVVVSDFH 0HPRU\5HDG0XOWLSOH 5HDGLQJDEORFNZKLFKFURVVHVDFDFKHOLQHERXQGDU\ VWD\RQHFDFKHOLQHDKHDGRIWKHPDVWHULISRVVLEOH RI GDWDLQDSUHIHWFKDEOHDGGUHVVUDQJH 7KHWDUJHWVKRXOGWUHDWWKHUHDGFRPPDQGVWKHVDPHHYHQWKRXJKWKH\GRQRWDGGUHVVWKH ILUVW':25'RIWKHFDFKHOLQH)RUH[DPSOHDWDUJHWWKDWLVDGGUHVVHGDW':25' LQVWHDGRI':25' VKRXOGRQO\SUHIHWFKWRWKHHQGRIWKHFXUUHQWFDFKHOLQH,IWKH &DFKHOLQH6L]HUHJLVWHULVQRWLPSOHPHQWHGWKHQWKHPDVWHUVKRXOGDVVXPHDFDFKHOLQH VL]HRIHLWKHURUE\WHVDQGXVHWKHUHDGFRPPDQGVUHFRPPHQGHGDERYH 7KLV DVVXPHVOLQHDUEXUVWRUGHULQJ Implementation Note: Using Read Commands 'LIIHUHQWUHDGFRPPDQGVZLOOKDYHGLIIHUHQWDIIHFWVRQV\VWHPSHUIRUPDQFHEHFDXVHKRVW EULGJHVDQG3&,WR3&,EULGJHVPXVWWUHDWWKHFRPPDQGVGLIIHUHQWO\:KHQWKH0HPRU\ 5HDGFRPPDQGLVXVHGDEULGJHZLOOJHQHUDOO\REWDLQRQO\WKHGDWDWKHPDVWHUUHTXHVWHG DQGQRPRUHVLQFHDVLGHHIIHFWPD\H[LVW7KHEULGJHFDQQRWUHDGPRUHEHFDXVHLWGRHV QRWNQRZZKLFKE\WHVDUHUHTXLUHGIRUWKHQH[WGDWDSKDVH7KDWLQIRUPDWLRQLVQRW DYDLODEOHXQWLOWKHFXUUHQWGDWDSKDVHFRPSOHWHV+RZHYHUIRU0HPRU\5HDG/LQHDQG 0HPRU\5HDG0XOWLSOHWKHPDVWHUJXDUDQWHHVWKDWWKHDGGUHVVUDQJHLVSUHIHWFKDEOH DQGWKHUHIRUHWKHEULGJHFDQREWDLQPRUHGDWDWKDQWKHPDVWHUDFWXDOO\UHTXHVWHG7KLV SURFHVVLQFUHDVHVV\VWHPSHUIRUPDQFHZKHQWKHEULGJHFDQSUHIHWFKDQGWKHPDVWHU UHTXLUHVPRUHWKDQDVLQJOH':25' 5HIHUWRWKH3&,3&,%ULGJH$UFKLWHFWXUH 6SHFLILFDWLRQIRUDGGLWLRQDOGHWDLOVDQGVSHFLDOFDVHV $VDQH[DPSOHVXSSRVHDPDVWHUQHHGHGWRUHDGWKUHH':25'VIURPDWDUJHWRQWKH RWKHUVLGHRID3&,WR3&,EULGJH,IWKHPDVWHUXVHGWKH0HPRU\5HDGFRPPDQGWKH EULGJHFRXOGQRWEHJLQUHDGLQJWKHVHFRQG':25'IURPWKHWDUJHWEHFDXVHLWGRHVQRW KDYHWKHQH[WVHWRIE\WHHQDEOHVDQGWKHUHIRUHZLOOWHUPLQDWHWKHWUDQVDFWLRQDIWHUD VLQJOHGDWDWUDQVIHU,IKRZHYHUWKHPDVWHUXVHGWKH0HPRU\5HDG/LQHFRPPDQGWKH EULGJHZRXOGEHIUHHWREXUVWGDWDIURPWKHWDUJHWWKURXJKWKHHQGRIWKHFDFKHOLQH DOORZLQJWKHGDWDWRIORZWRWKHPDVWHUPRUHTXLFNO\ 7KH0HPRU\5HDG0XOWLSOHFRPPDQGDOORZVEULGJHVWRSUHIHWFKGDWDIDUWKHUDKHDGRI WKHPDVWHUWKHUHE\LQFUHDVLQJWKHFKDQFHVWKDWDEXUVWWUDQVIHUFDQEHVXVWDLQHG
24 Revision 2.2
,WLVKLJKO\UHFRPPHQGHGWKDWWKH&DFKHOLQH6L]HUHJLVWHUEHLPSOHPHQWHGWRHQVXUH FRUUHFWXVHRIWKHUHDGFRPPDQGV7KH&DFKHOLQH6L]HUHJLVWHUPXVWEHLPSOHPHQWHG ZKHQXVLQJWKHRSWLRQDO&DFKHOLQH:UDSPRGHEXUVWRUGHULQJ 8VLQJWKHFRUUHFWUHDGFRPPDQGJLYHVRSWLPDOSHUIRUPDQFH,IKRZHYHUQRWDOOUHDG FRPPDQGVDUHLPSOHPHQWHGWKHQFKRRVHWKHRQHVZKLFKZRUNWKHEHVWPRVWRIWKHWLPH )RUH[DPSOHLIWKHODUJHPDMRULW\RIDFFHVVHVE\WKHPDVWHUUHDGHQWLUHFDFKHOLQHVDQG RQO\DVPDOOQXPEHURIDFFHVVHVUHDGPRUHWKDQDFDFKHOLQHLWZRXOGEHUHDVRQDEOHIRU WKHGHYLFHWRRQO\XVHWKH0HPRU\5HDG/LQHFRPPDQGIRUERWKW\SHVRIDFFHVVHV
$EULGJHWKDWSUHIHWFKHVLVUHVSRQVLEOHIRUDQ\ODWHQWGDWDQRWFRQVXPHGE\WKHPDVWHU 7KHVLPSOHVWZD\IRUWKHEULGJHWRFRUUHFWO\KDQGOHODWHQWGDWDLVWRVLPSO\PDUNLW LQYDOLGDWWKHHQGRIWKHFXUUHQWWUDQVDFWLRQ Implementation Note: Stale-Data Problems Caused By Not Discarding Prefetch Data 6XSSRVHD&38KDVWZREXIIHUVLQDGMDFHQWPDLQPHPRU\ORFDWLRQV7KH&38SUHSDUHVD PHVVDJHIRUDEXVPDVWHULQWKHILUVWEXIIHUDQGWKHQVLJQDOVWKHEXVPDVWHUWRSLFNXSWKH PHVVDJH:KHQWKHEXVPDVWHUUHDGVLWVPHVVDJHDEULGJHEHWZHHQWKHEXVPDVWHUDQG PDLQPHPRU\SUHIHWFKHVVXEVHTXHQWDGGUHVVHVLQFOXGLQJWKHVHFRQGEXIIHUORFDWLRQ 6RPHWLPHODWHUWKH&38SUHSDUHVDVHFRQGPHVVDJHXVLQJWKHVHFRQGEXIIHULQPDLQ PHPRU\DQGVLJQDOVWKHEXVPDVWHUWRFRPHDQGJHWLW,IWKHLQWHUYHQLQJEULGJHKDVQRW IOXVKHGWKHEDODQFHRIWKHSUHYLRXVSUHIHWFKWKHQZKHQWKHPDVWHUDWWHPSWVWRUHDGWKH VHFRQGEXIIHUWKHEULGJHPD\GHOLYHUVWDOHGDWD 6LPLODUO\LIDGHYLFHZHUHWRSROODPHPRU\ORFDWLRQEHKLQGDEULGJHWKHGHYLFHZRXOG QHYHUREVHUYHDQHZYDOXHRIWKHORFDWLRQLIWKHEULGJHGLGQRWIOXVKWKHEXIIHUDIWHUHDFK WLPHWKHGHYLFHUHDGLW
25 Revision 2.2
3.2. PCI Protocol Fundamentals 7KHEDVLFEXVWUDQVIHUPHFKDQLVPRQ3&,LVDEXUVW$EXUVWLVFRPSRVHGRIDQDGGUHVV SKDVHDQGRQHRUPRUHGDWDSKDVHV3&,VXSSRUWVEXUVWVLQERWK0HPRU\DQG,2 $GGUHVV6SDFHV $OOVLJQDOVDUHVDPSOHGRQWKHULVLQJHGJHRIWKHFORFN (DFKVLJQDOKDVDVHWXSDQG KROGDSHUWXUHZLWKUHVSHFWWRWKHULVLQJFORFNHGJHLQZKLFKWUDQVLWLRQVDUHQRWDOORZHG 2XWVLGHWKLVDSHUWXUHVLJQDOYDOXHVRUWUDQVLWLRQVKDYHQRVLJQLILFDQFH7KLVDSHUWXUH RFFXUVRQO\RQTXDOLILHGULVLQJFORFNHGJHVIRUAD[31::00]AD[63::32]PAR PAR64DQGIDSELVLJQDOV DQGRQHYHU\ULVLQJFORFNHGJHIRULOCK#, IRDY# TRDY#FRAME#DEVSEL#STOP#REQ#GNT#REQ64#ACK64#SERR# RQWKHIDOOLQJHGJHRISERR#RQO\ DQGPERR#C/BE[3::0]#C/BE[7::4]# DVEXV FRPPDQGV DUHTXDOLILHGRQWKHFORFNHGJHWKDWFRAME#LVILUVWDVVHUWHG C/BE[3::0]#C/BE[7::4]# DVE\WHHQDEOHV DUHTXDOLILHGRQHDFKULVLQJFORFNHGJH IROORZLQJWKHFRPSOHWLRQRIDQDGGUHVVSKDVHRUGDWDSKDVHDQGUHPDLQYDOLGWKHHQWLUH GDWDSKDVHRST#INTA#INTB#INTC#DQGINTD#DUHQRWTXDOLILHGQRU V\QFKURQRXV
3.2.1. Basic Transfer Control
7KHIXQGDPHQWDOVRIDOO3&,GDWDWUDQVIHUVDUHFRQWUROOHGZLWKWKUHHVLJQDOV VHH )LJXUH FRAME# is driven by the master to indicate the beginning and end of a transaction. IRDY# is driven by the master to indicate that it is ready to transfer data. TRDY# is driven by the target to indicate that it is ready to transfer data.
7KHLQWHUIDFHLVLQWKH,GOHVWDWHZKHQERWKFRAME#DQGIRDY#DUHGHDVVHUWHG7KH ILUVWFORFNHGJHRQZKLFKFRAME#LVDVVHUWHGLVWKHDGGUHVVSKDVHDQGWKHDGGUHVVDQG EXVFRPPDQGFRGHDUHWUDQVIHUUHGRQWKDWFORFNHGJH7KHQH[W FORFNHGJHEHJLQVWKH ILUVWRIRQHRUPRUHGDWDSKDVHVGXULQJZKLFKGDWDLVWUDQVIHUUHGEHWZHHQPDVWHUDQG WDUJHWRQHDFKFORFNHGJHIRUZKLFKERWKIRDY#DQGTRDY#DUHDVVHUWHG:DLWF\FOHV PD\EHLQVHUWHGLQDGDWDSKDVHE\HLWKHUWKHPDVWHURUWKHWDUJHWZKHQIRDY# RU TRDY#LVGHDVVHUWHG 7KHVRXUFHRIWKHGDWDLVUHTXLUHGWRDVVHUWLWV[RDY#VLJQDOXQFRQGLWLRQDOO\ZKHQGDWD LVYDOLG IRDY#RQDZULWHWUDQVDFWLRQTRDY#RQDUHDGWUDQVDFWLRQ 7KHUHFHLYLQJ DJHQWPD\GHOD\WKHDVVHUWLRQRILWV[RDY#ZKHQLWLVQRWUHDG\WRDFFHSWGDWD:KHQ GHOD\LQJWKHDVVHUWLRQRILWV[RDY#WKHWDUJHWDQGPDVWHUPXVWPHHWWKHODWHQF\ UHTXLUHPHQWVVSHFLILHGLQ6HFWLRQVDQG,QDOOFDVHVGDWDLVRQO\ WUDQVIHUUHGZKHQIRDY#DQGTRDY#DUHERWKDVVHUWHGRQWKHVDPHULVLQJFORFNHGJH
9 The only exceptions are 567,17$,17%,17& and ,17'which are discussed in Sections 2.2.1. and 2.2.6.
10 3$5 and 3$5 are treated like an $' line delayed by one clock. 11 The notion of qualifying $' and ,'6(/ signals is fully defined in Section 3.6.3. 12 Note: The address phase consists of two clocks when the command is the Dual Address Cycle (DAC).
26 Revision 2.2
2QFHDPDVWHUKDVDVVHUWHGIRDY#LWFDQQRWFKDQJHIRDY#RUFRAME#XQWLOWKH FXUUHQWGDWDSKDVHFRPSOHWHVUHJDUGOHVVRIWKHVWDWHRITRDY#2QFHDWDUJHWKDV DVVHUWHGTRDY#RUSTOP#LWFDQQRWFKDQJHDEVSEL#TRDY#RUSTOP#XQWLOWKH FXUUHQWGDWDSKDVHFRPSOHWHV1HLWKHUWKHPDVWHUQRUWKHWDUJHWFDQFKDQJHLWVPLQGRQFH LWKDVFRPPLWWHGWRWKHFXUUHQWGDWDWUDQVIHUXQWLOWKHFXUUHQWGDWDSKDVHFRPSOHWHV $ GDWDSKDVHFRPSOHWHVZKHQIRDY#DQG>TRDY#RUSTOP#@DUHDVVHUWHG 'DWDPD\RU PD\QRWWUDQVIHUGHSHQGLQJRQWKHVWDWHRITRDY# $WVXFKWLPHDVWKHPDVWHULQWHQGVWRFRPSOHWHRQO\RQHPRUHGDWDWUDQVIHU ZKLFKFRXOG EHLPPHGLDWHO\DIWHUWKHDGGUHVVSKDVH FRAME#LVGHDVVHUWHGDQGIRDY#LVDVVHUWHG LQGLFDWLQJWKHPDVWHULVUHDG\$IWHUWKHWDUJHWLQGLFDWHVWKDWLWLVUHDG\WRFRPSOHWHWKH ILQDOGDWDWUDQVIHU TRDY#LVDVVHUWHG WKHLQWHUIDFHUHWXUQVWRWKH,GOHVWDWHZLWKERWK FRAME#DQGIRDY#GHDVVHUWHG
3.2.2. Addressing
3&,GHILQHVWKUHHSK\VLFDODGGUHVVVSDFHV7KH0HPRU\DQG,2$GGUHVV6SDFHVDUH FXVWRPDU\7KH&RQILJXUDWLRQ$GGUHVV6SDFHKDVEHHQGHILQHGWRVXSSRUW3&,KDUGZDUH FRQILJXUDWLRQ$FFHVVHVWRWKLVVSDFHDUHIXUWKHUGHVFULEHGLQ6HFWLRQ 3&,WDUJHWV H[FHSWKRVWEXVEULGJHV DUHUHTXLUHGWRLPSOHPHQW%DVH$GGUHVVUHJLVWHU V WRUHTXHVWDUDQJHRIDGGUHVVHVZKLFKFDQEHXVHGWRSURYLGHDFFHVVWRLQWHUQDOUHJLVWHUV RUIXQFWLRQV UHIHUWR&KDSWHUIRUPRUHGHWDLOV 7KHFRQILJXUDWLRQVRIWZDUHXVHVWKH %DVH$GGUHVVUHJLVWHUWRGHWHUPLQHKRZPXFKVSDFHDGHYLFHUHTXLUHVLQDJLYHQDGGUHVV VSDFHDQGWKHQDVVLJQV LISRVVLEOH ZKHUHLQWKDWVSDFHWKHGHYLFHZLOOUHVLGH Implementation Note: Device Address Space ,WLVKLJKO\UHFRPPHQGHGWKDWDGHYLFHUHTXHVW YLD%DVH$GGUHVVUHJLVWHU V WKDWLWV LQWHUQDOUHJLVWHUVEHPDSSHGLQWR0HPRU\6SDFHDQGQRW,26SDFH$OWKRXJKWKHXVHRI ,26SDFHLVDOORZHG,26SDFHLVOLPLWHGDQGKLJKO\IUDJPHQWHGLQ3&V\VWHPVDQGZLOO EHFRPHPRUHGLIILFXOWWRDOORFDWHLQWKHIXWXUH5HTXHVWLQJ0HPRU\6SDFHLQVWHDGRI,2 6SDFHDOORZVDGHYLFHWREHXVHGLQDV\VWHPWKDWGRHVQRWVXSSRUW,26SDFH$GHYLFH PD\PDSLWVLQWHUQDOUHJLVWHULQWRERWK0HPRU\6SDFHDQGRSWLRQDOO\,26SDFHE\XVLQJ WZR%DVH$GGUHVVUHJLVWHUVRQHIRU,2DQGWKHRWKHUIRU0HPRU\7KHV\VWHP FRQILJXUDWLRQVRIWZDUHZLOODOORFDWH LISRVVLEOH VSDFHWRHDFK%DVH$GGUHVVUHJLVWHU :KHQWKHDJHQW¶VGHYLFHGULYHULVFDOOHGLWGHWHUPLQHVZKLFKDGGUHVVVSDFHLVWREHXVHG WRDFFHVVWKHGHYLFH,IWKHSUHIHUUHGDFFHVVPHFKDQLVPLV,26SDFHDQGWKH,2%DVH $GGUHVVUHJLVWHUZDVLQLWLDOL]HGWKHQWKHGULYHUZRXOGDFFHVVWKHGHYLFHXVLQJ,2EXV WUDQVDFWLRQVWRWKH,2$GGUHVV6SDFHDVVLJQHG2WKHUZLVHWKHGHYLFHGULYHUZRXOGEH UHTXLUHGWRXVHPHPRU\DFFHVVHVWRWKHDGGUHVVVSDFHGHILQHGE\WKH0HPRU\%DVH $GGUHVVUHJLVWHU1RWH %RWK%DVH$GGUHVVUHJLVWHUVSURYLGHDFFHVVWRWKHVDPH UHJLVWHUVLQWHUQDOO\
:KHQDWUDQVDFWLRQLVLQLWLDWHGRQWKHLQWHUIDFHHDFKSRWHQWLDOWDUJHWFRPSDUHVWKH DGGUHVVZLWKLWV%DVH$GGUHVVUHJLVWHU V WRGHWHUPLQHLILWLVWKHWDUJHWRIWKHFXUUHQW WUDQVDFWLRQ,ILWLVWKHWDUJHWWKHGHYLFHDVVHUWVDEVSEL#WRFODLPWKHDFFHVV)RU PRUHGHWDLOVDERXWDEVSEL#JHQHUDWLRQUHIHUWR6HFWLRQ+RZDWDUJHWFRPSOHWHV DGGUHVVGHFRGHLQHDFKDGGUHVVVSDFHLVGLVFXVVHGLQWKHIROORZLQJVHFWLRQV
27 Revision 2.2
3.2.2.1. I/O Space Decoding
,QWKH,2$GGUHVV6SDFHDOOADOLQHVDUHXVHGWRSURYLGHDIXOOE\WHDGGUHVV7KH PDVWHUWKDWLQLWLDWHVDQ,2WUDQVDFWLRQLVUHTXLUHGWRHQVXUHWKDWAD[1::0]LQGLFDWHWKH OHDVWVLJQLILFDQWYDOLGE\WHIRUWKHWUDQVDFWLRQ 7KHE\WHHQDEOHVLQGLFDWHWKHVL]HRIWKHWUDQVIHUDQGWKHDIIHFWHGE\WHVZLWKLQWKH ':25'DQGPXVWEHFRQVLVWHQWZLWKAD[1::0] 7DEOHLOOXVWUDWHVWKHYDOLG FRPELQDWLRQVIRUAD[1::0]DQGWKHE\WHHQDEOHVIRUWKHLQLWLDOGDWDSKDVH
7DEOH %\WH(QDEOHVDQGAD[1::0](QFRGLQJV
AD[1::0] 6WDUWLQJ%\WH 9DOLGBE#[3:0] &RPELQDWLRQV %\WH [[[RU %\WH [[RU %\WH [RU %\WH RU
1RWHLIBE#[3::0] AD[1::0]FDQKDYHDQ\YDOXH $IXQFWLRQPD\UHVWULFWZKDWW\SHRIDFFHVV HV LWVXSSRUWVLQ,26SDFH)RUH[DPSOHD GHYLFHPD\UHVWULFWLWVGULYHUWRRQO\DFFHVVWKHIXQFWLRQXVLQJE\WHZRUGRU':25' RSHUDWLRQVDQGLVIUHHWRWHUPLQDWHDOORWKHUDFFHVVHVZLWK7DUJHW$ERUW+RZDGHYLFH XVHVAD[1::0]DQGBE#[3::0]WRGHWHUPLQHZKLFKDFFHVVHVYLRODWHLWVDGGUHVVLQJ UHVWULFWLRQVLVLPSOHPHQWDWLRQVSHFLILF $GHYLFH RWKHUWKDQDQH[SDQVLRQEXVEULGJH WKDWFODLPVOHJDF\,2DGGUHVVHVZKHQHYHU LWV,26SDFHHQDEOHELWLVVHW LHZLWKRXWWKHXVHRI%DVH$GGUHVV5HJLVWHUV LVUHIHUUHG WRDVDOHJDF\,2GHYLFH/HJDF\,2GHYLFHVDUHGLVFXVVHGLQ$SSHQGL[*
3.2.2.2. Memory Space Decoding
,QWKH0HPRU\$GGUHVV6SDFHWKHAD[31::02]EXVSURYLGHVD':25'DOLJQHGDGGUHVV AD[1::0]DUHQRWSDUWRIWKHDGGUHVVGHFRGH+RZHYHUAD[1::0]LQGLFDWHWKHRUGHULQ ZKLFKWKHPDVWHULVUHTXHVWLQJWKHGDWDWREHWUDQVIHUUHG
28 Revision 2.2
7DEOHOLVWVWKHEXUVWRUGHULQJUHTXHVWHGE\WKHPDVWHUGXULQJ0HPRU\FRPPDQGVDV LQGLFDWHGRQAD[1::0]
7DEOH %XUVW2UGHULQJ(QFRGLQJ
AD1 AD0 Burst Order 0 0 Linear Incrementing 0 1 Reserved (disconnect after first data phase)13 1 0 Cacheline Wrap mode 1 1 Reserved (disconnect after first data phase)
$OOWDUJHWVDUHUHTXLUHGWRFKHFNAD[1::0]GXULQJDPHPRU\FRPPDQGWUDQVDFWLRQDQG HLWKHUSURYLGHWKHUHTXHVWHGEXUVWRUGHURUWHUPLQDWHWKHWUDQVDFWLRQZLWK'LVFRQQHFWLQ RQHRIWZRZD\V7KHWDUJHWFDQXVH'LVFRQQHFW:LWK'DWDGXULQJWKHLQLWLDOGDWDSKDVH RU'LVFRQQHFW:LWKRXW'DWDIRUWKHVHFRQGGDWDSKDVH:LWKHLWKHUWHUPLQDWLRQRQO\D VLQJOHGDWDSKDVHWUDQVIHUVGDWD7KHWDUJHWLVQRWDOORZHGWRWHUPLQDWHWKHWUDQVDFWLRQ ZLWK5HWU\VROHO\EHFDXVHLWGRHVQRWVXSSRUWDVSHFLILFEXUVWRUGHU,IWKHWDUJHWGRHVQRW VXSSRUWWKHEXUVWRUGHUUHTXHVWHGE\WKHPDVWHUWKHWDUJHWPXVWFRPSOHWHRQHGDWDSKDVH DQGWKHQWHUPLQDWHWKHUHTXHVWZLWK'LVFRQQHFW7KLVHQVXUHVWKDWWKHWUDQVDFWLRQZLOO FRPSOHWH DOEHLWVORZO\VLQFHHDFKUHTXHVWZLOOFRPSOHWHDVDVLQJOHGDWDSKDVH WUDQVDFWLRQ ,IDWDUJHWVXSSRUWVEXUVWLQJRQWKHEXVWKHWDUJHWPXVWVXSSRUWWKHOLQHDU EXUVWRUGHULQJ6XSSRUWIRUFDFKHOLQHZUDSLVRSWLRQDO ,QOLQHDUEXUVWRUGHUPRGHWKHDGGUHVVLVDVVXPHGWRLQFUHPHQWE\RQH':25' IRXU E\WHV IRUELWWUDQVDFWLRQVDQGWZR':25'V HLJKWE\WHV IRUELWWUDQVDFWLRQV DIWHUHDFKGDWDSKDVHXQWLOWKHWUDQVDFWLRQLVWHUPLQDWHG DQH[FHSWLRQLVGHVFULEHGLQ 6HFWLRQ 7UDQVDFWLRQVXVLQJWKH0HPRU\:ULWHDQG,QYDOLGDWHFRPPDQGFDQRQO\ XVHWKHOLQHDULQFUHPHQWLQJEXUVWPRGH
$FDFKHOLQHZUDSEXUVWPD\EHJLQDWDQ\DGGUHVVRIIVHWZLWKLQWKHFDFKHOLQH7KHOHQJWK RIDFDFKHOLQHLVGHILQHGE\WKH&DFKHOLQH6L]HUHJLVWHU UHIHUWR6HFWLRQ LQ &RQILJXUDWLRQ6SDFHZKLFKLVLQLWLDOL]HGE\FRQILJXUDWLRQVRIWZDUH7KHDFFHVVSURFHHGV E\LQFUHPHQWLQJRQH':25'DGGUHVV WZR':25'6IRUDELWGDWDWUDQVDFWLRQ XQWLOWKHHQGRIWKHFDFKHOLQHKDVEHHQUHDFKHGDQGWKHQZUDSVWRWKHEHJLQQLQJRIWKH VDPHFDFKHOLQH,WFRQWLQXHVXQWLOWKHUHVWRIWKHOLQHKDVEHHQWUDQVIHUUHG)RUH[DPSOH DQDFFHVVZKHUHWKHFDFKHOLQHVL]HLVE\WHV IRXU':25'V DQGWKHWUDQVDFWLRQ DGGUHVVHV':25'KWKHVHTXHQFHIRUDELWWUDQVDFWLRQZRXOGEH )LUVWGDWDSKDVHLVWR':25'K 6HFRQGGDWDSKDVHLVWR':25'&K ZKLFKLVWKHHQGRIWKHFXUUHQWFDFKHOLQH 7KLUGGDWDSKDVHLVWR':25'K ZKLFKLVWKHEHJLQQLQJRIWKHDGGUHVVHG FDFKHOLQH /DVWGDWDSKDVHLVWR':25'K ZKLFKFRPSOHWHVDFFHVVWRWKHHQWLUHFDFKHOLQH
13 This encoded value is reserved and cannot be assigned any “new” meaning for new designs. New designs (master or targets) cannot use this encoding. Note that in an earlier version of this specification, this encoding had meaning and there are masters that generate it and some targets may allow the transaction to continue past the initial data phase.
29 Revision 2.2
,IWKHEXUVWFRQWLQXHVRQFHDFRPSOHWHFDFKHOLQHKDVEHHQDFFHVVHGWKHEXUVWFRQWLQXHVDW WKHVDPH':25'RIIVHWRIWKHQH[WFDFKHOLQH&RQWLQXLQJWKHEXUVWRIWKHSUHYLRXV H[DPSOHZRXOGEH )LIWKGDWDSKDVHLVWR':25'K 6L[WKGDWDSKDVHLVWR':25'&K ZKLFKLVWKHHQGRIWKHVHFRQGFDFKHOLQH 6HYHQWKGDWDSKDVHLVWR':25'K ZKLFKLVWKHEHJLQQLQJRIWKHVHFRQG FDFKHOLQH /DVWGDWDSKDVHLVWR':25'K ZKLFKFRPSOHWHVDFFHVVWRWKHVHFRQG FDFKHOLQH ,IDWDUJHWGRHVQRWLPSOHPHQWWKH&DFKHOLQH6L]HUHJLVWHUWKHWDUJHWPXVWVLJQDO 'LVFRQQHFWZLWKRUDIWHUWKHFRPSOHWLRQRIWKHILUVWGDWDSKDVHLI&DFKHOLQH:UDSRUD UHVHUYHGPRGHLVXVHG ,IDPDVWHUVWDUWVZLWKRQHEXUVWRUGHULQJLWFDQQRWFKDQJHWKHEXUVWRUGHULQJXQWLOWKH FXUUHQWWUDQVDFWLRQHQGVVLQFHWKHEXUVWRUGHULQJLQIRUPDWLRQLVSURYLGHGRQAD[1::0] GXULQJWKHDGGUHVVSKDVH $GHYLFHPD\UHVWULFWZKDWDFFHVVJUDQXODULW\LWVXSSRUWVLQ0HPRU\6SDFH)RU H[DPSOHDGHYLFHPD\UHVWULFWLWVGULYHUWRRQO\DFFHVVWKHGHYLFHXVLQJE\WHZRUGRU ':25'RSHUDWLRQVDQGLVIUHHWRWHUPLQDWHDOORWKHUDFFHVVHVZLWK7DUJHW$ERUW
3.2.2.3. Configuration Space Decoding
(YHU\GHYLFHRWKHUWKDQKRVWEXVEULGJHVPXVWLPSOHPHQW&RQILJXUDWLRQ$GGUHVV6SDFH +RVWEXVEULGJHVPD\RSWLRQDOO\LPSOHPHQW&RQILJXUDWLRQ$GGUHVV6SDFH,QWKH &RQILJXUDWLRQ$GGUHVV6SDFHHDFKIXQFWLRQLVDVVLJQHGDXQLTXHE\WHVSDFHWKDWLV DFFHVVHGGLIIHUHQWO\WKDQ,2RU0HPRU\$GGUHVV6SDFHV&RQILJXUDWLRQUHJLVWHUVDUH GHVFULEHGLQ&KDSWHU7KHIROORZLQJVHFWLRQVGHVFULEH • &RQILJXUDWLRQFRPPDQGV 7\SHDQG7\SH • 6RIWZDUHJHQHUDWLRQRIFRQILJXUDWLRQFRPPDQGV • 6RIWZDUHJHQHUDWLRQRI6SHFLDO&\FOHV • 6HOHFWLRQRIDGHYLFH¶V&RQILJXUDWLRQ6SDFH • 6\VWHPJHQHUDWLRQRIIDSEL
3.2.2.3.1. Configuration Commands (Type 0 and Type 1)
%HFDXVHRIHOHFWULFDOORDGLQJLVVXHVWKHQXPEHURIGHYLFHVWKDWFDQEHVXSSRUWHGRQD JLYHQEXVVHJPHQWLVOLPLWHG7RDOORZV\VWHPVWREHEXLOWEH\RQGDVLQJOHEXVVHJPHQW 3&,WR3&,EULGJHVDUHGHILQHG$3&,WR3&,EULGJHUHTXLUHVDPHFKDQLVPWRNQRZKRZ DQGZKHQWRIRUZDUGFRQILJXUDWLRQDFFHVVHVWRGHYLFHVWKDWUHVLGHEHKLQGWKHEULGJH 7RVXSSRUWKLHUDUFKLFDO3&,EXVHVWZRW\SHVRIFRQILJXUDWLRQWUDQVDFWLRQVDUHXVHG 7KH\KDYHWKHIRUPDWVLOOXVWUDWHGLQ)LJXUHZKLFKVKRZVWKHLQWHUSUHWDWLRQRIAD OLQHVGXULQJWKHDGGUHVVSKDVHRIDFRQILJXUDWLRQWUDQVDFWLRQ
30 Revision 2.2
)XQFWLRQ HJLVWHUÃ HVHUYH Ã1XPEHU ÃÃ1XPEHU
7\SH
ÃÃÃ%XV 'HYLFH )XQFWLRQ HJLVWHUÃ 5HVHUYHG 1XPEHU 1XPEHU Ã1XPEHU ÃÃ1XPEHU
7\SH
)LJXUH $GGUHVV3KDVH)RUPDWVRI&RQILJXUDWLRQ7UDQVDFWLRQV
7\SHDQG7\SHFRQILJXUDWLRQWUDQVDFWLRQVDUHGLIIHUHQWLDWHGE\WKHYDOXHVRQ AD[1::0]$7\SHFRQILJXUDWLRQWUDQVDFWLRQ ZKHQAD[1::0] LVXVHGWRVHOHFW DGHYLFHRQWKHEXVZKHUHWKHWUDQVDFWLRQLVEHLQJUXQ$7\SHFRQILJXUDWLRQ WUDQVDFWLRQ ZKHQAD[1::0] LVXVHGWRSDVVDFRQILJXUDWLRQUHTXHVWWRDQRWKHU EXVVHJPHQW 7KH5HJLVWHU1XPEHUDQG)XQFWLRQ1XPEHUILHOGVKDYHWKHVDPHPHDQLQJIRUERWK FRQILJXUDWLRQW\SHVDQG'HYLFH1XPEHUDQG%XV1XPEHUDUHXVHGRQO\LQ7\SH WUDQVDFWLRQV7DUJHWVPXVWLJQRUHUHVHUYHGILHOGV
5HJLVWHU LVDQHQFRGHGYDOXHXVHGWRVHOHFWD':25'LQWKH 1XPEHU &RQILJXUDWLRQ6SDFHRIWKHLQWHQGHGWDUJHW )XQFWLRQ LVDQHQFRGHGYDOXHXVHGWRVHOHFWRQHRIHLJKWSRVVLEOH 1XPEHU IXQFWLRQVRQDPXOWLIXQFWLRQGHYLFH 'HYLFH LVDQHQFRGHGYDOXHXVHGWRVHOHFWRQHRIGHYLFHVRQD 1XPEHU JLYHQEXV 5HIHUWR6HFWLRQIRUOLPLWDWLRQVRQ WKHQXPEHURIGHYLFHVVXSSRUWHG %XV LVDQHQFRGHGYDOXHXVHGWRVHOHFWRIEXVHVLQD 1XPEHU V\VWHP
%ULGJHV ERWKKRVWDQG3&,WR3&, WKDWQHHGWRJHQHUDWHD7\SHFRQILJXUDWLRQ WUDQVDFWLRQXVHWKH'HYLFH1XPEHUWRVHOHFWZKLFKIDSELWRDVVHUW7KH)XQFWLRQ 1XPEHULVSURYLGHGRQAD[10::08]7KH5HJLVWHU1XPEHULVSURYLGHGRQAD[7::2] AD[1::0]PXVWEHIRUD7\SHFRQILJXUDWLRQWUDQVDFWLRQ $7\SHFRQILJXUDWLRQWUDQVDFWLRQLVQRWSURSDJDWHGEH\RQGWKHORFDO3&,EXVDQGPXVW EHFODLPHGE\DORFDOGHYLFHRUWHUPLQDWHGZLWK0DVWHU$ERUW ,IWKHWDUJHWRIDFRQILJXUDWLRQWUDQVDFWLRQUHVLGHVRQDQRWKHUEXV QRWWKHORFDOEXV D 7\SHFRQILJXUDWLRQWUDQVDFWLRQPXVWEHXVHG$OOWDUJHWVH[FHSW3&,WR3&,EULGJHV LJQRUH7\SHFRQILJXUDWLRQWUDQVDFWLRQV3&,WR3&,EULGJHVGHFRGHWKH%XV1XPEHU ILHOGWRGHWHUPLQHLIWKHGHVWLQDWLRQEXVRIWKHFRQILJXUDWLRQWUDQVDFWLRQUHVLGHVEHKLQG WKHEULGJH,IWKH%XV1XPEHULVQRWIRUDEXVEHKLQGWKHEULGJHWKHWUDQVDFWLRQLV LJQRUHG7KHEULGJHFODLPVWKHWUDQVDFWLRQLIWKHWUDQVDFWLRQLVWRDEXVEHKLQGWKH EULGJH,IWKH%XV1XPEHULVQRWWRWKHVHFRQGDU\EXVRIWKHEULGJHWKHWUDQVDFWLRQLV VLPSO\SDVVHGWKURXJKXQFKDQJHG,IWKH%XV1XPEHUPDWFKHVWKHVHFRQGDU\EXV QXPEHUWKHEULGJHFRQYHUWVWKHWUDQVDFWLRQLQWRD7\SHFRQILJXUDWLRQWUDQVDFWLRQ7KH EULGJHFKDQJHVAD[1::0]WRDQGSDVVHVAD[10::02]WKURXJKXQFKDQJHG7KH
31 Revision 2.2
'HYLFH1XPEHULVGHFRGHGWRVHOHFWRQHRIGHYLFHVRQWKHORFDOEXV7KHEULGJH DVVHUWVWKHFRUUHFWIDSELDQGLQLWLDWHVD7\SHFRQILJXUDWLRQWUDQVDFWLRQ1RWH 3&, WR3&,EULGJHVFDQDOVRIRUZDUGFRQILJXUDWLRQWUDQVDFWLRQVXSVWUHDP UHIHUWRWKH3&,WR 3&,%ULGJH$UFKLWHFWXUH6SHFLILFDWLRQIRUPRUHLQIRUPDWLRQ $VWDQGDUGH[SDQVLRQEXVEULGJHPXVWQRWIRUZDUGDFRQILJXUDWLRQWUDQVDFWLRQWRDQ H[SDQVLRQEXV
3.2.2.3.2. Software Generation of Configuration Transactions
6\VWHPVPXVWSURYLGHDPHFKDQLVPWKDWDOORZVVRIWZDUHWRJHQHUDWH3&,FRQILJXUDWLRQ WUDQVDFWLRQV7KLVPHFKDQLVPLVW\SLFDOO\ORFDWHGLQWKHKRVWEULGJH)RU3&$7 FRPSDWLEOHV\VWHPVWKHPHFKDQLVP IRUJHQHUDWLQJFRQILJXUDWLRQWUDQVDFWLRQVLV GHILQHGDQGVSHFLILHGLQWKLVVHFWLRQ$GHYLFHGULYHUVKRXOGXVHWKH$3,SURYLGHGE\WKH RSHUDWLQJV\VWHPWRDFFHVVWKH&RQILJXUDWLRQ6SDFHRILWVGHYLFHDQGQRWGLUHFWO\E\ZD\ RIWKHKDUGZDUHPHFKDQLVP)RURWKHUV\VWHPDUFKLWHFWXUHVWKHPHWKRGRIJHQHUDWLQJ FRQILJXUDWLRQWUDQVDFWLRQVLVQRWGHILQHGLQWKLVVSHFLILFDWLRQ 7ZR':25',2ORFDWLRQVDUHXVHGWRJHQHUDWHFRQILJXUDWLRQWUDQVDFWLRQVIRU3&$7 FRPSDWLEOHV\VWHPV7KHILUVW':25'ORFDWLRQ &)K UHIHUHQFHVDUHDGZULWHUHJLVWHU WKDWLVQDPHG&21),*B$''5(667KHVHFRQG':25'DGGUHVV &)&K UHIHUHQFHVD UHDGZULWHUHJLVWHUQDPHG&21),*B'$7$7KH&21),*B$''5(66UHJLVWHULVELWV ZLWKWKHIRUPDWVKRZQLQ)LJXUH%LWLVDQHQDEOHIODJIRUGHWHUPLQLQJZKHQ DFFHVVHVWR&21),*B'$7$DUHWREHWUDQVODWHGWRFRQILJXUDWLRQWUDQVDFWLRQVRQWKH3&, EXV%LWVWRDUHUHVHUYHGUHDGRQO\DQGPXVWUHWXUQ VZKHQUHDG%LWV WKURXJKFKRRVHDVSHFLILF3&,EXVLQWKHV\VWHP%LWVWKURXJKFKRRVHDVSHFLILF GHYLFHRQWKHEXV%LWVWKURXJKFKRRVHDVSHFLILFIXQFWLRQLQDGHYLFH LIWKHGHYLFH VXSSRUWVPXOWLSOHIXQFWLRQV %LWVWKURXJKFKRRVHD':25'LQWKHGHYLFH V &RQILJXUDWLRQ6SDFH%LWVDQGDUHUHDGRQO\DQGPXVWUHWXUQ VZKHQUHDG
31 30 2423 16 15 11 10 8 7 2 1 0 'HYLFH )XQFWLRQ 5HVHUYHG %XV 5HJLVWHU 1XPEHU 1XPEHU 1XPEHU 1XPEHU
(QDEOHELW HQDEOHG GLVDEOHG
)LJXUH /D\RXWRI&21),*B$''5(665HJLVWHU
$Q\WLPHDKRVWEULGJHVHHVDIXOO':25',2ZULWHIURPWKHKRVWWR &21),*B$''5(66WKHEULGJHPXVWODWFKWKHGDWDLQWRLWV&21),*B$''5(66 UHJLVWHU2QIXOO':25',2UHDGVWR&21),*B$''5(66WKHEULGJHPXVWUHWXUQWKH GDWDLQ&21),*B$''5(66$Q\RWKHUW\SHVRIDFFHVVHVWRWKLVDGGUHVV QRQ ':25' KDYHQRHIIHFWRQ&21),*B$''5(66DQGDUHH[HFXWHGDVQRUPDO,2 WUDQVDFWLRQVRQWKH3&,EXV7KHUHIRUHWKHRQO\,26SDFHFRQVXPHGE\WKLVUHJLVWHULVD ':25'DWWKHJLYHQDGGUHVV,2GHYLFHVWKDWVKDUHWKHVDPHDGGUHVVEXWXVH%<7(RU :25'UHJLVWHUVDUHQRWDIIHFWHGEHFDXVHWKHLUWUDQVDFWLRQVZLOOSDVVWKURXJKWKHKRVW EULGJHXQFKDQJHG
14 In versions 2.0 and 2.1 of this specification, two mechanisms were defined. However, only one mechanism (Configuration Mechanism #1) was allowed for new designs and the other (Configuration Mechanism #2) was included for reference.
32 Revision 2.2
:KHQDKRVWEULGJHVHHVDQ,2DFFHVVWKDWIDOOVLQVLGHWKH':25'EHJLQQLQJDW &21),*B'$7$DGGUHVVLWFKHFNVWKH(QDEOHELWDQGWKH%XV1XPEHULQWKH &21),*B$''5(66UHJLVWHU,I(QDEOHELWLVVHWDQGWKH%XV1XPEHUPDWFKHVWKH EULGJH V%XV1XPEHURUDQ\%XV1XPEHUEHKLQGWKHEULGJHDFRQILJXUDWLRQF\FOH WUDQVODWLRQPXVWEHGRQH 7KHUHDUHWZRW\SHVRIWUDQVODWLRQWKDWWDNHSODFH7KHILUVW7\SHLVDWUDQVODWLRQ ZKHUHWKHGHYLFHEHLQJDGGUHVVHGLVRQWKH3&,EXVFRQQHFWHGWRWKHKRVWEULGJH7KH VHFRQG7\SHRFFXUVZKHQWKHGHYLFHLVRQDQRWKHUEXVVRPHZKHUHEHKLQGWKLVEULGJH )RU7\SHWUDQVODWLRQV VHH)LJXUH WKHKRVWEULGJHGRHVDGHFRGHRIWKH'HYLFH 1XPEHUILHOGWRDVVHUWWKHDSSURSULDWHIDSELOLQH DQGSHUIRUPVDFRQILJXUDWLRQ WUDQVDFWLRQRQWKH3&,EXVZKHUHAD[1::0] %LWVRI&21),*B$''5(66 DUHFRSLHGWRAD[10::8]RQWKH3&,EXVDVDQHQFRGHGYDOXHZKLFKLVXVHGE\ FRPSRQHQWVWKDWFRQWDLQPXOWLSOHIXQFWLRQVAD[7::2]DUHDOVRFRSLHGIURPWKH &21),*B$''5(66UHJLVWHU)LJXUHVKRZVWKHWUDQVODWLRQIURPWKH &21),*B$''5(66UHJLVWHUWRADOLQHVRQWKH3&,EXV
Bus Device Register Reserved Function 0 0 CONFIG_ADDRESS Number Number Number Number
PCI AD BUS Only One "1" 0 0
)LJXUH +RVW%ULGJH7UDQVODWLRQIRU7\SH&RQILJXUDWLRQ7UDQVDFWLRQV$GGUHVV3KDVH
)RU7\SHWUDQVODWLRQVWKHKRVWEULGJHGLUHFWO\FRSLHVWKHFRQWHQWVRIWKH &21),*B$''5(66UHJLVWHU H[FOXGLQJELWVDQG RQWRWKH3&,ADOLQHVGXULQJWKH DGGUHVVSKDVHRIDFRQILJXUDWLRQWUDQVDFWLRQPDNLQJVXUHWKDWAD[1::0]LV ,QERWK7\SHDQG7\SHWUDQVODWLRQVE\WHHQDEOHVIRUWKHGDWDWUDQVIHUVPXVWEH GLUHFWO\FRSLHGIURPWKHSURFHVVRUEXV
15 If the Device Number field selects an IDSEL line that the bridge does not implement, the bridge must complete the processor access normally, dropping the data on writes and returning all ones on reads. The bridge may optionally implement this requirement by performing a Type 0 configuration access with no IDSEL asserted. This will terminate with Master-Abort which drops write data and returns all ones on reads.
33 Revision 2.2
Implementation Note: Bus Numbers Registers and Peer Host Bridges )RUKRVWEULGJHVWKDWGRQRWVXSSRUWSHHUKRVWEXVHVWUDQVODWLQJFRQILJXUDWLRQDFFHVVHV LQWRFRQILJXUDWLRQWUDQVDFWLRQVLVVLPSOH,IWKH%XV1XPEHULQWKH&21),*B$''5(66 UHJLVWHULV]HURD7\SHFRQILJXUDWLRQWUDQVODWLRQLVXVHG,IWKH%XV1XPEHULQWKH &21),*B$''5(66UHJLVWHULVQRQ]HURD7\SHFRQILJXUDWLRQWUDQVODWLRQLVXVHG )RUKRVWEULGJHVWKDWVXSSRUWSHHUKRVWEXVHVRQHSHHUEULGJHW\SLFDOO\LVGHVLJQDWHGWR DOZD\VDFNQRZOHGJHDFFHVVHVWRWKH&21),*B$''5(66UHJLVWHU2WKHUSHHUEULGJHV ZRXOGVQRRSWKHGDWDZULWWHQWRWKLVUHJLVWHU$FFHVVHVWRWKH&21),*B'$7$UHJLVWHU DUHW\SLFDOO\KDQGVKDNHQE\WKHEULGJHGRLQJWKHFRQILJXUDWLRQWUDQVODWLRQ +RVWEULGJHVWKDWVXSSRUWSHHUKRVWEXVHVUHTXLUHWZR&RQILJXUDWLRQ6SDFHUHJLVWHUV ZKRVHFRQWHQWVDUHXVHGWRGHWHUPLQHZKHQWKHEULGJHGRHVFRQILJXUDWLRQWUDQVDFWLRQ WUDQVODWLRQ2QHUHJLVWHU %XV1XPEHU VSHFLILHVWKHEXVQXPEHURIWKH3&,EXVGLUHFWO\ EHKLQGWKHEULGJHDQGWKHRWKHUUHJLVWHU 6XERUGLQDWH%XV1XPEHU VSHFLILHVWKHQXPEHU RIWKHODVWKLHUDUFKLFDOEXVEHKLQGWKHEULGJH $3&,WR3&,EULGJHUHTXLUHVDQ DGGLWLRQDOUHJLVWHUZKLFKLVLWV3ULPDU\%XV1XPEHU 6\VWHPFRQILJXUDWLRQVRIWZDUHLV UHVSRQVLEOHIRULQLWLDOL]LQJWKHVHUHJLVWHUVWRDSSURSULDWHYDOXHV7KHKRVWEULGJH GHWHUPLQHVWKHFRQILJXUDWLRQWUDQVODWLRQW\SH RU EDVHGRQWKHYDOXHRIWKHEXV QXPEHULQWKH&21),*B$''5(66UHJLVWHU,IWKH%XV1XPEHULQWKH &21),*B$''5(66UHJLVWHUPDWFKHVWKH%XV1XPEHUUHJLVWHUD7\SHFRQILJXUDWLRQ WUDQVDFWLRQLVXVHG,IWKH%XV1XPEHULQ&21),*B$''5(66LVJUHDWHUWKDQWKH%XV 1XPEHUUHJLVWHUDQGOHVVWKDQRUHTXDOWRWKH6XERUGLQDWH%XV1XPEHUUHJLVWHUD7\SH FRQILJXUDWLRQWUDQVDFWLRQLVXVHG,IWKH%XV1XPEHULQ&21),*B$''5(66LVOHVV WKDQWKH%XV1XPEHUUHJLVWHURUJUHDWHUWKDQWKH6XERUGLQDWH%XV1XPEHUUHJLVWHUWKH FRQILJXUDWLRQWUDQVDFWLRQLVDGGUHVVLQJDEXVWKDWLVQRWLPSOHPHQWHGRULVEHKLQGVRPH RWKHUKRVWEULGJHDQGLVLJQRUHG
3.2.2.3.3. Software Generation of Special Cycles
7KLVVHFWLRQGHILQHVKRZDKRVWEULGJHLQD3&$7FRPSDWLEOHV\VWHPVPD\RSWLRQDOO\ LPSOHPHQWWKHFRQILJXUDWLRQPHFKDQLVPIRUDFFHVVLQJ&RQILJXUDWLRQ6SDFHWRDOORZ VRIWZDUHWRJHQHUDWHDWUDQVDFWLRQWKDWXVHVD6SHFLDO&\FOHFRPPDQG+RVWEULGJHVDUH QRWUHTXLUHGWRSURYLGHDPHFKDQLVPIRUDOORZLQJVRIWZDUHWRJHQHUDWHDWUDQVDFWLRQ XVLQJD6SHFLDO&\FOHFRPPDQG :KHQWKH&21),*B$''5(66UHJLVWHULVZULWWHQZLWKDYDOXHVXFKWKDWWKH%XV 1XPEHUPDWFKHVWKHEULGJH VEXVQXPEHUWKH'HYLFH1XPEHULVDOO VWKH)XQFWLRQ 1XPEHULVDOO VDQGWKH5HJLVWHU1XPEHUKDVDYDOXHRI]HURWKHQWKHEULGJHLVSULPHG WRJHQHUDWHDWUDQVDFWLRQXVLQJD6SHFLDO&\FOHFRPPDQGWKHQH[WWLPHWKH &21),*B'$7$UHJLVWHULVZULWWHQ:KHQWKH&21),*B'$7$UHJLVWHULVZULWWHQWKH EULGJHJHQHUDWHVDWUDQVDFWLRQWKDWXVHVD6SHFLDO&\FOHFRPPDQGHQFRGLQJ UDWKHUWKDQ &RQILJXUDWLRQ:ULWHFRPPDQG RQWKHC/BE[3::0]#SLQVGXULQJWKHDGGUHVVSKDVHDQG GULYHVWKHGDWDIURPWKH,2ZULWHRQWRAD[31::00]GXULQJWKHILUVWGDWDSKDVH$IWHU &21),*B$''5(66KDVEHHQVHWXSWKLVZD\UHDGVWR&21),*B'$7$KDYH XQGHILQHGUHVXOWV,QRQHSRVVLEOHLPSOHPHQWDWLRQWKHEULGJHFDQWUHDWLWDVDQRUPDO FRQILJXUDWLRQRSHUDWLRQ LHJHQHUDWHD7\SHFRQILJXUDWLRQWUDQVDFWLRQRQWKH3&, EXV 7KLVZLOOWHUPLQDWHZLWKD0DVWHU$ERUWDQGWKHSURFHVVRUZLOOKDYHDOO V UHWXUQHG
34 Revision 2.2
,IWKH%XV1XPEHUILHOGRI&21),*B$''5(66GRHVQRWPDWFKWKHEULGJH VEXV QXPEHUWKHQWKHEULGJHSDVVHVWKHZULWHWR&21),*B'$7$RQWKURXJKWR3&,DVD 7\SHFRQILJXUDWLRQWUDQVDFWLRQMXVWOLNHDQ\RWKHUWLPHWKHEXVQXPEHUVGRQRWPDWFK
3.2.2.3.4. Selection of a Device’s Configuration Space
$FFHVVHVLQWKH&RQILJXUDWLRQ$GGUHVV6SDFHUHTXLUHGHYLFHVHOHFWLRQGHFRGLQJWREH GRQHH[WHUQDOO\DQGWREHVLJQDOHGWRWKHGHYLFHYLDLQLWLDOL]DWLRQGHYLFHVHOHFWRU IDSELZKLFKIXQFWLRQVDVDFODVVLFDO³FKLSVHOHFW´VLJQDO(DFKGHYLFHKDVLWVRZQ IDSELLQSXW H[FHSWIRUKRVWEXVEULGJHVZKLFKDUHSHUPLWWHGWRLPSOHPHQWWKHLU LQLWLDOL]DWLRQGHYLFHVHOHFWLRQLQWHUQDOO\ 'HYLFHVWKDWUHVSRQGWR7\SHFRQILJXUDWLRQF\FOHVDUHVHSDUDWHGLQWRWZRW\SHVDQGDUH GLIIHUHQWLDWHGE\DQHQFRGLQJLQWKH&RQILJXUDWLRQ6SDFHKHDGHU7KHILUVWW\SH VLQJOH IXQFWLRQGHYLFH LVGHILQHGIRUEDFNZDUGFRPSDWLELOLW\DQGRQO\XVHVLWVIDSELSLQDQG AD[1::0]WRGHWHUPLQHZKHWKHURUQRWWRUHVSRQG $VLQJOHIXQFWLRQGHYLFHDVVHUWVDEVSEL#WRFODLPDFRQILJXUDWLRQWUDQVDFWLRQZKHQ • DFRQILJXUDWLRQFRPPDQGLVGHFRGHG • WKHGHYLFH¶VIDSELLVDVVHUWHG DQG • AD[1::0]LV 7\SH&RQILJXUDWLRQ&RPPDQG GXULQJWKH$GGUHVV3KDVH 2WKHUZLVHWKHGHYLFHLJQRUHVWKHFXUUHQWWUDQVDFWLRQ$VLQJOHIXQFWLRQGHYLFHPD\ RSWLRQDOO\UHVSRQGWRDOOIXQFWLRQQXPEHUVDVWKHVDPHIXQFWLRQRUPD\GHFRGHWKH )XQFWLRQ1XPEHUILHOGAD[10::08]DQGUHVSRQGRQO\WRIXQFWLRQDQGQRWUHVSRQG 0DVWHU$ERUWWHUPLQDWLRQ WRWKHRWKHUIXQFWLRQQXPEHUV 7KHVHFRQGW\SHRIGHYLFH PXOWLIXQFWLRQGHYLFH GHFRGHVWKH)XQFWLRQ1XPEHUILHOG AD[10::08]WRVHOHFWRQHRIHLJKWSRVVLEOHIXQFWLRQVRQWKHGHYLFHZKHQGHWHUPLQLQJ ZKHWKHURUQRWWRUHVSRQG0XOWLIXQFWLRQGHYLFHVDUHUHTXLUHGWRGRDIXOOGHFRGHRQ AD[10::08]DQGRQO\UHVSRQGWRWKHFRQILJXUDWLRQF\FOHLIWKH\KDYHLPSOHPHQWHGWKH &RQILJXUDWLRQ6SDFHUHJLVWHUVIRUWKHVHOHFWHGIXQFWLRQ7KH\PXVWQRWUHVSRQG 0DVWHU $ERUWWHUPLQDWLRQ WRXQLPSOHPHQWHGIXQFWLRQQXPEHUV7KH\DUHDOVRUHTXLUHGWR DOZD\VLPSOHPHQWIXQFWLRQLQWKHGHYLFH,PSOHPHQWLQJRWKHUIXQFWLRQVLVRSWLRQDODQG PD\EHDVVLJQHGLQDQ\RUGHU LHDWZRIXQFWLRQGHYLFHPXVWUHVSRQGWRIXQFWLRQEXW FDQFKRRVHDQ\RIWKHRWKHUSRVVLEOHIXQFWLRQQXPEHUV IRUWKHVHFRQGIXQFWLRQ ,IDGHYLFHLPSOHPHQWVPXOWLSOHLQGHSHQGHQWIXQFWLRQVLWDVVHUWVDEVSEL#WRFODLPD FRQILJXUDWLRQWUDQVDFWLRQZKHQ • DFRQILJXUDWLRQFRPPDQGLVGHFRGHG • WKHWDUJHW¶VIDSELLVDVVHUWHG • AD[1::0]LV DQG • AD[10::08]PDWFKDIXQFWLRQWKDWLVLPSOHPHQWHG
2WKHUZLVHWKHWUDQVDFWLRQLVLJQRUHG)RUH[DPSOHLIIXQFWLRQVDQGDUHLPSOHPHQWHG IXQFWLRQVWKURXJKDQGWKURXJKDUHQRW WKHGHYLFHZRXOGDVVHUWDEVSEL#IRUD FRQILJXUDWLRQWUDQVDFWLRQLQZKLFKIDSELLVDVVHUWHGDQGAD[1::0]DUHDQG AD[10::08]PDWFKHVRUAD[31::11]DUHLJQRUHGE\DPXOWLIXQFWLRQGHYLFH GXULQJDQDFFHVVRILWVFRQILJXUDWLRQUHJLVWHUV 7KHRUGHULQZKLFKFRQILJXUDWLRQVRIWZDUHSUREHVGHYLFHVUHVLGLQJRQDEXVVHJPHQWLV QRWVSHFLILHG7\SLFDOO\FRQILJXUDWLRQVRIWZDUHHLWKHUVWDUWVZLWK'HYLFH1XPEHUDQG ZRUNVXSRUVWDUWVDW'HYLFH1XPEHUDQGZRUNVGRZQ,IDVLQJOHIXQFWLRQGHYLFHLV GHWHFWHG LHELWLQWKH+HDGHU7\SHUHJLVWHURIIXQFWLRQLV QRPRUHIXQFWLRQVIRU
35 Revision 2.2
WKDW'HYLFH1XPEHUZLOOEHFKHFNHG,IDPXOWLIXQFWLRQGHYLFHLVGHWHFWHG LHELWLQ WKH+HDGHU7\SHUHJLVWHURIIXQFWLRQLV WKHQDOOUHPDLQLQJ)XQFWLRQ1XPEHUVZLOO EHFKHFNHG 2QFHDIXQFWLRQKDVEHHQVHOHFWHGLWXVHVAD[7::2] WRDGGUHVVD':25'DQGWKHE\WH HQDEOHVWRGHWHUPLQHZKLFKE\WHVZLWKLQWKHDGGUHVVHG':25'DUHEHLQJDFFHVVHG$ IXQFWLRQPXVWQRWUHVWULFWWKHVL]HRIWKHDFFHVVLWVXSSRUWVLQ&RQILJXUDWLRQ6SDFH7KH FRQILJXUDWLRQFRPPDQGVOLNHRWKHUFRPPDQGVDOORZGDWDWREHDFFHVVHGXVLQJDQ\ FRPELQDWLRQRIE\WHV LQFOXGLQJDE\WHZRUG':25'RUQRQFRQWLJXRXVE\WHV DQG PXOWLSOHGDWDSKDVHVLQDEXUVW7KHWDUJHWLVUHTXLUHGWRKDQGOHDQ\FRPELQDWLRQRIE\WH HQDEOHV+RZHYHULWLVQRWUHTXLUHGWRKDQGOHDFRQILJXUDWLRQWUDQVDFWLRQWKDWFRQVLVWVRI PXOWLSOHGDWDSKDVHV,IDFRQILJXUDWLRQWUDQVDFWLRQFRQVLVWVRIPRUHWKDQDVLQJOHGDWD SKDVHWKHWDUJHWLVSHUPLWWHGWRWHUPLQDWHWKHUHTXHVWZLWK'LVFRQQHFW7KLVLVQRW VXIILFLHQWFDXVHIRUWKHWDUJHWWRWHUPLQDWHWKHWUDQVDFWLRQZLWK7DUJHW$ERUWVLQFHWKLVLV QRWDQHUURUFRQGLWLRQ ,IDFRQILJXUDWLRQWUDQVDFWLRQKDVPXOWLSOHGDWDSKDVHV EXUVW OLQHDUEXUVWRUGHULQJLVWKH RQO\DGGUHVVLQJPRGHDOORZHGVLQFHAD[1::0]FRQYH\FRQILJXUDWLRQWUDQVDFWLRQW\SH DQGQRWDEXUVWDGGUHVVLQJPRGHOLNH0HPRU\DFFHVVHV7KHLPSOLHGDGGUHVVRIHDFK VXEVHTXHQWGDWDSKDVHLVRQH':25'ODUJHUWKDQWKHSUHYLRXVGDWDSKDVH)RUH[DPSOH DWUDQVDFWLRQVWDUWVZLWKAD[7::2] HTXDOWR[[EWKHVHTXHQFHRIDEXUVWZRXOG EH [[E[[E[[E[[E ZKHUH[[LQGLFDWHZKHWKHUWKH WUDQVDFWLRQLVD7\SHRU7\SHFRQILJXUDWLRQWUDQVDFWLRQ 7KHUHVWRIWKH WUDQVDFWLRQLVWKHVDPHDVRWKHUFRPPDQGVLQFOXGLQJDOOWHUPLQDWLRQVHPDQWLFV 1RWH 7KH3&,WR3&,%ULGJH$UFKLWHFWXUH6SHFLILFDWLRQUHVWULFWV7\SHFRQILJXUDWLRQ WUDQVDFWLRQVWKDWDUHFRQYHUWHGLQWRDWUDQVDFWLRQWKDWXVHVD6SHFLDO&\FOHFRPPDQGWRD VLQJOHGDWDSKDVH QR6SHFLDO&\FOHEXUVWV ,IQRDJHQWUHVSRQGVWRDFRQILJXUDWLRQWUDQVDFWLRQWKHUHTXHVWLVWHUPLQDWHGYLD0DVWHU $ERUW UHIHUWR6HFWLRQ
3.2.2.3.5. System Generation of IDSEL
([DFWO\KRZWKHIDSELSLQLVGULYHQLVOHIWWRWKHGLVFUHWLRQRIWKHKRVWPHPRU\EULGJH RUV\VWHPGHVLJQHU7KLVVLJQDOKDVEHHQGHVLJQHGWRDOORZLWVFRQQHFWLRQWRRQHRIWKH XSSHUDGGUHVVOLQHVZKLFKDUHQRWRWKHUZLVHXVHGLQDFRQILJXUDWLRQDFFHVV +RZHYHUWKHUHLVQRVSHFLILHGZD\RIGHWHUPLQLQJIDSELIURPWKHXSSHUDGGUHVV ELWV7KHUHIRUHWKHIDSELSLQPXVWEHVXSSRUWHGE\DOOWDUJHWV'HYLFHVPXVWQRWPDNH DQLQWHUQDOFRQQHFWLRQEHWZHHQDQADOLQHDQGDQLQWHUQDOIDSELVLJQDOLQRUGHUWRVDYH DSLQ7KHRQO\H[FHSWLRQLVWKHKRVWEULGJHVLQFHLWGHILQHVKRZIDSELVDUHPDSSHG IDSELJHQHUDWLRQEHKLQGD3&,WR3&,EULGJHLVVSHFLILHGLQWKH3&,WR3&,%ULGJH $UFKLWHFWXUH6SHFLILFDWLRQ 7KHELQGLQJEHWZHHQDGHYLFHQXPEHULQWKH&21),*B$''5(66UHJLVWHURI3&$7 FRPSDWLEOHV\VWHPDQGWKHJHQHUDWLRQRIDQIDSELLVQRWVSHFLILHG7KHUHIRUH%,26 PXVWVFDQDOOGHYLFHQXPEHUVWRHQVXUHDOOFRPSRQHQWVDUHORFDWHG1RWH 7KH KDUGZDUHWKDWFRQYHUWVWKHGHYLFHQXPEHUWRDQIDSELLVUHTXLUHGWRHQVXUHWKDWRQO\D VLQJOHXQLTXHIDSELOLQHLVDVVHUWHGIRUHDFKGHYLFHQXPEHU&RQILJXUDWLRQWUDQVDFWLRQV WKDWDUHQRWFODLPHGE\DGHYLFHDUHWHUPLQDWHGZLWK0DVWHU$ERUW7KHPDVWHUWKDW LQLWLDWHGWKLVWUDQVDFWLRQVHWVWKHUHFHLYHG0DVWHU$ERUWELWLQWKH6WDWXVUHJLVWHU
36 Revision 2.2
Implementation Note: System Generation of IDSEL
+RZDV\VWHPJHQHUDWHVIDSELLVV\VWHPVSHFLILF KRZHYHULIQRRWKHUPDSSLQJLV UHTXLUHGWKHIROORZLQJH[DPSOHPD\EHXVHG7KHIDSELVLJQDODVVRFLDWHGZLWK'HYLFH 1XPEHULVFRQQHFWHGWRAD[16]IDSELRI'HYLFH1XPEHULVFRQQHFWHGWRAD[17] DQGVRIRUWKXQWLOIDSELRI'HYLFH1XPEHULVFRQQHFWHGWRAD[31])RU'HYLFH 1XPEHUVWKHKRVWEULGJHVKRXOGH[HFXWHWKHWUDQVDFWLRQEXWQRWDVVHUWDQ\RIWKH AD[31::16]OLQHVEXWDOORZWKHDFFHVVWREHWHUPLQDWHGZLWK0DVWHU$ERUW 7ZHQW\RQHGLIIHUHQWGHYLFHVFDQEHXQLTXHO\VHOHFWHGIRUFRQILJXUDWLRQDFFHVVHVE\ FRQQHFWLQJDGLIIHUHQWDGGUHVVOLQHWRHDFKGHYLFHDQGDVVHUWLQJRQHRIWKHAD[31::11] OLQHVDWDWLPH7KHLVVXHZLWKFRQQHFWLQJRQHRIWKHXSSHUADOLQHVWRIDSELLVDQ DGGLWLRQDOORDGRQWKHADOLQH7KLVFDQEHPLWLJDWHGE\UHVLVWLYHO\FRXSOLQJIDSELWR WKHDSSURSULDWHADOLQH7KLVGRHVKRZHYHUFUHDWHDYHU\VORZVOHZUDWHRQIDSEL FDXVLQJLWWREHLQDQLQYDOLGORJLFVWDWHPRVWRIWKHWLPHDVVKRZQLQ)LJXUHZLWKWKH ;;;;PDUNV+RZHYHUVLQFHLWLVRQO\XVHGRQWKHDGGUHVVSKDVHRID7\SH FRQILJXUDWLRQWUDQVDFWLRQWKHDGGUHVVEXVFDQEHSUHGULYHQDIHZFORFNVEHIRUH FRAME# WKXVJXDUDQWHHLQJIDSELWREHVWDEOHZKHQLWQHHGVWREHVDPSOHG3UH GULYLQJWKHDGGUHVVEXVLVHTXLYDOHQWWRDGGUHVVVWHSSLQJDVGLVFXVVHGLQ6HFWLRQ 1RWHWKDWLIUHVLVWLYHFRXSOLQJLVXVHGWKHEULGJHWKDWJHQHUDWHVWKHFRQILJXUDWLRQ WUDQVDFWLRQLVUHTXLUHGWRXVHDGGUHVVVWHSSLQJRUHQVXUHWKDWWKHFORFNSHULRGLV VXIILFLHQWO\ORQJWRDOORZIDSELWREHFRPHVWDEOHEHIRUHLQLWLDWLQJWKHFRQILJXUDWLRQ WUDQVDFWLRQ)RUDOORWKHUF\FOHVIDSELLVXQGHILQHGDQGPD\EHDWDQRQGHWHUPLQLVWLF OHYHOGXULQJWKHDGGUHVVSKDVH
16 The number of clocks the address bus should be pre-driven is determined from the RC time constant on IDSEL.
37 Revision 2.2
CLK 1 2 3 4 5 6
FRAME#
AD ADDRESS DATA
IDSEL
C/BE# CFG-RD BE#'s
IRDY#
TRDY#
DEVSEL#
)LJXUH &RQILJXUDWLRQ5HDG
3.2.3. Byte Lane and Byte Enable Usage
7KHEXVSURWRFROGRHVQRWVXSSRUWDXWRPDWLFEXVVL]LQJRQUHTXHVWVRID':25'RUOHVV $XWRPDWLFEXVVL]LQJDOORZVDGHYLFHWRUHTXHVWWKHPDVWHURIWKHFXUUHQWWUDQVDFWLRQWR EUHDNWKHDFFHVVLQWRVPDOOHUSLHFHVIRUWKHWDUJHWWRFRPSOHWH)RUH[DPSOHDQELW GHYLFHWKDWLVDFFHVVHGZLWKDELWUHTXHVWFRXOGWUDQVIHUWKHORZHUELWVDQGUHTXLUH WKHPDVWHUWRPRYHWKHXSSHUELWV RIWKHELWDFFHVV GRZQWRWKHORZHUE\WHODQHWR FRPSOHWHWKHUHTXHVW 6LQFHDOO3&,GHYLFHVFRQQHFWWRWKHORZHUELWVIRUDGGUHVV GHFRGHWKHGHYLFHLWVHOILVUHTXLUHGWRSURYLGHWKLVE\WHVWHHULQJZKHQUHTXLUHGRUWKH GULYHULVUHTXLUHGWRSODFHWKHGDWDRQWKHFRUUHFWE\WH,QJHQHUDOVRIWZDUHLVDZDUHRI WKHFKDUDFWHULVWLFVRIWKHWDUJHWGHYLFHDQGRQO\LVVXHVDSSURSULDWHOHQJWKDFFHVVHV 7KHEXVSURWRFROUHTXLUHVDXWRPDWLFEXVVL]LQJLIDPDVWHUUHTXHVWVDELWGDWDWUDQVIHU WRDELWWDUJHW,QWKLVFDVHWKHWDUJHWGRHVQRWLQGLFDWHWKDWLWFDQGRDELWGDWD WUDQVIHUDQGWKHPDVWHULVUHTXLUHGWRFRPSOHWHWKHFXUUHQWWUDQVDFWLRQXVLQJELWGDWD WUDQVIHUV)RUPRUHGHWDLOVDERXWELWGDWDWUDQVDFWLRQVUHIHUWR6HFWLRQ 7KHE\WHHQDEOHVDORQHDUHXVHGWRGHWHUPLQHZKLFKE\WHODQHVFDUU\PHDQLQJIXOGDWD 7KHE\WHHQDEOHVDUHIUHHWRFKDQJHEHWZHHQGDWDSKDVHVEXWPXVWEHYDOLGRQWKHFORFN WKDWVWDUWVHDFKGDWDSKDVHDQGPXVWVWD\YDOLGIRUWKHHQWLUHGDWDSKDVH,Q)LJXUH GDWDSKDVHVEHJLQRQFORFNVDQG &KDQJLQJE\WHHQDEOHVGXULQJDUHDGEXUVW WUDQVDFWLRQLVJHQHUDOO\QRWXVHIXOEXWLVSHUPLWWHG 7KHPDVWHULVIUHHWRFKDQJHWKH E\WHHQDEOHVRQHDFKQHZGDWDSKDVH DOWKRXJKWKHUHDGGLDJUDPGRHVQRWVKRZWKLV ,I WKHPDVWHUFKDQJHVE\WHHQDEOHVRQDUHDGWUDQVDFWLRQLWGRHVVRZLWKWKHVDPHWLPLQJDV ZRXOGEHXVHGLQDZULWHWUDQVDFWLRQ,IE\WHHQDEOHVDUHLPSRUWDQWIRUWKHWDUJHWRQD UHDGWUDQVDFWLRQWKHWDUJHWPXVWZDLWIRUWKHE\WHHQDEOHVWREHYDOLGRQHDFKGDWDSKDVH
38 Revision 2.2
EHIRUHFRPSOHWLQJWKHWUDQVIHU RWKHUZLVHLWPXVWUHWXUQDOOE\WHV1RWH %\WHHQDEOHV DUHYDOLGGXULQJWKHHQWLUHGDWDSKDVHLQGHSHQGHQWRIWKHVWDWHRIIRDY# ,IDWDUJHWVXSSRUWVSUHIHWFKLQJ ELWLVVHWLQWKH0HPRU\%DVH$GGUHVVUHJLVWHUUHIHU WR6HFWLRQ LWPXVWDOVRUHWXUQDOOGDWD UHJDUGOHVVRIZKLFKE\WHHQDEOHVDUH DVVHUWHG$WDUJHWFDQRQO\RSHUDWHLQWKLVPRGHZKHQWKHUHDUHQRVLGHHIIHFWV GDWD GHVWUR\HGRUVWDWXVFKDQJHVEHFDXVHRIWKHDFFHVV 3&,DOORZVDQ\FRQWLJXRXVRUQRQFRQWLJXRXVFRPELQDWLRQRIE\WHHQDEOHV,IQRE\WH HQDEOHVDUHDVVHUWHGWKHWDUJHWRIWKHDFFHVVPXVWFRPSOHWHWKHGDWDSKDVHE\DVVHUWLQJ TRDY#DQGSURYLGLQJSDULW\LIWKHWUDQVDFWLRQLVDUHDGUHTXHVW7KHWDUJHWRIDQDFFHVV ZKHUHQRE\WHHQDEOHVDUHDVVHUWHGPXVWFRPSOHWHWKHFXUUHQWGDWDSKDVHZLWKRXWDQ\ VWDWHFKDQJH2QDUHDGWUDQVDFWLRQWKLVPHDQVWKDWGDWDDQGVWDWXVDUHQRWFKDQJHG,I FRPSOHWLQJWKHDFFHVVKDVQRDIIHFWRQWKHGDWDRUVWDWXVWKHWDUJHWPD\FRPSOHWHWKH DFFHVVE\HLWKHUSURYLGLQJGDWDRUQRW7KHJHQHUDWLRQDQGFKHFNLQJRISDULW\LVWKHVDPH UHJDUGOHVVRIWKHVWDWHRIWKHE\WHHQDEOHVIRUERWKELWDQGELWGDWDWUDQVIHUV)RUD GLVFXVVLRQRQSDULW\JHQHUDWLRQDQGFKHFNLQJUHIHUWR6HFWLRQ ELWWUDQVDFWLRQV DQG6HFWLRQ ELWWUDQVDFWLRQV +RZHYHUVRPHWDUJHWVPD\QRWEHDEOHWRSURSHUO\LQWHUSUHWQRQFRQWLJXRXVSDWWHUQV HJH[SDQVLRQEXVEULGJHVWKDWLQWHUIDFHWRDQGELWGHYLFHV ([SDQVLRQEXV EULGJHVPD\RSWLRQDOO\UHSRUWSDWWHUQVWKDWDUHLOOHJDORQWKHH[SDQVLRQEXVDVDQ DV\QFKURQRXVHUURU SERR# RUEUHDNWKHWUDQVDFWLRQLQWRVPDOOHUWUDQVDFWLRQVWKDWDUH OHJDOIRUWKHLQWHQGHGDJHQW7KHWDUJHWRIDQ,2WUDQVDFWLRQLVUHTXLUHGWRVLJQDO7DUJHW $ERUWLILWLVXQDEOHWRFRPSOHWHWKHHQWLUHDFFHVVGHILQHGE\WKHE\WHHQDEOHV
3.2.4. Bus Driving and Turnaround
$WXUQDURXQGF\FOHLVUHTXLUHGRQDOOVLJQDOVWKDWDUHGULYHQE\PRUHWKDQRQHDJHQW 7KHWXUQDURXQGF\FOHLVUHTXLUHGWRDYRLGFRQWHQWLRQZKHQRQHDJHQWVWRSVGULYLQJD VLJQDODQGDQRWKHUDJHQWEHJLQVGULYLQJWKHVLJQDO7KLVLVLQGLFDWHGRQWKHWLPLQJ GLDJUDPVDVWZRDUURZVSRLQWLQJDWHDFKRWKHUV WDLO7KLVWXUQDURXQGF\FOHRFFXUVDW GLIIHUHQWWLPHVIRUGLIIHUHQWVLJQDOV)RULQVWDQFHIRDY#TRDY#DEVSEL# STOP#DQGACK64#XVHWKHDGGUHVVSKDVHDVWKHLUWXUQDURXQGF\FOHFRAME# REQ64#C/BE[3::0]#C/BE[7::4]#AD[31::00]DQGAD[63::32]XVHWKH,GOHVWDWH EHWZHHQWUDQVDFWLRQVDVWKHLUWXUQDURXQGF\FOH7KHWXUQDURXQGF\FOHIRULOCK#RFFXUV RQHFORFNDIWHUWKHFXUUHQWRZQHUUHOHDVHVLWPERR#KDVDWXUQDURXQGF\FOHRQWKH IRXUWKFORFNDIWHUWKHODVWGDWDSKDVHZKLFKLVWKUHHFORFNVDIWHUWKHWXUQDURXQGF\FOHIRU WKHADOLQHV$Q,GOHVWDWHLVZKHQERWKFRAME#DQGIRDY#DUHGHDVVHUWHG HJ FORFN LQ)LJXUH $OOADOLQHV LQFOXGLQJAD[63::32]ZKHQWKHPDVWHUVXSSRUWVDELWGDWDSDWK PXVW EHGULYHQWRVWDEOHYDOXHVGXULQJELWWUDQVIHUVHYHU\DGGUHVVDQGGDWDSKDVH(YHQ E\WHODQHVQRWLQYROYHGLQWKHFXUUHQWGDWDWUDQVIHUPXVWSK\VLFDOO\GULYHVWDEOH DOEHLW PHDQLQJOHVV GDWDRQWRWKHEXV7KHPRWLYDWLRQLVIRUSDULW\FDOFXODWLRQVDQGWRNHHS LQSXWEXIIHUVRQE\WHODQHVQRWLQYROYHGLQWKHWUDQVIHUIURPVZLWFKLQJDWWKHWKUHVKROG OHYHODQGPRUHJHQHUDOO\WRIDFLOLWDWHIDVWPHWDVWDELOLW\IUHHODWFKLQJ,QSRZHUVHQVLWLYH DSSOLFDWLRQVLWLVUHFRPPHQGHGWKDWLQWKHLQWHUHVWRIPLQLPL]LQJEXVVZLWFKLQJSRZHU FRQVXPSWLRQE\WHODQHVQRWEHLQJXVHGLQWKHFXUUHQWEXVSKDVHVKRXOGEHGULYHQZLWK WKHVDPHGDWDDVFRQWDLQHGLQWKHSUHYLRXVEXVSKDVH,QDSSOLFDWLRQVWKDWDUHQRWSRZHU
17 For a 32-bit data transfer, this means 4 bytes per data phase; for a 64-bit data transfer, this means 8 bytes per data phase.
39 Revision 2.2
VHQVLWLYHWKHDJHQWGULYLQJWKHADOLQHVPD\GULYHZKDWHYHULWGHVLUHVRQXQXVHGE\WH ODQHV3DULW\PXVWEHFDOFXODWHGRQDOOE\WHVUHJDUGOHVVRIWKHE\WHHQDEOHV
3.2.5. Transaction Ordering and Posting
7UDQVDFWLRQRUGHULQJUXOHVRQ3&,DFFRPSOLVKWKUHHWKLQJV)LUVWWKH\VDWLVI\WKHZULWH UHVXOWVRUGHULQJUHTXLUHPHQWVRIWKH3URGXFHU&RQVXPHU0RGHO7KLVPHDQVWKDWWKH UHVXOWVRIZULWHVIURPRQHPDVWHU WKH3URGXFHU DQ\ZKHUHLQWKHV\VWHPDUHREVHUYDEOH E\DQRWKHUPDVWHU WKH&RQVXPHU DQ\ZKHUHLQWKHV\VWHPRQO\LQWKHLURULJLQDORUGHU 'LIIHUHQWPDVWHUV 3URGXFHUV LQGLIIHUHQWSODFHVLQWKHV\VWHPKDYHQRIXQGDPHQWDO QHHGIRUWKHLUZULWHVWRKDSSHQLQDSDUWLFXODURUGHUZLWKUHVSHFWWRHDFKRWKHUVLQFHHDFK ZLOOKDYHDGLIIHUHQW&RQVXPHU,QWKLVFDVHWKHUXOHVDOORZIRUVRPHZULWHVWREH UHDUUDQJHG 5HIHUWR$SSHQGL[(IRUDFRPSOHWHGLVFXVVLRQRIWKH3URGXFHU&RQVXPHU 0RGHO6HFRQGWKH\DOORZIRUVRPHWUDQVDFWLRQVWREHSRVWHGWRLPSURYHSHUIRUPDQFH $QGWKLUGWKH\SUHYHQWEXVGHDGORFNFRQGLWLRQVZKHQSRVWLQJEXIIHUVKDYHWREHIOXVKHG WRPHHWWKHILUVWUHTXLUHPHQW 7KHRUGHUUHODWLRQVKLSRIDJLYHQWUDQVDFWLRQZLWKUHVSHFWWRRWKHUWUDQVDFWLRQVLV GHWHUPLQHGZKHQLWFRPSOHWHV LHZKHQGDWDLVWUDQVIHUUHG7UDQVDFWLRQVZKLFK WHUPLQDWHZLWK5HWU\KDYHQRWFRPSOHWHGVLQFHQRGDWDZDVWUDQVIHUUHGDQGWKHUHIRUH KDYHQRRUGHULQJUHTXLUHPHQWVUHODWLYHWRHDFKRWKHU7UDQVDFWLRQVWKDWWHUPLQDWHZLWK 0DVWHU$ERUWRU7DUJHW$ERUWDUHFRQVLGHUHGFRPSOHWHGZLWKRUZLWKRXWGDWDEHLQJ WUDQVIHUUHGDQGZLOOQRWEHUHSHDWHGE\WKHPDVWHU7KHV\VWHPPD\DFFHSWUHTXHVWVLQ DQ\RUGHUFRPSOHWLQJRQHZKLOHFRQWLQXLQJWR5HWU\DQRWKHU,IDPDVWHUUHTXLUHVRQH WUDQVDFWLRQWREHFRPSOHWHGEHIRUHDQRWKHUWKHPDVWHUPXVWQRWDWWHPSWWKHVHFRQG WUDQVDFWLRQXQWLOWKHILUVWRQHLVFRPSOHWH,IDPDVWHUKDVRQO\RQHRXWVWDQGLQJUHTXHVWDW DWLPHWKHQWKDWPDVWHU¶VWUDQVDFWLRQVZLOOFRPSOHWHWKURXJKRXWWKHV\VWHPLQWKHVDPH RUGHUWKHPDVWHUH[HFXWHGWKHP5HIHUWR6HFWLRQIRUIXUWKHUGLVFXVVLRQRI UHTXHVWRUGHULQJ 7UDQVDFWLRQVFDQEHGLYLGHGLQWRWZRJHQHUDOJURXSVEDVHGRQKRZWKH\DUHKDQGOHGE\ DQLQWHUPHGLDWHDJHQWVXFKDVDEULGJH7KHWZRJURXSVDUHSRVWHGDQGQRQSRVWHG WUDQVDFWLRQV3RVWHGWUDQVDFWLRQVFRPSOHWHDWWKHRULJLQDWLQJGHYLFHEHIRUHWKH\UHDFK WKHLUXOWLPDWHGHVWLQDWLRQ7KHPDVWHUZLOORIWHQSURFHHGZLWKRWKHUZRUNVRPHWLPHV LQFOXGLQJRWKHUEXVWUDQVDFWLRQVEHIRUHWKHSRVWHGWUDQVDFWLRQUHDFKHVLWXOWLPDWH GHVWLQDWLRQ,QHVVHQFHWKHLQWHUPHGLDWHDJHQWRIWKHDFFHVV HJDEULGJH DFFHSWVWKH GDWDRQEHKDOIRIWKHDFWXDOWDUJHWDQGDVVXPHVUHVSRQVLELOLW\IRUHQVXULQJWKDWWKHDFFHVV FRPSOHWHVDWWKHILQDOGHVWLQDWLRQ0HPRU\ZULWHV 0HPRU\:ULWHDQG0HPRU\:ULWH DQG,QYDOLGDWHFRPPDQGV DUHDOORZHGWREHSRVWHGRQWKH3&,EXV 1RQSRVWHGWUDQVDFWLRQVUHDFKWKHLUXOWLPDWHGHVWLQDWLRQEHIRUHFRPSOHWLQJDWWKH RULJLQDWLQJGHYLFH7KHPDVWHUFDQQRWSURFHHGZLWKDQ\RWKHUZRUNXQWLOWKHWUDQVDFWLRQ KDVFRPSOHWHGDWWKHXOWLPDWHGHVWLQDWLRQ LIDGHSHQGHQF\H[LVWV 0HPRU\UHDG WUDQVDFWLRQV 0HPRU\5HDG0HPRU\5HDG/LQHDQG0HPRU\5HDG0XOWLSOH ,2 WUDQVDFWLRQV ,25HDGDQG,2:ULWH DQGFRQILJXUDWLRQWUDQVDFWLRQV &RQILJXUDWLRQ 5HDGDQG&RQILJXUDWLRQ:ULWH DUHQRQSRVWHG H[FHSWDVQRWHGEHORZIRUKRVWEULGJHV 7KHUHDUHWZRFDWHJRULHVRIGHYLFHVZLWKGLIIHUHQWUHTXLUHPHQWVIRUWUDQVDFWLRQRUGHULQJ DQGSRVWLQJ(DFKFDWHJRU\ZLOOEHSUHVHQWHGVHSDUDWHO\
40 Revision 2.2
3.2.5.1. Transaction Ordering and Posting for Simple Devices
$VLPSOHGHYLFHLVDQ\GHYLFHWKDWZKLOHDFWLQJDVDEXVPDVWHUGRHVQRWUHTXLUHLWVZULWH GDWDWREHSRVWHGDWWKHEXVLQWHUIDFHORJLF*HQHUDOO\GHYLFHVWKDWGRQRWFRQQHFWWR ORFDO&38VDUHLPSOHPHQWHGDVVLPSOHGHYLFHV 7KHWDUJHWDQGPDVWHUVWDWHPDFKLQHVLQWKH3&,LQWHUIDFHRIDVLPSOHGHYLFHDUH FRPSOHWHO\LQGHSHQGHQW$VLPSOHGHYLFHFDQQRWPDNHWKHFRPSOHWLRQRIDQ\WUDQVDFWLRQ HLWKHUSRVWHGRUQRQSRVWHG DVDWDUJHWFRQWLQJHQWXSRQWKHSULRUFRPSOHWLRQRIDQ\ RWKHUWUDQVDFWLRQDVDPDVWHU6LPSOHGHYLFHVDUHDOORZHGWRWHUPLQDWHDWUDQVDFWLRQZLWK 5HWU\RQO\WRH[HFXWHWKHWUDQVDFWLRQDVD'HOD\HG7UDQVDFWLRQRUIRUWHPSRUDU\ FRQGLWLRQVZKLFKDUHJXDUDQWHHGWREHUHVROYHGZLWKWLPH HJGXULQJDYLGHRVFUHHQ UHIUHVKRUZKLOHDWUDQVDFWLRQEXIIHULVILOOHGZLWKWUDQVDFWLRQVPRYLQJLQWKHVDPH GLUHFWLRQ 5HIHUWR6HFWLRQIRUDOLPLWRQWKHOHQJWKRIWLPHDPHPRU\ZULWH WUDQVDFWLRQFDQEHWHUPLQDWHGZLWK5HWU\
Implementation Note: Deadlock When Target and Master Not Independent 7KHIROORZLQJLVDQH[DPSOHRIDGHDGORFNWKDWFRXOGRFFXULIGHYLFHVGRQRWPDNHWKHLU WDUJHWDQGPDVWHULQWHUIDFHVLQGHSHQGHQW 6XSSRVHWZRGHYLFHV'HYLFH$DQG'HYLFH%DUHWDONLQJGLUHFWO\WRHDFKRWKHU%RWK GHYLFHVDWWHPSW,2ZULWHVWRHDFKRWKHUVLPXOWDQHRXVO\6XSSRVH'HYLFH$LVJUDQWHG WKHEXVILUVWDQGH[HFXWHVLWV,2ZULWHDGGUHVVLQJ'HYLFH%'HYLFH%GHFRGHVLWV DGGUHVVDQGDVVHUWVDEVSEL#)XUWKHUVXSSRVHWKDW'HYLFH%YLRODWHVWKHUHTXLUHPHQW IRUWKHWDUJHWVWDWHPDFKLQHWREHLQGHSHQGHQWRIWKHPDVWHUVWDWHPDFKLQHDQGDOZD\V WHUPLQDWHVWUDQVDFWLRQVDVDWDUJHWZLWK5HWU\XQWLOLWVPDVWHUVWDWHPDFKLQHFRPSOHWHVLWV RXWVWDQGLQJUHTXHVWV6LQFH'HYLFH%DOVRKDVDQ,2WUDQVDFWLRQLWPXVWH[HFXWHDVD PDVWHULWWHUPLQDWHV'HYLFH$¶VWUDQVDFWLRQZLWK5HWU\ 'HYLFH%LVWKHQJUDQWHGWKHEXVDQG'HYLFH%H[HFXWHVLWV,2ZULWHDGGUHVVLQJ'HYLFH $,I'HYLFH$UHVSRQGVWKHVDPHZD\'HYLFH%GLGWKHV\VWHPZLOOGHDGORFN
41 Revision 2.2
Implementation Note: Deadlock When Posted Write Data is Not Accepted 'HDGORFNVFDQDOVRRFFXUZKHQDGHYLFHGRHVQRWDFFHSWDPHPRU\ZULWHWUDQVDFWLRQ IURPDEULGJH$VGHVFULEHGEHORZDEULGJHLVUHTXLUHGLQFHUWDLQFDVHVWRIOXVKLWV SRVWLQJEXIIHUDVDPDVWHUEHIRUHLWFRPSOHWHVDWUDQVDFWLRQDVDWDUJHW6XSSRVHD3&, WR3&,EULGJHFRQWDLQVSRVWHGPHPRU\ZULWHGDWDDGGUHVVHGWRDGRZQVWUHDPGHYLFH%XW EHIRUHWKHEULGJHFDQDFTXLUHWKHGRZQVWUHDPEXVWRGRWKHZULWHWUDQVDFWLRQD GRZQVWUHDPGHYLFHLQLWLDWHVDUHDGIURPKRVWPHPRU\6LQFHUHTXLUHPHQWLQWKHEULGJH UXOHVSUHVHQWHGEHORZVWDWHVWKDWSRVWLQJEXIIHUVPXVWEHIOXVKHGEHIRUHDUHDG WUDQVDFWLRQFDQEHFRPSOHWHGWKHEULGJHPXVW5HWU\WKHDJHQW¶VUHDGDQGDWWHPSWDZULWH WUDQVDFWLRQ,IWKHGRZQVWUHDPGHYLFHZHUHWRPDNHWKHDFFHSWDQFHRIWKHZULWHGDWD FRQWLQJHQWXSRQWKHSULRUFRPSOHWLRQRIWKHUHWULHGUHDGWUDQVDFWLRQ WKDWLVLILWFRXOG QRWDFFHSWWKHSRVWHGZULWHXQWLOLWILUVWFRPSOHWHGWKHUHDGWUDQVDFWLRQ WKHEXVZRXOGEH GHDGORFNHG 6LQFHFHUWDLQ3&,WR3&,EULGJHGHYLFHVGHVLJQHGWRSUHYLRXVYHUVLRQVRIWKLV VSHFLILFDWLRQUHTXLUHWKHLUSRVWLQJEXIIHUWREHIOXVKHGEHIRUHVWDUWLQJDQ\QRQSRVWHG WUDQVDFWLRQWKHVDPHGHDGORFNFRXOGRFFXULIWKHGRZQVWUHDPGHYLFHPDNHVWKH DFFHSWDQFHRIDSRVWHGZULWHFRQWLQJHQWRQWKHSULRUFRPSOHWLRQRIDQ\QRQSRVWHG WUDQVDFWLRQ
7KHUHTXLUHGLQGHSHQGHQFHRIWDUJHWDQGPDVWHUVWDWHPDFKLQHVLQDVLPSOHGHYLFH LPSOLHVWKDWDVLPSOHGHYLFHFDQQRWLQWHUQDOO\SRVWDQ\RXWERXQGWUDQVDFWLRQV)RU H[DPSOHLIGXULQJWKHFRXUVHRISHUIRUPLQJLWVLQWHQGHGIXQFWLRQDGHYLFHPXVWH[HFXWHD PHPRU\ZULWHDVDPDVWHURQWKH3&,EXVWKHGHYLFHFDQQRWSRVWWKDWPHPRU\ZULWHLQ WKHPDVWHULQWHUIDFHRIWKHGHYLFH0RUHVSHFLILFDOO\WKHGHYLFHFDQQRWSURFHHGWRRWKHU LQWHUQDORSHUDWLRQVVXFKDVXSGDWLQJVWDWXVUHJLVWHUVWKDWZRXOGEHREVHUYDEOHE\DQRWKHU PDVWHULQWKHV\VWHP7KHVLPSOHGHYLFHPXVWZDLWXQWLOWKHPHPRU\ZULWHWUDQVDFWLRQ FRPSOHWHVRQWKH3&,EXV TRDY# DVVHUWHG 0DVWHU$ERUWRU7DUJHW$ERUW EHIRUH SURFHHGLQJLQWHUQDOO\ 6LPSOHGHYLFHVDUHVWURQJO\HQFRXUDJHGWRSRVWLQERXQGPHPRU\ZULWHWUDQVDFWLRQVWR VSHHGWKHWUDQVDFWLRQRQWKH3&,EXV+RZVXFKDGHYLFHGHDOVZLWKRUGHULQJRILQERXQG SRVWHGZULWHGDWDLVVWULFWO\LPSOHPHQWDWLRQGHSHQGHQWDQGEH\RQGWKHVFRSHRIWKLV VSHFLILFDWLRQ 6LPSOHGHYLFHVGRQRWVXSSRUWH[FOXVLYHDFFHVVHVDQGGRQRWXVHWKHLOCK# VLJQDO 5HIHUWR$SSHQGL[)IRUDGLVFXVVLRQRIWKHXVHRILOCK#LQEULGJHGHYLFHV
3.2.5.2. Transaction Ordering and Posting for Bridges
$EULGJHGHYLFHLVDQ\GHYLFHWKDWLPSOHPHQWVLQWHUQDOSRVWLQJRIRXWERXQGPHPRU\ ZULWHWUDQVDFWLRQVLHZULWHWUDQVDFWLRQVWKDWPXVWEHH[HFXWHGE\WKHGHYLFHDVDPDVWHU RQWKH3&,EXV%ULGJHVQRUPDOO\MRLQWZREXVHVVXFKDVWZR3&,EXVHVDKRVWEXVDQGD 3&,EXVRUD3&,EXVDQGDEXVIRUDORFDO&38 LHDSHULSKHUDO&38
42 Revision 2.2
%ULGJHVDUHSHUPLWWHGWRSRVWPHPRU\ZULWHWUDQVDFWLRQVPRYLQJLQHLWKHUGLUHFWLRQ WKURXJKWKHEULGJH7KHIROORZLQJRUGHULQJUXOHVJXDUDQWHHWKDWWKHUHVXOWVRIRQH PDVWHU¶VZULWHWUDQVDFWLRQVDUHREVHUYDEOHE\RWKHUPDVWHUVLQWKHSURSHURUGHUHYHQ WKRXJKWKHZULWHWUDQVDFWLRQPD\EHSRVWHGLQDEULGJH7KH\DOVRJXDUDQWHHWKDWWKHEXV GRHVQRWGHDGORFNZKHQDEULGJHWULHVWRHPSW\LWVSRVWLQJEXIIHUV • 3RVWHGPHPRU\ZULWHVPRYLQJLQWKHVDPHGLUHFWLRQWKURXJKDEULGJHZLOOFRPSOHWH RQWKHGHVWLQDWLRQEXVLQWKHVDPHRUGHUWKH\FRPSOHWHRQWKHRULJLQDWLQJEXV(YHQ LIDVLQJOHEXUVWRQWKHRULJLQDWLQJEXVLVWHUPLQDWHGZLWK'LVFRQQHFWRQWKH GHVWLQDWLRQEXVVRWKDWLWLVEURNHQLQWRPXOWLSOHWUDQVDFWLRQVWKRVHWUDQVDFWLRQVPXVW QRWDOORZWKHGDWDSKDVHVWRFRPSOHWHRQWKHGHVWLQDWLRQEXVLQDQ\RUGHURWKHUWKDQ WKHLURUGHURQWKHRULJLQDWLQJEXV • :ULWHWUDQVDFWLRQVIORZLQJLQRQHGLUHFWLRQWKURXJKDEULGJHKDYHQRRUGHULQJ UHTXLUHPHQWVZLWKUHVSHFWWRZULWHVIORZLQJLQWKHRWKHUGLUHFWLRQWKURXJKWKHEULGJH • 3RVWHGPHPRU\ZULWHEXIIHUVLQERWKGLUHFWLRQVPXVWEHIOXVKHGEHIRUHFRPSOHWLQJD UHDGWUDQVDFWLRQLQHLWKHUGLUHFWLRQ3RVWHGPHPRU\ZULWHVRULJLQDWLQJRQWKHVDPH VLGHRIWKHEULGJHDVDUHDGWUDQVDFWLRQDQGFRPSOHWLQJEHIRUHWKHUHDGFRPPDQG FRPSOHWHVRQWKHRULJLQDWLQJEXVPXVWFRPSOHWHRQWKHGHVWLQDWLRQEXVLQWKHVDPH RUGHU3RVWHGPHPRU\ZULWHVRULJLQDWLQJRQWKHRSSRVLWHVLGHRIWKHEULGJHIURPD UHDGWUDQVDFWLRQDQGFRPSOHWLQJRQWKHUHDGGHVWLQDWLRQEXVEHIRUHWKHUHDG FRPPDQGFRPSOHWHVRQWKHUHDGGHVWLQDWLRQEXVPXVWFRPSOHWHRQWKHUHDGRULJLQ EXVLQWKHVDPHRUGHU,QRWKHUZRUGVDUHDGWUDQVDFWLRQPXVWSXVKDKHDGRILW WKURXJKWKHEULGJHDQ\SRVWHGZULWHVRULJLQDWLQJRQWKHVDPHVLGHRIWKHEULGJHDQG SRVWHGEHIRUHWKHUHDG,QDGGLWLRQEHIRUHWKHUHDGWUDQVDFWLRQFDQFRPSOHWHRQLWV RULJLQDWLQJEXVLWPXVWSXOORXWRIWKHEULGJHDQ\SRVWHGZULWHVWKDWRULJLQDWHGRQWKH RSSRVLWHVLGHDQGZHUHSRVWHGEHIRUHWKHUHDGFRPPDQGFRPSOHWHVRQWKHUHDG GHVWLQDWLRQEXV • $EULGJHFDQQHYHUPDNHWKHDFFHSWDQFH SRVWLQJ RIDPHPRU\ZULWHWUDQVDFWLRQDVD WDUJHWFRQWLQJHQWRQWKHSULRUFRPSOHWLRQRIDQRQORFNHGWUDQVDFWLRQDVDPDVWHURQ WKHVDPHEXV$EULGJHFDQPDNHWKHDFFHSWDQFHRIDPHPRU\ZULWHWUDQVDFWLRQDVD WDUJHWFRQWLQJHQWRQWKHSULRUFRPSOHWLRQRIDORFNHGWUDQVDFWLRQDVDPDVWHURQO\LI WKHEULGJHKDVDOUHDG\HVWDEOLVKHGDORFNHGRSHUDWLRQZLWKLWVLQWHQGHGWDUJHW RWKHUZLVHDGHDGORFNPD\RFFXU 5HIHUWR$SSHQGL[)IRUDGLVFXVVLRQRIWKHXVH RILOCK#LQEULGJHGHYLFHV ,QDOORWKHUFDVHVEULGJHVDUHDOORZHGWRUHIXVHWR DFFHSWDPHPRU\ZULWHRQO\IRUWHPSRUDU\FRQGLWLRQVZKLFKDUHJXDUDQWHHGWREH UHVROYHGZLWKWLPHHJGXULQJDYLGHRVFUHHQUHIUHVKRUZKLOHWKHPHPRU\EXIIHULV ILOOHGE\SUHYLRXVPHPRU\ZULWHWUDQVDFWLRQVPRYLQJLQWKHVDPHGLUHFWLRQ +RVWEXVEULGJHVDUHSHUPLWWHGWRSRVW,2ZULWHWUDQVDFWLRQVWKDWRULJLQDWHRQWKHKRVW EXVDQGFRPSOHWHRQD3&,EXVVHJPHQWZKHQWKH\IROORZWKHRUGHULQJUXOHVGHVFULEHGLQ WKLVVSHFLILFDWLRQDQGGRQRWFDXVHDGHDGORFN7KLVPHDQVWKDWZKHQDKRVWEXVEULGJH SRVWVDQ,2ZULWHWUDQVDFWLRQWKDWRULJLQDWHGRQWKHKRVWEXVLWPXVWSURYLGHDGHDGORFN IUHHHQYLURQPHQWZKHQWKHWUDQVDFWLRQFRPSOHWHVRQ3&,7KHWUDQVDFWLRQZLOOFRPSOHWH RQWKHGHVWLQDWLRQ3&,EXVEHIRUHFRPSOHWLQJRQWKHRULJLQDWLQJ3&,EXV 6LQFHPHPRU\ZULWHWUDQVDFWLRQVPD\EHSRVWHGLQEULGJHVDQ\ZKHUHLQWKHV\VWHPDQG ,2ZULWHVPD\EHSRVWHGLQWKHKRVWEXVEULGJHDPDVWHUFDQQRWDXWRPDWLFDOO\WHOOZKHQ LWVZULWHWUDQVDFWLRQFRPSOHWHVDWWKHILQDOGHVWLQDWLRQ)RUDGHYLFHGULYHUWRJXDUDQWHH WKDWDZULWHKDVFRPSOHWHGDWWKHDFWXDOWDUJHW DQGQRWDWDQLQWHUPHGLDWHEULGJH LWPXVW FRPSOHWHDUHDGWRWKHVDPHGHYLFHWKDWWKHZULWHWDUJHWHG7KHUHDG PHPRU\RU,2 IRUFHVDOOEULGJHVEHWZHHQWKHRULJLQDWLQJPDVWHUDQGWKHDFWXDOWDUJHWWRIOXVKDOOSRVWHG
43 Revision 2.2
GDWDEHIRUHDOORZLQJWKHUHDGWRFRPSOHWH)RUDGGLWLRQDOGHWDLOVRQGHYLFHGULYHUVUHIHU WR6HFWLRQ5HIHUWR6HFWLRQLWHPIRURWKHUFDVHVZKHUHDUHDGLVQHFHVVDU\ ,QWHUUXSWUHTXHVWV WKDWXVHINTx# GRQRWDSSHDUDVWUDQVDFWLRQVRQWKH3&,EXV WKH\DUH VLGHEDQGVLJQDOV DQGWKHUHIRUHKDYHQRRUGHULQJUHODWLRQVKLSWRDQ\EXVWUDQVDFWLRQV )XUWKHUPRUHWKHV\VWHPLVQRWUHTXLUHGWRXVHWKH,QWHUUXSW$FNQRZOHGJHEXVWUDQVDFWLRQ WRVHUYLFHLQWHUUXSWV6RLQWHUUXSWVDUHQRWV\QFKURQL]LQJHYHQWVDQGGHYLFHGULYHUV FDQQRWGHSHQGRQWKHPWRIOXVKSRVWLQJEXIIHUV+RZHYHUZKHQ06,DUHXVHGWKH\ KDYHWKHVDPHRUGHULQJUXOHVDVDPHPRU\ZULWHWUDQVDFWLRQ UHIHUWR6HFWLRQIRU PRUHLQIRUPDWLRQ
3.2.6. Combining, Merging, and Collapsing
8QGHUFHUWDLQFRQGLWLRQVEULGJHVWKDWUHFHLYH ZULWH GDWDPD\DWWHPSWWRFRQYHUWD WUDQVDFWLRQ ZLWKDVLQJOHRUPXOWLSOHGDWDSKDVHV LQWRDODUJHUWUDQVDFWLRQWRRSWLPL]H WKHGDWDWUDQVIHURQ3&,7KHWHUPVXVHGZKHQGHVFULELQJWKHDFWLRQDUH FRPELQLQJ PHUJLQJDQGFROODSVLQJ(DFKWHUPZLOOEHGHILQHGDQGWKHXVDJHIRUEULGJHV KRVW3&, WR3&,RUVWDQGDUGH[SDQVLRQEXV ZLOOEHGLVFXVVHG &RPELQLQJRFFXUVZKHQVHTXHQWLDOPHPRU\ZULWHWUDQVDFWLRQV VLQJOHGDWDSKDVHRU EXUVWDQGLQGHSHQGHQWRIDFWLYHE\WHHQDEOHV DUHFRPELQHGLQWRDVLQJOH3&,EXV WUDQVDFWLRQ XVLQJOLQHDUEXUVWRUGHULQJ 7KHFRPELQLQJRIGDWDLVQRWUHTXLUHGEXWLVUHFRPPHQGHGZKHQHYHUSRVWLQJRIZULWH GDWDLVEHLQJGRQH&RPELQLQJLVSHUPLWWHGRQO\ZKHQWKHLPSOLHGRUGHULQJLVQRW FKDQJHG,PSOLHGRUGHULQJPHDQVWKDWWKHWDUJHWVHHVWKHGDWDLQWKHVDPHRUGHUDVWKH RULJLQDOPDVWHUJHQHUDWHGLW)RUH[DPSOHDZULWHVHTXHQFHRI':25'DQGFDQ EHFRQYHUWHGLQWRDEXUVWVHTXHQFH+RZHYHUDZULWHRI':25'DQGFDQQRWEH FRPELQHGLQWRDEXUVWEXWPXVWDSSHDURQ3&,DVWKUHHVHSDUDWHWUDQVDFWLRQVLQWKHVDPH RUGHUDVWKH\RFFXUUHGRULJLQDOO\%XUVWVPD\LQFOXGHGDWDSKDVHVWKDWKDYHQRE\WH HQDEOHVDVVHUWHG)RUH[DPSOHWKHVHTXHQFH':25'DQGFRXOGEHFRPELQHG LQWRDEXUVWLQZKLFKGDWDSKDVHFRQWDLQVWKHGDWDDQGE\WHHQDEOHVSURYLGHGZLWK ':25'7KHVHFRQGGDWDSKDVHRIWKHEXUVWXVHVGDWDDQGE\WHHQDEOHVSURYLGHGZLWK ':25'ZKLOHGDWDSKDVHDVVHUWVQRE\WHHQDEOHVDQGSURYLGHVQRPHDQLQJIXOGDWD 7KHEXUVWFRPSOHWHVZLWKGDWDSKDVHXVLQJGDWDDQGE\WHHQDEOHVSURYLGHGZLWK ':25' ,IWKHWDUJHWLVXQDEOHWRKDQGOHPXOWLSOHGDWDSKDVHVIRUDVLQJOHWUDQVDFWLRQLWWHUPLQDWHV WKHEXUVWWUDQVDFWLRQZLWK'LVFRQQHFWZLWKRUDIWHUHDFKGDWDSKDVH7KHWDUJHWVHHVWKH GDWDLQWKHVDPHRUGHUWKHRULJLQDWLQJPDVWHUJHQHUDWHGLWZKHWKHUWKHWUDQVDFWLRQZDV RULJLQDOO\JHQHUDWHGDVDEXUVWRUDVDVHULHVRIVLQJOHGDWDSKDVHDFFHVVHVZKLFKZHUH FRPELQHGLQWRDEXUVW %\WH0HUJLQJRFFXUVZKHQDVHTXHQFHRILQGLYLGXDOPHPRU\ZULWHV E\WHVRUZRUGV DUHPHUJHGLQWRDVLQJOH':25' 7KHPHUJLQJRIE\WHVZLWKLQWKHVDPH':25'IRUELWWUDQVIHUVRU48$':25' HLJKWE\WHV IRUELWWUDQVIHUVLVQRWUHTXLUHGEXWLVUHFRPPHQGHGZKHQSRVWLQJRI ZULWHGDWDLVGRQH%\WHPHUJLQJLVSHUPLWWHGRQO\ZKHQWKHE\WHVZLWKLQDGDWDSKDVH DUHLQDSUHIHWFKDEOHDGGUHVVUDQJH:KLOHVLPLODUWRFRPELQLQJLQFRQFHSWPHUJLQJFDQ EHGRQHLQDQ\RUGHU ZLWKLQWKHVDPHGDWDSKDVH DVORQJDVHDFKE\WHLVRQO\ZULWWHQ RQFH)RUH[DPSOHLQDVHTXHQFHZKHUHE\WHVDQGDUHZULWWHQWRWKHVDPH ':25'DGGUHVVWKHEULGJHFRXOGPHUJHWKHPLQWRDVLQJOHGDWDSKDVHPHPRU\ZULWHRQ 3&,ZLWK%\WH(QDEOHDQGDOODVVHUWHGLQVWHDGRIIRXULQGLYLGXDOZULWH WUDQVDFWLRQV+RZHYHULIWKHVHTXHQFHZULWWHQWRWKHVDPH':25'DGGUHVVZHUH
44 Revision 2.2
E\WHDQGE\WHDJDLQ ZLWKWKHVDPHRUGLIIHUHQWGDWD E\WHDQGE\WHWKHEULGJH FDQQRWPHUJHWKHILUVWWZRZULWHVLQWRDVLQJOHGDWDSKDVHEHFDXVHWKHVDPHE\WHORFDWLRQ PXVWEHZULWWHQWZLFH+RZHYHUWKHODVWWKUHHWUDQVDFWLRQVFRXOGEHPHUJHGLQWRDVLQJOH GDWDSKDVHZLWK%\WH(QDEOHEHLQJGHDVVHUWHGDQG%\WH(QDEOHDQGEHLQJ DVVHUWHG0HUJLQJFDQQHYHUEHGRQHWRDUDQJHRI,2RU0HPRU\0DSSHG,2DGGUHVVHV QRWSUHIHWFKDEOH 1RWH 0HUJLQJDQGFRPELQLQJFDQEHGRQHLQGHSHQGHQWO\RIHDFKRWKHU%\WHVZLWKLQD ':25'PD\EHPHUJHGDQGPHUJHG':25'VFDQEHFRPELQHGZLWKRWKHU':25'V ZKHQFRQGLWLRQVDOORZ$GHYLFHFDQLPSOHPHQWRQO\E\WHPHUJLQJRQO\FRPELQLQJ ERWKE\WHPHUJLQJDQGFRPELQLQJRUQHLWKHUE\WHPHUJLQJRUFRPELQLQJ &ROODSVLQJLVZKHQDVHTXHQFHRIPHPRU\ZULWHVWRWKHVDPHORFDWLRQ E\WHZRUGRU ':25'DGGUHVV DUHFROODSVHGLQWRDVLQJOHEXVWUDQVDFWLRQ &ROODSVLQJLVQRWSHUPLWWHGE\3&,EULGJHV KRVW3&,WR3&,RUVWDQGDUGH[SDQVLRQ H[FHSWDVQRWHGEHORZ)RUH[DPSOHDPHPRU\ZULWHWUDQVDFWLRQZLWK%\WH(QDEOH DVVHUWHGWR':25'DGGUHVV;IROORZHGE\DPHPRU\ZULWHDFFHVVWRWKHVDPHDGGUHVV ; DVDE\WHZRUGRU':25'RUDQ\RWKHUFRPELQDWLRQRIE\WHVDOORZHGE\3&, ZKHUH%\WH(QDEOHLVDVVHUWHGFDQQRWEHPHUJHGLQWRDVLQJOH3&,WUDQVDFWLRQ7KHVH WZRDFFHVVHVPXVWDSSHDURQ3&,DVWZRVHSDUDWHDQGGLVWLQFWWUDQVDFWLRQV 1RWH 7KHFRPELQLQJDQGPHUJLQJRI,2DQG&RQILJXUDWLRQWUDQVDFWLRQVDUHQRW DOORZHG7KHFROODSVLQJRIGDWDRIDQ\W\SHRIWUDQVDFWLRQ &RQILJXUDWLRQ0HPRU\RU ,2 LVQHYHUDOORZHG H[FHSWZKHUHQRWHGEHORZ 1RWH ,IDGHYLFHFDQQRWWROHUDWHPHPRU\ZULWHFRPELQLQJLWKDVEHHQGHVLJQHG LQFRUUHFWO\,IDGHYLFHFDQQRWWROHUDWHPHPRU\ZULWHE\WHPHUJLQJLWPXVWPDUNLWVHOIDV QRWSUHIHWFKDEOH 5HIHUWR6HFWLRQIRUDGHVFULSWLRQRISUHIHWFKDEOH $GHYLFH WKDWPDUNVLWVHOISUHIHWFKDEOHPXVWWROHUDWHFRPELQLQJ ZLWKRXWUHRUGHULQJ DQGE\WH PHUJLQJ ZLWKRXWFROODSVLQJ RIZULWHVDVGHVFULEHGSUHYLRXVO\$GHYLFHLVH[SOLFLWO\ QRWUHTXLUHGWRWROHUDWHUHRUGHULQJRI':25'VRUFROODSVLQJRIGDWD$SUHIHWFKDEOH DGGUHVVUDQJHPD\KDYHZULWHVLGHHIIHFWVEXWLWPD\QRWKDYHUHDGVLGHHIIHFWV$ EULGJH KRVWEXV3&,WR3&,RUVWDQGDUGH[SDQVLRQEXV FDQQRWUHRUGHU':25'VLQ DQ\VSDFHHYHQLQDSUHIHWFKDEOHVSDFH %ULGJHVPD\RSWLRQDOO\DOORZGDWDWREHFROODSVHGLQDVSHFLILFDGGUHVVUDQJHZKHQD GHYLFHGULYHULQGLFDWHVWKDWWKHUHDUHQRDGYHUVHVLGHHIIHFWVGXHWRFROODSVLQJ+RZD GHYLFHGULYHULQGLFDWHVWKLVWRWKHV\VWHPLVEH\RQGWKHVFRSHRIWKLVVSHFLILFDWLRQ
45 Revision 2.2
Implementation Note: Combining, Merging, and Collapsing %ULGJHVWKDWSRVWPHPRU\ZULWHGDWDVKRXOGFRQVLGHULPSOHPHQWLQJ&RPELQLQJDQG%\WH 0HUJLQJ7KHFROODSVLQJRIPXOWLSOHPHPRU\ZULWHWUDQVDFWLRQVLQWRDVLQJOH3&,EXV WUDQVDFWLRQLVQHYHUDOORZHG H[FHSWDVQRWHGDERYH 7KHFRPELQLQJRIVHTXHQWLDO ':25'PHPRU\ZULWHVLQWRD3&,EXUVWKDVVLJQLILFDQWSHUIRUPDQFHEHQHILWV)RU H[DPSOHDSURFHVVRULVGRLQJDODUJHQXPEHURI':25'ZULWHVWRDIUDPHEXIIHU:KHQ WKHKRVWEXVEULGJHFRPELQHVWKHVHDFFHVVHVLQWRDVLQJOH3&,WUDQVDFWLRQWKH3&,EXV FDQNHHSXSZLWKDKRVWEXVWKDWLVUXQQLQJIDVWHUDQGRUZLGHUWKDQ3&, 7KHPHUJLQJRIE\WHVZLWKLQDVLQJOH':25'SURYLGHVDSHUIRUPDQFHLPSURYHPHQWEXW QRWDVVLJQLILFDQWDVFRPELQLQJ+RZHYHUIRUXQDOLJQHGPXOWLE\WHGDWDWUDQVIHUV PHUJLQJDOORZVWKHKRVWEULGJHWRPHUJHPLVDOLJQHGGDWDLQWRVLQJOH':25'PHPRU\ ZULWHWUDQVDFWLRQV7KLVUHGXFHV DWDPLQLPXP WKHQXPEHURI3&,WUDQVDFWLRQVE\D IDFWRURIWZR:KHQWKHEULGJHPHUJHVE\WHVLQWRD':25'DQGWKHQFRPELQHV ':25'VLQWRDEXUVWWKHQXPEHURIWUDQVDFWLRQVRQ3&,FDQEHUHGXFHGHYHQIXUWKHU WKDQMXVWE\PHUJLQJ:LWKWKHDGGLWLRQRIFRPELQLQJVHTXHQWLDO':25'VWKHQXPEHU RIWUDQVDFWLRQVRQ3&,FDQEHUHGXFHGHYHQIXUWKHU0HUJLQJGDWD ':25'V ZLWKLQD VLQJOHFDFKHOLQHDSSHDUVWRKDYHPLQLPDOSHUIRUPDQFHJDLQV
3.3. Bus Transactions 7KHWLPLQJGLDJUDPVLQWKLVVHFWLRQVKRZWKHUHODWLRQVKLSRIVLJQLILFDQWVLJQDOVLQYROYHG LQELWWUDQVDFWLRQV:KHQDVLJQDOLVGUDZQDVDVROLGOLQHLWLVDFWLYHO\EHLQJGULYHQ E\WKHFXUUHQWPDVWHURUWDUJHW:KHQDVLJQDOLVGUDZQDVDGDVKHGOLQHQRDJHQWLV DFWLYHO\GULYLQJLW+RZHYHULWPD\VWLOOEHDVVXPHGWRFRQWDLQDVWDEOHYDOXHLIWKH GDVKHGOLQHLVDWWKHKLJKUDLO7ULVWDWHGVLJQDOVDUHLQGLFDWHGWRKDYHLQGHWHUPLQDWH YDOXHVZKHQWKHGDVKHGOLQHLVEHWZHHQWKHWZRUDLOV HJADRUC/BE#OLQHV :KHQD VROLGOLQHEHFRPHVDGRWWHGOLQHLWLQGLFDWHVWKHVLJQDOZDVDFWLYHO\GULYHQDQGQRZLVWUL VWDWHG:KHQDVROLGOLQHPDNHVDORZWRKLJKWUDQVLWLRQDQGWKHQEHFRPHVDGRWWHGOLQH LWLQGLFDWHVWKHVLJQDOZDVDFWLYHO\GULYHQKLJKWRSUHFKDUJHWKHEXVDQGWKHQWULVWDWHG 7KHF\FOHVEHIRUHDQGDIWHUHDFKWUDQVDFWLRQZLOOEHGLVFXVVHGLQ6HFWLRQ
46 Revision 2.2
3.3.1. Read Transaction
)LJXUHLOOXVWUDWHVDUHDGWUDQVDFWLRQDQGVWDUWVZLWKDQDGGUHVVSKDVHZKLFKRFFXUV ZKHQFRAME#LVDVVHUWHGIRUWKHILUVWWLPHDQGRFFXUVRQFORFN'XULQJWKHDGGUHVV SKDVHAD[31::00]FRQWDLQDYDOLGDGGUHVVDQGC/BE[3::0]#FRQWDLQDYDOLGEXV FRPPDQG
CLK 1 2 3 4 5 6 7 8 9
FRAME#
AD ADDRESS DATA-1 DATA-2 DATA-3
C/BE# BUS CMD BE#'s
IRDY# WAIT WAIT TRDY# WAIT WAIT DATA TRANSFER DATA DATA TRANSFER DATA TRANSFER
DEVSEL#
ADDRESS DATA DATA DATA PHASE PHASE PHASE PHASE BUS TRANSACTION
)LJXUH %DVLF5HDG2SHUDWLRQ
7KHILUVWFORFNRIWKHILUVWGDWDSKDVHLVFORFN'XULQJWKHGDWDSKDVHC/BE#LQGLFDWH ZKLFKE\WHODQHVDUHLQYROYHGLQWKHFXUUHQWGDWDSKDVH$GDWDSKDVHPD\FRQVLVWRI ZDLWF\FOHVDQGDGDWDWUDQVIHU7KHC/BE#RXWSXWEXIIHUVPXVWUHPDLQHQDEOHG IRU ERWKUHDGDQGZULWHV IURPWKHILUVWFORFNRIWKHGDWDSKDVHWKURXJKWKHHQGRIWKH WUDQVDFWLRQ7KLVHQVXUHVC/BE#DUHQRWOHIWIORDWLQJIRUORQJLQWHUYDOV7KHC/BE# OLQHVFRQWDLQYDOLGE\WHHQDEOHLQIRUPDWLRQGXULQJWKHHQWLUHGDWDSKDVHLQGHSHQGHQWRI WKHVWDWHRIIRDY#7KHC/BE#OLQHVFRQWDLQWKHE\WHHQDEOHLQIRUPDWLRQIRUGDWDSKDVH 1RQWKHFORFNIROORZLQJWKHFRPSOHWLRQRIWKHGDWDSKDVH17KLVLVQRWVKRZQLQ )LJXUHEHFDXVHDEXUVWUHDGWUDQVDFWLRQW\SLFDOO\KDVDOOE\WHHQDEOHVDVVHUWHG KRZHYHULWLVVKRZQLQ)LJXUH1RWLFHRQFORFNLQ)LJXUHWKHPDVWHULQVHUWHGD ZDLWVWDWHE\GHDVVHUWLQJIRDY#+RZHYHUWKHE\WHHQDEOHVIRUGDWDSKDVHDUHYDOLG RQFORFNDQGUHPDLQYDOLGXQWLOWKHGDWDSKDVHFRPSOHWHVRQFORFN 7KHILUVWGDWDSKDVHRQDUHDGWUDQVDFWLRQUHTXLUHVDWXUQDURXQGF\FOH HQIRUFHGE\WKH WDUJHWYLDTRDY# ,QWKLVFDVHWKHDGGUHVVLVYDOLGRQFORFNDQGWKHQWKHPDVWHUVWRSV GULYLQJAD7KHHDUOLHVWWKHWDUJHWFDQSURYLGHYDOLGGDWDLVFORFN7KHWDUJHWPXVW GULYHWKHADOLQHVIROORZLQJWKHWXUQDURXQGF\FOHZKHQDEVSEL#LVDVVHUWHG2QFH HQDEOHGWKHRXWSXWEXIIHUVPXVWVWD\HQDEOHGWKURXJKWKHHQGRIWKHWUDQVDFWLRQ 7KLV HQVXUHVWKDWWKHADOLQHVDUHQRWOHIWIORDWLQJIRUORQJLQWHUYDOV 2QHZD\IRUDGDWDSKDVHWRFRPSOHWHLVZKHQGDWDLVWUDQVIHUUHGZKLFKRFFXUVZKHQ ERWKIRDY#DQGTRDY#DUHDVVHUWHGRQWKHVDPHULVLQJFORFNHGJH7KHUHDUHRWKHU FRQGLWLRQVWKDWFRPSOHWHDGDWDSKDVHDQGWKHVHDUHGLVFXVVHGLQ6HFWLRQ
47 Revision 2.2
TRDY#FDQQRWEHGULYHQXQWLODEVSEL#LVDVVHUWHG :KHQHLWKHUIRDY#RUTRDY# LVGHDVVHUWHGDZDLWF\FOHLVLQVHUWHGDQGQRGDWDLVWUDQVIHUUHG$VQRWHGLQ)LJXUH GDWDLVVXFFHVVIXOO\WUDQVIHUUHGRQFORFNVDQGDQGZDLWF\FOHVDUHLQVHUWHGRQ FORFNVDQG7KHILUVWGDWDSKDVHFRPSOHWHVLQWKHPLQLPXPWLPHIRUDUHDG WUDQVDFWLRQ7KHVHFRQGGDWDSKDVHLVH[WHQGHGRQFORFNEHFDXVHTRDY#LV GHDVVHUWHG7KHODVWGDWDSKDVHLVH[WHQGHGEHFDXVHIRDY#ZDVGHDVVHUWHGRQFORFN 7KHPDVWHUNQRZVDWFORFNWKDWWKHQH[WGDWDSKDVHLVWKHODVW+RZHYHUEHFDXVHWKH PDVWHULVQRWUHDG\WRFRPSOHWHWKHODVWWUDQVIHU IRDY#LVGHDVVHUWHGRQFORFN FRAME#VWD\VDVVHUWHG2QO\ZKHQIRDY#LVDVVHUWHGFDQFRAME#EHGHDVVHUWHGDV RFFXUVRQFORFNLQGLFDWLQJWRWKHWDUJHWWKDWWKLVLVWKHODVWGDWDSKDVHRIWKH WUDQVDFWLRQ
3.3.2. Write Transaction
)LJXUHLOOXVWUDWHVDZULWHWUDQVDFWLRQ7KHWUDQVDFWLRQVWDUWVZKHQFRAME#LV DVVHUWHGIRUWKHILUVWWLPHZKLFKRFFXUVRQFORFN$ZULWHWUDQVDFWLRQLVVLPLODUWRD UHDGWUDQVDFWLRQH[FHSWQRWXUQDURXQGF\FOHLVUHTXLUHGIROORZLQJWKHDGGUHVVSKDVH EHFDXVHWKHPDVWHUSURYLGHVERWKDGGUHVVDQGGDWD'DWDSKDVHVZRUNWKHVDPHIRUERWK UHDGDQGZULWHWUDQVDFWLRQV
CLK 1 2 3 4 5 6 7 8 9
FRAME#
AD ADDRESS DATA-1 DATA-2 DATA-3
C/BE# BUS CMD BE#'s-1 BE#'s-2 BE#'s-3
IRDY# WAIT TRDY# WAIT WAIT DATA TRANSFER DATA DATA TRANSFER DATA TRANSFER
DEVSEL#
ADDRESS DATA DATA DATA PHASE PHASE PHASE PHASE BUS TRANSACTION
)LJXUH %DVLF:ULWH2SHUDWLRQ
,Q)LJXUHWKHILUVWDQGVHFRQGGDWDSKDVHVFRPSOHWHZLWK]HURZDLWF\FOHV+RZHYHU WKHWKLUGGDWDSKDVHKDVWKUHHZDLWF\FOHVLQVHUWHGE\WKHWDUJHW1RWLFHERWKDJHQWVLQVHUW DZDLWF\FOHRQFORFNIRDY#PXVWEHDVVHUWHGZKHQFRAME#LVGHDVVHUWHG LQGLFDWLQJWKHODVWGDWDSKDVH 7KHGDWDWUDQVIHUZDVGHOD\HGE\WKHPDVWHURQFORFNEHFDXVHIRDY#ZDVGHDVVHUWHG 7KHODVWGDWDSKDVHLVVLJQDOHGE\WKHPDVWHURQFORFNEXWLWGRHVQRWFRPSOHWHXQWLO FORFN
48 Revision 2.2
1RWH $OWKRXJKWKLVDOORZHGWKHPDVWHUWRGHOD\GDWDLWGLGQRWDOORZWKHE\WHHQDEOHVWR EHGHOD\HG
3.3.3. Transaction Termination
7HUPLQDWLRQRID3&,WUDQVDFWLRQPD\EHLQLWLDWHGE\HLWKHUWKHPDVWHURUWKHWDUJHW :KLOHQHLWKHUFDQDFWXDOO\VWRSWKHWUDQVDFWLRQXQLODWHUDOO\WKHPDVWHUUHPDLQVLQ XOWLPDWHFRQWUROEULQJLQJDOOWUDQVDFWLRQVWRDQRUGHUO\DQGV\VWHPDWLFFRQFOXVLRQ UHJDUGOHVVRIZKDWFDXVHGWKHWHUPLQDWLRQ$OOWUDQVDFWLRQVDUHFRQFOXGHGZKHQ FRAME#DQGIRDY#DUHERWKGHDVVHUWHGLQGLFDWLQJDQ,GOHVWDWH HJFORFN LQ )LJXUH
3.3.3.1. Master Initiated Termination
7KHPHFKDQLVPXVHGLQPDVWHULQLWLDWHGWHUPLQDWLRQLVZKHQFRAME#LVGHDVVHUWHGDQG IRDY#LVDVVHUWHG7KLVFRQGLWLRQVLJQDOVWKHWDUJHWWKDWWKHILQDOGDWDSKDVHLVLQ SURJUHVV7KHILQDOGDWDWUDQVIHURFFXUVZKHQERWKIRDY#DQGTRDY#DUHDVVHUWHG 7KHWUDQVDFWLRQUHDFKHVFRPSOHWLRQZKHQERWKFRAME#DQGIRDY#DUHGHDVVHUWHG ,GOHVWDWH 7KHPDVWHUPD\LQLWLDWHWHUPLQDWLRQXVLQJWKLVPHFKDQLVPIRURQHRIWZRUHDVRQV Completion refers to termination when the master has concluded its intended transaction. This is the most common reason for termination. Timeout Uefers to termination when the master's GNT# line is deasserted and its internal Latency Timer has expired. The intended transaction is not necessarily concluded. The timer may have expired because of target-induced access latency or because the intended operation was very long. Refer to Section 3.5.4. for a description of the Latency Timer operation. A Memory Write and Invalidate transaction is not governed by the Latency Timer except at cacheline boundaries. A master that initiates a transaction with the Memory Write and Invalidate command ignores the Latency Timer until a cacheline boundary. When the transaction reaches a cacheline boundary and the Latency Timer has expired (and GNT# is deasserted), the master must terminate the transaction.
$PRGLILHGYHUVLRQRIWKLVWHUPLQDWLRQPHFKDQLVPDOORZVWKHPDVWHUWRWHUPLQDWHWKH WUDQVDFWLRQZKHQQRWDUJHWUHVSRQGV7KLVDEQRUPDOWHUPLQDWLRQLVUHIHUUHGWRDV0DVWHU $ERUW$OWKRXJKLWPD\FDXVHDIDWDOHUURUIRUWKHDSSOLFDWLRQRULJLQDOO\UHTXHVWLQJWKH WUDQVDFWLRQWKHWUDQVDFWLRQFRPSOHWHVJUDFHIXOO\WKXVSUHVHUYLQJQRUPDO3&,RSHUDWLRQ IRURWKHUDJHQWV 7ZRH[DPSOHVRIQRUPDOFRPSOHWLRQDUHVKRZQLQ)LJXUH7KHILQDOGDWDSKDVHLV LQGLFDWHGE\WKHGHDVVHUWLRQRIFRAME#DQGWKHDVVHUWLRQRIIRDY#7KHILQDOGDWD SKDVHFRPSOHWHVZKHQFRAME#LVGHDVVHUWHGDQGIRDY#DQGTRDY#DUHERWK DVVHUWHG7KHEXVUHDFKHVDQ,GOHVWDWHZKHQIRDY#LVGHDVVHUWHGZKLFKRFFXUVRQ FORFN%HFDXVHWKHWUDQVDFWLRQKDVFRPSOHWHGTRDY#LVGHDVVHUWHGRQFORFNDOVR 1RWH TRDY# LVQRWUHTXLUHGWREHDVVHUWHGRQFORFNEXWFRXOGKDYHGHOD\HGWKHILQDO GDWDWUDQVIHU DQGWUDQVDFWLRQWHUPLQDWLRQ XQWLOLWLVUHDG\E\GHOD\LQJWKHILQDODVVHUWLRQ
49 Revision 2.2
RITRDY#,IWKHWDUJHWGRHVWKDWWKHPDVWHULVUHTXLUHGWRNHHSIRDY#DVVHUWHGXQWLO WKHILQDOGDWDWUDQVIHURFFXUV
CLK 1 2 3 4 1 2 3 4
GNT#
T/O FRAME#
T/O IRDY#
TRDY#
)LJXUH 0DVWHU,QLWLDWHG7HUPLQDWLRQ
%RWKVLGHVRI)LJXUHFRXOGKDYHEHHQFDXVHGE\DWLPHRXWWHUPLQDWLRQ2QWKHOHIW VLGHFRAME#LVGHDVVHUWHGRQFORFNEHFDXVHWKHWLPHUH[SLUHVGNT#LVGHDVVHUWHG DQGWKHPDVWHULVUHDG\ IRDY#DVVHUWHG IRUWKHILQDOWUDQVIHU%HFDXVHGNT#ZDV GHDVVHUWHGZKHQWKHWLPHUH[SLUHGFRQWLQXHGXVHRIWKHEXVLVQRWDOORZHGH[FHSWZKHQ XVLQJWKH0HPRU\:ULWHDQG,QYDOLGDWHFRPPDQG UHIHUWR6HFWLRQ ZKLFKPXVW EHVWRSSHGDWWKHFDFKHOLQHERXQGDU\7HUPLQDWLRQWKHQSURFHHGVDVQRUPDO,ITRDY# LVGHDVVHUWHGRQFORFNWKDWGDWDSKDVHFRQWLQXHVXQWLOTRDY#LVDVVHUWHGFRAME# PXVWUHPDLQGHDVVHUWHGDQGIRDY#PXVWUHPDLQDVVHUWHGXQWLOWKHGDWDSKDVHFRPSOHWHV 7KHULJKWKDQGH[DPSOHVKRZVDWLPHUH[SLULQJRQFORFN%HFDXVHWKHPDVWHULVQRW UHDG\WRWUDQVIHUGDWD IRDY#LVGHDVVHUWHGRQFORFN FRAME#LVUHTXLUHGWRVWD\ DVVHUWHGFRAME#LVGHDVVHUWHGRQFORFNEHFDXVHWKHPDVWHULVUHDG\ IRDY#LV DVVHUWHG WRFRPSOHWHWKHWUDQVDFWLRQRQFORFN7KHPDVWHUPXVWEHGULYLQJYDOLGGDWD ZULWH RUEHFDSDEOHRIUHFHLYLQJGDWD UHDG ZKHQHYHUIRDY#LVDVVHUWHG7KLVGHOD\LQ WHUPLQDWLRQVKRXOGQRWEHH[WHQGHGPRUHWKDQWZRRUWKUHHFORFNV$OVRQRWHWKDWWKH WUDQVDFWLRQQHHGQRWEHWHUPLQDWHGDIWHUWLPHUH[SLUDWLRQXQOHVVGNT#LVGHDVVHUWHG 0DVWHU$ERUWWHUPLQDWLRQDVVKRZQLQ)LJXUHLVDQDEQRUPDOFDVH H[FHSWIRU FRQILJXUDWLRQRU6SHFLDO&\FOHFRPPDQGV RIPDVWHULQLWLDWHGWHUPLQDWLRQ$PDVWHU GHWHUPLQHVWKDWWKHUHZLOOEHQRUHVSRQVHWRDWUDQVDFWLRQLIDEVSEL#UHPDLQV GHDVVHUWHGRQFORFN )RUDFRPSOHWHGHVFULSWLRQRIDEVSEL#RSHUDWLRQUHIHUWR 6HFWLRQ 7KHPDVWHUPXVWDVVXPHWKDWWKHWDUJHWRIWKHDFFHVVLVLQFDSDEOHRI GHDOLQJZLWKWKHUHTXHVWHGWUDQVDFWLRQRUWKDWWKHDGGUHVVZDVEDGDQGPXVWQRWUHSHDW WKHWUDQVDFWLRQ2QFHWKHPDVWHUKDVGHWHFWHGWKHPLVVLQJDEVSEL# FORFNLQWKLV H[DPSOH FRAME#LVGHDVVHUWHGRQFORFNDQGIRDY#LVGHDVVHUWHGRQFORFN7KH HDUOLHVWDPDVWHUFDQWHUPLQDWHDWUDQVDFWLRQZLWK0DVWHU$ERUWLVILYHFORFNVDIWHU FRAME#ZDVILUVWVDPSOHGDVVHUWHGZKLFKRFFXUVZKHQWKHPDVWHUDWWHPSWVDVLQJOH GDWDWUDQVIHU,IDEXUVWLVDWWHPSWHGWKHWUDQVDFWLRQLVORQJHUWKDQILYHFORFNV+RZHYHU WKHPDVWHUPD\WDNHORQJHUWRGHDVVHUWFRAME#DQGWHUPLQDWHWKHDFFHVV7KHPDVWHU PXVWVXSSRUWWKHFRAME#IRDY#UHODWLRQVKLSRQDOOWUDQVDFWLRQVLQFOXGLQJ0DVWHU $ERUWFRAME#FDQQRWEHGHDVVHUWHGEHIRUHIRDY#LVDVVHUWHGDQGIRDY#PXVW
50 Revision 2.2
UHPDLQDVVHUWHGIRUDWOHDVWRQHFORFNDIWHUFRAME#LVGHDVVHUWHGHYHQZKHQWKH WUDQVDFWLRQLVWHUPLQDWHGZLWK0DVWHU$ERUW $OWHUQDWLYHO\IRDY#FRXOGEHGHDVVHUWHGRQFORFNLIFRAME#ZDVGHDVVHUWHGDVLQ WKHFDVHRIDWUDQVDFWLRQZLWKDVLQJOHGDWDSKDVH7KHPDVWHUZLOOQRUPDOO\QRWUHSHDWD WUDQVDFWLRQWHUPLQDWHGZLWK0DVWHU$ERUW 5HIHUWR6HFWLRQ 1RWH ,IDEVSEL# KDGEHHQDVVHUWHGRQFORFNVRURIWKLVH[DPSOHLWZRXOGLQGLFDWHWKHUHTXHVW KDGEHHQDFNQRZOHGJHGE\DQDJHQWDQG0DVWHU$ERUWWHUPLQDWLRQZRXOGQRWEH SHUPLVVLEOH 7KHKRVWEXVEULGJHLQ3&FRPSDWLEOHV\VWHPVPXVWUHWXUQDOO VRQDUHDGWUDQVDFWLRQ DQGGLVFDUGGDWDRQDZULWHWUDQVDFWLRQZKHQWHUPLQDWHGZLWK0DVWHU$ERUW7KHEULGJH LVUHTXLUHGWRVHWWKH0DVWHU$ERUWGHWHFWHGELWLQWKHVWDWXVUHJLVWHU2WKHUPDVWHU GHYLFHVPD\UHSRUWWKLVFRQGLWLRQDVDQHUURUE\VLJQDOLQJSERR#ZKHQWKHPDVWHU FDQQRWUHSRUWWKHHUURUWKURXJKLWVGHYLFHGULYHU$3&,WR3&,EULGJHPXVWVXSSRUW3& FRPSDWLELOLW\DVGHVFULEHGIRUWKHKRVWEXVEULGJH:KHQWKH3&,WR3&,EULGJHLVXVHG LQRWKHUV\VWHPVWKHEULGJHEHKDYHVOLNHRWKHUPDVWHUVDQGUHSRUWVDQHUURU3UHIHWFKLQJ RIUHDGGDWDEH\RQGWKHDFWXDOUHTXHVWE\DEULGJHPXVWEHWRWDOO\WUDQVSDUHQWWRWKH V\VWHP7KLVPHDQVWKDWZKHQDSUHIHWFKHGWUDQVDFWLRQLVWHUPLQDWHGZLWK0DVWHU$ERUW WKHEULGJHPXVWVLPSO\VWRSWKHWUDQVDFWLRQDQGFRQWLQXHQRUPDORSHUDWLRQZLWKRXW UHSRUWLQJDQHUURU7KLVRFFXUVZKHQDWUDQVDFWLRQLVQRWFODLPHGE\DWDUJHW
CLK 1 2 3 4 5 6 7 8
FRAME#
IRDY#
TRDY#
NO RESPONSE DEVSEL# FAST MED SLOW SUB ACKNOWLEDGE
)LJXUH 0DVWHU$ERUW7HUPLQDWLRQ
,QVXPPDU\WKHIROORZLQJJHQHUDOUXOHVJRYHUQFRAME#DQGIRDY#LQDOO3&, WUDQVDFWLRQV FRAME#DQGLWVFRUUHVSRQGLQJIRDY#GHILQHWKH%XV\,GOHVWDWHRIWKHEXV ZKHQ HLWKHULVDVVHUWHGWKHEXVLV%XV\ ZKHQERWKDUHGHDVVHUWHGWKHEXVLV,GOH 2QFHFRAME#KDVEHHQGHDVVHUWHGLWFDQQRWEHUHDVVHUWHGGXULQJWKHVDPH WUDQVDFWLRQ FRAME#FDQQRWEHGHDVVHUWHGXQOHVVIRDY#LVDVVHUWHG IRDY#PXVWDOZD\VEH DVVHUWHGRQWKHILUVWFORFNHGJHWKDWFRAME#LVGHDVVHUWHG 2QFHDPDVWHUKDVDVVHUWHGIRDY#,LWFDQQRWFKDQJHIRDY#RUFRAME#XQWLOWKH FXUUHQWGDWDSKDVHFRPSOHWHV 7KHPDVWHUPXVWGHDVVHUWIRDY#WKHFORFNDIWHUWKHFRPSOHWLRQRIWKHODVWGDWD SKDVH
51 Revision 2.2
3.3.3.2. Target Initiated Termination
8QGHUPRVWFRQGLWLRQVWKHWDUJHWLVDEOHWRVRXUFHRUVLQNWKHGDWDUHTXHVWHGE\WKH PDVWHUXQWLOWKHPDVWHUWHUPLQDWHVWKHWUDQVDFWLRQ%XWZKHQWKHWDUJHWLVXQDEOHWR FRPSOHWHWKHUHTXHVWLWPD\XVHWKHSTOP#VLJQDOWRLQLWLDWHWHUPLQDWLRQRIWKH WUDQVDFWLRQ+RZWKHWDUJHWFRPELQHVSTOP#ZLWKRWKHUVLJQDOVZLOOLQGLFDWHWRWKH PDVWHUVRPHWKLQJDERXWWKHFRQGLWLRQZKLFKOHDGWRWKHWHUPLQDWLRQ 7KHWKUHHW\SHVRIWDUJHWLQLWLDWHGWHUPLQDWLRQDUH 5HWU\ refers to termination requested before any data is transferred because the target is busy and temporarily unable to process the transaction. This condition may occur, for example, because the device cannot meet the initial latency requirement, is currently locked by another master, or there is a conflict for a internal resource. Retry is a special case of Disconnect without data being transferred on the initial data phase. The target signals Retry by asserting STOP# and not asserting TRDY# on the initial data phase of the transaction (STOP# cannot be asserted during the turn-around cycle between the address phase and first data phase of a read transaction). When the target uses Retry, no data is transferred. Disconnect refers to termination requested with or after data was transferred on the initial data phase because the target is unable to respond within the target subsequent latency requirement and, therefore, is temporarily unable to continue bursting. This might be because the burst crosses a resource boundary or a resource conflict occurs. Data may or may not transfer on the data phase where Disconnect is signaled. Notice that Disconnect differs from Retry in that Retry is always on the initial data phase, and no data transfers. If data is transferred with or before the target terminates the transaction, it is a Disconnect. This may also occur on the initial data phase because the target is not capable of doing a burst. Disconnect with data may be signaled on any data phase by asserting TRDY# and STOP# together. This termination is used when the target is only willing to complete the current data phase and no more. Disconnect without data may be signaled on any subsequent data phase (meaning data was transferred on the previous data phase) by deasserting TRDY# and asserting STOP#.
52 Revision 2.2
Target-Abort refers to an abnormal termination requested because the target detected a fatal error or the target will never be able to complete the request. Although it may cause a fatal error for the application originally requesting the transaction, the transaction completes gracefully, thus, preserving normal operation for other agents. For example, a master requests all bytes in an I/O Address Space DWORD to be read, but the target design restricts access to a single byte in this range. Since the target cannot complete the request, the target terminates the request with Target-Abort. Once the target has claimed an access by asserting DEVSEL#, it can signal Target-Abort on any subsequent clock. The target signals Target-Abort by deasserting DEVSEL# and asserting STOP# at the same time.
0RVWWDUJHWVZLOOEHUHTXLUHGWRLPSOHPHQWDWOHDVW5HWU\FDSDELOLW\EXWDQ\RWKHU YHUVLRQVRIWDUJHWLQLWLDWHGWHUPLQDWLRQDUHRSWLRQDOIRUWDUJHWV0DVWHUVPXVWEHFDSDEOH RISURSHUO\GHDOLQJZLWKWKHPDOO5HWU\LVRSWLRQDOWRYHU\VLPSOHWDUJHWVWKDW
• GRQRWVXSSRUWH[FOXVLYH ORFNHG DFFHVVHV
• GRQRWKDYHDSRVWHGPHPRU\ZULWHEXIIHUZKLFKQHHGVWREHIOXVKHGWRPHHWWKH3&, RUGHULQJUXOHV
• FDQQRWJHWLQWRDVWDWHZKHUHWKH\PD\QHHGWRUHMHFWDQDFFHVV
• FDQDOZD\VPHHWWDUJHWLQLWLDOODWHQF\ $WDUJHWLVSHUPLWWHGWRVLJQDO'LVFRQQHFWZLWKGDWD DVVHUWSTOP# DQGTRDY# RQWKH LQLWLDOGDWDSKDVHHYHQLIWKHPDVWHULVQRWEXUVWLQJ LHFRAME#LVGHDVVHUWHG
3.3.3.2.1. Target Termination Signaling Rules
7KHIROORZLQJJHQHUDOUXOHVJRYHUQFRAME#IRDY#TRDY#STOP#DQG DEVSEL#ZKLOHWHUPLQDWLQJWUDQVDFWLRQV $GDWDSKDVHFRPSOHWHVRQDQ\ULVLQJFORFNHGJHRQZKLFKIRDY#LVDVVHUWHGDQG HLWKHUSTOP#RUTRDY#LVDVVHUWHG ,QGHSHQGHQWRIWKHVWDWHRISTOP#DGDWDWUDQVIHUWDNHVSODFHRQHYHU\ULVLQJHGJH RIFORFNZKHUHERWKIRDY#DQGTRDY#DUHDVVHUWHG 2QFHWKHWDUJHWDVVHUWVSTOP#LWPXVWNHHSSTOP#DVVHUWHGXQWLOFRAME#LV GHDVVHUWHGZKHUHXSRQLWPXVWGHDVVHUWSTOP# 2QFHDWDUJHWKDVDVVHUWHGTRDY#RUSTOP#LWFDQQRWFKDQJHDEVSEL# TRDY#RUSTOP#XQWLOWKHFXUUHQWGDWDSKDVHFRPSOHWHV :KHQHYHUSTOP#LVDVVHUWHGWKHPDVWHUPXVWGHDVVHUWFRAME#DVVRRQDVIRDY# FDQEHDVVHUWHG
53 Revision 2.2
,IQRWDOUHDG\GHDVVHUWHGTRDY#STOP#DQGDEVSEL#PXVWEHGHDVVHUWHGWKH FORFNIROORZLQJWKHFRPSOHWLRQRIWKHODVWGDWDSKDVHDQGPXVWEHWULVWDWHGWKHQH[W FORFN 5XOHPHDQVWKDWDGDWDSKDVHFDQFRPSOHWHZLWKRUZLWKRXWTRDY# EHLQJDVVHUWHG :KHQDWDUJHWLVXQDEOHWRFRPSOHWHDGDWDWUDQVIHULWFDQDVVHUWSTOP#ZLWKRXW DVVHUWLQJTRDY# :KHQERWKFRAME#DQGIRDY#DUHDVVHUWHGWKHPDVWHUKDVFRPPLWWHGWRFRPSOHWH WZRGDWDSKDVHV7KHPDVWHULVXQDEOHWRGHDVVHUWFRAME#XQWLOWKHFXUUHQWGDWDSKDVH FRPSOHWHVEHFDXVHIRDY#LVDVVHUWHG%HFDXVHDGDWDSKDVHLVDOORZHGWRFRPSOHWH ZKHQSTOP#DQGIRDY#DUHDVVHUWHGWKHPDVWHULVDOORZHGWRVWDUWWKHILQDOGDWDSKDVH E\GHDVVHUWLQJFRAME#DQGNHHSLQJIRDY#DVVHUWHG7KHPDVWHUPXVWGHDVVHUW IRDY#WKHFORFNDIWHUWKHFRPSOHWLRQRIWKHODVWGDWDSKDVH 5XOHLQGLFDWHVWKDWGDWDWUDQVIHUVUHJDUGOHVVRIWKHVWDWHRISTOP#ZKHQERWKTRDY# DQGIRDY#DUHDVVHUWHG 5XOHPHDQVWKDWRQFHSTOP#LVDVVHUWHGLWPXVWUHPDLQDVVHUWHGXQWLOWKHWUDQVDFWLRQ LVFRPSOHWH7KHODVWGDWDSKDVHRIDWUDQVDFWLRQFRPSOHWHVZKHQFRAME#LV GHDVVHUWHGIRDY#LVDVVHUWHGDQGSTOP# RUTRDY# LVDVVHUWHG7KHWDUJHWPXVWQRW DVVXPHDQ\WLPLQJUHODWLRQVKLSEHWZHHQWKHDVVHUWLRQRISTOP#DQGWKHGHDVVHUWLRQRI FRAME#EXWPXVWNHHSSTOP#DVVHUWHGXQWLOFRAME#LVGHDVVHUWHGDQGIRDY#LV DVVHUWHG WKHODVWGDWDSKDVHFRPSOHWHV STOP#PXVWEHGHDVVHUWHGRQWKHFORFN IROORZLQJWKHFRPSOHWLRQRIWKHODVWGDWDSKDVH :KHQERWKSTOP#DQGTRDY#DUHDVVHUWHGLQWKHVDPHGDWDSKDVHWKHWDUJHWZLOO WUDQVIHUGDWDLQWKDWGDWDSKDVH,QWKLVFDVHTRDY#PXVWEHGHDVVHUWHGZKHQWKHGDWD SKDVHFRPSOHWHV$VEHIRUHSTOP#PXVWUHPDLQDVVHUWHGXQWLOWKHWUDQVDFWLRQHQGV ZKHUHXSRQLWLVGHDVVHUWHG ,IWKHWDUJHWUHTXLUHVZDLWVWDWHVLQWKHGDWDSKDVHZKHUHLWDVVHUWVSTOP#LWPXVWGHOD\ WKHDVVHUWLRQRISTOP#XQWLOLWLVUHDG\WRFRPSOHWHWKHGDWDSKDVH 5XOHPHDQVWKHWDUJHWLVQRWDOORZHGWRFKDQJHLWVPLQGRQFHLWKDVFRPPLWWHGWR FRPSOHWHWKHFXUUHQWGDWDSKDVH&RPPLWWLQJWRFRPSOHWHDGDWDSKDVHRFFXUVZKHQWKH WDUJHWDVVHUWVHLWKHUTRDY#RUSTOP#.7KHWDUJHWFRPPLWVWR • 7UDQVIHUGDWDLQWKHFXUUHQWGDWDSKDVHDQGFRQWLQXHWKHWUDQVDFWLRQ LIDEXUVW E\ DVVHUWLQJTRDY#DQGQRWDVVHUWLQJSTOP# • 7UDQVIHUGDWDLQWKHFXUUHQWGDWDSKDVHDQGWHUPLQDWHWKHWUDQVDFWLRQE\DVVHUWLQJ ERWKTRDY#DQG STOP# • 1RWWUDQVIHUGDWDLQWKHFXUUHQWGDWDSKDVHDQGWHUPLQDWHWKHWUDQVDFWLRQE\DVVHUWLQJ STOP#DQGGHDVVHUWLQJTRDY# • 1RWWUDQVIHUGDWDLQWKHFXUUHQWGDWDSKDVHDQGWHUPLQDWHWKHWUDQVDFWLRQZLWKDQHUURU FRQGLWLRQ 7DUJHW$ERUW E\DVVHUWLQJSTOP#DQGGHDVVHUWLQJTRDY#DQG DEVSEL#
7KHWDUJHWKDVQRWFRPPLWWHGWRFRPSOHWHWKHFXUUHQWGDWDSKDVHZKLOHTRDY# DQG STOP#DUHERWKGHDVVHUWHG7KHWDUJHWLVVLPSO\LQVHUWLQJZDLWVWDWHV 5XOHPHDQVWKDWZKHQWKHPDVWHUVDPSOHVSTOP#DVVHUWHGLWPXVWGHDVVHUWFRAME# RQWKHILUVWF\FOHWKHUHDIWHULQZKLFKIRDY#LVDVVHUWHG7KHDVVHUWLRQRIIRDY# DQG GHDVVHUWLRQRIFRAME#VKRXOGRFFXUDVVRRQDVSRVVLEOHDIWHUSTOP#LVDVVHUWHG SUHIHUDEO\ZLWKLQRQHWRWKUHHF\FOHV7KLVDVVHUWLRQRIIRDY# DQGWKHUHIRUHFRAME#
54 Revision 2.2
GHDVVHUWLRQ PD\RFFXUDVDFRQVHTXHQFHRIWKHQRUPDOIRDY#EHKDYLRURIWKHPDVWHU KDGWKHFXUUHQWWUDQVDFWLRQQRWEHHQWDUJHWWHUPLQDWHG$OWHUQDWLYHO\LITRDY#LV GHDVVHUWHG LQGLFDWLQJWKHUHZLOOEHQRIXUWKHUGDWDWUDQVIHU WKHPDVWHUPD\DVVHUW IRDY#LPPHGLDWHO\ HYHQZLWKRXWEHLQJSUHSDUHGWRFRPSOHWHDGDWDWUDQVIHU ,ID 0HPRU\:ULWHDQG,QYDOLGDWHWUDQVDFWLRQLVWHUPLQDWHGE\WKHWDUJHWWKHPDVWHU FRPSOHWHVWKHWUDQVDFWLRQ WKHUHVWRIWKHFDFKHOLQH DVVRRQDVSRVVLEOH DGKHULQJWRWKH STOP#SURWRFRO XVLQJWKH0HPRU\:ULWHFRPPDQG VLQFHWKHFRQGLWLRQVWRLVVXH 0HPRU\:ULWHDQG,QYDOLGDWHDUHQRORQJHUWUXH 5XOHUHTXLUHVWKHWDUJHWWRUHOHDVHFRQWURORIWKHWDUJHWVLJQDOVLQWKHVDPHPDQQHULW ZRXOGLIWKHWUDQVDFWLRQKDGFRPSOHWHGXVLQJPDVWHUWHUPLQDWLRQ5HWU\DQG'LVFRQQHFW DUHQRUPDOWHUPLQDWLRQFRQGLWLRQVRQWKHEXV2QO\7DUJHW$ERUWLVDQDEQRUPDO WHUPLQDWLRQWKDWPD\KDYHFDXVHGDQHUURU%HFDXVHWKHUHSRUWLQJRIHUURUVLVRSWLRQDO WKHEXVPXVWFRQWLQXHRSHUDWLQJDVWKRXJKWKHHUURUQHYHURFFXUUHG
([DPSOHVRI7DUJHW7HUPLQDWLRQ 5HWU\ )LJXUH VKRZVDWUDQVDFWLRQEHLQJWHUPLQDWHGZLWK5HWU\7KHWUDQVDFWLRQVWDUWVZLWK FRAME#DVVHUWHGRQFORFNDQGIRDY#DVVHUWHGRQFORFN7KHPDVWHUUHTXHVWV PXOWLSOHGDWDSKDVHVEHFDXVHERWKFRAME#DQGIRDY#DUHDVVHUWHGRQFORFN7KH WDUJHWFODLPVWKHWUDQVDFWLRQE\DVVHUWLQJDEVSEL#RQFORFN 7KHWDUJHWGHWHUPLQHVLWFDQQRWFRPSOHWHWKHPDVWHU¶VUHTXHVWDQGDOVRDVVHUWVSTOP# RQFORFNZKLOHNHHSLQJTRDY#GHDVVHUWHG7KHILUVWGDWDSKDVHFRPSOHWHVRQFORFN EHFDXVHERWKIRDY#DQGSTOP#DUHDVVHUWHG6LQFHTRDY#ZDVGHDVVHUWHGQRGDWD ZDVWUDQVIHUUHGGXULQJWKHLQLWLDOGDWDSKDVH%HFDXVHSTOP#ZDVDVVHUWHGDQGTRDY# ZDVGHDVVHUWHGRQFORFNWKHPDVWHUNQRZVWKHWDUJHWLVXQZLOOLQJWRWUDQVIHUDQ\GDWD IRUWKLVWUDQVDFWLRQDWWKHSUHVHQWWLPH7KHPDVWHULVUHTXLUHGWRGHDVVHUWFRAME#DV VRRQDVIRDY#FDQEHDVVHUWHG,QWKLVFDVHFRAME#LVGHDVVHUWHGRQFORFNEHFDXVH IRDY#LVDVVHUWHGRQFORFN7KHODVWGDWDSKDVHFRPSOHWHVRQFORFNEHFDXVH FRAME#LVGHDVVHUWHGDQGSTOP#LVDVVHUWHG7KHWDUJHWGHDVVHUWVSTOP#DQG DEVSEL#RQFORFNEHFDXVHWKHWUDQVDFWLRQLVFRPSOHWH7KLVWUDQVDFWLRQFRQVLVWHGRI WZRGDWDSKDVHVLQZKLFKQRGDWDZDVWUDQVIHUUHGDQGWKHPDVWHULVUHTXLUHGWRUHSHDWWKH UHTXHVWDJDLQ
CLK 1 2 3 4 5 6
FRAME#
IRDY#
TRDY#
STOP#
DEVSEL#
)LJXUH 5HWU\
55 Revision 2.2
'LVFRQQHFW:LWK'DWD 'LVFRQQHFW$LQ)LJXUHLVZKHUHWKHPDVWHULVLQVHUWLQJDZDLWVWDWHZKHQWKH WDUJHWVLJQDOV'LVFRQQHFWZLWKGDWD7KLVWUDQVDFWLRQVWDUWVSULRUWRFORFN7KHFXUUHQW GDWDSKDVHZKLFKFRXOGEHWKHLQLWLDORUDVXEVHTXHQWGDWDSKDVHFRPSOHWHVRQFORFN 7KHPDVWHULQVHUWVDZDLWVWDWHRQFORFNVDQGZKLOHWKHWDUJHWLQVHUWVDZDLWVWDWHRQO\ RQFORFN6LQFHWKHWDUJHWZDQWVWRFRPSOHWHRQO\WKHFXUUHQWGDWDSKDVHDQGQRPRUH LWDVVHUWVTRDY#DQGSTOP#DWWKHVDPHWLPH,QWKLVH[DPSOHWKHGDWDLVWUDQVIHUUHG GXULQJWKHODVWGDWDSKDVH%HFDXVHWKHPDVWHUVDPSOHGSTOP#DVVHUWHGRQFORFN FRAME#LVGHDVVHUWHGRQFORFNDQGWKHPDVWHULVUHDG\WRFRPSOHWHWKHGDWDSKDVH IRDY#LVDVVHUWHG 6LQFHFRAME#LVGHDVVHUWHGRQFORFNWKHODVWGDWDSKDVH FRPSOHWHVEHFDXVHSTOP#LVDVVHUWHGDQGGDWDWUDQVIHUVEHFDXVHERWKIRDY#DQG TRDY#DUHDVVHUWHG1RWLFHWKDWSTOP#UHPDLQVDVVHUWHGIRUERWKFORFNVDQG7KH WDUJHWLVUHTXLUHGWRNHHSSTOP#DVVHUWHGXQWLOFRAME#LVGHDVVHUWHG 'LVFRQQHFW%LQ)LJXUHLVDOPRVWWKHVDPHDV'LVFRQQHFW$EXWTRDY#LVQRW DVVHUWHGLQWKHODVWGDWDSKDVH,QWKLVH[DPSOHGDWDZDVWUDQVIHUUHGRQFORFNVDQG EXWQRWGXULQJWKHODVWGDWDSKDVH7KHWDUJHWLQGLFDWHVWKDWLWFDQQRWFRQWLQXHWKHEXUVW E\DVVHUWLQJERWKSTOP#DQGTRDY#WRJHWKHU:KHQWKHGDWDSKDVHFRPSOHWHVRQ FORFNWKHWDUJHWLVUHTXLUHGWRGHDVVHUWTRDY#DQGNHHSSTOP#DVVHUWHG7KHODVW GDWDSKDVHFRPSOHWHVZLWKRXWWUDQVIHUULQJGDWDRQFORFNEHFDXVHTRDY#LV GHDVVHUWHGDQGSTOP#LVDVVHUWHG,QWKLVH[DPSOHWKHUHDUHWKUHHGDWDSKDVHVWZRWKDW WUDQVIHUGDWDDQGRQHWKDWGRHVQRW
CLK 1 2 3 4 1 2 3 4
FRAME#
IRDY#
TRDY#
STOP#
DEVSEL# Disconnect - A Disconnect - B
)LJXUH 'LVFRQQHFW:LWK'DWD
56 Revision 2.2
)LJXUHLVDQH[DPSOHRI0DVWHU&RPSOHWLRQWHUPLQDWLRQZKHUHWKHWDUJHWEOLQGO\ DVVHUWVSTOP#.7KLVLVDOHJDOWHUPLQDWLRQZKHUHWKHPDVWHULVUHTXHVWLQJDWUDQVDFWLRQ ZLWKDVLQJOHGDWDSKDVHDQGWKHWDUJHWEOLQGO\DVVHUWVSTOP#DQGTRDY#LQGLFDWLQJLW FDQFRPSOHWHRQO\DVLQJOHGDWDSKDVH7KHWUDQVDFWLRQVWDUWVOLNHDOOWUDQVDFWLRQVZLWK WKHDVVHUWLRQRIFRAME#7KHPDVWHULQGLFDWHVWKDWWKHLQLWLDOGDWDSKDVHLVWKHILQDO GDWDSKDVHEHFDXVHFRAME#LVGHDVVHUWHGDQGIRDY#LVDVVHUWHGRQFORFN7KH WDUJHWFODLPVWKHWUDQVDFWLRQLQGLFDWHVLWLVUHDG\WRWUDQVIHUGDWDDQGUHTXHVWVWKH WUDQVDFWLRQWRVWRSE\DVVHUWLQJDEVSEL#TRDY#DQGSTOP#DOODWWKHVDPHWLPH
CLK 1 2 3 4 5
FRAME#
IRDY#
TRDY#
STOP#
DEVSEL#
)LJXUH 0DVWHU&RPSOHWLRQ7HUPLQDWLRQ
'LVFRQQHFW:LWKRXW'DWD )LJXUHVKRZVDWUDQVDFWLRQEHLQJWHUPLQDWHGZLWK'LVFRQQHFWZLWKRXWGDWD7KH WUDQVDFWLRQVWDUWVZLWKFRAME#EHLQJDVVHUWHGRQFORFNDQGIRDY#EHLQJDVVHUWHGRQ FORFN7KHPDVWHULVUHTXHVWLQJPXOWLSOHGDWDSKDVHVEHFDXVHERWKFRAME#DQG IRDY#DUHDVVHUWHGRQFORFN7KHWDUJHWFODLPVWKHWUDQVDFWLRQE\DVVHUWLQJ DEVSEL#RQFORFN 7KHILUVWGDWDSKDVHFRPSOHWHVRQFORFNDQGWKHVHFRQGFRPSOHWHVRQFORFN2Q FORFNWKHPDVWHUZDQWVWRFRQWLQXHEXUVWLQJEHFDXVHFRAME#DQGIRDY#DUHVWLOO DVVHUWHG+RZHYHUWKHWDUJHWFDQQRWFRPSOHWHDQ\PRUHGDWDSKDVHVDQGDVVHUWVSTOP# DQGGHDVVHUWVTRDY#RQFORFN6LQFHIRDY#DQGSTOP#DUHDVVHUWHGRQFORFNWKH WKLUGGDWDSKDVHFRPSOHWHV7KHWDUJHWFRQWLQXHVWRNHHSSTOP# DVVHUWHGRQFORFN EHFDXVHFRAME#LVVWLOODVVHUWHGRQFORFN7KHIRXUWKDQGILQDOGDWDSKDVHFRPSOHWHV RQFORFNVLQFHFRAME#LVGHDVVHUWHG IRDY#LVDVVHUWHG DQGSTOP#LVDVVHUWHGRQ FORFN7KHEXVUHWXUQVWRWKH,GOHVWDWHRQFORFN ,QWKLVH[DPSOHWKHILUVWWZRGDWDSKDVHVFRPSOHWHWUDQVIHUULQJGDWDZKLOHWKHODVWWZRGR QRW7KLVPLJKWKDSSHQLIDGHYLFHDFFHSWHGWZR':25'VRIGDWDDQGWKHQGHWHUPLQHG WKDWLWVEXIIHUVZHUHIXOORULIWKHEXUVWFURVVHGDUHVRXUFHERXQGDU\7KHWDUJHWLVDEOHWR FRPSOHWHWKHILUVWWZRGDWDSKDVHVEXWFDQQRWFRPSOHWHWKHWKLUG:KHQDQGLIWKHPDVWHU FRQWLQXHVWKHEXUVWWKHGHYLFHWKDWRZQVWKHDGGUHVVRIWKHQH[WXQWUDQVIHUUHGGDWDZLOO FODLPWKHDFFHVVDQGFRQWLQXHWKHEXUVW
57 Revision 2.2
CLK 1 2 3 4 5 6 7 8
FRAME#
IRDY# DATA TRANSFER TRDY# DATA TRANSFER
STOP#
DEVSEL#
DATA PHASE DATA DATA DATA PHASE PHASE PHASE
)LJXUH 'LVFRQQHFW:LWKRXW'DWD7HUPLQDWLRQ
)LJXUHVKRZVWKHVDPHWUDQVDFWLRQDVGHVFULEHGLQ)LJXUHH[FHSWWKDWWKH PDVWHULQVHUWVDZDLWVWDWHRQFORFN6LQFHFRAME#ZDVQRWGHDVVHUWHGRQFORFN WKHPDVWHUFRPPLWWHGWRDWOHDVWRQHPRUHGDWDSKDVHDQGPXVWFRPSOHWHLW7KHPDVWHU LVQRWDOORZHGVLPSO\WRWUDQVLWLRQWKHEXVWRWKH,GOHVWDWHE\GHDVVHUWLQJFRAME#DQG NHHSLQJIRDY#GHDVVHUWHG7KLVZRXOGEHDYLRODWLRQRIEXVSURWRFRO:KHQWKHPDVWHU LVUHDG\WRDVVHUWIRDY#LWGHDVVHUWVFRAME#LQGLFDWLQJWKHODVWGDWDSKDVHZKLFK FRPSOHWHVRQFORFNVLQFHSTOP#LVDVVHUWHG7KLVH[DPSOHRQO\FRQVLVWVRIWKUHHGDWD SKDVHVZKLOHWKHSUHYLRXVKDGIRXU7KHIDFWWKDWWKHPDVWHULQVHUWHGDZDLWVWDWHDOORZHG WKHPDVWHUWRFRPSOHWHWKHWUDQVDFWLRQZLWKWKHWKLUGGDWDSKDVH+RZHYHUIURPDFORFN FRXQWWKHWZRWUDQVDFWLRQVDUHWKHVDPH
CLK 1 2 3 4 5 6 7 8
FRAME#
IRDY# DATA TRANSFER TRDY# DATA TRANSFER
STOP#
DEVSEL#
DATA PHASE DATA DATA PHASE PHASE
)LJXUH 'LVFRQQHFW:LWKRXW'DWD7HUPLQDWLRQ
58 Revision 2.2
7DUJHW$ERUW )LJXUHVKRZVDWUDQVDFWLRQEHLQJWHUPLQDWHGZLWK7DUJHW$ERUW7DUJHW$ERUW LQGLFDWHVWKHWDUJHWUHTXLUHVWKHWUDQVDFWLRQWREHVWRSSHGDQGGRHVQRWZDQWWKHPDVWHUWR UHSHDWWKHUHTXHVWDJDLQ6RPHWLPHSULRUWRFORFNWKHPDVWHUDVVHUWHGFRAME#WR LQLWLDWHWKHUHTXHVWDQGWKHWDUJHWFODLPHGWKHDFFHVVE\DVVHUWLQJDEVSEL#'DWD SKDVHVPD\RUPD\QRWKDYHFRPSOHWHGSULRUWRFORFN7KHWDUJHWGHWHUPLQHVWKDWWKH PDVWHUKDVUHTXHVWHGDWUDQVDFWLRQWKDWWKHWDUJHWLVLQFDSDEOHRIFRPSOHWLQJRUKDV GHWHUPLQHGWKDWDIDWDOHUURUKDVRFFXUUHG%HIRUHWKHWDUJHWFDQVLJQDO7DUJHW$ERUW DEVSEL#PXVWEHDVVHUWHGIRURQHRUPRUHFORFNV7RVLJQDO7DUJHW$ERUWTRDY# PXVWEHGHDVVHUWHGZKHQDEVSEL#LVGHDVVHUWHGDQGSTOP#LVDVVHUWHGZKLFKRFFXUV RQFORFN,IDQ\GDWDZDVWUDQVIHUUHGGXULQJWKHSUHYLRXVGDWDSKDVHVRIWKHFXUUHQW WUDQVDFWLRQLWPD\KDYHEHHQFRUUXSWHG%HFDXVHSTOP#LVDVVHUWHGRQFORFNDQGWKH PDVWHUFDQDVVHUWIRDY#RQFORFNWKHPDVWHUGHDVVHUWVFRAME#RQFORFN7KH WUDQVDFWLRQFRPSOHWHVRQFORFNEHFDXVHIRDY#DQGSTOP#DUHDVVHUWHG7KHPDVWHU GHDVVHUWVIRDY#DQGWKHWDUJHWGHDVVHUWVSTOP#RQFORFN
CLK 1 2 3 4
FRAME#
IRDY#
TRDY#
STOP#
DEVSEL#
)LJXUH 7DUJHW$ERUW
3.3.3.2.2. Requirements on a Master Because of Target Termination
$OWKRXJKQRWDOOWDUJHWVZLOOLPSOHPHQWDOOIRUPVRIWDUJHWWHUPLQDWLRQPDVWHUVPXVWEH FDSDEOHRISURSHUO\GHDOLQJZLWKWKHPDOO
'HDVVHUWLRQRIREQ#:KHQ7DUJHW7HUPLQDWHG :KHQWKHFXUUHQWWUDQVDFWLRQLVWHUPLQDWHGE\WKHWDUJHWHLWKHUE\5HWU\RU'LVFRQQHFW ZLWKRUZLWKRXWGDWD WKHPDVWHUPXVWGHDVVHUWLWVREQ#VLJQDOEHIRUHUHSHDWLQJWKH WUDQVDFWLRQ$GHYLFHFRQWDLQLQJDVLQJOHVRXUFHRIPDVWHUDFWLYLW\PXVWGHDVVHUWREQ# IRUDPLQLPXPRIWZRFORFNVRQHEHLQJZKHQWKHEXVJRHVWRWKH,GOHVWDWH DWWKHHQGRI WKHWUDQVDFWLRQZKHUHSTOP#ZDVDVVHUWHG DQGHLWKHUWKHFORFNEHIRUHRUWKHFORFNDIWHU WKH,GOHVWDWH
59 Revision 2.2
6RPHGHYLFHVFRQWDLQPXOWLSOHVRXUFHVRIPDVWHUDFWLYLW\WKDWVKDUHWKHVDPHREQ#SLQ ([DPSOHVRIVXFKGHYLFHVLQFOXGHWKHIROORZLQJ • $VLQJOHIXQFWLRQGHYLFHWKDWFRQWDLQVWZRLQGHSHQGHQWVXEIXQFWLRQV2QHWKDW SURGXFHVGDWDDQGRQHWKDWFRQVXPHVGDWD • $PXOWLIXQFWLRQGHYLFH • $3&,WR3&,EULGJHWKDWLVFDSDEOHRIIRUZDUGLQJPXOWLSOH'HOD\HG7UDQVDFWLRQV IURPWKHRWKHUEXV $GHYLFHFRQWDLQLQJPXOWLSOHVRXUFHVRIPDVWHUDFWLYLW\WKDWVKDUHDVLQJOHREQ#SLQLV SHUPLWWHGWRDOORZHDFKVRXUFHWRXVHWKHEXV DVVXPLQJWKDWGNT#LVVWLOODVVHUWHG ZLWKRXWGHDVVHUWLQJREQ#HYHQLIRQHRUPRUHVRXUFHVDUHWDUJHWWHUPLQDWHG STOP# DVVHUWHG +RZHYHUWKHGHYLFHPXVWGHDVVHUWREQ#IRUWZRFRQVHFXWLYHFORFNVRQHRI ZKLFKZKLOHWKHEXVLV,GOHEHIRUHDQ\WUDQVDFWLRQWKDWZDVWDUJHWWHUPLQDWHGFDQEH UHSHDWHG 7KHPDVWHULVQRWUHTXLUHGWRGHDVVHUWLWVREQ#ZKHQWKHWDUJHWUHTXHVWVWKHWUDQVDFWLRQ WRHQGE\DVVHUWLQJSTOP#LQWKHODVWGDWDSKDVH$QH[DPSOHLV)LJXUHZKLFKLV UHDOO\0DVWHU&RPSOHWLRQWHUPLQDWLRQDQGQRWWDUJHWWHUPLQDWLRQ
5HSHDW5HTXHVW7HUPLQDWHG:LWK5HWU\ $PDVWHUZKLFKLVWDUJHWWHUPLQDWHGZLWK5HWU\PXVWXQFRQGLWLRQDOO\UHSHDWWKHVDPH UHTXHVWXQWLOLWFRPSOHWHV KRZHYHULWLVQRWUHTXLUHGWRUHSHDWWKHWUDQVDFWLRQZKHQ WHUPLQDWHGZLWK'LVFRQQHFW6DPHUHTXHVWPHDQVWKDWWKHVDPHDGGUHVVVDPH FRPPDQGVDPHE\WHHQDEOHVVDPHZULWHGDWDIRUZULWHWUDQVDFWLRQV HYHQLIWKHE\WH HQDEOHIRUWKDWE\WHODQHLVQRWDVVHUWHG DQGLIVXSSRUWHGLOCK#DQGREQ64# WKDW ZHUHXVHGRQWKHRULJLQDOUHTXHVWPXVWEHXVHGZKHQWKHDFFHVVLVUHSHDWHG 8QFRQGLWLRQDOO\LQWKHDERYHUXOHPHDQVWKHPDVWHUPXVWUHSHDWWKHVDPHWUDQVDFWLRQ WKDWZDVWHUPLQDWHGZLWK5HWU\LQGHSHQGHQWRIDQ\VXEVHTXHQWHYHQWV H[FHSWDVQRWHG EHORZ XQWLOWKHRULJLQDOWUDQVDFWLRQLVVDWLVILHG 7KLVGRHVQRWPHDQWKHPDVWHUPXVWLPPHGLDWHO\UHSHDWWKHVDPHWUDQVDFWLRQ,QWKH VLPSOHVWIRUPWKHPDVWHUZRXOGUHTXHVWXVHRIWKHEXVDIWHUWKHWZRFORFNVREQ#ZDV GHDVVHUWHGDQGUHSHDWWKHVDPHWUDQVDFWLRQ7KHPDVWHULVSHUPLWWHGWRSHUIRUPRWKHUEXV WUDQVDFWLRQVEXWFDQQRWUHTXLUHWKHPWRFRPSOHWHEHIRUHUHSHDWLQJWKHRULJLQDO WUDQVDFWLRQ,IWKHGHYLFHDOVRLPSOHPHQWVWDUJHWIXQFWLRQDOLW\LWPXVWEHDEOHWRDFFHSW DFFHVVHVGXULQJWKLVWLPHDVZHOO $PXOWLIXQFWLRQGHYLFHLVDJRRGH[DPSOHRIKRZWKLVZRUNV)XQFWLRQVDQGRID VLQJOHGHYLFHDUHDOOUHTXHVWLQJXVHRIWKHLQWHUIDFH)XQFWLRQUHTXHVWVDUHDG WUDQVDFWLRQDQGLVWHUPLQDWHGZLWK5HWU\2QFH)XQFWLRQKDVUHWXUQHGWKHEXVWRDQ,GOH VWDWH)XQFWLRQPD\DWWHPSWDWUDQVDFWLRQ DVVXPLQJGNT#LVVWLOODFWLYHIRUWKH GHYLFH $IWHU)XQFWLRQUHOHDVHVWKHEXV)XQFWLRQPD\SURFHHGLIGNT#LVVWLOO DFWLYH2QFH)XQFWLRQFRPSOHWHVWKHGHYLFHPXVWGHDVVHUWLWVREQ#IRUWKHWZR FORFNVEHIRUHUHDVVHUWLQJLW$VLOOXVWUDWHGDERYH)XQFWLRQLVQRWUHTXLUHGWRFRPSOHWH LWVWUDQVDFWLRQEHIRUHDQRWKHUIXQFWLRQFDQUHTXHVWDWUDQVDFWLRQ%XW)XQFWLRQPXVW UHSHDWLWVDFFHVVUHJDUGOHVVRIKRZWKHWUDQVDFWLRQVLQLWLDWHGE\)XQFWLRQRUDUH WHUPLQDWHG7KHPDVWHURIDWUDQVDFWLRQPXVWUHSHDWLWVWUDQVDFWLRQXQFRQGLWLRQDOO\ ZKLFKPHDQVWKHUHSHDWRIWKHWUDQVDFWLRQFDQQRWEHJDWHGE\DQ\RWKHUHYHQWRU FRQGLWLRQ 7KLVUXOHDSSOLHVWRDOOWUDQVDFWLRQVWKDWDUHWHUPLQDWHGE\5HWU\UHJDUGOHVVRIKRZPDQ\ SUHYLRXVWUDQVDFWLRQVPD\KDYHEHHQWHUPLQDWHGE\5HWU\,QWKHH[DPSOHDERYHLI )XQFWLRQDWWHPSWHGWRGRDWUDQVDFWLRQDQGZDVWHUPLQDWHGE\5HWU\LWPXVWUHSHDWWKDW
60 Revision 2.2
WUDQVDFWLRQXQFRQGLWLRQDOO\MXVWDV)XQFWLRQLVUHTXLUHGWRUHSHDWLWVWUDQVDFWLRQ XQFRQGLWLRQDOO\1HLWKHU)XQFWLRQQRU)XQFWLRQFDQGHSHQGRQWKHFRPSOHWLRQRIWKH RWKHUIXQFWLRQ VWUDQVDFWLRQRUWKHVXFFHVVRIDQ\WUDQVDFWLRQDWWHPSWHGE\)XQFWLRQWR EHDEOHWRUHSHDWLWVRULJLQDOUHTXHVW $VXEVHTXHQWWUDQVDFWLRQ QRWWKHRULJLQDOUHTXHVW FRXOGUHVXOWLQWKHDVVHUWLRQRI SERR#PERR#RUEHLQJWHUPLQDWHGZLWK5HWU\'LVFRQQHFW7DUJHW$ERUWRU0DVWHU $ERUW$Q\RIWKHVHHYHQWVZRXOGKDYHQRHIIHFWRQWKHUHTXLUHPHQWWKDWWKHPDVWHUPXVW UHSHDWDQDFFHVVWKDWZDVWHUPLQDWHGZLWK5HWU\ $PDVWHUVKRXOGUHSHDWDWUDQVDFWLRQWHUPLQDWHGE\5HWU\DVVRRQDVSRVVLEOHSUHIHUDEO\ ZLWKLQFORFNV+RZHYHUWKHUHDUHDIHZFRQGLWLRQVZKHQDPDVWHULVXQDEOHWRUHSHDW WKHUHTXHVW7KHVHFRQGLWLRQVW\SLFDOO\DUHFDXVHGZKHQDQHUURURFFXUV IRUH[DPSOH WKHV\VWHPDVVHUWVRST#WKHGHYLFHGULYHUUHVHWVDQGWKHQUHLQLWLDOL]HVWKHFRPSRQHQW RUVRIWZDUHGLVDEOHVWKHPDVWHUE\UHVHWWLQJWKH%XV0DVWHUELW ELWLQWKH&RPPDQG UHJLVWHU 5HIHUWR6HFWLRQIRUDGHVFULSWLRQRIKRZDWDUJHWXVLQJ'HOD\HG 7UDQVDFWLRQWHUPLQDWLRQKDQGOHVWKLVHUURUFRQGLWLRQ +RZHYHUZKHQWKHPDVWHUUHSHDWVWKHWUDQVDFWLRQDQGILQDOO\LVVXFFHVVIXOLQWUDQVIHUULQJ GDWDLWLVQRWUHTXLUHGWRFRQWLQXHWKHWUDQVDFWLRQSDVWWKHILUVWGDWDSKDVH Implementation Note: Potential Temporary Deadlock and Resulting Performance Impacts 7KHSUHYLRXVSDUDJUDSKVWDWHVWKDWDPDVWHUPD\SHUIRUPRWKHUEXVWUDQVDFWLRQVEXW FDQQRWUHTXLUHWKHPWRFRPSOHWHEHIRUHUHSHDWLQJWKHRULJLQDOWUDQVDFWLRQ RQHSUHYLRXVO\ WDUJHWWHUPLQDWHGZLWK5HWU\ ,IDPDVWHUGRHVQRWPHHWWKLVUHTXLUHPHQWLWPD\FDXVH WHPSRUDU\GHDGORFNVUHVXOWLQJLQVLJQLILFDQWGHYLFHDQGV\VWHPSHUIRUPDQFHLPSDFWV 'HYLFHVGHVLJQHGSULRUWR5HYLVLRQRIWKLVVSHFLILFDWLRQPD\H[KLELWWKLVEHKDYLRU 6XFKWHPSRUDU\GHDGORFNVVKRXOGHYHQWXDOO\FOHDUZKHQWKHGLVFDUGWLPHU UHIHUWR 6HFWLRQ H[SLUHV
3.3.3.3. Delayed Transactions
'HOD\HG7UDQVDFWLRQWHUPLQDWLRQLVXVHGE\WDUJHWVWKDWFDQQRWFRPSOHWHWKHLQLWLDOGDWD SKDVHZLWKLQWKHUHTXLUHPHQWVRIWKLVVSHFLILFDWLRQ7KHUHDUHWZRW\SHVRIGHYLFHVWKDW ZLOOXVH'HOD\HG7UDQVDFWLRQV ,2FRQWUROOHUVDQGEULGJHV LQSDUWLFXODU3&,WR3&, EULGJHV ,QJHQHUDO,2FRQWUROOHUVZLOOKDQGOHRQO\DVLQJOH'HOD\HG7UDQVDFWLRQDWD WLPHZKLOHEULGJHVPD\FKRRVHWRKDQGOHPXOWLSOHWUDQVDFWLRQVWRLPSURYHV\VWHP SHUIRUPDQFH 2QHDGYDQWDJHRID'HOD\HG7UDQVDFWLRQLVWKDWWKHEXVLVQRWKHOGLQZDLWVWDWHVZKLOH FRPSOHWLQJDQDFFHVVWRDVORZGHYLFH:KLOHWKHRULJLQDWLQJPDVWHUUHDUELWUDWHVIRUWKH EXVRWKHUEXVPDVWHUVDUHDOORZHGWRXVHWKHEXVEDQGZLGWKWKDWZRXOGQRUPDOO\EH ZDVWHGKROGLQJWKHPDVWHULQZDLWVWDWHV$QRWKHUDGYDQWDJHLVWKDWDOOSRVWHG PHPRU\ ZULWH GDWDLVQRWUHTXLUHGWREHIOXVKHGEHIRUHWKHUHTXHVWLVDFFHSWHG7KHDFWXDO IOXVKLQJRIWKHSRVWHGPHPRU\ZULWHGDWDRFFXUVEHIRUHWKH'HOD\HG7UDQVDFWLRQ FRPSOHWHVRQWKHRULJLQDWLQJEXV7KLVDOORZVSRVWLQJWRUHPDLQHQDEOHGZKLOHDQRQ SRVWDEOHWUDQVDFWLRQFRPSOHWHVDQGVWLOOPDLQWDLQVWKHV\VWHPRUGHULQJUXOHV 7KHIROORZLQJGLVFXVVLRQIRFXVHVRQWKHEDVLFRSHUDWLRQDQGUHTXLUHPHQWVRIDGHYLFH WKDWVXSSRUWVDVLQJOH'HOD\HG7UDQVDFWLRQDWDWLPH6HFWLRQH[WHQGVWKHEDVLF FRQFHSWVIURPVXSSRUWRIDVLQJOH'HOD\HG7UDQVDFWLRQWRWKHVXSSRUWRIPXOWLSOH 'HOD\HG7UDQVDFWLRQVDWDWLPH
61 Revision 2.2
3.3.3.3.1. Basic Operation of a Delayed Transaction
$OOEXVFRPPDQGVWKDWPXVWFRPSOHWHRQWKHGHVWLQDWLRQEXVEHIRUHFRPSOHWLQJRQWKH RULJLQDWLQJEXVPD\EHFRPSOHWHGDVD'HOD\HG7UDQVDFWLRQ7KHVHLQFOXGH,QWHUUXSW $FNQRZOHGJH,25HDG,2:ULWH&RQILJXUDWLRQ5HDG&RQILJXUDWLRQ:ULWH0HPRU\ 5HDG0HPRU\5HDG/LQHDQG0HPRU\5HDG0XOWLSOHFRPPDQGV0HPRU\:ULWHDQG 0HPRU\:ULWHDQG,QYDOLGDWHFRPPDQGVFDQFRPSOHWHRQWKHRULJLQDWLQJEXVEHIRUH FRPSOHWLQJRQWKHGHVWLQDWLRQEXV LHFDQEHSRVWHG (DFKFRPPDQGLVQRWFRPSOHWHG XVLQJ'HOD\HG7UDQVDFWLRQWHUPLQDWLRQDQGDUHHLWKHUSRVWHGRUWHUPLQDWHGZLWK5HWU\ )RU,2FRQWUROOHUVWKHWHUPGHVWLQDWLRQEXVUHIHUVWRWKHLQWHUQDOEXVZKHUHWKHUHVRXUFH DGGUHVVHGE\WKHWUDQVDFWLRQUHVLGHV)RUDEULGJHWKHGHVWLQDWLRQEXVPHDQVWKH LQWHUIDFHWKDWZDVQRWDFWLQJDVWKHWDUJHWRIWKHRULJLQDOUHTXHVW)RUH[DPSOHWKH VHFRQGDU\EXVRIDEULGJHLVWKHGHVWLQDWLRQEXVZKHQDWUDQVDFWLRQRULJLQDWHVRQWKH SULPDU\EXVRIWKHEULGJHDQGWDUJHWV DGGUHVVHV DGHYLFHDWWDFKHGWRWKHVHFRQGDU\EXV RIWKHEULGJH+RZHYHUDWUDQVDFWLRQWKDWLVPRYLQJLQWKHRSSRVLWHGLUHFWLRQZRXOG KDYHWKHSULPDU\EXVDVWKHGHVWLQDWLRQEXV $'HOD\HG7UDQVDFWLRQSURJUHVVHVWRFRPSOHWLRQLQWKUHHVWHSV 5HTXHVWE\WKHPDVWHU &RPSOHWLRQRIWKHUHTXHVWE\WKHWDUJHW &RPSOHWLRQRIWKHWUDQVDFWLRQE\WKHPDVWHU 'XULQJWKHILUVWVWHSWKHPDVWHUJHQHUDWHVDWUDQVDFWLRQRQWKHEXVWKHWDUJHWGHFRGHVWKH DFFHVVODWFKHVWKHLQIRUPDWLRQUHTXLUHGWRFRPSOHWHWKHDFFHVVDQGWHUPLQDWHVWKH UHTXHVWZLWK5HWU\7KHODWFKHGUHTXHVWLQIRUPDWLRQLVUHIHUUHGWRDVD'HOD\HG5HTXHVW 7KHPDVWHURIDUHTXHVWWKDWLVWHUPLQDWHGZLWK5HWU\FDQQRWGLVWLQJXLVKEHWZHHQDWDUJHW ZKLFKLVFRPSOHWLQJWKHWUDQVDFWLRQXVLQJ'HOD\HG7UDQVDFWLRQWHUPLQDWLRQDQGDWDUJHW ZKLFKVLPSO\FDQQRWFRPSOHWHWKHWUDQVDFWLRQDWWKHFXUUHQWWLPH6LQFHWKHPDVWHU FDQQRWWHOOWKHGLIIHUHQFHLWPXVWUHLVVXHDQ\UHTXHVWWKDWKDVEHHQWHUPLQDWHGZLWK5HWU\ XQWLOWKHUHTXHVWFRPSOHWHV UHIHUWR6HFWLRQ 'XULQJWKHVHFRQGVWHSWKHWDUJHWLQGHSHQGHQWO\FRPSOHWHVWKHUHTXHVWRQWKHGHVWLQDWLRQ EXVXVLQJWKHODWFKHGLQIRUPDWLRQIURPWKH'HOD\HG5HTXHVW,IWKH'HOD\HG5HTXHVWLVD UHDGWKHWDUJHWREWDLQVWKHUHTXHVWHGGDWDDQGFRPSOHWLRQVWDWXV,IWKH'HOD\HG5HTXHVW LVDZULWHWKHWDUJHWGHOLYHUVWKHZULWHGDWDDQGREWDLQVWKHFRPSOHWLRQVWDWXV7KHUHVXOW RIFRPSOHWLQJWKH'HOD\HG5HTXHVWRQWKHGHVWLQDWLRQEXVSURGXFHVD'HOD\HG &RPSOHWLRQZKLFKFRQVLVWVRIWKHODWFKHGLQIRUPDWLRQRIWKH'HOD\5HTXHVWDQGWKH FRPSOHWLRQVWDWXV DQGGDWDLIDUHDGUHTXHVW 7KHWDUJHWVWRUHVWKH'HOD\HG&RPSOHWLRQ XQWLOWKHPDVWHUUHSHDWVWKHLQLWLDOUHTXHVW 'XULQJWKHWKLUGVWHSWKHPDVWHUVXFFHVVIXOO\UHDUELWUDWHVIRUWKHEXVDQGUHLVVXHVWKH RULJLQDOUHTXHVW7KHWDUJHWGHFRGHVWKHUHTXHVWDQGJLYHVWKHPDVWHUWKHFRPSOHWLRQ VWDWXV DQGGDWDLIDUHDGUHTXHVW $WWKLVSRLQWWKH'HOD\HG&RPSOHWLRQLVUHWLUHGDQG WKHWUDQVDFWLRQKDVFRPSOHWHG7KHVWDWXVUHWXUQHGWRWKHPDVWHULVH[DFWO\WKHVDPHDV WKHWDUJHWREWDLQHGZKHQLWH[HFXWHG FRPSOHWHG WKH'HOD\HG5HTXHVW LH0DVWHU $ERUW7DUJHW$ERUWSDULW\HUURUQRUPDO'LVFRQQHFWHWF
62 Revision 2.2
3.3.3.3.2. Information Required to Complete a Delayed Transaction
7RFRPSOHWHDWUDQVDFWLRQXVLQJ'HOD\HG7UDQVDFWLRQWHUPLQDWLRQDWDUJHWPXVWODWFKWKH IROORZLQJLQIRUPDWLRQ • DGGUHVV • FRPPDQG • E\WHHQDEOHV • DGGUHVVDQGGDWDSDULW\LIWKH3DULW\(UURU5HVSRQVHELW ELWRIWKHFRPPDQG UHJLVWHU LVVHW • REQ64# LIDELWWUDQVIHU )RUZULWHWUDQVDFWLRQVFRPSOHWHGXVLQJ'HOD\HG7UDQVDFWLRQWHUPLQDWLRQDWDUJHWPXVW DOVRODWFKGDWDIURPE\WHODQHVIRUZKLFKWKHE\WHHQDEOHLVDVVHUWHGDQGPD\RSWLRQDOO\ ODWFKGDWDIURPE\WHODQHVIRUZKLFKWKHE\WHHQDEOHLVGHDVVHUWHG5HIHUWR$SSHQGL[) IRUUHTXLUHPHQWVIRUDEULGJHWRODWFKLOCK#ZKHQFRPSOHWLQJD'HOD\HG7UDQVDFWLRQ 2QDUHDGWUDQVDFWLRQWKHDGGUHVVDQGFRPPDQGDUHDYDLODEOHGXULQJWKHDGGUHVVSKDVH DQGWKHE\WHHQDEOHVGXULQJWKHIROORZLQJFORFN%\WHHQDEOHVIRUERWKUHDGDQGZULWH WUDQVDFWLRQVDUHYDOLGWKHHQWLUHGDWDSKDVHDQGDUHLQGHSHQGHQWRIIRDY#2QDZULWH WUDQVDFWLRQDOOLQIRUPDWLRQLVYDOLGDWWKHVDPHWLPHDVDUHDGWUDQVDFWLRQH[FHSWIRUWKH DFWXDOGDWDZKLFKLVYDOLGRQO\ZKHQIRDY#LVDVVHUWHG 1RWH :ULWHGDWDLVRQO\YDOLGZKHQIRDY#LVDVVHUWHG%\WHHQDEOHVDUHDOZD\V YDOLGIRUWKHHQWLUHGDWDSKDVHUHJDUGOHVVRIWKHVWDWHRIIRDY# 7KHWDUJHWGLIIHUHQWLDWHVEHWZHHQWUDQVDFWLRQV E\WKHVDPHRUGLIIHUHQWPDVWHUV E\ FRPSDULQJWKHFXUUHQWWUDQVDFWLRQZLWKLQIRUPDWLRQODWFKHGSUHYLRXVO\ IRUERWK'HOD\HG 5HTXHVW V DQG'HOD\HG&RPSOHWLRQ V 'XULQJDUHDGWUDQVDFWLRQWKHWDUJHWLVQRW UHTXLUHGWRXVHE\WHHQDEOHVDVSDUWRIWKHFRPSDULVRQLIDOOE\WHVDUHUHWXUQHG LQGHSHQGHQWRIWKHDVVHUWHGE\WHHQDEOHVDQGWKHDFFHVVHGORFDWLRQKDVQRUHDGVLGH HIIHFWV SUHIHWFKDEOH ,IWKHFRPSDUHPDWFKHVD'HOD\HG5HTXHVW DOUHDG\HQTXHXHG WKHWDUJHWGRHVQRWHQTXHXHWKHUHTXHVWDJDLQEXWVLPSO\WHUPLQDWHVWKHWUDQVDFWLRQZLWK 5HWU\LQGLFDWLQJWKDWWKHWDUJHWLVQRW\HWUHDG\WRFRPSOHWHWKHUHTXHVW,IWKHFRPSDUH PDWFKHVD'HOD\HG&RPSOHWLRQWKHWDUJHWUHVSRQGVE\VLJQDOLQJWKHVWDWXVDQGSURYLGLQJ WKHGDWDLIDUHDGWUDQVDFWLRQ 7KHPDVWHUPXVWUHSHDWWKHWUDQVDFWLRQH[DFWO\DVWKHRULJLQDOUHTXHVWLQFOXGLQJZULWH GDWDLQDOOE\WHODQHV ZKHWKHUWKHFRUUHVSRQGLQJE\WHHQDEOHVDUHDVVHUWHGRUQRW 2WKHUZLVHWKHWDUJHWZLOODVVXPHLWLVDQHZWUDQVDFWLRQ,IWKHRULJLQDOWUDQVDFWLRQLV QHYHUUHSHDWHGLWZLOOHYHQWXDOO\EHGLVFDUGHGZKHQWKH'LVFDUG7LPHUH[SLUHV UHIHUWR 6HFWLRQ 7ZRPDVWHUVFRXOGUHTXHVWWKHH[DFWVDPHWUDQVDFWLRQDQGWKHWDUJHW FDQQRWDQGQHHGQRWGLVWLQJXLVKEHWZHHQWKHPDQGZLOOVLPSO\FRPSOHWHWKHDFFHVV 6SHFLDOUHTXLUHPHQWVDSSO\LIDGDWDSDULW\HUURURFFXUVZKLOHLQLWLDWLQJRUFRPSOHWLQJD 'HOD\HG7UDQVDFWLRQ5HIHUWR6HFWLRQIRUGHWDLOVDERXWDSDULW\HUURUDQG'HOD\HG 7UDQVDFWLRQV
63 Revision 2.2
3.3.3.3.3. Discarding a Delayed Transaction
$GHYLFHLVDOORZHGWRGLVFDUGD'HOD\HG5HTXHVWIURPWKHWLPHLWLVHQTXHXHGXQWLOLWKDV EHHQDWWHPSWHGRQWKHGHVWLQDWLRQEXVVLQFHWKHPDVWHULVUHTXLUHGWRUHSHDWWKHUHTXHVW XQWLOLWFRPSOHWHV2QFHD5HTXHVWKDVEHHQDWWHPSWHGRQWKHGHVWLQDWLRQEXVLWPXVW FRQWLQXHWREHUHSHDWHGXQWLOLWFRPSOHWHVRQWKHGHVWLQDWLRQEXVDQGFDQQRWEHGLVFDUGHG 7KHPDVWHULVDOORZHGWRSUHVHQWRWKHUUHTXHVWV%XWLILWDWWHPSWVPRUHWKDQRQHUHTXHVW WKHPDVWHUPXVWFRQWLQXHWRUHSHDWDOOUHTXHVWVWKDWKDYHEHHQDWWHPSWHGXQFRQGLWLRQDOO\ XQWLOWKH\FRPSOHWH7KHUHSHDWLQJRIWKHUHTXHVWVLVQRWUHTXLUHGWREHHTXDOEXWLV UHTXLUHGWREHIDLU :KHQD'HOD\HG5HTXHVWFRPSOHWHVRQWKHGHVWLQDWLRQEXVLWEHFRPHVD'HOD\HG &RPSOHWLRQ7KHWDUJHWGHYLFHLVDOORZHGWRGLVFDUG'HOD\HG&RPSOHWLRQVLQRQO\WZR FDVHV7KHILUVWFDVHLVZKHQWKH'HOD\HG&RPSOHWLRQLVDUHDGWRDSUHIHWFKDEOHUHJLRQ RUWKHFRPPDQGZDV0HPRU\5HDG/LQHRU0HPRU\5HDG0XOWLSOH 7KHVHFRQGFDVH LVIRUDOO'HOD\HG&RPSOHWLRQV UHDGRUZULWHSUHIHWFKDEOHRUQRW ZKHQWKHPDVWHUKDV QRWUHSHDWHGWKHUHTXHVWZLWKLQ FORFNV:KHQWKLVWLPHU UHIHUUHGWRDVWKH'LVFDUG 7LPHU H[SLUHVWKHGHYLFHLVUHTXLUHGWRGLVFDUGWKHGDWD RWKHUZLVHDGHDGORFNPD\ RFFXU 1RWH :KHQWKHWUDQVDFWLRQLVGLVFDUGHGGDWDPD\EHGHVWUR\HG7KLVRFFXUVZKHQWKH GLVFDUGHG'HOD\HG&RPSOHWLRQLVDUHDGWRDQRQSUHIHWFKDEOHUHJLRQ ,IWKH'LVFDUG7LPHUH[SLUHVWKHGHYLFHPD\FKRRVHWRUHSRUWDQHUURURUQRW,IWKHGDWD LVSUHIHWFKDEOH FDVH LWLVUHFRPPHQGHGWKDWWKHGHYLFHQRWUHSRUWDQHUURUVLQFH V\VWHPLQWHJULW\LVQRWHIIHFWHG+RZHYHULIWKHGDWDRQDUHDGDFFHVVLVQRWSUHIHWFKDEOH FDVH LWLVUHFRPPHQGHGWKDWWKHGHYLFHUHSRUWWKHHUURUWRLWVGHYLFHGULYHUVLQFH V\VWHPLQWHJULW\LVDIIHFWHG
3.3.3.3.4. Memory Writes and Delayed Transactions
:KLOHFRPSOHWLQJD'HOD\HG5HTXHVWWKHWDUJHWLVDOVRUHTXLUHGWRFRPSOHWHDOOPHPRU\ ZULWHWUDQVDFWLRQVDGGUHVVHGWRLW7KHWDUJHWPD\IURPWLPHWRWLPHUHWU\DPHPRU\ ZULWHZKLOHWHPSRUDU\LQWHUQDOFRQIOLFWVDUHEHLQJUHVROYHG IRUH[DPSOHZKHQDOOWKH PHPRU\ZULWHGDWDEXIIHUVDUHIXOORUEHIRUHWKH'HOD\HG5HTXHVWKDVFRPSOHWHGRQWKH GHVWLQDWLRQEXV EXWLVJXDUDQWHHGWRFRPSOHWH +RZHYHUWKHWDUJHWFDQQRWUHTXLUHWKH 'HOD\HG7UDQVDFWLRQWRFRPSOHWHRQWKHRULJLQDWLQJEXVEHIRUHDFFHSWLQJWKHPHPRU\ ZULWHGDWD RWKHUZLVHDGHDGORFNPD\RFFXU5HIHUWR6HFWLRQLWHPIRU DGGLWLRQDOLQIRUPDWLRQ7KHIROORZLQJLPSOHPHQWDWLRQQRWHGHVFULEHVWKHGHDGORFN
64 Revision 2.2
Implementation Note: Deadlock When Memory Write Data is Not Accepted 7KHGHDGORFNRFFXUVZKHQWKHPDVWHUDQGWKHWDUJHWRIDWUDQVDFWLRQUHVLGHRQGLIIHUHQW EXVHV RUVHJPHQWV 7KH3&,WR3&,EULGJH WKDWFRQQHFWVWKHWZREXVHVWRJHWKHUGRHV QRWLPSOHPHQW'HOD\HG7UDQVDFWLRQV7KHPDVWHULQLWLDWHVDUHTXHVWWKDWLVIRUZDUGHGWR WKHWDUJHWE\WKHEULGJH7KHWDUJHWUHVSRQGVWRWKHUHTXHVWE\XVLQJ'HOD\HG7UDQVDFWLRQ WHUPLQDWLRQ WHUPLQDWHGZLWK5HWU\ 7KHEULGJHWHUPLQDWHVWKHPDVWHU¶VUHTXHVWZLWK 5HWU\ ZLWKRXWODWFKLQJWKHUHTXHVW $QRWKHUPDVWHU RQWKHVDPHEXVVHJPHQWDVWKH RULJLQDOPDVWHU SRVWVZULWHGDWDLQWRWKHEULGJHWDUJHWHGDWWKHVDPHGHYLFHDVWKHUHDG UHTXHVW%HFDXVHLWLVGHVLJQHGWRWKHSUHYLRXVYHUVLRQRIWKLVVSHFLILFDWLRQEHIRUH 'HOD\HG7UDQVDFWLRQVWKHEULGJHLVUHTXLUHGWRIOXVKWKHPHPRU\ZULWHGDWDEHIRUHWKH UHDGFDQEHUHSHDWHG,IWKHWDUJHWWKDWXVHV'HOD\HG7UDQVDFWLRQWHUPLQDWLRQZLOOQRW DFFHSWWKHPHPRU\ZULWHGDWDXQWLOWKHPDVWHUUHSHDWVWKHLQLWLDOUHDGDGHDGORFNRFFXUV EHFDXVHWKHEULGJHFDQQRWUHSHDWWKHUHTXHVWXQWLOWKHWDUJHWDFFHSWVWKHZULWHGDWD7R SUHYHQWWKLVIURPRFFXUULQJWKHWDUJHWWKDWXVHVWKH'HOD\HG7UDQVDFWLRQWHUPLQDWLRQWR PHHWWKHLQLWLDOODWHQF\UHTXLUHPHQWVLVUHTXLUHGWRDFFHSWPHPRU\ZULWHGDWDHYHQ WKRXJKWKH'HOD\HG7UDQVDFWLRQKDVQRWFRPSOHWHG
3.3.3.3.5. Supporting Multiple Delayed Transactions
7KLVVHFWLRQWDNHVWKHEDVLFFRQFHSWVRIDVLQJOH'HOD\HG7UDQVDFWLRQDVGHVFULEHGLQWKH SUHYLRXVVHFWLRQDQGH[WHQGVWKHPWRVXSSRUWPXOWLSOH'HOD\HG7UDQVDFWLRQVDWWKHVDPH WLPH%ULGJHV LQSDUWLFXODU3&,WR3&,EULGJHV DUHWKHPRVWOLNHO\FDQGLGDWHVWRKDQGOH PXOWLSOH'HOD\HG7UDQVDFWLRQVDVDZD\WRLPSURYHV\VWHPSHUIRUPDQFHDQGPHHWWKH LQLWLDOODWHQF\UHTXLUHPHQWV7RDVVLVWLQXQGHUVWDQGLQJWKHUHTXLUHPHQWVRIVXSSRUWLQJ PXOWLSOH'HOD\HG7UDQVDFWLRQVWKHIROORZLQJVHFWLRQIRFXVHVRQD3&,WR3&,EULGJH 7KLVIRFXVDOORZVWKHVDPHWHUPLQRORJ\WREHXVHGZKHQGHVFULELQJWUDQVDFWLRQVLQLWLDWHG RQHLWKHULQWHUIDFHRIWKHEULGJH0RVWRWKHUEULGJHV KRVWEXVEULGJHDQGVWDQGDUG H[SDQVLRQEXVEULGJH ZLOOW\SLFDOO\KDQGOHRQO\DVLQJOH'HOD\HG7UDQVDFWLRQ 6XSSRUWLQJPXOWLSOHWUDQVDFWLRQVLVSRVVLEOHEXWWKHGHWDLOVPD\YDU\7KHIXQGDPHQWDO UHTXLUHPHQWVLQDOOFDVHVDUHWKDWWUDQVDFWLRQRUGHULQJEHPDLQWDLQHGDVGHVFULEHGLQ 6HFWLRQDQG6HFWLRQDQGGHDGORFNVZLOOEHDYRLGHG
7UDQVDFWLRQ'HILQLWLRQV 30:3RVWHG0HPRU\:ULWHLVDWUDQVDFWLRQWKDWKDVFRPSOHWHGRQWKHRULJLQDWLQJEXV EHIRUHFRPSOHWLQJRQWKHGHVWLQDWLRQEXVDQGFDQRQO\RFFXUIRU0HPRU\:ULWHDQG 0HPRU\:ULWHDQG,QYDOLGDWHFRPPDQGV '55'HOD\HG5HDG5HTXHVWLVDWUDQVDFWLRQWKDWPXVWFRPSOHWHRQWKHGHVWLQDWLRQEXV EHIRUHFRPSOHWLQJRQWKHRULJLQDWLQJEXVDQGFDQEHDQ,QWHUUXSW$FNQRZOHGJH,2 5HDG&RQILJXUDWLRQ5HDG0HPRU\5HDG0HPRU\5HDG/LQHRU0HPRU\5HDG 0XOWLSOHFRPPDQG$VPHQWLRQHGHDUOLHURQFHDUHTXHVWKDVEHHQDWWHPSWHGRQWKH GHVWLQDWLRQEXVLWPXVWFRQWLQXHWREHUHSHDWHGXQWLOLWFRPSOHWHVRQWKHGHVWLQDWLRQEXV 8QWLOWKDWWLPHWKH'55LVRQO\DUHTXHVWDQGPD\EHGLVFDUGHGDWDQ\WLPHWRSUHYHQW GHDGORFNRULPSURYHSHUIRUPDQFHVLQFHWKHPDVWHUPXVWUHSHDWWKHUHTXHVWODWHU ':5'HOD\HG:ULWH5HTXHVWLVDWUDQVDFWLRQWKDWPXVWFRPSOHWHRQWKHGHVWLQDWLRQEXV EHIRUHFRPSOHWLQJRQWKHRULJLQDWLQJEXVDQGFDQEHDQ,2:ULWHRU&RQILJXUDWLRQ:ULWH
18 This is a bridge that is built to an earlier version of this specification.
65 Revision 2.2
FRPPDQG1RWH 0HPRU\:ULWHDQG0HPRU\:ULWHDQG,QYDOLGDWHFRPPDQGVPXVWEH SRVWHG 30: DQGQRWEHFRPSOHWHGDV':5$VPHQWLRQHGHDUOLHURQFHDUHTXHVWKDV EHHQDWWHPSWHGRQWKHGHVWLQDWLRQEXVLWPXVWFRQWLQXHWREHUHSHDWHGXQWLOLWFRPSOHWHV 8QWLOWKDWWLPHWKH':5LVRQO\DUHTXHVWDQGPD\EHGLVFDUGHGDWDQ\WLPHWRSUHYHQW GHDGORFNRULPSURYHSHUIRUPDQFHVLQFHWKHPDVWHUPXVWUHSHDWWKHUHTXHVWODWHU '5&'HOD\HG5HDG&RPSOHWLRQLVDWUDQVDFWLRQWKDWKDVFRPSOHWHGRQWKHGHVWLQDWLRQ EXVDQGLVQRZPRYLQJWRZDUGWKHRULJLQDWLQJEXVWRFRPSOHWH7KH'5&FRQWDLQVWKH GDWDUHTXHVWHGE\WKHPDVWHUDQGWKHVWDWXVRIWKHWDUJHW QRUPDO0DVWHU$ERUW7DUJHW $ERUWSDULW\HUURUHWF ':&'HOD\HG:ULWH&RPSOHWLRQLVDWUDQVDFWLRQWKDWKDVFRPSOHWHGRQWKHGHVWLQDWLRQ EXVDQGLVQRZPRYLQJWRZDUGWKHRULJLQDWLQJEXV7KH':&GRHVQRWFRQWDLQWKHGDWD RIWKHDFFHVVEXWRQO\VWDWXVRIKRZLWFRPSOHWHG QRUPDO0DVWHU$ERUW7DUJHW$ERUW SDULW\HUURUHWF 7KHZULWHGDWDKDVEHHQZULWWHQWRWKHVSHFLILHGWDUJHW
2UGHULQJ5XOHVIRU0XOWLSOH'HOD\HG7UDQVDFWLRQV 7DEOHUHSUHVHQWVWKHRUGHULQJUXOHVZKHQDEULGJHLQWKHV\VWHPLVFDSDEOHRI DOORZLQJPXOWLSOHWUDQVDFWLRQVWRSURFHHGLQHDFKGLUHFWLRQDWWKHVDPHWLPH7KH QXPEHURIVLPXOWDQHRXVWUDQVDFWLRQVLVOLPLWHGE\WKHLPSOHPHQWDWLRQDQGQRWE\WKH DUFKLWHFWXUH%HFDXVHWKHUHDUHILYHW\SHVRIWUDQVDFWLRQVWKDWFDQEHKDQGOHGLQHDFK GLUHFWLRQWKHIROORZLQJWDEOHKDVHQWULHV2IWKHER[HVLQWKHWDEOHRQO\IRXUDUH UHTXLUHG1R¶VHLJKWDUHUHTXLUHG 7DEOH 2UGHULQJ5XOHVIRU0XOWLSOH'HOD\HG7UDQVDFWLRQV Row pass PMW (Col 2) DRR (Col 3) DWR (Col 4) DRC (Col 5) DWC (Col 6) Col.? PMW (Row 1) No Yes Yes Yes Yes DRR (Row 2) No Yes/No Yes/No Yes/No Yes/No DWR (Row 3) No Yes/No Yes/No Yes/No Yes/No DRC (Row 4) No Yes Yes Yes/No Yes/No DWC (Row 5) Yes/No Yes Yes Yes/No Yes/No 1RLQGLFDWHVWKHVXEVHTXHQWWUDQVDFWLRQLVQRWDOORZHGWRFRPSOHWHEHIRUHWKHSUHYLRXV WUDQVDFWLRQWRSUHVHUYHRUGHULQJLQWKHV\VWHP7KHIRXU1RER[HVDUHIRXQGLQFROXPQ DQGPDLQWDLQDFRQVLVWHQWYLHZRIGDWDLQWKHV\VWHPDVGHVFULEHGE\WKH3URGXFHU &RQVXPHU0RGHOIRXQGLQ$SSHQGL[(7KHVHER[HVSUHYHQW30:GDWDIURPEHLQJ SDVVHGE\RWKHUDFFHVVHV 66 Revision 2.2 FRQWLQXHVDWWHPSWLQJWRFRPSOHWH'HOD\HG5HTXHVWVLWPXVWEHIDLULQDWWHPSWLQJWR FRPSOHWHWKH30:7KHUHLVQRRUGHULQJYLRODWLRQZKHQDVXEVHTXHQWWUDQVDFWLRQ FRPSOHWHVEHIRUHDSULRUWUDQVDFWLRQ 7KHIRXU 2UGHULQJRI'HOD\HG7UDQVDFWLRQV 7KHRUGHULQJRI'HOD\HG7UDQVDFWLRQVLVHVWDEOLVKHGZKHQWKHWUDQVDFWLRQFRPSOHWHVRQ WKHRULJLQDWLQJEXV LHWKHUHTXHVWLQJPDVWHUUHFHLYHVDUHVSRQVHRWKHUWKDQ5HWU\ 'HOD\HG5HTXHVWVDQG'HOD\HG&RPSOHWLRQVDUHLQWHUPHGLDWHVWHSVLQWKHSURFHVVRI FRPSOHWLQJD'HOD\HG7UDQVDFWLRQZKLFKRFFXUSULRUWRWKHFRPSOHWLRQRIWKH WUDQVDFWLRQRQWKHRULJLQDWLQJEXV$VDUHVXOWUHRUGHULQJLVDOORZHGIRU'HOD\HG 5HTXHVWVZLWKUHVSHFWWRRWKHU'HOD\HG5HTXHVWV'HOD\HG5HTXHVWVZLWKUHVSHFWWR 'HOD\HG&RPSOHWLRQVRUIRU'HOD\HG&RPSOHWLRQVZLWKUHVSHFWWRRWKHU'HOD\HG &RPSOHWLRQV+RZHYHUUHRUGHULQJLVQRWDOORZHGZLWKUHVSHFWWRPHPRU\ZULWH WUDQVDFWLRQVZKLFKLVGHVFULEHGLQ7DEOH WKH1RER[HV ,QJHQHUDODPDVWHUGRHVQRWQHHGWRZDLWIRURQHUHTXHVWWREHFRPSOHWHGEHIRUHLWLVVXHV DQRWKHUUHTXHVW$VGHVFULEHGLQ6HFWLRQDPDVWHUPD\KDYHDQ\QXPEHURI UHTXHVWVWHUPLQDWHGZLWK5HWU\DWRQHWLPHVRPHRIZKLFKPD\EHVHUYLFHGDV'HOD\HG 7UDQVDFWLRQVDQGVRPHQRW+RZHYHULIWKHPDVWHUGRHVLVVXHDVHFRQGUHTXHVWEHIRUH WKHILUVWLVFRPSOHWHGWKHPDVWHUPXVWFRQWLQXHWRUHSHDWHDFKRIWKHUHTXHVWVIDLUO\VR WKDWHDFKKDVDIDLURSSRUWXQLW\WREHFRPSOHWHG,IDPDVWHUKDVDVSHFLILFQHHGIRUWZR WUDQVDFWLRQVWREHFRPSOHWHGLQDSDUWLFXODURUGHULWPXVWZDLWIRUWKHILUVWRQHWR FRPSOHWHEHIRUHUHTXHVWLQJWKHVHFRQG 67 Revision 2.2 3.4. Arbitration ,QRUGHUWRPLQLPL]HDFFHVVODWHQF\WKH3&,DUELWUDWLRQDSSURDFKLVDFFHVVEDVHGUDWKHU WKDQWLPHVORWEDVHG7KDWLVDEXVPDVWHUPXVWDUELWUDWHIRUHDFKDFFHVVLWSHUIRUPVRQ WKHEXV3&,XVHVDFHQWUDODUELWUDWLRQVFKHPHZKHUHHDFKPDVWHUDJHQWKDVDXQLTXH UHTXHVW REQ# DQGJUDQW GNT# VLJQDO$VLPSOHUHTXHVWJUDQWKDQGVKDNHLVXVHGWR JDLQDFFHVVWRWKHEXV$UELWUDWLRQLVKLGGHQZKLFKPHDQVLWRFFXUVGXULQJWKH SUHYLRXVDFFHVVVRWKDWQR3&,EXVF\FOHVDUHFRQVXPHGGXHWRDUELWUDWLRQH[FHSWZKHQ WKHEXVLVLQDQ,GOHVWDWH $QDUELWUDWLRQDOJRULWKPPXVWEHGHILQHGWRHVWDEOLVKDEDVLVIRUDZRUVWFDVHODWHQF\ JXDUDQWHH+RZHYHUVLQFHWKHDUELWUDWLRQDOJRULWKPLVIXQGDPHQWDOO\QRWSDUWRIWKHEXV VSHFLILFDWLRQV\VWHPGHVLJQHUVPD\HOHFWWRPRGLI\LWEXWPXVWSURYLGHIRUWKHODWHQF\ UHTXLUHPHQWVRIWKHLUVHOHFWHG,2FRQWUROOHUVDQGIRUH[SDQVLRQERDUGV5HIHUWR 6HFWLRQIRULQIRUPDWLRQRQODWHQF\JXLGHOLQHV7KHEXVDOORZVEDFNWREDFN WUDQVDFWLRQVE\WKHVDPHDJHQWDQGDOORZVIOH[LELOLW\IRUWKHDUELWHUWRSULRULWL]HDQG ZHLJKWUHTXHVWV$QDUELWHUFDQLPSOHPHQWDQ\VFKHPHDVORQJDVLWLVIDLUDQGRQO\D VLQJOHGNT#LVDVVHUWHGRQDQ\ULVLQJFORFN 7KHDUELWHULVUHTXLUHGWRLPSOHPHQWDIDLUQHVVDOJRULWKPWRDYRLGGHDGORFNV,QJHQHUDO WKHDUELWHUPXVWDGYDQFHWRDQHZDJHQWZKHQWKHFXUUHQWPDVWHUGHDVVHUWVLWVREQ# )DLUQHVVPHDQVWKDWHDFKSRWHQWLDOPDVWHUPXVWEHJUDQWHGDFFHVVWRWKHEXVLQGHSHQGHQW RIRWKHUUHTXHVWV+RZHYHUWKLVGRHVQRWPHDQWKDWDOODJHQWVDUHUHTXLUHGWRKDYHHTXDO DFFHVVWRWKHEXV%\UHTXLULQJDIDLUQHVVDOJRULWKPWKHUHDUHQRVSHFLDOFRQGLWLRQVWR KDQGOHZKHQLOCK#LVDFWLYH DVVXPLQJDUHVRXUFHORFN $V\VWHPWKDWXVHVDIDLUQHVV DOJRULWKPLVVWLOOFRQVLGHUHGIDLULILWLPSOHPHQWVDFRPSOHWHEXVORFNLQVWHDGRIUHVRXUFH ORFN+RZHYHUWKHDUELWHUPXVWDGYDQFHWRDQHZDJHQWLIWKHLQLWLDOWUDQVDFWLRQ DWWHPSWLQJWRHVWDEOLVKWKHORFNLVWHUPLQDWHGZLWK5HWU\ 68 Revision 2.2 Implementation Note: System Arbitration Algorithm 2QHH[DPSOHRIEXLOGLQJDQDUELWHUWRLPSOHPHQWDIDLUQHVVDOJRULWKPLVZKHQWKHUHDUHWZROHYHOV WRZKLFKEXVPDVWHUVDUHDVVLJQHG,QWKLVH[DPSOHWKHDJHQWVWKDWDUHDVVLJQHGWRWKHILUVWOHYHO KDYHDJUHDWHUQHHGWRXVHWKHEXVWKDQDJHQWVDVVLJQHGWRWKHVHFRQGOHYHO LHORZHUODWHQF\RU JUHDWHUWKURXJKSXW 6HFRQGOHYHODJHQWVKDYHHTXDODFFHVVWRWKHEXVZLWKUHVSHFWWRRWKHUVHFRQG OHYHODJHQWV+RZHYHUWKHVHFRQGOHYHODJHQWVDVDJURXSKDYHHTXDODFFHVVWRWKHEXVDVHDFK DJHQWRIWKHILUVWOHYHO$QH[DPSOHRIKRZDV\VWHPPD\DVVLJQDJHQWVWRDJLYHQOHYHOLVZKHUH GHYLFHVVXFKDVYLGHR$70RU)'',EXVPDVWHUVZRXOGEHDVVLJQHGWR/HYHOZKLOHGHYLFHV VXFKDV6&6,/$1RUVWDQGDUGH[SDQVLRQEXVPDVWHUVZRXOGEHDVVLJQHGWRWKHVHFRQGOHYHO 7KHILJXUHEHORZLVDQH[DPSOHRIDIDLUQHVVDUELWUDWLRQDOJRULWKPWKDWXVHVWZROHYHOVRI DUELWUDWLRQ7KHILUVWOHYHOFRQVLVWVRI$JHQW$$JHQW%DQG/HYHOZKHUH/HYHOLVWKHQH[W DJHQWDWWKDWOHYHOUHTXHVWLQJDFFHVVWRWKHEXV/HYHOFRQVLVWVRI$JHQW;$JHQW<DQG$JHQW =,IDOODJHQWVRQOHYHODQGKDYHWKHLUREQ#OLQHVDVVHUWHGDQGFRQWLQXHWRDVVHUWWKHPDQGLI $JHQW$LVWKHQH[WWRUHFHLYHWKHEXVIRU/HYHODQG$JHQW;LVWKHQH[WIRU/HYHOWKHQWKH RUGHURIWKHDJHQWVDFFHVVLQJWKHEXVZRXOGEH $%/HYHO WKLVWLPHLWLV; $%/HYHO WKLVWLPHLWLV< $%/HYHO WKLVWLPHLWLV= DQGVRIRUWK ,IRQO\$JHQW%DQG$JHQW<KDGWKHLUREQ#VDVVHUWHGDQGFRQWLQXHGWRDVVHUWWKHPWKHRUGHU ZRXOGEH %/HYHO < %/HYHO < %\UHTXLULQJDIDLUQHVVDUELWUDWLRQDOJRULWKPWKHV\VWHPGHVLJQHUFDQEDODQFHWKHQHHGVRIKLJK SHUIRUPDQFHDJHQWVVXFKDVYLGHR$70RU)'',ZLWKORZHUSHUIRUPDQFHEXVGHYLFHVOLNH/$1 DQG6&6,$QRWKHUV\VWHPGHVLJQHUPD\SXWRQO\PXOWLPHGLDGHYLFHVRQDUELWUDWLRQ/HYHODQG SXWWKH)'', RU$70 /$1DQG6&6,GHYLFHVRQ/HYHO7KHVHH[DPSOHVDFKLHYHWKHKLJKHVW OHYHORIV\VWHPSHUIRUPDQFHSRVVLEOHIRUWKURXJKSXWRUORZHVWODWHQF\ZLWKRXWSRVVLEOHVWDUYDWLRQ FRQGLWLRQV7KHSHUIRUPDQFHRIWKHV\VWHPFDQEHEDODQFHGE\DOORFDWLQJDVSHFLILFDPRXQWRIEXV EDQGZLGWKWRHDFKDJHQWE\FDUHIXODVVLJQPHQWRIHDFKPDVWHUWRDQDUELWUDWLRQOHYHODQG SURJUDPPLQJHDFKDJHQW¶V/DWHQF\7LPHUDSSURSULDWHO\ $JHQWÃ$ /HYHOÃ $JHQWÃ% /HYHOÃ $JHQWÃ; $JHQWÃ= $JHQWÃ< /HYHOÃ 69 Revision 2.2 3.4.1. Arbitration Signaling Protocol $QDJHQWUHTXHVWVWKHEXVE\DVVHUWLQJLWVREQ#$JHQWVPXVWRQO\XVHREQ#WRVLJQDO DWUXHQHHGWRXVHWKHEXV$QDJHQWPXVWQHYHUXVHREQ#WRSDUNLWVHOIRQWKHEXV,I EXVSDUNLQJLVLPSOHPHQWHGLWLVWKHDUELWHUWKDWGHVLJQDWHVWKHGHIDXOWRZQHU:KHQWKH DUELWHUGHWHUPLQHVDQDJHQWPD\XVHWKHEXVLWDVVHUWVWKHDJHQW VGNT# 7KHDUELWHUPD\GHDVVHUWDQDJHQW VGNT#RQDQ\FORFN$QDJHQWPXVWHQVXUHLWVGNT# LVDVVHUWHGRQWKHULVLQJFORFNHGJHLWZDQWVWRVWDUWDWUDQVDFWLRQ1RWH $PDVWHULV DOORZHGWRVWDUWDWUDQVDFWLRQZKHQLWVGNT#LVDVVHUWHGDQGWKHEXVLVLQDQ,GOHVWDWH LQGHSHQGHQWRIWKHVWDWHRILWVREQ#,IGNT#LVGHDVVHUWHGWKHWUDQVDFWLRQPXVWQRW SURFHHG2QFHDVVHUWHGGNT#PD\EHGHDVVHUWHGDFFRUGLQJWRWKHIROORZLQJUXOHV ,IGNT#LVGHDVVHUWHGDQGFRAME#LVDVVHUWHGRQWKHVDPHFORFNWKHEXV WUDQVDFWLRQLVYDOLGDQGZLOOFRQWLQXH 2QHGNT#FDQEHGHDVVHUWHGFRLQFLGHQWZLWKDQRWKHUGNT# EHLQJDVVHUWHGLIWKH EXVLVQRWLQWKH,GOHVWDWH2WKHUZLVHDRQHFORFNGHOD\LVUHTXLUHGEHWZHHQWKH GHDVVHUWLRQRIDGNT#DQGWKHDVVHUWLRQRIWKHQH[WGNT#RUHOVHWKHUHPD\EH FRQWHQWLRQRQWKHADOLQHVDQGPARGXHWRWKHFXUUHQWPDVWHUGRLQJDGGUHVV VWHSSLQJ :KLOHFRAME#LVGHDVVHUWHGGNT#PD\EHGHDVVHUWHGDWDQ\WLPHLQRUGHUWR VHUYLFHDKLJKHUSULRULW\ PDVWHURULQUHVSRQVHWRWKHDVVRFLDWHGREQ#EHLQJ GHDVVHUWHG )LJXUHLOOXVWUDWHVEDVLFDUELWUDWLRQ7ZRDJHQWVDUHXVHGWRLOOXVWUDWHKRZDQDUELWHU PD\DOWHUQDWHEXVDFFHVVHV CLK 1 2 3 4 5 6 7 REQ#-a REQ#-b GNT#-a GNT#-b FRAME# AD ADDRESS DATA ADDRESS DATA access - A access - B )LJXUH %DVLF$UELWUDWLRQ REQ#DLVDVVHUWHGSULRUWRRUDWFORFNWRUHTXHVWXVHRIWKHLQWHUIDFH$JHQW$LV JUDQWHGDFFHVVWRWKHEXVEHFDXVHGNT#DLVDVVHUWHGDWFORFN$JHQW$PD\VWDUWD WUDQVDFWLRQDWFORFNEHFDXVHFRAME#DQGIRDY#DUHGHDVVHUWHGDQGGNT#DLV DVVHUWHG$JHQW$ VWUDQVDFWLRQVWDUWVZKHQFRAME#LVDVVHUWHGRQFORFN6LQFH 19 Higher priority here does not imply a fixed priority arbitration, but refers to the agent that would win arbitration at a given instant in time. 70 Revision 2.2 $JHQW$GHVLUHVWRSHUIRUPDQRWKHUWUDQVDFWLRQLWOHDYHVREQ#DDVVHUWHG:KHQ FRAME#LVDVVHUWHGRQFORFNWKHDUELWHUGHWHUPLQHV$JHQW%VKRXOGJRQH[WDQG DVVHUWVGNT#EDQGGHDVVHUWVGNT#DRQFORFN :KHQDJHQW$FRPSOHWHVLWVWUDQVDFWLRQRQFORFNLWUHOLQTXLVKHVWKHEXV$OO3&, DJHQWVFDQGHWHUPLQHWKHHQGRIWKHFXUUHQWWUDQVDFWLRQZKHQERWKFRAME#DQGIRDY# DUHGHDVVHUWHG$JHQW%EHFRPHVWKHRZQHURQFORFN EHFDXVHFRAME#DQGIRDY# DUHGHDVVHUWHG DQGFRPSOHWHVLWVWUDQVDFWLRQRQFORFN 1RWLFHWKDWREQ#ELVGHDVVHUWHGDQGFRAME#LVDVVHUWHGRQFORFNLQGLFDWLQJDJHQW %UHTXLUHVRQO\DVLQJOHWUDQVDFWLRQ7KHDUELWHUJUDQWVWKHQH[WWUDQVDFWLRQWR$JHQW$ EHFDXVHLWVREQ#LVVWLOODVVHUWHG 7KHFXUUHQWRZQHURIWKHEXVNHHSVREQ#DVVHUWHGZKHQLWUHTXLUHVDGGLWLRQDO WUDQVDFWLRQV,IQRRWKHUUHTXHVWVDUHDVVHUWHGRUWKHFXUUHQWPDVWHUKDVKLJKHVWSULRULW\ WKHDUELWHUFRQWLQXHVWRJUDQWWKHEXVWRWKHFXUUHQWPDVWHU Implementation Note: Bus Parking :KHQQRREQ#VDUHDVVHUWHGLWLVUHFRPPHQGHGQRWWRUHPRYHWKHFXUUHQWPDVWHU¶V GNT#WRSDUNWKHEXVDWDGLIIHUHQWPDVWHUXQWLOWKHEXVHQWHUVLWV,GOHVWDWH,IWKH FXUUHQWEXVPDVWHU¶VGNT#LVGHDVVHUWHGWKHGXUDWLRQRIWKHFXUUHQWWUDQVDFWLRQLV OLPLWHGWRWKHYDOXHRIWKH/DWHQF\7LPHU,IWKHPDVWHULVOLPLWHGE\WKH/DWHQF\7LPHU LWPXVWUHDUELWUDWHIRUWKHEXVZKLFKZRXOGZDVWHEXVEDQGZLGWK,WLVUHFRPPHQGHGWR OHDYH GNT#DVVHUWHGDWWKHFXUUHQWPDVWHU ZKHQQRRWKHUREQ#VDUHDVVHUWHG XQWLOWKH EXVHQWHUVLWV,GOHVWDWH:KHQWKHEXVLVLQWKH,GOHVWDWHDQGQRREQ#VDUHDVVHUWHGWKH DUELWHUPD\SDUNWKHEXVDWDQ\DJHQWLWGHVLUHV GNT#JLYHVDQDJHQWDFFHVVWRWKHEXVIRUDVLQJOHWUDQVDFWLRQ,IDQDJHQWGHVLUHV DQRWKHUDFFHVVLWVKRXOGFRQWLQXHWRDVVHUWREQ#$QDJHQWPD\GHDVVHUWREQ# DQ\WLPHEXWWKHDUELWHUPD\LQWHUSUHWWKLVWRPHDQWKHDJHQWQRORQJHUUHTXLUHVXVHRIWKH EXVDQGPD\GHDVVHUWLWVGNT#$QDJHQWVKRXOGGHDVVHUWREQ#LQWKHVDPHFORFN FRAME#LVDVVHUWHGLILWRQO\ZDQWVWRGRDVLQJOHWUDQVDFWLRQ:KHQDWUDQVDFWLRQLV WHUPLQDWHGE\DWDUJHW STOP#DVVHUWHG WKHPDVWHUPXVWGHDVVHUWLWVREQ#IRUD PLQLPXPRIWZRFORFNVRQHEHLQJZKHQWKHEXVJRHVWRWKH,GOHVWDWH DWWKHHQGRIWKH WUDQVDFWLRQZKHUHSTOP#ZDVDVVHUWHG DQGWKHRWKHUEHLQJHLWKHUWKHFORFNEHIRUHRU WKHFORFNDIWHUWKH,GOHVWDWH)RUDQH[FHSWLRQUHIHUWR6HFWLRQ7KLVDOORZV DQRWKHUDJHQWWRXVHWKHLQWHUIDFHZKLOHWKHSUHYLRXVWDUJHWSUHSDUHVIRUWKHQH[WDFFHVV 7KHDUELWHUFDQDVVXPHWKHFXUUHQWPDVWHULVEURNHQLILWKDVQRWVWDUWHGDQDFFHVVDIWHU LWVGNT#KDVEHHQDVVHUWHG LWVREQ#LVDOVRDVVHUWHG DQGWKHEXVLVLQWKH,GOHVWDWHIRU FORFNV7KHDUELWHULVDOORZHGWRLJQRUHDQ\³EURNHQ´PDVWHU¶VREQ#DQGPD\ RSWLRQDOO\UHSRUWWKLVFRQGLWLRQWRWKHV\VWHP+RZHYHUWKHDUELWHUPD\UHPRYHGNT# DWDQ\WLPHWRVHUYLFHDKLJKHUSULRULW\DJHQW$PDVWHUWKDWKDVUHTXHVWHGXVHRIWKHEXV WKDWGRHVQRWDVVHUWFRAME#ZKHQWKHEXVLVLQWKH,GOHVWDWHDQGLWVGNT#LVDVVHUWHG IDFHVWKHSRVVLELOLW\RIORVLQJLWVWXUQRQWKHEXV1RWH ,QDEXV\V\VWHPDPDVWHUWKDW GHOD\VWKHDVVHUWLRQRIFRAME#UXQVWKHULVNRIVWDUYDWLRQEHFDXVHWKHDUELWHUPD\JUDQW WKHEXVWRDQRWKHUDJHQW)RUDPDVWHUWRHQVXUHWKDWLWJDLQVDFFHVVWRWKHEXVLWPXVW DVVHUWFRAME#WKHILUVWFORFNSRVVLEOHZKHQFRAME#DQGIRDY#DUHGHDVVHUWHGDQG LWVGNT#LVDVVHUWHG 71 Revision 2.2 3.4.2. Fast Back-to-Back Transactions 7KHUHDUHWZRW\SHVRIIDVWEDFNWREDFNWUDQVDFWLRQVWKDWFDQEHLQLWLDWHGE\WKHVDPH PDVWHU WKRVHWKDWDFFHVVWKHVDPHDJHQWDQGWKRVHWKDWGRQRW)DVWEDFNWREDFN WUDQVDFWLRQVDUHDOORZHGRQ3&,ZKHQFRQWHQWLRQRQTRDY#DEVSEL#STOP#RU PERR#LVDYRLGHG 7KHILUVWW\SHRIIDVWEDFNWREDFNVXSSRUWSODFHVWKHEXUGHQRIDYRLGLQJFRQWHQWLRQRQ WKHPDVWHUZKLOHWKHVHFRQGSODFHVWKHEXUGHQRQDOOSRWHQWLDOWDUJHWV7KHPDVWHUPD\ UHPRYHWKH,GOHVWDWHEHWZHHQWUDQVDFWLRQVZKHQLWFDQJXDUDQWHHWKDWQRFRQWHQWLRQ RFFXUV7KLVFDQEHDFFRPSOLVKHGZKHQWKHPDVWHU VFXUUHQWWUDQVDFWLRQLVWRWKHVDPH WDUJHWDVWKHSUHYLRXVZULWHWUDQVDFWLRQ7KLVW\SHRIIDVWEDFNWREDFNWUDQVDFWLRQ UHTXLUHVWKHPDVWHUWRXQGHUVWDQGWKHDGGUHVVERXQGDULHVRIWKHSRWHQWLDOWDUJHW RWKHUZLVHFRQWHQWLRQPD\RFFXU7KLVW\SHRIIDVWEDFNWREDFNLVRSWLRQDOIRUDPDVWHU EXWPXVWEHGHFRGHGE\DWDUJHW7KHWDUJHWPXVWEHDEOHWRGHWHFWDQHZDVVHUWLRQRI FRAME# IURPWKHVDPHPDVWHU ZLWKRXWWKHEXVJRLQJWRWKH,GOHVWDWH The second type of fast back-to-back support places the burden of no contention on all potential targets. The Fast Back-to-Back Capable bit in the Status register may be hardwired to a logical one (high) if, and, only if, the device, while acting as a bus target, meets the following two requirements: 7KHWDUJHWPXVWQRWPLVVWKHEHJLQQLQJRIDEXVWUDQVDFWLRQQRUORVHWKHDGGUHVV ZKHQWKDWWUDQVDFWLRQLVVWDUWHGZLWKRXWDEXV,GOHVWDWHSUHFHGLQJWKHWUDQVDFWLRQ ,QRWKHUZRUGVWKHWDUJHWLVFDSDEOHRIIROORZLQJDEXVVWDWHWUDQVLWLRQIURPDILQDO GDWDWUDQVIHU(FRAME#KLJKIRDY#ORZ GLUHFWO\WRDQDGGUHVVSKDVH FRAME# ORZIRDY#KLJK RQFRQVHFXWLYHFORFNF\FOHV1RWH 7KHWDUJHWPD\RUPD\QRW EHVHOHFWHGRQHLWKHURUERWKRIWKHVHWUDQVDFWLRQVEXWPXVWWUDFNEXVVWDWHV QRQHWKHOHVV 7KHWDUJHWPXVWDYRLGVLJQDOFRQIOLFWVRQDEVSEL#TRDY#STOP#DQG PERR#,IWKHWDUJHWGRHVQRWLPSOHPHQWWKHIDVWHVWSRVVLEOHDEVSEL#DVVHUWLRQ WLPHWKLVJXDUDQWHHLVDOUHDG\SURYLGHG)RUWKRVHWDUJHWVWKDWGRSHUIRUP]HUR ZDLWVWDWHGHFRGHVWKHWDUJHWPXVWGHOD\DVVHUWLRQRIWKHVHIRXUVLJQDOVIRUDVLQJOH FORFNH[FHSWLQHLWKHURQHRIWKHIROORZLQJWZRFRQGLWLRQV D 7KHFXUUHQWEXVWUDQVDFWLRQZDVLPPHGLDWHO\SUHFHGHGE\DEXV,GOHVWDWH WKDWLVWKLVLVQRWDEDFNWREDFNWUDQVDFWLRQRU E 7KHFXUUHQWWDUJHWKDGGULYHQDEVSEL#RQWKHSUHYLRXVEXVWUDQVDFWLRQ WKDWLVWKLVLVDEDFNWREDFNWUDQVDFWLRQLQYROYLQJWKHVDPHWDUJHWDVWKH SUHYLRXVWUDQVDFWLRQ 1RWH 'HOD\LQJWKHDVVHUWLRQRIDEVSEL#WRDYRLGFRQWHQWLRQRQIDVWEDFNWREDFN WUDQVDFWLRQVGRHVQRWDIIHFWWKHGHFRGHVSHHGLQGLFDWHGLQWKHVWDWXVUHJLVWHU$ GHYLFHWKDWQRUPDOO\DVVHUWVIDVWDEVSEL# VWLOOLQGLFDWHV³IDVW´LQWKHVWDWXVUHJLVWHU HYHQWKRXJKDEVSEL#LVGHOD\HGE\RQHFORFNLQWKLVFDVH7KHVWDWXVELWV DVVRFLDWHGZLWKGHFRGHWLPHDUHXVHGE\WKHV\VWHPWRDOORZWKHVXEWUDFWLYHGHFRGLQJ DJHQWWRPRYHLQWKHWLPHZKHQLWFODLPVXQFODLPHGDFFHVVHV+RZHYHULIWKH 20 It is recommended that this be done by returning the target state machine (refer to Appendix B) from the B_BUSY state to the IDLE state as soon as FRAME# is deasserted and the device's decode time has been met (a miss occurs) or when DEVSEL# is asserted by another target and not waiting for a bus Idle state (IRDY# deasserted). 72 Revision 2.2 VXEWUDFWLYHGHFRGHDJHQWFODLPVWKHDFFHVVGXULQJPHGLXPRUVORZGHFRGHWLPH LQVWHDGRIZDLWLQJIRUWKHVXEWUDFWLYHGHFRGHWLPHLWPXVWGHOD\WKHDVVHUWLRQRI DEVSEL#ZKHQDIDVWEDFNWREDFNWUDQVDFWLRQLVLQSURJUHVV RWKHUZLVHFRQWHQWLRQ RQDEVSEL#STOP#TRDY# DQGPERR#PD\RFFXU )RUPDVWHUVWKDWZDQWWRSHUIRUPIDVWEDFNWREDFNWUDQVDFWLRQVWKDWDUHVXSSRUWHGE\WKH WDUJHWPHFKDQLVPWKH)DVW%DFNWR%DFN(QDEOHELWLQWKH&RPPDQGUHJLVWHULVUHTXLUHG 7KLVELWLVRQO\PHDQLQJIXOLQGHYLFHVWKDWDFWDVEXVPDVWHUVDQGLVIXOO\RSWLRQDO ,WLV DUHDGZULWHELWZKHQLPSOHPHQWHG:KHQVHWWRDRQH KLJK WKHEXVPDVWHUPD\VWDUWD 3&,WUDQVDFWLRQXVLQJIDVWEDFNWREDFNWLPLQJZLWKRXWUHJDUGWRZKLFKWDUJHWLVEHLQJ DGGUHVVHGSURYLGLQJWKHSUHYLRXVWUDQVDFWLRQZDVDZULWHWUDQVDFWLRQLVVXHGE\WKH FXUUHQWEXVPDVWHU,IWKLVELWLVVHWWRD]HUR ORZ RUQRWLPSOHPHQWHGWKHPDVWHUPD\ SHUIRUPIDVWEDFNWREDFNRQO\LILWFDQJXDUDQWHHWKDWWKHQHZWUDQVDFWLRQJRHVWRWKH VDPHWDUJHWDVWKHSUHYLRXVRQH PDVWHUEDVHGPHFKDQLVP 7KLVELWZRXOGEHVHWE\WKHV\VWHPFRQILJXUDWLRQURXWLQHDIWHUHQVXULQJWKDWDOOWDUJHWV RQWKHVDPHEXVKDGWKH)DVW%DFNWR%DFN&DSDEOH%LWVHW 1RWH 7KHPDVWHUEDVHGIDVWEDFNWREDFNPHFKDQLVPGRHVQRWDOORZWKHVHIDVWF\FOHVWR RFFXUZLWKVHSDUDWHWDUJHWVZKLOHWKHWDUJHWEDVHGPHFKDQLVPGRHV ,IWKHWDUJHWLVXQDEOHWRSURYLGHERWKRIWKHJXDUDQWHHVVSHFLILHGDERYHLWPXVWQRW LPSOHPHQWWKLVELWDWDOODQGLWZLOODXWRPDWLFDOO\EHUHWXUQHGDVD]HURZKHQWKH6WDWXV UHJLVWHULVUHDG )DVWEDFNWREDFNWUDQVDFWLRQVDOORZDJHQWVWRXWLOL]HEXVEDQGZLGWKPRUHHIIHFWLYHO\,W LVUHFRPPHQGHGWKDWWDUJHWVDQGWKRVHPDVWHUVWKDWFDQLPSURYHEXVXWLOL]DWLRQVKRXOG LPSOHPHQWWKLVIHDWXUHSDUWLFXODUO\VLQFHWKHLPSOHPHQWDWLRQFRVWLVQHJOLJLEOH 8QGHUDOORWKHUFRQGLWLRQVWKHPDVWHUPXVWLQVHUWDPLQLPXPRIRQH,GOHEXVVWDWH $OVRWKHUHLVDOZD\VDWOHDVWRQH,GOHEXVVWDWHEHWZHHQWUDQVDFWLRQVE\GLIIHUHQW PDVWHUV 1RWH 7KHPDVWHULVUHTXLUHGWRFDXVHDQ,GOHVWDWHWRDSSHDURQWKHEXVZKHQ WKHUHTXLUHPHQWVIRUDIDVWEDFNWREDFNWUDQVDFWLRQDUHQRWPHWRUZKHQEXVRZQHUVKLS FKDQJHV 'XULQJDIDVWEDFNWREDFNWUDQVDFWLRQWKHPDVWHUVWDUWVWKHQH[WWUDQVDFWLRQLPPHGLDWHO\ ZLWKRXWDQ,GOHEXVVWDWH DVVXPLQJLWVGNT#LVVWLOODVVHUWHG ,IGNT#LVGHDVVHUWHGLQ WKHODVWGDWDSKDVHRIDWUDQVDFWLRQWKHPDVWHUKDVORVWDFFHVVWRWKHEXVDQGPXVW UHOLQTXLVKWKHEXVWRWKHQH[WPDVWHU7KHODVWGDWDSKDVHFRPSOHWHVZKHQFRAME#LV GHDVVHUWHGDQGIRDY#DQGTRDY# RUSTOP# DUHDVVHUWHG7KHFXUUHQWPDVWHUVWDUWV DQRWKHUWUDQVDFWLRQRQWKHFORFNIROORZLQJWKHFRPSOHWLRQRIWKHODVWGDWDSKDVHRIWKH SUHYLRXVWUDQVDFWLRQ ,WLVLPSRUWDQWWRQRWHWKDWDJHQWVQRWLQYROYHGLQDIDVWEDFNWREDFNWUDQVDFWLRQ VHTXHQFHFDQQRW DQGJHQHUDOO\QHHGQRW GLVWLQJXLVKLQWHUPHGLDWHWUDQVDFWLRQERXQGDULHV XVLQJRQO\FRAME#DQGIRDY# WKHUHLVQREXV,GOHVWDWH 'XULQJIDVWEDFNWREDFNV RQO\WKHPDVWHUDQGWDUJHWLQYROYHGQHHGWRGLVWLQJXLVKWKHVHERXQGDULHV:KHQWKHODVW WUDQVDFWLRQLVRYHUDOODJHQWVZLOOVHHDQ,GOHVWDWH+RZHYHUWKRVHWKDWGRVXSSRUWWKH WDUJHWEDVHGPHFKDQLVPPXVWEHDEOHWRGLVWLQJXLVKWKHFRPSOHWLRQRIDOO3&, WUDQVDFWLRQVDQGEHDEOHWRGHWHFWDOODGGUHVVSKDVHV ,Q)LJXUHWKHPDVWHUFRPSOHWHVDZULWHRQFORFNDQGVWDUWVWKHQH[WWUDQVDFWLRQRQ FORFN7KHWDUJHWPXVWEHJLQVDPSOLQJFRAME#RQFORFNVLQFHWKHSUHYLRXV WUDQVDFWLRQFRPSOHWHGRQFORFN RWKHUZLVHLWZLOOPLVVWKHDGGUHVVRIWKHQH[W WUDQVDFWLRQ$GHYLFHPXVWEHDEOHWRGHFRGHEDFNWREDFNRSHUDWLRQVWRGHWHUPLQHLILW 73 Revision 2.2 LVWKHFXUUHQWWDUJHWZKLOHDPDVWHUPD\RSWLRQDOO\VXSSRUWWKLVIXQFWLRQ$WDUJHWLVIUHH WRFODLPRZQHUVKLSE\DVVHUWLQJDEVSEL#WKHQ5HWU\WKHUHTXHVW CLK 1 2 3 4 5 6 7 REQ# GNT# FRAME# AD ADDRESS DATA ADDRESS DATA IRDY# TRDY# )LJXUH $UELWUDWLRQIRU%DFNWR%DFN$FFHVV 3.4.3. Arbitration Parking 7KHWHUPSDUNLPSOLHVSHUPLVVLRQIRUWKHDUELWHUWRDVVHUWGNT#WRDVHOHFWHGDJHQW ZKHQQRDJHQWLVFXUUHQWO\XVLQJRUUHTXHVWLQJWKHEXV7KHDUELWHUFDQVHOHFWWKHGHIDXOW RZQHUDQ\ZD\LWZDQWV IL[HGODVWXVHGHWF RUFDQFKRRVHQRWWRSDUNDWDOO HIIHFWLYHO\ GHVLJQDWLQJLWVHOIWKHGHIDXOWRZQHU :KHQWKHDUELWHUDVVHUWVDQDJHQW VGNT#DQGWKH EXVLVLQWKH,GOHVWDWHWKDWDJHQWPXVWHQDEOHLWVAD[31::00]C/BE[3::0]#DQG RQH FORFNODWHU PARRXWSXWEXIIHUVZLWKLQHLJKWFORFNV UHTXLUHG ZKLOHWZRWKUHHFORFNVLV UHFRPPHQGHG 5HIHUWR6HFWLRQIRUDGHVFULSWLRQRIWKHWLPLQJUHODWLRQVKLSRI PARWRAD 7KHDJHQWLVQRWFRPSHOOHGWRWXUQRQDOOEXIIHUVLQDVLQJOHFORFN7KLV UHTXLUHPHQWHQVXUHVWKDWWKHDUELWHUFDQVDIHO\SDUNWKHEXVDWVRPHDJHQWDQGNQRZWKDW WKHEXVZLOOQRWIORDW ,IWKHDUELWHUGRHVQRWSDUNWKHEXVWKHFHQWUDOUHVRXUFHGHYLFHLQ ZKLFKWKHDUELWHULVHPEHGGHGW\SLFDOO\GULYHVWKHEXV ,IWKHEXVLVLQWKH,GOHVWDWHDQGWKHDUELWHUUHPRYHVDQDJHQW VGNT#WKHDJHQWKDVORVW DFFHVVWRWKHEXVH[FHSWIRURQHFDVH7KHRQHFDVHLVLIWKHDUELWHUGHDVVHUWHGGNT# FRLQFLGHQWZLWKWKHDJHQWDVVHUWLQJFRAME#,QWKLVFDVHWKHPDVWHUZLOOFRQWLQXHWKH WUDQVDFWLRQ2WKHUZLVHWKHDJHQWPXVWWULVWDWHAD[31::00]C/BE#[3::0]DQG RQH FORFNODWHU PAR8QOLNHDERYHWKHDJHQWPXVWGLVDEOHDOOEXIIHUVLQDVLQJOHFORFNWR DYRLGSRVVLEOHFRQWHQWLRQZLWKWKHQH[WEXVRZQHU *LYHQWKHDERYHWKHPLQLPXPDUELWUDWLRQODWHQF\DFKLHYDEOHRQ3&,IURPWKHEXV,GOH VWDWHLVDVIROORZV • 3DUNHG ]HURFORFNVIRUSDUNHGDJHQWWZRFORFNVIRURWKHUV • 1RW3DUNHG RQHFORFNIRUHYHU\DJHQW :KHQWKHEXVLVSDUNHGDWDQDJHQWWKHDJHQWLVDOORZHGWRVWDUWDWUDQVDFWLRQZLWKRXW REQ#EHLQJDVVHUWHG $PDVWHUFDQVWDUWDWUDQVDFWLRQZKHQWKHEXVLVLQWKH,GOHVWDWH DQGGNT#LVDVVHUWHG :KHQWKHDJHQWQHHGVWRGRPXOWLSOHWUDQVDFWLRQVLWVKRXOG DVVHUWREQ#WRLQIRUPWKHDUELWHUWKDWLWLQWHQGVWRGRPXOWLSOHWUDQVDFWLRQV:KHQD PDVWHUUHTXLUHVRQO\DVLQJOHWUDQVDFWLRQLWVKRXOGQRWDVVHUWREQ# RWKHUZLVHWKH DUELWHUPD\FRQWLQXHWRDVVHUWLWVGNT#ZKHQLWGRHVQRWUHTXLUHXVHRIWKHEXV 74 Revision 2.2 3.5. Latency 3&,LVDORZODWHQF\KLJKWKURXJKSXW,2EXV%RWKWDUJHWVDQGPDVWHUVDUHOLPLWHGDVWR WKHQXPEHURIZDLWVWDWHVWKH\FDQDGGWRDWUDQVDFWLRQ)XUWKHUPRUHHDFKPDVWHUKDVD SURJUDPPDEOHWLPHUOLPLWLQJLWVPD[LPXPWHQXUHRQWKHEXVGXULQJWLPHVRIKHDY\EXV WUDIILF*LYHQWKHVHWZROLPLWVDQGWKHEXVDUELWUDWLRQRUGHUZRUVWFDVHEXVDFTXLVLWLRQ ODWHQFLHVFDQEHSUHGLFWHGZLWKUHODWLYHO\KLJKSUHFLVLRQIRUDQ\3&,EXVPDVWHU(YHQ EULGJHVWRVWDQGDUGH[SDQVLRQEXVHVZLWKORQJDFFHVVWLPHV ,6$(,6$RU0& FDQEH GHVLJQHGWRKDYHPLQLPDOLPSDFWRQWKH3&,EXVDQGVWLOONHHS3&,EXVDFTXLVLWLRQ ODWHQF\SUHGLFWDEOH 3.5.1. Target Latency 7DUJHWODWHQF\LVWKHQXPEHURIFORFNVWKHWDUJHWZDLWVEHIRUHDVVHUWLQJTRDY# 5HTXLUHPHQWVRQWKHLQLWLDOGDWDSKDVHDUHGLIIHUHQWIURPWKRVHRIVXEVHTXHQWGDWD SKDVHV 3.5.1.1. Target Initial Latency 7DUJHWLQLWLDOODWHQF\LVWKHQXPEHURIFORFNVIURPWKHDVVHUWLRQRIFRAME#WRWKH DVVHUWLRQRITRDY#ZKLFKFRPSOHWHVWKHLQLWLDOGDWDSKDVHRUWRWKHDVVHUWLRQRI STOP#LQWKH5HWU\DQG7DUJHW$ERUWFDVHV7KLVQXPEHURIFORFNVYDULHVGHSHQGLQJRQ ZKHWKHUWKHFRPPDQGLVDUHDGRUZULWHDQGLIDZULWHZKHWKHULWFDQEHSRVWHGRUQRW $PHPRU\ZULWHFRPPDQGVKRXOGVLPSO\EHSRVWHGE\WKHWDUJHWLQDEXIIHUDQGZULWWHQ WRWKHILQDOGHVWLQDWLRQODWHU,QWKLVFDVHWKHWDUJHWLQLWLDOODWHQF\LVVPDOOEHFDXVHWKH WUDQVDFWLRQZDVVLPSO\DUHJLVWHUWRUHJLVWHUWUDQVIHU0HHWLQJWDUJHWLQLWLDOODWHQF\RQ UHDGWUDQVDFWLRQVLVPRUHGLIILFXOWVLQFHWKLVODWHQF\LVDFRPELQDWLRQRIWKHDFFHVVWLPH RIWKHVWRUDJHPHGLD HJGLVN'5$0HWF DQGWKHGHOD\RIWKHLQWHUIDFHORJLF 0HHWLQJLQLWLDOODWHQF\RQ,2DQGFRQILJXUDWLRQZULWHWUDQVDFWLRQVDUHVLPLODUWRUHDG ODWHQF\ 7DUJHWLQLWLDOODWHQF\UHTXLUHPHQWVGHSHQGRQWKHVWDWHRIV\VWHPRSHUDWLRQ7KHV\VWHP FDQHLWKHUEHRSHUDWLQJLQLQLWLDOL]DWLRQWLPHRUUXQWLPH,QLWLDOL]DWLRQWLPHEHJLQVZKHQ RST#LVGHDVVHUWHGDQGFRPSOHWHV 3&,FORFNVODWHU5XQWLPHIROORZVLQLWLDOL]DWLRQ WLPH ,IDWDUJHWLVDFFHVVHGGXULQJLQLWLDOL]DWLRQWLPHLWLVDOORZHGWRGRDQ\RIWKHIROORZLQJ • ,JQRUHWKHUHTXHVW H[FHSWLILWLVDERRWGHYLFH • &ODLPWKHDFFHVVDQGKROGLQZDLWVWDWHVXQWLOLWFDQFRPSOHWHWKHUHTXHVWQRWWR H[FHHGWKHHQGRILQLWLDOL]DWLRQWLPH • &ODLPWKHDFFHVVDQGWHUPLQDWHZLWK5HWU\ ,IDWDUJHWLVDFFHVVHGGXULQJUXQWLPH RST#KDVEHHQGHDVVHUWHGJUHDWHUWKDQ FORFNV LWPXVWFRPSOHWHWKHLQLWLDOGDWDSKDVHRIDWUDQVDFWLRQ UHDGRUZULWH ZLWKLQ FORFNVIURPWKHDVVHUWLRQRIFRAME#7KHWDUJHWFRPSOHWHVWKHLQLWLDOGDWDSKDVHE\ DVVHUWLQJTRDY# WRDFFHSWRUSURYLGHWKHUHTXHVWHGGDWD RUE\WHUPLQDWLQJWKHUHTXHVW E\DVVHUWLQJSTOP#ZLWKLQWKHWDUJHWLQLWLDOODWHQF\UHTXLUHPHQW +RVWEXVEULGJHVDUHJUDQWHGDQDGGLWLRQDOFORFNVWRDPD[LPXPRIFORFNVWR FRPSOHWHWKHLQLWLDOGDWDSKDVHZKHQWKHDFFHVVKLWVDPRGLILHGOLQHLQDFDFKH+RZHYHU WKHKRVWEXVEULGJHFDQQHYHUH[FHHGFORFNVRQDQ\LQLWLDOGDWDSKDVH 75 Revision 2.2 ,QPRVWGHVLJQVWKHLQLWLDOGDWDSKDVHODWHQF\LVNQRZQZKHQWKHGHYLFHLVGHVLJQHG,I WKHWLPHUHTXLUHGWRFRPSOHWHWKHLQLWLDOGDWDSKDVHZLOOQRUPDOO\H[FHHGWKHPD[LPXP WDUJHWLQLWLDOODWHQF\VSHFLILFDWLRQWKHGHYLFHPXVWWHUPLQDWHWKHWUDQVDFWLRQZLWK5HWU\ DVVRRQDVSRVVLEOHDQGH[HFXWHWKHWUDQVDFWLRQDVD'HOD\HG7UDQVDFWLRQ ,QWKHXQXVXDOFDVHLQZKLFKWKHLQLWLDOGDWDSKDVHODWHQF\FDQQRWEHGHWHUPLQHGLQ DGYDQFHWKHWDUJHWLVDOORZHGWRLPSOHPHQWDFRXQWHUWKDWFDXVHVWKHWDUJHWWRDVVHUW STOP#DQGWREHJLQH[HFXWLRQRIWKHWUDQVDFWLRQDVD'HOD\HG7UDQVDFWLRQRQRUEHIRUH WKHVL[WHHQWKFORFNLITRDY#LVQRWDVVHUWHGVRRQHU$WDUJHWGHYLFHWKDWZDLWVIRUDQ LQLWLDOGDWDSKDVHODWHQF\FRXQWHUWRH[SLUHSULRUWREHJLQQLQJD'HOD\HG7UDQVDFWLRQ UHGXFHV3&,EDQGZLGWKDYDLODEOHWRRWKHUDJHQWVDQGOLPLWVWUDQVDFWLRQHIILFLHQF\ 7KHUHIRUHWKLVEHKDYLRULVVWURQJO\GLVFRXUDJHG Implementation Note: Working with Older Targets that Violate the Target Initial Latency Specification $OOQHZWDUJHWGHYLFHVPXVWDGKHUHWRWKHFORFNLQLWLDOODWHQF\UHTXLUHPHQWH[FHSWDV QRWHGDERYH+RZHYHUDQHZPDVWHUVKRXOGQRWGHSHQGRQWDUJHWVPHHWLQJWKHFORFN PD[LPXPLQLWLDODFFHVVODWHQF\IRUIXQFWLRQDORSHUDWLRQ LQWKHQHDUWHUP EXWPXVW IXQFWLRQQRUPDOO\ DOEHLWZLWKUHGXFHGSHUIRUPDQFH VLQFHV\VWHPVDQGGHYLFHVZHUH GHVLJQHGDQGEXLOWDJDLQVWDQHDUOLHUYHUVLRQRIWKLVVSHFLILFDWLRQDQGPD\QRWPHHWWKH QHZUHTXLUHPHQWV1HZGHYLFHVVKRXOGZRUNZLWKH[LVWLQJGHYLFHV 7KUHHRSWLRQVDUHJLYHQWRWDUJHWVWRPHHWWKHLQLWLDOODWHQF\UHTXLUHPHQWV0RVWWDUJHWV ZLOOXVHHLWKHU2SWLRQRU2SWLRQ7KRVHGHYLFHVXQDEOHWRXVH2SWLRQRU2SWLRQ DUHUHTXLUHGWRXVH2SWLRQ 2SWLRQLVIRUDGHYLFHWKDWDOZD\VWUDQVIHUVGDWD DVVHUWVTRDY# ZLWKLQFORFNV IURPWKHDVVHUWLRQRIFRAME# 1RWH 7KHPDMRULW\RI,2FRQWUROOHUVEXLOWSULRUWRUHYLVLRQRIWKLVVSHFLILFDWLRQ ZLOOPHHWWKHLQLWLDOODWHQF\UHTXLUHPHQWVXVLQJ2SWLRQ,QWKLVFDVHWKHWDUJHW DOZD\VDVVHUWVTRDY#WRFRPSOHWHWKHLQLWLDOGDWDSKDVHRIWKHWUDQVDFWLRQZLWKLQ FORFNVRIWKHDVVHUWLRQRIFRAME# 2SWLRQLVIRUGHYLFHVWKDWQRUPDOO\WUDQVIHUGDWDZLWKLQFORFNVEXWXQGHUVRPH VSHFLILFFRQGLWLRQVZLOOH[FHHGWKHLQLWLDOODWHQF\UHTXLUHPHQW8QGHUWKHVHFRQGLWLRQV WKHGHYLFHWHUPLQDWHVWKHDFFHVVZLWK5HWU\ZLWKLQFORFNVIURPWKHDVVHUWLRQRI FRAME# )RUGHYLFHVWKDWFDQQRWXVH2SWLRQDVPDOOPRGLILFDWLRQPD\EHUHTXLUHGWRPHHW WKHLQLWLDOODWHQF\UHTXLUHPHQWVDVGHVFULEHGE\2SWLRQ7KLVRSWLRQLVXVHGE\D WDUJHWWKDWFDQQRUPDOO\FRPSOHWHWKHLQLWLDOGDWDSKDVHZLWKLQFORFNV VDPHDV 2SWLRQ EXWRFFDVLRQDOO\ZLOOWDNHORQJHUDQGXVHVWKHDVVHUWLRQRISTOP#WR PHHWWKHLQLWLDOODWHQF\UHTXLUHPHQW,WWKHQEHFRPHVWKHUHVSRQVLELOLW\RIWKHPDVWHU WRDWWHPSWWKHWUDQVDFWLRQDJDLQDWDODWHUWLPH$WDUJHWLVSHUPLWWHGWRGRWKLVRQO\ ZKHQWKHUHLVDKLJKSUREDELOLW\WKHWDUJHWZLOOEHDEOHWRFRPSOHWHWKHWUDQVDFWLRQ ZKHQWKHPDVWHUUHSHDWVWKHUHTXHVW RWKHUZLVHWKHWDUJHWPXVWXVH2SWLRQ 76 Revision 2.2 Implementation Note: An Example of Option 2 &RQVLGHUDVLPSOHJUDSKLFGHYLFHWKDWQRUPDOO\UHVSRQGVWRDUHTXHVWZLWKLQFORFNV EXWXQGHUVSHFLDOFRQGLWLRQVVXFKDVUHIUHVKLQJWKHVFUHHQWKHLQWHUQDOEXVLV³EXV\´DQG SUHYHQWVGDWDIURPWUDQVIHUULQJ,QWKLVFDVHWKHWDUJHWWHUPLQDWHVWKHDFFHVVZLWK5HWU\ NQRZLQJWKHPDVWHUZLOOUHSHDWWKHWUDQVDFWLRQDQGWKHWDUJHWZLOOPRVWOLNHO\EHDEOHWR FRPSOHWHWKHWUDQVIHUWKHQ 7KHGHYLFHFRXOGKDYHDQLQWHUQDOVLJQDOWKDWLQGLFDWHVWRWKHEXVLQWHUIDFHXQLWWKDWWKH LQWHUQDOEXVLVEXV\DQGGDWDFDQQRWEHWUDQVIHUUHGDWWKLVWLPH7KLVDOORZVWKHGHYLFHWR FODLPWKHDFFHVV DVVHUWVDEVSEL# DQGLPPHGLDWHO\WHUPLQDWHWKHDFFHVVZLWK5HWU\ %\GRLQJWKLVLQVWHDGRIWHUPLQDWLQJWKHWUDQVDFWLRQFORFNVDIWHUWKHDVVHUWLRQRI FRAME#RWKHUDJHQWVFDQXVHWKHEXV 2SWLRQLVIRUDGHYLFHWKDWIUHTXHQWO\FDQQRWWUDQVIHUGDWDZLWKLQFORFNV7KLV RSWLRQUHTXLUHVWKHGHYLFHWRXVH'HOD\HG7UDQVDFWLRQVZKLFKDUHGLVFXVVHGLQGHWDLOLQ 6HFWLRQ 7KRVHGHYLFHVWKDWFDQQRWPHHWWKHUHTXLUHPHQWVRI2SWLRQRUDUHUHTXLUHGWRXVH 2SWLRQ7KLVRSWLRQLVXVHGE\GHYLFHVWKDWXQGHUQRUPDOFRQGLWLRQVFDQQRW FRPSOHWHWKHWUDQVDFWLRQZLWKLQWKHLQLWLDOODWHQF\UHTXLUHPHQWV$QH[DPSOHFRXOG EHDQ,2FRQWUROOHUWKDWKDVVHYHUDOLQWHUQDOIXQFWLRQVFRQWHQGLQJZLWKWKH3&, LQWHUIDFHWRDFFHVVDQLQWHUQDOUHVRXUFH$QRWKHUH[DPSOHFRXOGEHDGHYLFHWKDWDFWV OLNHDEULGJHWRDQRWKHUGHYLFHRUEXVZKHUHWKHLQLWLDOODWHQF\WRFRPSOHWHWKHDFFHVV PD\EHJUHDWHUWKDQFORFNV7KHPRVWFRPPRQW\SHVRIEULGJHVDUHKRVWEXV EULGJHVVWDQGDUGH[SDQVLRQEXVEULGJHVDQG3&,WR3&,EULGJHV Implementation Note: Using More Than One Option to Meet Initial Latency $FRPELQDWLRQRIWKHGLIIHUHQWRSWLRQVPD\EHXVHGEDVHGRQWKHDFFHVVODWHQF\RID SDUWLFXODUGHYLFH)RUH[DPSOHDJUDSKLFVFRQWUROOHUPD\PHHWWKHLQLWLDOODWHQF\ UHTXLUHPHQWVXVLQJ2SWLRQZKHQDFFHVVLQJFRQILJXUDWLRQRULQWHUQDO ,2RUPHPRU\ PDSSHG UHJLVWHUV+RZHYHULWPD\EHUHTXLUHGWRXVH2SWLRQRULQVRPHFDVHV 2SWLRQZKHQDFFHVVLQJWKHIUDPHEXIIHU 3.5.1.2. Target Subsequent Latency 7DUJHWVXEVHTXHQWODWHQF\LVWKHQXPEHURIFORFNVIURPWKHDVVHUWLRQRIIRDY#DQG TRDY#IRURQHGDWDSKDVHWRWKHDVVHUWLRQRITRDY#RUSTOP#IRUWKHQH[WGDWDSKDVH LQDEXUVWWUDQVIHU7KHWDUJHWLVUHTXLUHGWRFRPSOHWHDVXEVHTXHQWGDWDSKDVHZLWKLQ HLJKWFORFNVIURPWKHFRPSOHWLRQRIWKHSUHYLRXVGDWDSKDVH7KLVUHTXLUHVWKHWDUJHWWR FRPSOHWHWKHGDWDSKDVHHLWKHUE\WUDQVIHUULQJGDWD TRDY#DVVHUWHG E\GRLQJWDUJHW 'LVFRQQHFWZLWKRXWGDWD STOP#DVVHUWHGTRDY#GHDVVHUWHG RUE\GRLQJ7DUJHW $ERUW STOP#DVVHUWHGDEVSEL#GHDVVHUWHG ZLWKLQWKHWDUJHWVXEVHTXHQWODWHQF\ UHTXLUHPHQW ,QPRVWGHVLJQVWKHODWHQF\WRFRPSOHWHDVXEVHTXHQWGDWDSKDVHLVNQRZQZKHQWKH GHYLFHLVEHLQJGHVLJQHG,QWKLVFDVHWKHWDUJHWPXVWPDQLSXODWHTRDY#DQGSTOP# VRDVWRHQGWKHWUDQVDFWLRQ VXEVHTXHQWGDWDSKDVH XSRQFRPSOHWLRQRIGDWDSKDVH1 ZKHUH1 LILQFUHPHQWDOODWHQF\WRGDWDSKDVH1LVJUHDWHUWKDQHLJKW FORFNV)RUH[DPSOHDVVXPHD3&,PDVWHUUHDGIURPDQH[SDQVLRQEXVWDNHVDPLQLPXP RIFORFNVWRFRPSOHWHHDFKGDWDSKDVH$SSO\LQJWKHUXOHIRU1 WKHLQFUHPHQWDO ODWHQF\WRGDWDSKDVHLVFORFNV WKXVWKHWDUJHWPXVWWHUPLQDWHXSRQFRPSOHWLRQRI 77 Revision 2.2 GDWDSKDVH LHDWDUJHWWKLVVORZPXVWEUHDNDWWHPSWHGEXUVWVRQGDWDSKDVH ERXQGDULHV )RUGHVLJQVZKHUHWKHODWHQF\WRFRPSOHWHDVXEVHTXHQWGDWDSKDVHFDQQRWEHGHWHUPLQHG LQDGYDQFHWKHWDUJHWLVDOORZHGWRLPSOHPHQWDFRXQWHUWKDWFDXVHVWKHWDUJHWWRDVVHUW STOP#EHIRUHRUGXULQJWKHHLJKWKFORFNLITRDY#LVQRWDVVHUWHG,ITRDY#LV DVVHUWHGEHIRUHWKHFRXQWH[SLUHVWKHFRXQWHULVUHVHWDQGWKHWDUJHWFRQWLQXHVWKH WUDQVDFWLRQ 3.5.2. Master Data Latency 0DVWHUGDWDODWHQF\LVWKHQXPEHURIFORFNVWKHPDVWHUWDNHVWRDVVHUWIRDY#LQGLFDWLQJ LWLVUHDG\WRWUDQVIHUGDWD$OOPDVWHUVDUHUHTXLUHGWRDVVHUWIRDY#ZLWKLQHLJKWFORFNV RIWKHDVVHUWLRQRIFRAME#RQWKHLQLWLDOGDWDSKDVHDQGZLWKLQHLJKWFORFNVRQDOO VXEVHTXHQWGDWDSKDVHV*HQHUDOO\LQWKHILUVWGDWDSKDVHRIDWUDQVDFWLRQWKHUHLVQR UHDVRQIRUDPDVWHUWRGHOD\WKHDVVHUWLRQRIIRDY#PRUHWKDQRQHRUWZRFORFNVIRUD ZULWHWUDQVDFWLRQ7KHPDVWHUVKRXOGQHYHUGHOD\WKHDVVHUWLRQRIIRDY#RQDUHDG WUDQVDFWLRQ,IWKHPDVWHUKDVQREXIIHUDYDLODEOHWRVWRUHWKHUHDGGDWDLWVKRXOGGHOD\ UHTXHVWLQJXVHRIWKHEXVXQWLODEXIIHULVDYDLODEOH2QDZULWHWUDQVDFWLRQWKHPDVWHU VKRXOGKDYHWKHGDWDDYDLODEOHEHIRUHUHTXHVWLQJWKHEXVWRWUDQVIHUWKHGDWD'DWD WUDQVIHUVRQ3&,VKRXOGEHGRQHDVUHJLVWHUWRUHJLVWHUWUDQVIHUVWRPD[LPL]H SHUIRUPDQFH 3.5.3. Memory Write Maximum Completion Time Limit $WDUJHWPD\IURPWLPHWRWLPHWHUPLQDWHDPHPRU\ZULWHWUDQVDFWLRQZLWK5HWU\ZKLOH WHPSRUDU\LQWHUQDOFRQIOLFWVDUHEHLQJUHVROYHG IRUH[DPSOHZKHQDOOWKHPHPRU\ZULWH GDWDEXIIHUVDUHIXOORUGXULQJDYLGHRVFUHHQUHIUHVK+RZHYHUDWDUJHWLVQRWSHUPLWWHG WRWHUPLQDWHPHPRU\ZULWHWUDQVDFWLRQVZLWK5HWU\LQGHILQLWHO\ $IWHUDWDUJHWWHUPLQDWHVDPHPRU\ZULWHWUDQVDFWLRQZLWK5HWU\LWLVUHTXLUHGWREHUHDG\ WRFRPSOHWHDWOHDVWRQHGDWDSKDVHRIDPHPRU\ZULWHZLWKLQDVSHFLILHGQXPEHURI3&, FORFNF\FOHVIURPWKHILUVW5HWU\WHUPLQDWLRQ7KLVVSHFLILHGQXPEHURIFORFNF\FOHVLV FORFNVIRUV\VWHPVUXQQLQJDW0+]RUVORZHUDQGFORFNVIRUV\VWHPVUXQQLQJ DW0+]7KLVWLPHOLPLWZKLFKWUDQVODWHVWRPLFURVHFRQGVDWPD[LPXP IUHTXHQFLHV 0+]DQG0+] LVFDOOHGWKH0D[LPXP&RPSOHWLRQ7LPH,IDWDUJHW LVSUHVHQWHGZLWKPXOWLSOHPHPRU\ZULWHUHTXHVWVWKH0D[LPXP&RPSOHWLRQ7LPHLV PHDVXUHGIURPWKHWLPHWKHILUVWPHPRU\ZULWHWUDQVDFWLRQLVWHUPLQDWHGZLWK5HWU\XQWLO WKHWLPHWKHILUVWGDWDSKDVHRIDQ\PHPRU\ZULWHWRWKHWDUJHWLVFRPSOHWHGZLWK VRPHWKLQJRWKHUWKDQ5HWU\2QFHDQRQ5HWU\WHUPLQDWLRQKDVRFFXUUHGWKH0D[LPXP &RPSOHWLRQ7LPHOLPLWVWDUWVRYHUDJDLQZLWKWKHQH[W5HWU\WHUPLQDWLRQ 7KHDFWXDOWLPHWKDWWKHGDWDSKDVHFRPSOHWHVZLOODOVRGHSHQGXSRQZKHQWKHPDVWHU UHSHDWVWKHWUDQVDFWLRQ7DUJHWVPXVWEHGHVLJQHGWRPHHWWKH0D[LPXP&RPSOHWLRQ 7LPHUHTXLUHPHQWVDVVXPLQJWKHPDVWHUZLOOUHSHDWWKHPHPRU\ZULWHWUDQVDFWLRQ SUHFLVHO\DWWKHOLPLWRIWKH0D[LPXP&RPSOHWLRQ7LPH 78 Revision 2.2 Implementation Note: Meeting Maximum Completion Time Limit by Restricting Use of the Device 6RPHWDUJHWKDUGZDUHGHVLJQVPD\QRWEHDEOHWRSURFHVVHYHU\PHPRU\ZULWH WUDQVDFWLRQZLWKLQWKH0D[LPXP&RPSOHWLRQ7LPH$QH[DPSOHLVZULWLQJWRD FRPPDQGTXHXHZKHUHFRPPDQGVFDQWDNHORQJHUWKDQWKH0D[LPXP&RPSOHWLRQ7LPH WRFRPSOHWH6XEVHTXHQWZULWHVWRVXFKDWDUJHWZKHQLWLVFXUUHQWO\SURFHVVLQJD SUHYLRXVZULWHFRXOGH[SHULHQFHFRPSOHWLRQWLPHVWKDWDUHORQJHUWKDQWKH0D[LPXP &RPSOHWLRQ7LPH'HYLFHVWKDWWDNHORQJHUWKDQWKH0D[LPXP&RPSOHWLRQ7LPHWR SURFHVVVRPHPHPRU\ZULWHWUDQVDFWLRQPXVWUHVWULFWWKHXVDJHRIWKHGHYLFHWRSUHYHQW ZULWHWUDQVDFWLRQVZKHQWKHGHYLFHFDQQRWFRPSOHWHWKHPZLWKLQWKH0D[LPXP &RPSOHWLRQ7LPH7KLVLVW\SLFDOO\GRQHE\WKHGHYLFHGULYHUDQGLVDFFRPSOLVKHGE\ OLPLWLQJWKHUDWHDWZKLFKPHPRU\ZULWHVDUHLVVXHGWRWKHGHYLFHRUE\UHDGLQJWKH GHYLFHWRGHWHUPLQHWKDWDEXIIHULVDYDLODEOHEHIRUHWKHZULWHWUDQVDFWLRQLVLVVXHG %ULGJHGHYLFHV %DVH&ODVV [ DUHH[HPSWIURPWKH0D[LPXP&RPSOHWLRQ7LPH UHTXLUHPHQWIRUDQ\UHTXHVWVWKDWPRYHGDWDDFURVVWKHEULGJH%ULGJHGHYLFHVPXVW IROORZWKH0D[LPXP&RPSOHWLRQ7LPHUHTXLUHPHQWIRUWUDQVDFWLRQVWKDWDGGUHVV ORFDWLRQVZLWKLQ RUDVVRFLDWHGZLWK WKHEULGJH 7KH0D[LPXP&RPSOHWLRQ7LPHUHTXLUHPHQWLVQRWLQHIIHFWGXULQJGHYLFHLQLWLDOL]DWLRQ WLPHZKLFKLVGHILQHGDVWKH 3&,FORFNVLPPHGLDWHO\IROORZLQJWKHGHDVVHUWLRQRI RST# (YHQWKRXJKWDUJHWVDUHUHTXLUHGWRFRPSOHWHPHPRU\ZULWHWUDQVDFWLRQVZLWKLQWKH 0D[LPXP&RPSOHWLRQ7LPHPDVWHUVFDQQRWUHO\RQPHPRU\ZULWHWUDQVDFWLRQV FRPSOHWLQJZLWKLQWKLVWLPH$WUDQVDFWLRQPD\IORZWKURXJKD3&,WR3&,EULGJHRUEH RQHRIPXOWLSOHWUDQVDFWLRQVWRDWDUJHW,QERWKRIWKHVHFDVHVWKHDFWXDOFRPSOHWLRQ WLPHPD\H[FHHGWKHQRUPDOOLPLW 3.5.4. Arbitration Latency $UELWUDWLRQODWHQF\LVWKHQXPEHURIFORFNVIURPZKHQDPDVWHUDVVHUWVLWVREQ#XQWLO WKHEXVUHDFKHVDQ,GOHVWDWHDQGWKHPDVWHU¶VGNT#LVDVVHUWHG,QDOLJKWO\ORDGHG V\VWHPDUELWUDWLRQODWHQF\ZLOOJHQHUDOO\MXVWEHWKHWLPHIRUWKHEXVDUELWHUWRDVVHUWWKH PDVWHU¶VGNT#,IDWUDQVDFWLRQLVLQSURJUHVVZKHQWKHPDVWHU¶VGNT#LVDVVHUWHGWKH PDVWHUPXVWZDLWWKHDGGLWLRQDOWLPHIRUWKHFXUUHQWWUDQVDFWLRQWRFRPSOHWH 7KHWRWDODUELWUDWLRQODWHQF\IRUDPDVWHULVDIXQFWLRQRIKRZPDQ\RWKHUPDVWHUVDUH JUDQWHGWKHEXVEHIRUHLWDQGKRZORQJHDFKRQHNHHSVWKHEXV7KHQXPEHURIRWKHU PDVWHUVJUDQWHGWKHEXVLVGHWHUPLQHGE\WKHEXVDUELWHUDVGLVFXVVHGLQ6HFWLRQ (DFKPDVWHU¶VWHQXUHRQWKHEXVLVOLPLWHGE\LWVPDVWHU/DWHQF\7LPHUZKHQLWVGNT# KDVEHHQGHDVVHUWHG 79 Revision 2.2 7KHPDVWHU/DWHQF\7LPHULVDSURJUDPPDEOHWLPHULQHDFKPDVWHU¶V&RQILJXUDWLRQ 6SDFH UHIHUWR6HFWLRQ ,WLVUHTXLUHGIRUHDFKPDVWHUZKLFKLVFDSDEOHRIEXUVWLQJ PRUHWKDQWZRGDWDSKDVHV(DFKPDVWHU V/DWHQF\7LPHULVFOHDUHGDQGVXVSHQGHG ZKHQHYHULWLVQRWDVVHUWLQJFRAME#:KHQDPDVWHUDVVHUWVFRAME#LWHQDEOHVLWV /DWHQF\7LPHUWRFRXQW7KHPDVWHU¶VEHKDYLRUXSRQH[SLUDWLRQRIWKH/DWHQF\7LPHU GHSHQGVRQZKDWFRPPDQGLVEHLQJXVHGDQGWKHVWDWHRIFRAME#DQGGNT#ZKHQWKH /DWHQF\7LPHUH[SLUHV • ,IWKHPDVWHUGHDVVHUWVFRAME#SULRUWRRURQWKHVDPHFORFNWKDWWKHFRXQWHU H[SLUHVWKH/DWHQF\7LPHULVPHDQLQJOHVV7KHF\FOHWHUPLQDWHVDVLWQRUPDOO\ ZRXOGZKHQWKHFXUUHQWGDWDSKDVHFRPSOHWHV • ,IFRAME#LVDVVHUWHGZKHQWKH/DWHQF\7LPHUH[SLUHVDQGWKHFRPPDQGLVQRW 0HPRU\:ULWHDQG,QYDOLGDWHWKHPDVWHUPXVWLQLWLDWHWUDQVDFWLRQWHUPLQDWLRQZKHQ GNT#LVGHDVVHUWHGIROORZLQJWKHUXOHVGHVFULEHGLQ6HFWLRQ,QWKLVFDVH WKHPDVWHUKDVFRPPLWWHGWRWKHWDUJHWWKDWLWZLOOFRPSOHWHWKHFXUUHQWGDWDSKDVH DQGRQHPRUH WKHILQDOGDWDSKDVHLVLQGLFDWHGZKHQFRAME#LVGHDVVHUWHG • ,IFRAME#LVDVVHUWHGZKHQWKH/DWHQF\7LPHUH[SLUHVWKHFRPPDQGLV0HPRU\ :ULWHDQG,QYDOLGDWHDQGWKHFXUUHQWGDWDSKDVHLVQRWWUDQVIHUULQJWKHODVW':25' RIWKHFXUUHQWFDFKHOLQHZKHQGNT#LVGHDVVHUWHGWKHPDVWHUPXVWWHUPLQDWHWKH WUDQVDFWLRQDWWKHHQGRIWKHFXUUHQWFDFKHOLQH RUZKHQSTOP#LVDVVHUWHG • ,IFRAME#LVDVVHUWHGZKHQWKH/DWHQF\7LPHUH[SLUHVWKHFRPPDQGLV0HPRU\ :ULWHDQG,QYDOLGDWHDQGWKHFXUUHQWGDWDSKDVHLVWUDQVIHUULQJWKHODVW':25'RI WKHFXUUHQWFDFKHOLQHZKHQGNT#LVGHDVVHUWHGWKHPDVWHUPXVWWHUPLQDWHWKH WUDQVDFWLRQDWWKHHQGRIWKHQH[WFDFKHOLQH 7KLVLVUHTXLUHGVLQFHWKHPDVWHU FRPPLWWHGWRWKHWDUJHWDWOHDVWRQHPRUHGDWDSKDVHZKLFKZRXOGEHWKHEHJLQQLQJ RIWKHQH[WFDFKHOLQHZKLFKLWPXVWFRPSOHWHXQOHVVSTOP#LVDVVHUWHG ,QHVVHQFHWKHYDOXHSURJUDPPHGLQWRWKH/DWHQF\7LPHUUHSUHVHQWVDPLQLPXP JXDUDQWHHGQXPEHURIFORFNVDOORWWHGWRWKHPDVWHUDIWHUZKLFKLWPXVWVXUUHQGHUWHQXUH DVVRRQDVSRVVLEOHDIWHULWVGNT#LVGHDVVHUWHG7KHDFWXDOGXUDWLRQRIDWUDQVDFWLRQ DVVXPLQJLWVGNT#LVGHDVVHUWHG FDQEHIURPDPLQLPXPRIWKH/DWHQF\7LPHUYDOXH SOXVRQHFORFNWRDPD[LPXPRIWKH/DWHQF\7LPHUYDOXHSOXVWKHQXPEHURIFORFNV UHTXLUHGWRFRPSOHWHDQHQWLUHFDFKHOLQHWUDQVIHU XQOHVVWKHWDUJHWDVVHUWVSTOP# 3.5.4.1. Bandwidth and Latency Considerations In PCI systems, there is a tradeoff between the desire to achieve low latency and the desire to achieve high bandwidth (throughput). High throughput is achieved by allowing devices to use long burst transfers. Low latency is achieved by reducing the maximum burst transfer length. The following discussion is provided (for a 32-bit bus) to illustrate this tradeoff. A given PCI bus master introduces latency on PCI each time it uses the PCI bus to do a transaction. This latency is a function of the behavior of both the master and the target device during the transaction as well as the state of the master’s GNT# signal. The bus command used, transaction burst length, master data latency for each data phase, and the Latency Timer are the primary parameters which control the master’s behavior. The bus command used, target latency, and target subsequent latency are the primary parameters which control the target’s behavior. 80 Revision 2.2 A master is required to assert its IRDY# within eight clocks for any given data phase (initial and subsequent). For the first data phase, a target is required to assert its TRDY# or STOP# within 16 clocks from the assertion of FRAME# (unless the access hits a modified cacheline in which case 32 clocks are allowed for host bus bridges). For all subsequent data phases in a burst transfer, the target must assert its TRDY# or STOP# within eight clocks. If the effects of the Latency Timer are ignored, it is a straightforward exercise to develop equations for the worst case latencies that a PCI bus master can introduce from these specification requirements. latency_max (clocks) = 32 + 8 * (n-1) if a modified cacheline is hit (for a host bus bridge only) or = 16 + 8 * (n-1) if not a modified cacheline where n is the total number of data transfers in the transaction However, it is more useful to consider transactions that exhibit typical behavior. PCI is designed so that data transfers between a bus master and a target occur as register to register transfers. Therefore, bus masters typically do not insert wait states since they only request transactions when they are prepared to transfer data. Targets typically have an initial access latency less than the 16 (32 for modified cacheline hit for host bus bridge) clock maximum allowed. Once targets begin transferring data (complete their first data phase), they are typically able to sustain burst transfers at full rate (one clock per data phase) until the transaction is either completed by the master or the target's buffers are filled or are temporarily empty. The target can use the target Disconnect protocol to terminate the burst transaction early when its buffers fill or temporarily empty during the transaction. Using these more realistic considerations, the worst case latency equations can be modified to give a typical latency (assuming that the target’s initial data phase latency is eight clocks) again ignoring the effects of the Latency Timer. ODWHQF\BW\SLFDO FORFNV Q ,IDPDVWHUZHUHDOORZHGWREXUVWLQGHILQLWHO\ZLWKDWDUJHWZKLFKFRXOGDEVRUERUVRXUFH WKHGDWDLQGHILQLWHO\WKHQWKHUHZRXOGEHQRXSSHUERXQGRQWKHODWHQF\ZKLFKDPDVWHU FRXOGLQWURGXFHLQWRD3&,V\VWHP+RZHYHUWKHPDVWHU/DWHQF\7LPHUSURYLGHVD PHFKDQLVPWRFRQVWUDLQDPDVWHU VWHQXUHRQWKHEXV ZKHQRWKHUEXVPDVWHUVQHHGWRXVH WKHEXV ,QHIIHFWWKH/DWHQF\7LPHUFRQWUROVWKHWUDGHRIIEHWZHHQKLJKWKURXJKSXW KLJKHU /DWHQF\7LPHUYDOXHV DQGORZODWHQF\ ORZHU/DWHQF\7LPHUYDOXHV 7DEOHVKRZV WKHODWHQF\IRUGLIIHUHQWEXUVWOHQJWKWUDQVIHUVXVLQJWKHIROORZLQJDVVXPSWLRQV • 7KHLQLWLDOODWHQF\LQWURGXFHGE\WKHPDVWHURUWDUJHWLVHLJKWFORFNV • 7KHUHLVQRODWHQF\RQVXEVHTXHQWGDWDSKDVHV IRDY#DQGTRDY#DUHDOZD\V DVVHUWHG • 7KHQXPEHURIGDWDSKDVHVDUHSRZHUVRIWZREHFDXVHWKHVHDUHHDV\WRFRUUHODWHWR FDFKHOLQHVL]HV • 7KH/DWHQF\7LPHUYDOXHVZHUHFKRVHQWRH[SLUHGXULQJWKHQH[WWRODVWGDWDSKDVH ZKLFKDOORZVWKHPDVWHUWRFRPSOHWHWKHFRUUHFWQXPEHURIGDWDSKDVHV )RUH[DPSOHZLWKD/DWHQF\7LPHURIDQGDWDUJHWLQLWLDOODWHQF\RIWKH/DWHQF\ 7LPHUH[SLUHVGXULQJWKHVHYHQWKGDWDSKDVH7KHWUDQVDFWLRQFRPSOHWHVZLWKWKHHLJKWK GDWDSKDVH 81 Revision 2.2 7DEOH /DWHQF\IRU'LIIHUHQW%XUVW/HQJWK7UDQVIHUV Data Bytes Total Latency Timer Bandwidth Latency Phases Transferred Clocks (clocks) (MB/s) (ms) 8 32 16 14 60 .48 16 64 24 22 80 .72 32 128 40 38 96 1.20 64 256 72 70 107 2.16 Data Phases Number of data phases completed during transaction Bytes Transferred Total number of bytes transferred during transaction (assuming 32-bit transfers) Total Clocks Total number of clocks used to complete the transfer total_clocks = 8 + (n-1) + 1 (Idle time on bus) Latency Timer Latency Timer value in clocks such that the Latency Timer expires in next to last data phase latency_timer = total_clocks - 2 Bandwidth Calculated bandwidth in MB/s bandwidth = bytes_transferred / (total clocks * 30 ns) Latency Latency in microseconds introduced by transaction latency = total clocks * 30 ns Table 3-4 clearly shows that as the burst length increases, the amount of data transferred increases. Note: The amount of data doubles between each row in the table, while the latency increases by less than double. The amount of data transferred between the first row and the last row increases by a factor of 8, while the latency increases by a factor of 4.5. The longer the transaction (more data phases), the more efficiently the bus is being used. However, this increase in efficiency comes at the expense of larger buffers. 3.5.4.2. Determining Arbitration Latency $UELWUDWLRQODWHQF\LVWKHQXPEHURIFORFNVDPDVWHUPXVWZDLWDIWHUDVVHUWLQJLWVREQ# EHIRUHLWFDQEHJLQDWUDQVDFWLRQ7KLVQXPEHULVDIXQFWLRQRIWKHDUELWUDWLRQDOJRULWKP RIWKHV\VWHP LHWKHVHTXHQFHLQZKLFKPDVWHUVDUHJLYHQDFFHVVWRWKHEXVDQGWKH YDOXHRIWKH/DWHQF\7LPHURIHDFKPDVWHU6LQFHWKHVHIDFWRUVZLOOYDU\IURPV\VWHPWR V\VWHPWKHEHVWDQLQGLYLGXDOPDVWHUFDQGRLVWRSLFNDFRQILJXUDWLRQWKDWLVFRQVLGHUHG WKHW\SLFDOFDVHDQGDSSO\WKHODWHQF\GLVFXVVLRQWRLWWRGHWHUPLQHWKHODWHQF\DGHYLFH ZLOOH[SHULHQFH 82 Revision 2.2 $UELWUDWLRQODWHQF\LVDOVRDIIHFWHGE\WKHORDGLQJRIWKHV\VWHPDQGKRZHIILFLHQWWKHEXV LVEHLQJXVHG7KHIROORZLQJWZRH[DPSOHVLOOXVWUDWHDOLJKWO\DQGKHDYLO\ORDGHGV\VWHP ZKHUHWKHEXV 3&, LVELW7KHOLJKWO\ORDGHGH[DPSOHLVWKHPRUHW\SLFDOFDVHRI V\VWHPVWRGD\ZKLOHWKHVHFRQGLVPRUHRIDWKHRUHWLFDOPD[LPXP /LJKWO\/RDGHG6\VWHP )RUWKLVH[DPSOHDVVXPHWKDWQRRWKHUREQ#VDUHDVVHUWHGDQGWKHEXVLVHLWKHULQ WKH,GOHVWDWHRUWKDWDPDVWHULVFXUUHQWO\XVLQJWKHEXV6LQFHQRRWKHUREQ#VDUH DVVHUWHGDVVRRQDV$JHQW$¶VREQ#LVDVVHUWHGWKHDUELWHUZLOODVVHUWLWVGNT#RQ WKHQH[WHYDOXDWLRQRIWKHREQ#OLQHV,QWKLVFDVH$JHQW$¶VGNT# ZLOOEH DVVHUWHGZLWKLQDIHZFORFNV$JHQW$JDLQVDFFHVVWRWKHEXVZKHQWKHEXVLVLQWKH ,GOHVWDWH DVVXPLQJLWVGNT#LVVWLOODFWLYH +HDYLO\/RDGHG6\VWHP 7KLVH[DPSOHZLOOXVHWKHDUELWHUGHVFULEHGLQWKHLPSOHPHQWDWLRQQRWHLQ 6HFWLRQ$VVXPHWKDWDOODJHQWVKDYHWKHLUREQ#OLQHVDVVHUWHGDQGDOOZDQWWR WUDQVIHUPRUHGDWDWKDQWKHLU/DWHQF\7LPHUVDOORZ7RVWDUWWKHVHTXHQFHDVVXPH WKDWWKHQH[WEXVPDVWHULV$JHQW$RQOHYHODQG$JHQW;RQOHYHO,QWKLV H[DPSOH$JHQW$KDVDYHU\VPDOOQXPEHURIFORFNVEHIRUHLWJDLQVDFFHVVWRWKH EXVZKLOH$JHQW=KDVWKHODUJHVWQXPEHU,QWKLVH[DPSOH$JHQWV$DQG%HDFK JHWDWXUQEHIRUHDQ$JHQWDW/HYHO7KHUHIRUH$JHQWV$DQG%HDFKJHWWKUHH WXUQVRQWKHEXVDQG$JHQWV;DQG<HDFKJHWRQHWXUQEHIRUH$JHQW=JHWVDWXUQ $UELWUDWLRQODWHQF\ LQWKLVH[DPSOH FDQEHDVVKRUWDVDIHZFORFNVIRU$JHQW$RU DVVXPLQJD/DWHQF\7LPHURIFORFNV DVORQJDVFORFNV PDVWHUV FORFNVPDVWHU IRU$JHQW=-XVWWRNHHSWKLVLQSHUVSHFWLYHWKHKHDYLO\ORDGHG V\VWHPLVFRQVWDQWO\PRYLQJDERXW 0%VRIGDWD DVVXPLQJWDUJHWLQLWLDOODWHQF\ RIHLJKWFORFNVDQGWDUJHWVXEVHTXHQWODWHQF\RIRQHFORFN $VVHHQLQWKHH[DPSOHDPDVWHUH[SHULHQFHVLWVPD[LPXPDUELWUDWLRQODWHQF\ZKHQDOO WKHRWKHUPDVWHUVXVHWKHEXVXSWRWKHOLPLWVRIWKHLU/DWHQF\7LPHUV7KHSUREDELOLW\RI WKLVKDSSHQLQJLQFUHDVHVDVWKHORDGLQJRIWKHEXVLQFUHDVHV,QDOLJKWO\ORDGHGV\VWHP IHZHUPDVWHUVZLOOQHHGWRXVHWKHEXVRUZLOOXVHLWOHVVWKDQWKHLU/DWHQF\7LPHUZRXOG DOORZWKXVDOORZLQJTXLFNHUDFFHVVE\WKHRWKHUPDVWHUV +RZHIILFLHQWO\HDFKDJHQWXVHVWKHEXVZLOODOVRDIIHFWDYHUDJHDUELWUDWLRQODWHQFLHV 7KHPRUHZDLWVWDWHVDPDVWHURUWDUJHWLQVHUWVRQHDFKWUDQVDFWLRQWKHORQJHUHDFK WUDQVDFWLRQZLOOWDNHWKXVLQFUHDVLQJWKHSUREDELOLW\WKDWHDFKPDVWHUZLOOXVHWKHEXVXS WRWKHOLPLWRILWV/DWHQF\7LPHU 83 Revision 2.2 7KHIROORZLQJH[DPSOHVLOOXVWUDWHWKHLPSDFWRQDUELWUDWLRQODWHQF\DVWKHHIILFLHQF\RI WKHEXVJRHVGRZQGXHWRZDLWVWDWHVEHLQJLQVHUWHG,QERWKH[DPSOHVWKHV\VWHPKDVD VLQJOHDUELWUDWLRQOHYHOWKH/DWHQF\7LPHULVVHWWRDQGWKHUHDUHILYHPDVWHUVWKDW KDYHGDWDWRPRYH$/DWHQF\7LPHURIDOORZVHDFKPDVWHUWRPRYHDE\WH FDFKHOLQHLILQLWLDOODWHQF\LVRQO\HLJKWFORFNVDQGVXEVHTXHQWODWHQF\LVRQHFORFN7KH KLJKEXVHIILFLHQF\H[DPSOHLOOXVWUDWHVWKDWWKHLPSDFWRQDUELWUDWLRQODWHQF\LVVPDOO ZKHQWKHEXVLVEHLQJXVHGHIILFLHQWO\ 6\VWHPZLWK+LJK%XV(IILFLHQF\ ,QWKLVH[DPSOHHDFKPDVWHULVDEOHWRPRYHDQHQWLUHE\WHFDFKHOLQHEHIRUHLWV UHVSHFWLYH/DWHQF\7LPHUH[SLUHV7KLVH[DPSOHDVVXPHVWKDWHDFKPDVWHULVUHDG\ WRWUDQVIHUDQRWKHUFDFKHOLQHMXVWDIWHULWFRPSOHWHVLWVFXUUHQWWUDQVDFWLRQ,QWKLV H[DPSOHWKH/DWHQF\7LPHUKDVQRDIIHFW,WWDNHVWKHPDVWHU > LGOHFORFN LQLWLDOTRDY#FORFNV VXEVHTXHQWTRDY#FORFNV @ QVFORFN QV WRFRPSOHWHHDFKFDFKHOLQHWUDQVIHU ,IDOOILYHPDVWHUVXVHWKHVDPHQXPEHURIFORFNVWKHQHDFKPDVWHUZLOOKDYHWRZDLW IRUWKHRWKHUIRXURU QVPDVWHU RWKHUPDVWHUV µV EHWZHHQDFFHVVHV(DFKPDVWHUPRYHVGDWDDWDERXW 0%V 7KH/RZ%XV(IILFLHQF\H[DPSOHLOOXVWUDWHVWKHLPSDFWRQDUELWUDWLRQODWHQF\DVDUHVXOW RIWKHEXVEHLQJXVHGLQHIILFLHQWO\7KHILUVWHIIHFWLVWKDWWKH/DWHQF\7LPHUH[SLUHV 7KHVHFRQGHIIHFWLVWKDWLVWDNHVWZRWUDQVDFWLRQVWRFRPSOHWHDVLQJOHFDFKHOLQHWUDQVIHU ZKLFKFDXVHVWKHORDGLQJWRLQFUHDVH 6\VWHPZLWK/RZ%XV(IILFLHQF\ 7KLVH[DPSOHNHHSVWKHWDUJHWLQLWLDOODWHQF\WKHVDPHEXWLQFUHDVHVWKHVXEVHTXHQW ODWHQF\ PDVWHURUWDUJHWLQGXFHG IURPWR,QWKLVH[DPSOHWKH/DWHQF\7LPHU ZLOOH[SLUHEHIRUHWKHPDVWHUKDVWUDQVIHUUHGWKHIXOOE\WHFDFKHOLQH:KHQWKH /DWHQF\7LPHUH[SLUHVGNT#LVGHDVVHUWHGDQGFRAME#LVDVVHUWHGWKHPDVWHU PXVWVWRSWKHWUDQVDFWLRQSUHPDWXUHO\DQGFRPSOHWHVWKHILQDOWZRGDWDSKDVHVLWKDV FRPPLWWHGWRFRPSOHWH XQOHVVD0:,FRPPDQGLQZKLFKFDVHLWFRPSOHWHVWKH FXUUHQWFDFKHOLQH (DFKPDVWHU¶VWHQXUHRQWKHEXVZRXOGEH > LGOHFORFN /DWHQF\7LPHUFORFNV VXEVHTXHQWTRDY#FORFNV @ QVFORFN QV DQGHDFKPDVWHUKDVWRZDLW QVPDVWHU RWKHUPDVWHUV µV EHWZHHQDFFHVVHV+RZHYHUWKHPDVWHURQO\WRRNVOLJKWO\PRUHWLPHWKDQWKH+LJK %XV(IILFLHQF\H[DPSOHEXWRQO\FRPSOHWHGQLQHGDWDSKDVHV E\WHVMXVWRYHU KDOIDFDFKHOLQH LQVWHDGRIGDWDSKDVHV(DFKPDVWHUPRYHVGDWDDWRQO\DERXW 0%V 7KHDUELWUDWLRQODWHQF\LQWKH/RZ%XV(IILFLHQF\H[DPSOHLVµVLQVWHDGRI µVDVLQ WKH+LJK%XV(IILFLHQF\H[DPSOH EXWLWWRRNWKHPDVWHUWZRWUDQVDFWLRQVWRFRPSOHWHWKH WUDQVIHURIDVLQJOHFDFKHOLQH7KLVGRXEOHGWKHORDGLQJRIWKHV\VWHPZLWKRXWLQFUHDVLQJ 84 Revision 2.2 WKHGDWDWKURXJKSXW7KLVUHVXOWHGIURPVLPSO\DGGLQJDVLQJOHZDLWVWDWHWRHDFKGDWD SKDVH $OVRQRWHWKDWWKHDERYHGHVFULSWLRQDVVXPHVWKDWDOOILYHPDVWHUVDUHLQWKHVDPH DUELWUDWLRQOHYHO:KHQDPDVWHULVLQDORZHUDUELWUDWLRQOHYHORUUHVLGHVEHKLQGD3&, WR3&,EULGJHLWZLOOH[SHULHQFHORQJHUODWHQFLHVEHWZHHQDFFHVVHVZKHQWKHSULPDU\3&, EXVLVLQXVH 7KHPD[LPXPOLPLWVRIDWDUJHWDQGPDVWHUGDWDODWHQF\LQWKLVVSHFLILFDWLRQDUHSURYLGHG IRULQVWDQWDQHRXVFRQGLWLRQVZKLOHWKHUHFRPPHQGDWLRQVDUHXVHGIRUQRUPDOEHKDYLRU $QH[DPSOHRIDQLQVWDQWDQHRXVFRQGLWLRQLVZKHQWKHGHYLFHLVXQDEOHWRFRQWLQXH FRPSOHWLQJDGDWDSKDVHRQHDFKFORFN5DWKHUWKDQVWRSSLQJWKHWUDQVIHU LQWURGXFLQJ WKHRYHUKHDGRIUHDUELWUDWLRQDQGWDUJHWLQLWLDOODWHQF\ WKHWDUJHWZRXOGLQVHUWDFRXSOH RIZDLWVWDWHVDQGFRQWLQXHWKHEXUVWE\FRPSOHWLQJDGDWDSKDVHRQHDFKFORFN7KH PD[LPXPOLPLWVDUHQRWLQWHQGHGWREHXVHGRQHYHU\GDWDSKDVHEXWUDWKHURQWKRVHUDUH RFFDVLRQVZKHQGDWDLVWHPSRUDULO\XQDEOHWRWUDQVIHU 7KHIROORZLQJGLVFXVVLRQDVVXPHVWKDWGHYLFHVDUHFRPSOLDQWZLWKWKHVSHFLILFDWLRQDQG KDYHEHHQGHVLJQHGWRPLQLPL]HWKHLULPSDFWRQWKHEXV)RUH[DPSOHDPDVWHULV UHTXLUHGWRDVVHUWIRDY#ZLWKLQHLJKWFORFNVIRUDOOGDWDSKDVHV KRZHYHULWLV UHFRPPHQGHGWKDWLWDVVHUWIRDY#ZLWKLQRQHRUWZRFORFNV ([DPSOHRID6\VWHP 7KHIROORZLQJV\VWHPFRQILJXUDWLRQDQGWKHEDQGZLGWKHDFKGHYLFHUHTXLUHVDUH JHQHURXVDQGH[FHHGWKHQHHGVRIFXUUHQWLPSOHPHQWDWLRQV7KHV\VWHPWKDWZLOOEH XVHGIRUDGLVFXVVLRQDERXWODWHQF\LVDZRUNVWDWLRQFRPSULVHGRI +RVWEXVEULGJH ZLWKLQWHJUDWHGPHPRU\FRQWUROOHU *UDSKLFVGHYLFH 9*$DQGHQKDQFHGJUDSKLFV )UDPHJUDEEHU IRUYLGHRFRQIHUHQFLQJ /$1FRQQHFWLRQ 'LVN DVLQJOHVSLQGOH,'(RU6&6, 6WDQGDUGH[SDQVLRQEXVEULGJH 3&,WR,6$ $3&,WR3&,EULGJHIRUSURYLGLQJPRUHWKDQWKUHHDGGLQVORWV 7KHJUDSKLFVFRQWUROOHULVFDSDEOHRIVLQNLQJ0%V7KLVDVVXPHVWKDWWKHKRVW EXVEULGJHJHQHUDWHV0%VDQGWKHIUDPHJUDEEHUJHQHUDWHV0%V 7KH/$1FRQWUROOHUUHTXLUHVRQO\DERXW0%V 0E RQDYHUDJH ZRUNVWDWLRQ UHTXLUHPHQWV DQGLVW\SLFDOO\PXFKOHVV 7KHGLVNFRQWUROOHUFDQPRYHDERXW0%V 7KHVWDQGDUGH[SDQVLRQEXVSURYLGHVDFRVWHIIHFWLYHZD\RIFRQQHFWLQJVWDQGDUG,2 FRQWUROOHUV LHNH\ERDUGPRXVHVHULDOSDUDOOHOSRUWVHWF DQGPDVWHUVRQWKLVEXV SODFHDPD[LPXPRIDERXW0%V DJJUHJDWHSOXVRYHUKHDG RQ3&,DQGZLOO GHFUHDVHLQIXWXUHV\VWHPV 7KH3&,WR3&,EULGJHLQDQGRILWVHOIGRHVQRWXVH3&,EDQGZLGWKEXWDSODFH KROGHURI 0%VLVDOORFDWHGIRUGHYLFHVWKDWUHVLGHEHKLQGLW 7KHWRWDOEDQGZLGWKQHHGVRIWKHV\VWHPLVDERXW0%V LIDOO GHYLFHVZDQWWRXVHWKHEXVDWWKHVDPHWLPH 85 Revision 2.2 7RVKRZWKDWWKHEXVFDQKDQGOHDOOWKHGHYLFHVWKHVHEDQGZLGWKQXPEHUVZLOOEH XVHGLQWKHIROORZLQJGLVFXVVLRQ7KHSUREDELOLW\RIDOOGHYLFHVUHTXLULQJXVHRIWKH EXVDWWKHVDPHWLPHLVH[WUHPHO\ORZDQGWKHW\SLFDOODWHQF\ZLOOEHPXFKORZHU WKDQWKHZRUVWFDVHVQXPEHUGLVFXVVHG)RUWKLVGLVFXVVLRQWKHW\SLFDOQXPEHUVXVHG DUHDWDVWHDG\VWDWHFRQGLWLRQZKHUHWKHV\VWHPKDVEHHQRSHUDWLQJIRUDZKLOHDQG QRWDOOGHYLFHVUHTXLUHDFFHVVWRWKHEXVDWWKHVDPHWLPH Table 3-5 lists the requirements of each device in the target system and how many transactions each device must complete to sustain its bandwidth requirements within 10 µs time slices. 7KHILUVWFROXPQLGHQWLILHVWKHGHYLFHJHQHUDWLQJWKHGDWDWUDQVIHU 7KHVHFRQGFROXPQLVWKHWRWDOEDQGZLGWKWKHGHYLFHQHHGV 7KHWKLUGFROXPQLVWKHDSSUR[LPDWHQXPEHURIE\WHVWKDWQHHGWREHWUDQVIHUUHG GXULQJWKLVµVWLPHVOLFH 7KHIRXUWKFROXPQLVWKHDPRXQWRIWLPHUHTXLUHGWRPRYHWKHGDWD The last column indicates how many different transactions that are required to move the data. This assumes that the entire transfer cannot be completed as a single transaction. 7DEOH ([DPSOH6\VWHP Device Bandwidth Bytes/10 ms Time Used Number of Notes (MB/s) (ms) Transactions per Slice Graphics 50 500 6.15 10 1 LAN 4 40 0.54 1 2 Disk 5 50 0.63 1 3 ISA bridge 4 40 0.78 2 4 PCI-to PCI 9 90 1.17 2 5 bridge Total 72 720 9.27 16 Notes: 1. Graphics is a combination of host bus bridge and frame grabber writing data to the frame buffer. The host moves 300 bytes using five transactions with 15 data phases each, assuming eight clocks of target initial latency. The frame grabber moves 200 bytes using five transactions with 10 data phases each, assuming eight clocks of target initial latency. 2. The LAN uses a single transaction with 10 data phases with eight clocks of target initial latency. 3. The disk uses a single transaction with 13 data phases with eight clocks of target initial latency. 4. The ISA bridge uses two transactions with five data phases each with eight clocks of target initial latency. 5. The PCI-to-PCI bridge uses two transactions. One transaction is similar to the LAN and the second is similar to the disk requirements. 86 Revision 2.2 ,IWKHWDUJHWHGV\VWHPRQO\QHHGVIXOOPRWLRQYLGHRRUDIUDPHJUDEEHUEXWQRWERWK WKHQUHSODFHWKH*UDSKLFVURZLQ7DEOHZLWKWKHDSSURSULDWHURZLQ7DEOH,Q HLWKHUFDVHWKHWRWDOEDQGZLGWKUHTXLUHGRQ3&,LVUHGXFHG 7DEOH )UDPH*UDEEHURU)XOO0RWLRQ9LGHR([DPSOH Device Bandwidth Bytes/10 ms Time Used Number of Notes (MB/s) (ms) Transactions per Slice Host 40 400 4.2 5 1 writing to the frame buffer Frame 20 200 3.7 5 2 grabber Notes 1. The host uses five transactions with 20 data phases each, assuming eight clocks of target initial latency. 2. The frame grabber uses five transactions with 10 data phases each, assuming eight clocks of target initial latency. 7KHWRWDOVIRU7DEOHLQGLFDWHWKDWZLWKLQDµVZLQGRZDOOWKHGHYLFHVOLVWHGLQ WKHWDEOHPRYHWKHGDWDWKH\UHTXLUHGIRUWKDWWLPHVOLFH,QDUHDOV\VWHPQRWDOO GHYLFHVQHHGWRPRYHGDWDDOOWKHWLPH%XWWKH\PD\EHDEOHWRPRYHPRUHGDWDLQD VLQJOHWUDQVDFWLRQ:KHQGHYLFHVPRYHGDWDPRUHHIILFLHQWO\WKHODWHQF\HDFK GHYLFHH[SHULHQFHVLVUHGXFHG ,IWKHDERYHV\VWHPVXSSRUWHGWKHDUELWHULOOXVWUDWHGLQWKH6\VWHP$UELWUDWLRQ$OJRULWKP ,PSOHPHQWDWLRQ1RWH UHIHUWR6HFWLRQ WKHIUDPHJUDEEHU RUJUDSKLFVGHYLFHZKHQ LWLVDPDVWHU DQGWKH3&,WR3&,EULGJHZRXOGEHSXWLQWKHKLJKHVWOHYHO$OORWKHU GHYLFHVZRXOGEHSXWLQWKHORZHUOHYHO LHOHYHOWZR 7DEOHVKRZVWKDWLIDOO GHYLFHVSURYLGHµVRIEXIIHULQJWKH\ZRXOGQRWH[SHULHQFHXQGHUUXQVRURYHUUXQV +RZHYHUIRUGHYLFHVWKDWPRYHODUJHEORFNVRIGDWDDQGDUHJHQHUDOO\JLYHQKLJKHU SULRULW\LQDV\VWHPWKHQDODWHQF\RIµVLVUHDVRQDEOH :KHQRQO\WZRDJHQWVDUHDW WKHKLJKHVWOHYHOHDFKH[SHULHQFHVDERXWµVRIGHOD\EHWZHHQWUDQVDFWLRQV7KHWDEOH DVVXPHVWKDWWKHWDUJHWLVDEOHWRFRQVXPHDOOGDWDDVDVLQJOHWUDQVDFWLRQ 3.5.4.3. Determining Buffer Requirements (DFKGHYLFHWKDWLQWHUIDFHVWRWKHEXVQHHGVEXIIHULQJWRPDWFKWKHUDWHWKHGHYLFH SURGXFHVRUFRQVXPHVGDWDZLWKWKHUDWHWKDWLWFDQPRYHGDWDDFURVVWKHEXV7KHVL]HRI EXIIHULQJFDQEHGHWHUPLQHGE\VHYHUDOIDFWRUVEDVHGRQWKHIXQFWLRQDOLW\RIWKHGHYLFH DQGWKHUDWHDWZKLFKLWKDQGOHVGDWD$VGLVFXVVHGLQWKHSUHYLRXVVHFWLRQWKHDUELWUDWLRQ ODWHQF\DPDVWHUH[SHULHQFHVDQGKRZHIILFLHQWO\GDWDLVWUDQVIHUUHGRQWKHEXVZLOODIIHFW WKHDPRXQWRIEXIIHULQJDGHYLFHUHTXLUHV ,QVRPHFDVHVDVPDOODPRXQWRIEXIIHULQJLVUHTXLUHGWRKDQGOHHUURUVZKLOHPRUH EXIIHULQJPD\JLYHEHWWHUEXVXWLOL]DWLRQ)RUGHYLFHVZKLFKGRQRWXVHWKHEXVYHU\ PXFK GHYLFHVZKLFKUDUHO\UHTXLUHPRUHWKDQ0%V LWLVUHFRPPHQGHGWKDWD PLQLPXPRIIRXU':25'VRIEXIIHULQJEHVXSSRUWHGWRHQVXUHWKDWWUDQVDFWLRQVRQWKH EXVDUHGRQHZLWKUHDVRQDEOHHIILFLHQF\0RYLQJGDWDDVHQWLUHFDFKHOLQHVLVWKH SUHIHUUHGWUDQVIHUVL]H7UDQVDFWLRQVOHVVWKDQIRXU':25'VLQOHQJWKDUHLQHIILFLHQW 87 Revision 2.2 DQGZDVWHEXVEDQGZLGWK)RUGHYLFHVZKLFKXVHWKHEXVDORW GHYLFHVZKLFKIUHTXHQWO\ UHTXLUHPRUHWKDQ0%V LWLVUHFRPPHQGHGWKDWDPLQLPXPRI':25'VRI EXIIHULQJEHVXSSRUWHGWRHQVXUHWKDWWUDQVDFWLRQVRQWKHEXVDUHGRQHHIILFLHQWO\ 'HYLFHVWKDWGRQRWXVHWKHEXVHIILFLHQWO\ZLOOKDYHDQHJDWLYHLPSDFWRQV\VWHP SHUIRUPDQFHDQGDODUJHULPSDFWRQIXWXUHV\VWHPV :KLOHWKHVHUHFRPPHQGDWLRQVDUHPLQLPXPVWKHUHDODPRXQWRIEXIIHULQJDGHYLFH QHHGVLVGLUHFWO\SURSRUWLRQDOWRWKHGLIILFXOW\UHTXLUHGWRUHFRYHUIURPDQXQGHUUXQRU RYHUUXQ)RUH[DPSOHDGLVNFRQWUROOHUZRXOGSURYLGHVXIILFLHQWEXIIHULQJWRPRYHGDWD HIILFLHQWO\DFURVV3&,EXWZRXOGSURYLGHQRDGGLWLRQDOEXIIHULQJIRUXQGHUUXQVDQG RYHUUXQV VLQFHWKH\ZLOOQRWRFFXU :KHQGDWDLVQRWDYDLODEOHWRZULWHWRWKHGLVNWKH FRQWUROOHUZRXOGMXVWZDLWXQWLOGDWDLVDYDLODEOH)RUUHDGVZKHQDEXIIHULVQRW DYDLODEOHLWVLPSO\GRHVQRWDFFHSWDQ\QHZGDWD $IUDPHJUDEEHUPXVWHPSW\LWVEXIIHUVEHIRUHQHZGDWDDUULYHVRUGDWDLVGHVWUR\HG)RU V\VWHPVWKDWUHTXLUHJRRGYLGHRSHUIRUPDQFHWKHV\VWHPGHVLJQHUQHHGVWRSURYLGHDZD\ IRUWKDWDJHQWWREHJLYHQVXIILFLHQWEXVEDQGZLGWKWRSUHYHQWGDWDFRUUXSWLRQ7KLVFDQ EHDFFRPSOLVKHGE\SURYLGLQJDQDUELWHUWKDWKDVGLIIHUHQWOHYHOVDQGRUDGMXVWLQJWKH /DWHQF\7LPHURIRWKHUPDVWHUVWROLPLWWKHLUWHQXUHRQWKHEXV 7KHNH\IRUIXWXUHV\VWHPVLVWRKDYHDOOGHYLFHVXVHWKHEXVDVHIILFLHQWO\DVSRVVLEOH 7KLVPHDQVWRPRYHDVPXFKGDWDDVSRVVLEOH SUHIHUDEO\VHYHUDOFDFKHOLQHV LQWKH VPDOOHVWQXPEHURIFORFNV SUHIHUDEO\RQHFORFNVXEVHTXHQWODWHQF\ $VGHYLFHVGRWKLV WKHHQWLUHV\VWHPH[SHULHQFHVJUHDWHUWKURXJKSXWDQGORZHUODWHQFLHV/RZHUODWHQFLHV DOORZVPDOOHUEXIIHUVWREHSURYLGHGLQLQGLYLGXDOGHYLFHV)XWXUHEHQFKPDUNVZLOO DOORZV\VWHPGHVLJQHUVWRGLVWLQJXLVKEHWZHHQGHYLFHVWKDWXVHWKHEXVHIILFLHQWO\DQG WKRVHWKDWGRQRW7KRVHWKDWGRZLOOHQDEOHV\VWHPVWREHEXLOWWKDWPHHWWKHGHPDQGVRI PXOWLPHGLDV\VWHPV 3.6. Other Bus Operations 3.6.1. Device Selection DEVSEL#LVGULYHQE\WKHWDUJHWRIWKHFXUUHQWWUDQVDFWLRQDVVKRZQLQ)LJXUHWR LQGLFDWHWKDWLWLVUHVSRQGLQJWRWKHWUDQVDFWLRQDEVSEL#PD\EHGULYHQRQHWZRRU WKUHHFORFNVIROORZLQJWKHDGGUHVVSKDVH(DFKWDUJHWLQGLFDWHVWKHDEVSEL#WLPLQJLW XVHVLQLWV&RQILJXUDWLRQ6SDFH6WDWXVUHJLVWHUGHVFULEHGLQ6HFWLRQDEVSEL# PXVWEHDVVHUWHGZLWKRUSULRUWRWKHHGJHDWZKLFKWKHWDUJHWHQDEOHVLWVTRDY# STOP#DQGGDWDLIDUHDGWUDQVDFWLRQ,QRWKHUZRUGVDWDUJHWPXVWDVVHUWDEVSEL# FODLPWKHWUDQVDFWLRQ EHIRUHRUFRLQFLGHQWZLWKVLJQDOLQJDQ\RWKHUWDUJHWUHVSRQVH 2QFHDEVSEL#KDVEHHQDVVHUWHGLWFDQQRWEHGHDVVHUWHGXQWLOWKHODVWGDWDSKDVHKDV FRPSOHWHGH[FHSWWRVLJQDO7DUJHW$ERUW5HIHUWR6HFWLRQIRUPRUH LQIRUPDWLRQ 88 Revision 2.2 CLK 1 2 3 4 5 6 7 8 FRAME# IRDY# TRDY# NO RESPONSE DEVSEL# FAST MED SLOW SUB ACKNOWLEDGE )LJXUH DEVSEL# $VVHUWLRQ ,IQRDJHQWDVVHUWVDEVSEL#ZLWKLQWKUHHFORFNVRIFRAME#WKHDJHQWGRLQJ VXEWUDFWLYHGHFRGHPD\FODLPDQGDVVHUWDEVSEL#,IWKHV\VWHPGRHVQRWKDYHD VXEWUDFWLYHGHFRGHDJHQWWKHPDVWHUQHYHUVHHVDEVSEL#DVVHUWHGDQGWHUPLQDWHVWKH WUDQVDFWLRQSHUWKH0DVWHU$ERUWPHFKDQLVP UHIHUWR6HFWLRQ $WDUJHWPXVWGRDIXOOGHFRGHEHIRUHGULYLQJDVVHUWLQJDEVSEL#RUDQ\RWKHUWDUJHW UHVSRQVHVLJQDO,WLVLOOHJDOWRGULYHDEVSEL#SULRUWRDFRPSOHWHGHFRGHDQGWKHQOHW WKHGHFRGHFRPELQDWLRQDOO\UHVROYHRQWKHEXV 7KLVFRXOGFDXVHFRQWHQWLRQ $WDUJHW PXVWTXDOLI\WKHADOLQHVZLWKFRAME#EHIRUHDEVSEL#FDQEHDVVHUWHGRQ FRPPDQGVRWKHUWKDQFRQILJXUDWLRQ$WDUJHWPXVWTXDOLI\IDSELZLWKFRAME#DQG AD[1::0]EHIRUHDEVSEL#FDQEHDVVHUWHGRQDFRQILJXUDWLRQFRPPDQG ,WLVH[SHFWHGWKDWPRVW SHUKDSVDOO WDUJHWGHYLFHVZLOOEHDEOHWRFRPSOHWHDGHFRGHDQG DVVHUWDEVSEL#ZLWKLQRQHRUWZRFORFNVRIFRAME#EHLQJDVVHUWHG IDVWDQGPHGLXP LQWKHILJXUH $FFRUGLQJO\WKHVXEWUDFWLYHGHFRGHDJHQWPD\SURYLGHDQRSWLRQDOGHYLFHGHSHQGHQW FRQILJXUDWLRQUHJLVWHUWKDWFDQEHSURJUDPPHGWRSXOOLQE\RQHRUWZRFORFNVWKHHGJHDW ZKLFKLWDVVHUWVDEVSEL#DOORZLQJIDVWHUDFFHVVWRWKHH[SDQVLRQEXV8VHRIVXFKDQ RSWLRQLVOLPLWHGE\WKHVORZHVWSRVLWLYHGHFRGHDJHQWRQWKHEXV ,IWKHILUVWE\WHDGGUHVVHGE\WKHWUDQVDFWLRQPDSVLQWRWKHWDUJHW VDGGUHVVUDQJHLW DVVHUWVDEVSEL#WRFODLPWKHDFFHVV%XWLIWKHPDVWHUDWWHPSWVWRFRQWLQXHWKHEXUVW WUDQVDFWLRQDFURVVWKHUHVRXUFHERXQGDU\WKHWDUJHWLVUHTXLUHGWRVLJQDO'LVFRQQHFW :KHQDWDUJHWFODLPVDQ,2DFFHVVDQGWKHE\WHHQDEOHVLQGLFDWHRQHRUPRUHE\WHVRI WKHDFFHVVDUHRXWVLGHWKHWDUJHW VDGGUHVVUDQJHLWPXVWVLJQDO7DUJHW$ERUW 5HIHUWR 6HFWLRQIRUPRUHLQIRUPDWLRQ 7RGHDOZLWKWKLVW\SHRI,2DFFHVVSUREOHPD VXEWUDFWLYHGHFRGHGHYLFH H[SDQVLRQEXVEULGJH PD\GRRQHRIWKHIROORZLQJ • 'RSRVLWLYHGHFRGH E\LQFOXGLQJDE\WHPDS RQDGGUHVVHVIRUZKLFKGLIIHUHQW GHYLFHVVKDUHFRPPRQ':25'VDGGLWLRQDOO\XVLQJE\WHHQDEOHVWRGHWHFWWKLV SUREOHPDQGVLJQDO7DUJHW$ERUW • 3DVVWKHIXOODFFHVVWRWKHH[SDQVLRQEXVZKHUHWKHSRUWLRQRIWKHDFFHVVWKDW FDQQRWEHVHUYLFHGZLOOTXLHWO\GURSRQWKHIORRU 7KLVRFFXUVRQO\ZKHQWKHILUVW DGGUHVVHGWDUJHWUHVLGHVRQWKHH[SDQVLRQEXVDQGWKHRWKHULVRQ3&, 89 Revision 2.2 3.6.2. Special Cycle 7KH6SHFLDO&\FOHFRPPDQGSURYLGHVDVLPSOHPHVVDJHEURDGFDVWPHFKDQLVPRQ3&, ,QDGGLWLRQWRFRPPXQLFDWLQJSURFHVVRUVWDWXV DVLVGRQHRQ,QWHOSURFHVVRUEXVHV LW PD\DOVREHXVHGIRUORJLFDOVLGHEDQGVLJQDOLQJEHWZHHQ3&,DJHQWVZKHQVXFKVLJQDOLQJ GRHVQRWUHTXLUHWKHSUHFLVHWLPLQJRUV\QFKURQL]DWLRQRISK\VLFDOVLJQDOV $JRRGSDUDGLJPIRUWKH6SHFLDO&\FOHFRPPDQGLVWKDWRID³ORJLFDOZLUH´ZKLFKRQO\ VLJQDOVVLQJOHFORFNSXOVHV LHLWFDQEHXVHGWRVHWDQGUHVHWIOLSIORSVLQUHDOWLPH LPSO\LQJWKDWGHOLYHU\LVJXDUDQWHHG7KLVDOORZVWKHGHVLJQHUWRGHILQHQHFHVVDU\ VLGHEDQGFRPPXQLFDWLRQZLWKRXWUHTXLULQJDGGLWLRQDOSLQV$VZLWKVLGHEDQGVLJQDOLQJ LQJHQHUDOLPSOHPHQWDWLRQRI6SHFLDO&\FOHFRPPDQGVXSSRUWLVRSWLRQDO 7KH6SHFLDO&\FOHFRPPDQGFRQWDLQVQRH[SOLFLWGHVWLQDWLRQDGGUHVVEXWLVEURDGFDVWWR DOODJHQWVRQWKHVDPHEXVVHJPHQW(DFKUHFHLYLQJDJHQWPXVWGHWHUPLQHZKHWKHUWKH PHVVDJHLVDSSOLFDEOHWRLW3&,DJHQWVZLOOQHYHUDVVHUWDEVSEL#LQUHVSRQVHWRD 6SHFLDO&\FOHFRPPDQG 1RWH 6SHFLDO&\FOHFRPPDQGVGRQRWFURVV3&,WR3&,EULGJHV,IDPDVWHUGHVLUHVWR JHQHUDWHD6SHFLDO&\FOHFRPPDQGRQDVSHFLILFEXVLQWKHKLHUDUFK\LWPXVWXVHD7\SH FRQILJXUDWLRQZULWHFRPPDQGWRGRVR7\SHFRQILJXUDWLRQZULWHFRPPDQGVFDQ WUDYHUVH3&,WR3&,EULGJHVLQERWKGLUHFWLRQVIRUWKHSXUSRVHRIJHQHUDWLQJ6SHFLDO &\FOHFRPPDQGVRQDQ\EXVLQWKHKLHUDUFK\DQGDUHUHVWULFWHGWRDVLQJOHGDWDSKDVHLQ OHQJWK+RZHYHUWKHPDVWHUPXVWNQRZWKHVSHFLILFEXVRQZKLFKLWGHVLUHVWRJHQHUDWH WKH6SHFLDO&\FOHFRPPDQGDQGFDQQRWVLPSO\GRDEURDGFDVWWRRQHEXVDQGH[SHFWLWWR SURSDJDWHWRDOOEXVHV5HIHUWR6HFWLRQIRUPRUHLQIRUPDWLRQ $6SHFLDO&\FOHFRPPDQGPD\FRQWDLQRSWLRQDOPHVVDJHGHSHQGHQWGDWDZKLFKLVQRW LQWHUSUHWHGE\WKH3&,VHTXHQFHULWVHOIEXWLVSDVVHGDVQHFHVVDU\WRWKHKDUGZDUH DSSOLFDWLRQFRQQHFWHGWRWKH3&,VHTXHQFHU,QPRVWFDVHVH[SOLFLWO\DGGUHVVHG PHVVDJHVVKRXOGEHKDQGOHGLQRQHRIWKHWKUHHSK\VLFDODGGUHVVVSDFHVRQ3&,DQGQRW ZLWKWKH6SHFLDO&\FOHFRPPDQG 8VLQJDPHVVDJHGHSHQGHQWGDWDILHOGFDQEUHDNWKHORJLFDOZLUHSDUDGLJPPHQWLRQHG DERYHDQGFUHDWHGHOLYHU\JXDUDQWHHSUREOHPV+RZHYHUVLQFHWDUJHWVRQO\DFFHSW PHVVDJHVWKH\UHFRJQL]HDQGXQGHUVWDQGWKHEXUGHQLVSODFHGRQWKHPWRIXOO\SURFHVV WKHPHVVDJHLQWKHPLQLPXPGHOLYHU\WLPH VL[EXVFORFNV RUWRSURYLGHDQ\QHFHVVDU\ EXIIHULQJIRUPHVVDJHVWKH\DFFHSW1RUPDOO\WKLVEXIIHULQJLVOLPLWHGWRDVLQJOHIOLS IORS7KLVDOORZVGHOLYHU\WREHJXDUDQWHHG,QVRPHFDVHVLWPD\QRWEHSRVVLEOHWR EXIIHURUSURFHVVDOOPHVVDJHVWKDWFRXOGEHUHFHLYHG,QWKLVFDVHWKHUHLVQRJXDUDQWHH RIGHOLYHU\ $6SHFLDO&\FOHFRPPDQGLVOLNHDQ\RWKHUEXVFRPPDQGZKHUHWKHUHLVDQDGGUHVV SKDVHDQGDGDWDSKDVH7KHDGGUHVVSKDVHVWDUWVOLNHDOORWKHUFRPPDQGVZLWKWKH DVVHUWLRQRIFRAME#DQGFRPSOHWHVOLNHDOORWKHUFRPPDQGVZKHQFRAME#DQG IRDY#DUHGHDVVHUWHG7KHXQLTXHQHVVRIWKLVFRPPDQGFRPSDUHGWRWKHRWKHUVLVWKDW QRDJHQWUHVSRQGVZLWKWKHDVVHUWLRQRIDEVSEL#DQGWKHWUDQVDFWLRQFRQFOXGHVZLWKD 0DVWHU$ERUWWHUPLQDWLRQ0DVWHU$ERUWLVWKHQRUPDOWHUPLQDWLRQIRU6SHFLDO&\FOH WUDQVDFWLRQVDQGQRHUURUVDUHUHSRUWHGIRUWKLVFDVHRI0DVWHU$ERUWWHUPLQDWLRQ7KLV FRPPDQGLVEDVLFDOO\DEURDGFDVWWRDOODJHQWVDQGLQWHUHVWHGDJHQWVDFFHSWWKH FRPPDQGDQGSURFHVVWKHUHTXHVW 7KHDGGUHVVSKDVHFRQWDLQVQRYDOLGLQIRUPDWLRQRWKHUWKDQWKHFRPPDQGILHOG7KHUHLV QRH[SOLFLWDGGUHVV KRZHYHUAD[31::00]DUHGULYHQWRDVWDEOHOHYHODQGSDULW\LV JHQHUDWHG'XULQJWKHGDWDSKDVHAD[31::00]FRQWDLQWKHPHVVDJHW\SHDQGDQRSWLRQDO 90 Revision 2.2 GDWDILHOG7KHPHVVDJHLVHQFRGHGRQWKHOHDVWVLJQLILFDQWOLQHVQDPHO\AD[15::00] 7KHRSWLRQDOGDWDILHOGLVHQFRGHGRQWKHPRVWVLJQLILFDQWOLQHVQDPHO\AD[31::16] DQGLVQRWUHTXLUHGRQDOOPHVVDJHV7KHPDVWHURID6SHFLDO&\FOHFRPPDQGFDQLQVHUW ZDLWVWDWHVOLNHDQ\RWKHUFRPPDQGZKLOHWKHWDUJHWFDQQRW VLQFHQRWDUJHWFODLPHGWKH DFFHVVE\DVVHUWLQJDEVSEL# 7KHPHVVDJHDQGDVVRFLDWHGGDWDDUHRQO\YDOLGRQWKH ILUVWFORFNIRDY#LVDVVHUWHG7KHLQIRUPDWLRQFRQWDLQHGLQDQGWKHWLPLQJRI VXEVHTXHQWGDWDSKDVHVDUHPHVVDJHGHSHQGHQW:KHQWKHPDVWHULQVHUWVDZDLWVWDWHRU SHUIRUPVPXOWLSOHGDWDSKDVHVLWPXVWH[WHQGWKHWUDQVDFWLRQWRJLYHSRWHQWLDOWDUJHWV VXIILFLHQWWLPHWRSURFHVVWKHPHVVDJH7KLVPHDQVWKHPDVWHUPXVWJXDUDQWHHWKHDFFHVV ZLOOQRWFRPSOHWHIRUDWOHDVWIRXUFORFNV PD\EHORQJHU DIWHUWKHODVWYDOLGGDWD FRPSOHWHV)RUH[DPSOHDPDVWHUNHHSVIRDY#GHDVVHUWHGIRUWZRFORFNVIRUDVLQJOH GDWDSKDVH6SHFLDO&\FOHFRPPDQG%HFDXVHWKHPDVWHULQVHUWHGZDLWVWDWHVWKH WUDQVDFWLRQFDQQRWEHWHUPLQDWHGZLWK0DVWHU$ERUWRQWKHILIWKFORFNDIWHUFRAME# WKHFORFNDIWHUVXEWUDFWLYHGHFRGHWLPH OLNHXVXDOEXWPXVWEHH[WHQGHGDWOHDVWDQ DGGLWLRQDOWZRFORFNV:KHQWKHWUDQVDFWLRQKDVPXOWLSOHGDWDSKDVHVWKHPDVWHUFDQQRW WHUPLQDWHWKH6SHFLDO&\FOHFRPPDQGXQWLODWOHDVWIRXUFORFNVDIWHUWKHODVWYDOLGGDWD SKDVH1RWH 7KHPHVVDJHW\SHRURSWLRQDOGDWDILHOGZLOOLQGLFDWHWRSRWHQWLDOWDUJHWV WKHDPRXQWRIGDWDWREHWUDQVIHUUHG7KHWDUJHWPXVWODWFKGDWDRQWKHILUVWFORFNIRDY# LVDVVHUWHGIRUHDFKSLHFHRIGDWDWUDQVIHUUHG 'XULQJWKHDGGUHVVSKDVHC/BE[3::0]# 6SHFLDO&\FOHFRPPDQG DQG AD[31::00]DUHGULYHQWRUDQGRPYDOXHVDQGPXVWEHLJQRUHG'XULQJWKHGDWDSKDVH C/BE[3::0]#DUHDVVHUWHGDQGAD[31::00]DUHDVIROORZV AD[15::00] Encoded message AD[31::16] Message dependent (optional) data field 7KH3&,EXVVHTXHQFHUVWDUWVWKLVFRPPDQGOLNHDOORWKHUVDQGWHUPLQDWHVLWZLWKD 0DVWHU$ERUW7KHKDUGZDUHDSSOLFDWLRQSURYLGHVDOOWKHLQIRUPDWLRQOLNHDQ\RWKHU FRPPDQGDQGVWDUWVWKHEXVVHTXHQFHU:KHQWKHVHTXHQFHUUHSRUWVWKDWWKHDFFHVV WHUPLQDWHGZLWKD0DVWHU$ERUWWKHKDUGZDUHDSSOLFDWLRQNQRZVWKHDFFHVVFRPSOHWHG ,QWKLVFDVHWKH5HFHLYHG0DVWHU$ERUWELWLQWKHFRQILJXUDWLRQ6WDWXVUHJLVWHU 6HFWLRQ PXVWQRWEHVHW7KHTXLFNHVWD6SHFLDO&\FOHFRPPDQGFDQFRPSOHWHLV ILYHFORFNV2QHDGGLWLRQDOFORFNLVUHTXLUHGIRUWKHWXUQDURXQGF\FOHEHIRUHWKHQH[W DFFHVV7KHUHIRUHDWRWDORIVL[FORFNVLVUHTXLUHGIURPWKHEHJLQQLQJRID6SHFLDO&\FOH FRPPDQGWRWKHEHJLQQLQJRIDQRWKHUDFFHVV 7KHUHDUHDWRWDORI.PHVVDJHV7KHPHVVDJHHQFRGLQJVDUHGHILQHGDQGGHVFULEHGLQ $SSHQGL[$ 3.6.3. Address/Data Stepping 7KHDELOLW\RIDQDJHQWWRVSUHDGDVVHUWLRQRITXDOLILHGVLJQDOVRYHUVHYHUDOFORFNVLV UHIHUUHGWRDVVWHSSLQJ7KLVQRWLRQDOORZVDQDJHQWZLWKZHDNRXWSXWEXIIHUVWRGULYH DVHWRIVLJQDOVWRDYDOLGVWDWHRYHUVHYHUDOFORFNV FRQWLQXRXVVWHSSLQJ WKHUHE\ UHGXFLQJWKHJURXQGFXUUHQWORDGJHQHUDWHGE\HDFKEXIIHU$QDOWHUQDWLYHDSSURDFK DOORZVDQDJHQWZLWKVWURQJRXWSXWEXIIHUVWRGULYHDVXEVHWRIWKHPRQHDFKRIVHYHUDO FORFNHGJHVXQWLOWKH\DUHDOOGULYHQ GLVFUHWHVWHSSLQJ WKHUHE\UHGXFLQJWKHQXPEHURI VLJQDOVWKDWPXVWEHVZLWFKHGVLPXOWDQHRXVO\$OODJHQWVPXVWEHDEOHWRKDQGOHDGGUHVV DQGGDWDVWHSSLQJZKLOHJHQHUDWLQJLWLVRSWLRQDO5HIHUWR6HFWLRQIRUFRQGLWLRQV DVVRFLDWHGZLWKLQGHWHUPLQDWHVLJQDOOHYHOVRQWKHULVLQJHGJHRICLK 91 Revision 2.2 (LWKHUFRQWLQXRXVRUGLVFUHWHVWHSSLQJDOORZVDQDJHQWWRWUDGHRIISHUIRUPDQFHIRUFRVW IHZHUSRZHUJURXQGSLQV :KHQXVLQJWKHFRQWLQXRXVVWHSSLQJDSSURDFKFDUHPXVWEH WDNHQWRDYRLGPXWXDOFRXSOLQJEHWZHHQFULWLFDOFRQWUROVLJQDOVWKDWPXVWEHVDPSOHGRQ HDFKFORFNHGJHDQGWKHVWHSSHGVLJQDOVWKDWPD\EHWUDQVLWLRQLQJRQDFORFNHGJH 3HUIRUPDQFHFULWLFDOSHULSKHUDOVVKRXOGDSSO\WKLVSHUPLVVLRQVSDULQJO\ 6WHSSLQJLVRQO\SHUPLWWHGRQAD[31::00]AD[63::32]PARPAR64# IRUELWGDWD WUDQVIHUVEXWQRWIRUWKH'$&FRPPDQG DQGIDSELSLQVEHFDXVHWKH\DUHDOZD\V TXDOLILHGE\FRQWUROVLJQDOV LHWKHVHVLJQDOVDUHRQO\FRQVLGHUHGYDOLGRQFORFNHGJHV IRUZKLFKWKH\DUHTXDOLILHGADVDUHTXDOLILHGE\FRAME#LQDGGUHVVSKDVHVDQGE\ IRDY#RUTRDY#LQGDWDSKDVHV GHSHQGLQJRQZKLFKGLUHFWLRQGDWDLVEHLQJ WUDQVIHUUHG PARLVLPSOLFLWO\TXDOLILHGRQHDFKFORFNDIWHUZKLFKADZDVTXDOLILHG IDSELLVTXDOLILHGE\WKHFRPELQDWLRQRIFRAME#DQGDGHFRGHG7\SHFRQILJXUDWLRQ FRPPDQG )LJXUHLOOXVWUDWHVDPDVWHUGHOD\LQJWKHDVVHUWLRQRIFRAME#XQWLOLWKDV VXFFHVVIXOO\GULYHQDOOADOLQHV7KHPDVWHULVERWKSHUPLWWHGDQGUHTXLUHGWRGULYHAD DQGC/BE#RQFHRZQHUVKLSKDVEHHQJUDQWHGDQGWKHEXVLVLQWKH,GOHVWDWH%XWLWPD\ WDNHPXOWLSOHFORFNVWRGULYHDYDOLGDGGUHVVEHIRUHDVVHUWLQJFRAME#+RZHYHUE\ GHOD\LQJDVVHUWLRQRIFRAME#WKHPDVWHUUXQVWKHULVNRIORVLQJLWVWXUQRQWKHEXV$V ZLWKDQ\PDVWHUGNT#PXVWEHDVVHUWHGRQWKHULVLQJFORFNHGJHEHIRUHFRAME#LV DVVHUWHG,IGNT#ZHUHGHDVVHUWHGRQWKHFORFNHGJHVPDUNHG$WKHPDVWHULV UHTXLUHGWRLPPHGLDWHO\WULVWDWHLWVVLJQDOVEHFDXVHWKHDUELWHUKDVJUDQWHGWKHEXVWR DQRWKHUDJHQW 7KHQHZPDVWHUZRXOGEHDWDKLJKHUSULRULW\OHYHO ,IGNT#ZHUH GHDVVHUWHGRQWKHFORFNHGJHVPDUNHG%RU&FRAME#ZLOOKDYHDOUHDG\EHHQ DVVHUWHGDQGWKHWUDQVDFWLRQFRQWLQXHV CLK 1 2 3 4 5 6 7 8 9 A A B C GNT# FRAME# IRDY# AD ADDRESS DATA-0 C/BE# BUS CMD BE#'s-0 )LJXUH $GGUHVV6WHSSLQJ 92 Revision 2.2 3.6.4. Interrupt Acknowledge 7KH3&,EXVVXSSRUWVDQ,QWHUUXSW$FNQRZOHGJHF\FOHDVVKRZQLQ)LJXUH 7KLV ILJXUHLOOXVWUDWHVDQ[,QWHUUXSW$FNQRZOHGJHF\FOHRQ3&,ZKHUHDVLQJOHE\WHHQDEOH LVDVVHUWHGDQGLVSUHVHQWHGRQO\DVDQH[DPSOH,QJHQHUDOWKHE\WHHQDEOHVGHWHUPLQH ZKLFKE\WHVDUHLQYROYHGLQWKHWUDQVDFWLRQ'XULQJWKHDGGUHVVSKDVHAD[31::00]GR QRWFRQWDLQDYDOLGDGGUHVVEXWPXVWEHGULYHQZLWKVWDEOHGDWDPARLVYDOLGDQGSDULW\ PD\EHFKHFNHG$Q,QWHUUXSW$FNQRZOHGJHWUDQVDFWLRQKDVQRDGGUHVVLQJPHFKDQLVP DQGLVLPSOLFLWO\WDUJHWHGWRWKHLQWHUUXSWFRQWUROOHULQWKHV\VWHP$VGHILQHGLQWKH3&, WR3&,%ULGJH$UFKLWHFWXUH6SHFLILFDWLRQWKH,QWHUUXSW$FNQRZOHGJHFRPPDQGLVQRW IRUZDUGHGWRDQRWKHU3&,VHJPHQW7KH,QWHUUXSW$FNQRZOHGJHF\FOHLVOLNHDQ\RWKHU WUDQVDFWLRQLQWKDWDEVSEL#PXVWEHDVVHUWHGRQHWZRRUWKUHHFORFNVDIWHUWKH DVVHUWLRQRIFRAME#IRUSRVLWLYHGHFRGHDQGPD\DOVREHVXEWUDFWLYHO\GHFRGHGE\D VWDQGDUGH[SDQVLRQEXVEULGJH:DLWVWDWHVFDQEHLQVHUWHGDQGWKHUHTXHVWFDQEH WHUPLQDWHGDVGLVFXVVHGLQ6HFWLRQ7KHYHFWRUPXVWEHUHWXUQHGZKHQTRDY# LVDVVHUWHG CLK 1 2 3 4 5 FRAME# NOT VECTOR AD VALID C/BE# INT-ACK BE#'s (1110) IRDY# TRDY# )LJXUH ,QWHUUXSW$FNQRZOHGJH&\FOH 8QOLNHWKHWUDGLWLRQDO GXDOF\FOHDFNQRZOHGJH3&,UXQVDVLQJOHF\FOH DFNQRZOHGJH&RQYHUVLRQIURPWKHSURFHVVRU VWZRF\FOHIRUPDWWRWKH3&,RQHF\FOH IRUPDWLVHDVLO\GRQHLQWKHEULGJHE\GLVFDUGLQJWKHILUVW,QWHUUXSW$FNQRZOHGJHUHTXHVW IURPWKHSURFHVVRU 3.7. Error Functions 3&,SURYLGHVIRUSDULW\DQGRWKHUV\VWHPHUURUVWREHGHWHFWHGDQGUHSRUWHG$VLQJOH V\VWHPPD\LQFOXGHGHYLFHVWKDWKDYHQRLQWHUHVWLQHUURUV SDUWLFXODUO\SDULW\HUURUV DQG DJHQWVWKDWGHWHFWVLJQDODQGUHFRYHUIURPHUURUV3&,HUURUUHSRUWLQJDOORZVDJHQWVWKDW UHFRYHUIURPSDULW\HUURUVWRDYRLGDIIHFWLQJWKHRSHUDWLRQRIDJHQWVWKDWGRQRW7R DOORZWKLVUDQJHRIIOH[LELOLW\WKHJHQHUDWLRQRISDULW\LVUHTXLUHGRQDOOWUDQVDFWLRQVE\ DOODJHQWV7KHGHWHFWLRQDQGUHSRUWLQJRIHUURUVLVJHQHUDOO\UHTXLUHGZLWKOLPLWHG H[FOXVLRQVIRUFHUWDLQFODVVHVRI3&,DJHQWVDVOLVWHGLQ6HFWLRQ 93 Revision 2.2 3.7.1. Parity Generation 3DULW\RQ3&,SURYLGHVDPHFKDQLVPWRGHWHUPLQHIRUHDFKWUDQVDFWLRQLIWKHPDVWHULV VXFFHVVIXOLQDGGUHVVLQJWKHGHVLUHGWDUJHWDQGLIGDWDWUDQVIHUVFRUUHFWO\EHWZHHQWKHP 7RHQVXUHWKDWWKHFRUUHFWEXVRSHUDWLRQLVSHUIRUPHGWKHIRXUFRPPDQGOLQHVDUH LQFOXGHGLQWKHSDULW\FDOFXODWLRQ7RHQVXUHWKDWFRUUHFWGDWDLVWUDQVIHUUHGWKHIRXUE\WH HQDEOHVDUHDOVRLQFOXGHGLQWKHSDULW\FDOFXODWLRQ7KHDJHQWWKDWLVUHVSRQVLEOHIRU GULYLQJAD[31::00]RQDQ\JLYHQEXVSKDVHLVDOVRUHVSRQVLEOHIRUGULYLQJHYHQSDULW\ RQPAR7KHIROORZLQJUHTXLUHPHQWVDOVRDSSO\ZKHQWKHELWH[WHQVLRQVDUHXVHG UHIHUWR6HFWLRQIRUPRUHLQIRUPDWLRQ 'XULQJDGGUHVVDQGGDWDSKDVHVSDULW\FRYHUVAD[31::00]DQGC/BE[3::0]#OLQHV UHJDUGOHVVRIZKHWKHURUQRWDOOOLQHVFDUU\PHDQLQJIXOLQIRUPDWLRQ%\WHODQHVQRW DFWXDOO\WUDQVIHUULQJGDWDDUHVWLOOUHTXLUHGWREHGULYHQZLWKVWDEOH DOEHLWPHDQLQJOHVV GDWDDQGDUHLQFOXGHGLQWKHSDULW\FDOFXODWLRQ'XULQJFRQILJXUDWLRQ6SHFLDO&\FOHRU ,QWHUUXSW$FNQRZOHGJHWUDQVDFWLRQVVRPH RUDOO DGGUHVVOLQHVDUHQRWGHILQHGEXWDUH UHTXLUHGWREHGULYHQWRVWDEOHYDOXHVDQGDUHLQFOXGHGLQWKHSDULW\FDOFXODWLRQ 3DULW\LVJHQHUDWHGDFFRUGLQJWRWKHIROORZLQJUXOHV • 3DULW\LVFDOFXODWHGWKHVDPHRQDOO3&,WUDQVDFWLRQVUHJDUGOHVVRIWKHW\SHRUIRUP • 7KHQXPEHURIVRQAD[31::00]C/BE[3::0]#DQGPARHTXDOVDQHYHQ QXPEHU • 3DULW\JHQHUDWLRQLVQRWRSWLRQDO LWPXVWEHGRQHE\DOO3&,FRPSOLDQWGHYLFHV 2QDQ\JLYHQEXVSKDVHPARLVGULYHQE\WKHDJHQWWKDWGULYHVAD[31::00]DQGODJV WKHFRUUHVSRQGLQJDGGUHVVRUGDWDE\RQHFORFN)LJXUHLOOXVWUDWHVERWKUHDGDQG ZULWHWUDQVDFWLRQVZLWKSDULW\7KHPDVWHUGULYHVPARIRUWKHDGGUHVVSKDVHVRQFORFNV DQG7KHWDUJHWGULYHVPARIRUWKHGDWDSKDVHRQWKHUHDGWUDQVDFWLRQ FORFN DQG WKHPDVWHUGULYHVPARIRUWKHGDWDSKDVHRQWKHZULWHWUDQVDFWLRQ FORFN 1RWH 2WKHUWKDQWKHRQHFORFNODJPAREHKDYHVH[DFWO\OLNHAD[31::00]LQFOXGLQJZDLW VWDWHVDQGWXUQDURXQGF\FOHV CLK 1 2 3 4 5 6 7 8 9 FRAME# AD ADDRESS DATA ADDRESS DATA PAR PERR# )LJXUH 3DULW\2SHUDWLRQ 94 Revision 2.2 3.7.2. Parity Checking 3DULW\PXVWEHFKHFNHGWRGHWHUPLQHLIWKHPDVWHUVXFFHVVIXOO\DGGUHVVHGWKHGHVLUHG WDUJHWDQGLIGDWDWUDQVIHUUHGFRUUHFWO\$OOGHYLFHVDUHUHTXLUHGWRFKHFNSDULW\H[FHSW GHYLFHVLQWKHIROORZLQJWZRFODVVHVIRUZKLFKSDULW\FKHFNLQJLVRSWLRQDO • 'HYLFHVWKDWDUHGHVLJQHGH[FOXVLYHO\IRUXVHRQWKHPRWKHUERDUGRUSODQDU HJFKLS VHWV6\VWHPYHQGRUVKDYHFRQWURORYHUWKHXVHRIWKHVHGHYLFHVVLQFHWKH\ZLOOQHYHU DSSHDURQH[SDQVLRQERDUGV • 'HYLFHVWKDWQHYHUGHDOZLWKRUFRQWDLQRUDFFHVVDQ\GDWDWKDWUHSUHVHQWVSHUPDQHQW RUUHVLGXDOV\VWHPRUDSSOLFDWLRQVWDWH HJKXPDQLQWHUIDFHDQGYLGHRDXGLR GHYLFHV7KHVHGHYLFHVRQO\WRXFKGDWDWKDWLVDWHPSRUDU\UHSUHVHQWDWLRQ HJ SL[HOV RISHUPDQHQWRUUHVLGXDOV\VWHPRUDSSOLFDWLRQVWDWH7KHUHIRUHWKH\DUHQRW SURQHWRFUHDWHV\VWHPLQWHJULW\SUREOHPVLQWKHHYHQWRIXQGHWHFWHGIDLOXUH 3.7.3. Address Parity Errors $GHYLFHLVVDLGWRKDYHGHWHFWHGDQDGGUHVVSDULW\HUURULIWKHGHYLFH¶VSDULW\FKHFNLQJ ORJLFGHWHFWVDQHUURULQDVLQJOHDGGUHVVF\FOHRUHLWKHUDGGUHVVSKDVHRIDGXDODGGUHVV F\FOH • ,IDGHYLFHGHWHFWVDQDGGUHVVSDULW\HUURULQVRPHFDVHVLWZLOODVVHUWSERR# UHIHU WR6HFWLRQ DQGLQDOOFDVHVLWZLOOVHWWKH'HWHFWHG3DULW\(UURUELW 6WDWXV UHJLVWHUELW UHIHUWR6HFWLRQ ,IDGHYLFHGHWHFWVDQDGGUHVVSDULW\HUURUDQGWKHGHYLFH¶V3DULW\(UURU5HVSRQVHELW &RPPDQGUHJLVWHUELW LVVHWDQGWKHGHYLFH¶VDGGUHVVGHFRGHULQGLFDWHVWKDWWKH GHYLFHLVVHOHFWHGWKHGHYLFHPXVWGRRQHRIWKHIROORZLQJ • FODLPWKHWUDQVDFWLRQDQGWHUPLQDWHLWDVLIWKHUHZDVQRDGGUHVVFRPPDQGHUURU • FODLPWKHWUDQVDFWLRQDQGWHUPLQDWHZLWK7DUJHW$ERUW • QRWFODLPWKHWUDQVDFWLRQDQGOHWLWWHUPLQDWHZLWK0DVWHU$ERUW $QHUURULQWKHDGGUHVVSKDVHRIDWUDQVDFWLRQPD\DIIHFWDQ\RUDOORIWKHDGGUHVVELWV WKHFRPPDQGELWVDQGWKHSDULW\ELW6LQFHGHYLFHVPRQLWRULQJWKHWUDQVDFWLRQFDQQRW GHWHUPLQHZKLFKELWVDUHDFWXDOO\LQHUURUXVHRIDWUDQVDFWLRQWKDWFRQWDLQHGDQDGGUHVV SDULW\HUURUPD\FDXVHXQSUHGLFWDEOHUHVXOWV 7KHWDUJHWLVQRWDOORZHGWRFODLPDWUDQVDFWLRQDQGWHUPLQDWHLWZLWK5HWU\VROHO\ EHFDXVHRIDQDGGUHVVSDULW\HUURURUDZULWH GDWDSDULW\HUURU+RZHYHUWKHRFFXUUHQFH RIDSDULW\HUURUGRHVQRWSUHYHQWWKHWDUJHWIURPWHUPLQDWLQJWKHWUDQVDFWLRQZLWK5HWU\ IRURWKHUUHDVRQV 3.7.4. Error Reporting 3&,SURYLGHVIRUWKHGHWHFWLRQDQGVLJQDOLQJRIWZRNLQGVRIHUURUV GDWDSDULW\HUURUVDQG RWKHUV\VWHPHUURUV,WLVLQWHQGHGWKDWGDWDSDULW\HUURUVEHUHSRUWHGXSWKURXJKWKH DFFHVVDQGGHYLFHGULYHUFKDLQZKHQHYHUSRVVLEOH7KLVHUURUUHSRUWLQJFKDLQIURPWDUJHW 21 Targets check data parity only on write transactions. 95 Revision 2.2 WREXVPDVWHUWRGHYLFHGULYHUWRGHYLFHPDQDJHUWRRSHUDWLQJV\VWHPLVLQWHQGHGWRDOORZ HUURUUHFRYHU\RSWLRQVWREHLPSOHPHQWHGDWDQ\OHYHO6LQFHLWLVJHQHUDOO\QRWSRVVLEOH WRDVVRFLDWHV\VWHPHUURUVZLWKDVSHFLILFDFFHVVFKDLQWKH\DUHUHSRUWHGYLDDVHSDUDWH V\VWHPHUURUVLJQDO UHIHUWR6HFWLRQ 3&,GHYLFHVDUHHQDEOHGWRUHSRUWGDWDSDULW\HUURUVE\WKH3DULW\(UURU5HVSRQVHELW ELW RIWKH&RPPDQGUHJLVWHU 7KLVELWLVUHTXLUHGLQDOOGHYLFHVH[FHSWWKRVHQRWUHTXLUHG WRFKHFNSDULW\ UHIHUWR6HFWLRQ ,IWKH3DULW\(UURU5HVSRQVHELWLVVHWGHYLFHV PXVWUHVSRQGWRDQGUHSRUWGDWDSDULW\HUURUVIRUDOOEXVRSHUDWLRQV H[FHSWWKRVHWKDW RFFXUGXULQJD6SHFLDO&\FOHWUDQVDFWLRQ ,IWKH3DULW\(UURU5HVSRQVHELWLVFOHDUHGDQ DJHQWWKDWGHWHFWVDGDWDSDULW\HUURUPXVWLJQRUHWKHHUURUDQGFRPSOHWHWKHWUDQVDFWLRQ DVWKRXJKSDULW\ZDVFRUUHFW,QWKLVFDVHQRVSHFLDOKDQGOLQJRIWKHGDWDSDULW\HUURUFDQ RFFXU 7ZRVLJQDOV SLQV DQGWZRVWDWXVELWVDUHXVHGLQWKH3&,HUURUUHSRUWLQJVFKHPH(DFK ZLOOEHGLVFXVVHGVHSDUDWHO\ 3.7.4.1. Data Parity Error Signaling on PERR# PERR# LVXVHGIRUVLJQDOLQJGDWDSDULW\HUURUVRQDOOWUDQVDFWLRQVH[FHSW6SHFLDO&\FOH WUDQVDFWLRQV'DWDSDULW\HUURUVWKDWRFFXUGXULQJD6SHFLDO&\FOHWUDQVDFWLRQDUH UHSRUWHGRQSERR#DVGHVFULEHGLQ6HFWLRQPERR#LVUHTXLUHGIRUDOOGHYLFHV H[FHSWWKRVHQRWUHTXLUHGWRFKHFNSDULW\ UHIHUWR6HFWLRQ ,ISDULW\HUURUUHVSRQVHLVHQDEOHG ELWRIWKH&RPPDQGUHJLVWHULVVHW DQGDGDWDSDULW\ HUURULVGHWHFWHGE\DPDVWHUGXULQJDUHDGWUDQVDFWLRQWKHPDVWHUPXVWDVVHUWPERR# ,ISDULW\HUURUUHVSRQVHLVHQDEOHG ELWRIWKH&RPPDQGUHJLVWHULVVHW DQGDGDWDSDULW\ HUURULVGHWHFWHGE\DWDUJHWGXULQJDZULWHWUDQVDFWLRQWKHWDUJHWPXVWDVVHUWPERR# 0DVWHUVXVHWKLVLQIRUPDWLRQWRUHFRUGWKHRFFXUUHQFHRIWKHHUURUIRUWKHGHYLFHGULYHU PERR#LVERWKDQLQSXWDQGRXWSXWVLJQDOIRUDPDVWHUDQGRQO\DQRXWSXWVLJQDOIRUD WDUJHW $GHYLFHDVVHUWLQJPERR#PXVWGRVRWZRFORFNVDIWHUWKHFRPSOHWLRQRIDGDWDSKDVH LQZKLFKDQHUURURFFXUVDVVKRZQLQ)LJXUH,IWKHUHFHLYLQJDJHQWLQVHUWVZDLW VWDWHVWKDWDJHQWLVSHUPLWWHGWRDVVHUWPERR#DVVRRQDVDGDWDSDULW\HUURULVGHWHFWHG ,QRWKHUZRUGVLIWKHWDUJHWLVLQVHUWLQJZDLWVWDWHVGXULQJDZULWHWUDQVDFWLRQWKHWDUJHWLV SHUPLWWHGWRDVVHUWPERR#WZRFORFNVDIWHUGDWDLVYDOLG IRDY#DVVHUWHG EXWEHIRUH WKHGDWDWUDQVIHUV TRDY#LVDOVRDVVHUWHG ,IWKHPDVWHULVLQVHUWLQJZDLWVWDWHVGXULQJ DUHDGWUDQVDFWLRQWKHPDVWHULVSHUPLWWHGWRDVVHUWPERR#WZRFORFNVDIWHUGDWDLV YDOLG TRDY#LVDVVHUWHG EXWEHIRUHWKHGDWDWUDQVIHUV IRDY#LVDOVRDVVHUWHG 2QFH PERR#LVDVVHUWHGLWPXVWUHPDLQDVVHUWHGXQWLOWZRFORFNVIROORZLQJWKHFRPSOHWLRQ RIWKHGDWDSKDVH IRDY#DQGTRDY#ERWKDVVHUWHG 1RWHWKDWWKHPDVWHULVUHTXLUHG WRSURYLGHYDOLGE\WHHQDEOHVGXULQJHYHU\FORFNF\FOHRIHYHU\GDWDSKDVHIRUERWKUHDG DQGZULWHWUDQVDFWLRQVLQGHSHQGHQWRIIRDY# ,IDPDVWHUDVVHUWVPERR#SULRUWRFRPSOHWLRQRIDUHDGGDWDSKDVHLWPXVWHYHQWXDOO\ DVVHUWIRDY#WRFRPSOHWHWKHGDWDSKDVH,IDWDUJHWDVVHUWVPERR#SULRUWR FRPSOHWLRQRIDZULWHGDWDSKDVHLWPXVWHYHQWXDOO\DVVHUWTRDY#WRFRPSOHWHWKHGDWD SKDVH7KHWDUJHWFDQQRWWHUPLQDWHWKHGDWDSKDVHE\VLJQDOLQJ5HWU\'LVFRQQHFW ZLWKRXWGDWDRU7DUJHW$ERUWDIWHUVLJQDOLQJPERR#$PDVWHUNQRZVDGDWDSDULW\ HUURURFFXUUHGRQDZULWHGDWDSKDVHDQ\WLPHPERR#LVDVVHUWHGZKLFKPD\EHSULRUWR WKHFRPSOHWLRQRIWKHGDWDSKDVH%XWWKHPDVWHURQO\NQRZVWKHGDWDSKDVHZDVHUURU IUHHWZRFORFNVIROORZLQJWKHFRPSOHWLRQRIWKHGDWDSKDVH 96 Revision 2.2 %RWKPDVWHUVDQGWDUJHWVDUHSHUPLWWHGHLWKHUWRFRQWLQXHDEXUVWWUDQVDFWLRQRUVWRSLW DIWHUGHWHFWLQJDGDWDSDULW\HUURU'XULQJDEXUVWWUDQVDFWLRQLQZKLFKPXOWLSOHGDWD SKDVHVDUHFRPSOHWHGZLWKRXWLQWHUYHQLQJZDLWVWDWHVPERR#ZLOOEHTXDOLILHGRQ PXOWLSOHFRQVHFXWLYHFORFNVDFFRUGLQJO\DQGPD\EHDVVHUWHGLQDQ\RUDOORIWKHP PERR#LVDVXVWDLQHGWULVWDWHVLJQDOWKDWLVEXVHGWRDOO3&,DJHQWV,WPXVWEHDFWLYHO\ GULYHQWRWKHFRUUHFWYDOXHRQHDFKTXDOLILHGFORFNHGJHE\WKHDJHQWUHFHLYLQJWKHGDWD $WWKHHQGRIHDFKEXVRSHUDWLRQPERR#PXVWDFWLYHO\EHGULYHQKLJKIRURQHFORFN SHULRGE\WKHDJHQWUHFHLYLQJGDWDVWDUWLQJWZRFORFNVDIWHUWKHADEXVWXUQDURXQGF\FOH HJFORFNLQ)LJXUH 7KHPERR#WXUQDURXQGF\FOHRFFXUVRQHFORFNODWHU FORFNLQ)LJXUH PERR#FDQQRWEHGULYHQ HQDEOHG IRUWKHFXUUHQWWUDQVDFWLRQ XQWLODWOHDVWWKUHHFORFNVDIWHUWKHDGGUHVVSKDVH ZKLFKLVRQHFORFNORQJIRUVLQJOH DGGUHVVF\FOHVDQGWZRFORFNVORQJIRUGXDODGGUHVVF\FOHV 1RWHWKDWWKHWDUJHWRID ZULWHWUDQVDFWLRQPXVWQRWGULYHDQ\VLJQDOXQWLODIWHUDVVHUWLQJDEVSEL# IRU H[DPSOHIRUGHFRGHVSHHG³VORZ´WKHWDUJHWPXVWQRWGULYHPERR#XQWLOIRXUFORFNV DIWHUWKHDGGUHVVSKDVH 3.7.4.2. Other Error Signaling on SERR# ,IDGHYLFHLVHQDEOHGWRDVVHUWSERR# LH6(55(QDEOHELWRIWKH&RPPDQG UHJLVWHULVVHW DQGWKHGHYLFH¶V3DULW\(UURU5HVSRQVHELW &RPPDQGUHJLVWHUELW LV VHWWKHGHYLFHPXVWDVVHUWSERR#LIDQ\RIWKHIROORZLQJFRQGLWLRQVRFFXUV • 7KHGHYLFH¶VSDULW\FKHFNLQJORJLFGHWHFWVDQHUURULQDVLQJOHDGGUHVVF\FOHRUHLWKHU DGGUHVVSKDVHRIDGXDODGGUHVVF\FOH UHJDUGOHVVRIWKHLQWHQGHGWDUJHW • 7KHGHYLFHPRQLWRUV6SHFLDO&\FOHWUDQVDFWLRQVDQGWKH6SHFLDO&\FOHVELW &RPPDQGUHJLVWHUELW LVVHWDQGWKHGHYLFH¶VSDULW\FKHFNLQJORJLFGHWHFWVDGDWD SDULW\HUURU • 7KHGHYLFHLVWKHPDVWHURID0HVVDJH6LJQDOHG,QWHUUXSWDQGWKHWUDQVDFWLRQ FRPSHWHVZLWK0DVWHU$ERUWRU7DUJHW$ERUWRUWKHWDUJHWDVVHUWVPERR# UHIHUWR 6HFWLRQ SERR#PD\RSWLRQDOO\EHXVHGWRUHSRUWRWKHULQWHUQDOHUURUVWKDWPLJKWMHRSDUGL]H V\VWHPRUGDWDLQWHJULW\,WPXVWEHDVVXPHGKRZHYHUWKDWVLJQDOLQJRQSERR#ZLOO JHQHUDWHDFULWLFDOV\VWHPLQWHUUXSW HJ10,RU0DFKLQH&KHFN DQGLVWKHUHIRUHIDWDO &RQVHTXHQWO\FDUHVKRXOGEHWDNHQLQXVLQJSERR#WRUHSRUWQRQSDULW\RUV\VWHP HUURUV SERR#LVUHTXLUHGIRUDOOGHYLFHVH[FHSWWKRVHQRWUHTXLUHGWRFKHFNSDULW\ UHIHUWR 6HFWLRQ SERR#LVDQRSHQGUDLQVLJQDOWKDWLVZLUH25HGZLWKDOORWKHU3&, DJHQWVDQGWKHUHIRUHPD\EHVLPXOWDQHRXVO\GULYHQE\PXOWLSOHDJHQWV$QDJHQW UHSRUWLQJDQHUURURQSERR#GULYHVLWDFWLYHIRUDVLQJOHFORFNDQGWKHQWULVWDWHVLW 5HIHUWR6HFWLRQIRUPRUHGHWDLOV 6LQFHRSHQGUDLQVLJQDOLQJFDQQRWJXDUDQWHH VWDEOHVLJQDOVRQHYHU\ULVLQJFORFNHGJHRQFHSERR#LVDVVHUWHGLWVORJLFDOYDOXHPXVW EHDVVXPHGWREHLQGHWHUPLQDWHXQWLOWKHVLJQDOLVVDPSOHGLQWKHGHDVVHUWHGVWDWHRQDW OHDVWWZRVXFFHVVLYHULVLQJFORFNHGJHV 97 Revision 2.2 3.7.4.3. Master Data Parity Error Status Bit 7KH0DVWHU'DWD3DULW\(UURUELW 6WDWXVUHJLVWHUELW PXVWEHVHWE\WKHPDVWHULILWV 3DULW\(UURU5HVSRQVHELW &RPPDQGUHJLVWHUELW LVVHWDQGHLWKHURIWKHIROORZLQJWZR FRQGLWLRQVRFFXUV • 7KHPDVWHUGHWHFWVDGDWDSDULW\HUURURQDUHDGWUDQVDFWLRQ • 7KHPDVWHUVDPSOHVPERR#DVVHUWHGRQDZULWHWUDQVDFWLRQ ,IWKH3DULW\(UURU5HVSRQVHELWLVFOHDUHGWKHPDVWHUPXVWQRWVHWWKH0DVWHU'DWD3DULW\ (UURUELWHYHQLIWKHPDVWHUGHWHFWVDSDULW\HUURURUWKHWDUJHWDVVHUWVPERR# 7DUJHWVQHYHUVHWWKH0DVWHU'DWD3DULW\(UURUELW 3.7.4.4. Detected Parity Error Status Bit 7KH'HWHFWHG3DULW\(UURUELW 6WDWXVUHJLVWHUELW PXVWEHVHWE\DGHYLFHZKHQHYHU LWVSDULW\FKHFNLQJORJLFGHWHFWVDSDULW\HUURUUHJDUGOHVVRIWKHVWDWHWKH3DULW\(UURU 5HVSRQVHELW ELWRIWKHFRPPDQGUHJLVWHU 7KH'HWHFWHG3DULW\(UURUELWLVUHTXLUHG WREHVHWE\WKHGHYLFHZKHQDQ\RIWKHIROORZLQJFRQGLWLRQVRFFXUV • 7KHGHYLFH¶VSDULW\FKHFNLQJORJLFGHWHFWVDQHUURULQDVLQJOHDGGUHVVF\FOHRUHLWKHU DGGUHVVSKDVHRIDGXDODGGUHVVF\FOH • 7KHGHYLFH¶VSDULW\FKHFNLQJORJLFGHWHFWVDGDWDSDULW\HUURUDQGWKHGHYLFHLVWKH WDUJHWRIDZULWHWUDQVDFWLRQ • 7KHGHYLFH¶VSDULW\FKHFNLQJORJLFGHWHFWVDGDWDSDULW\HUURUDQGWKHGHYLFHLVWKH PDVWHURIDUHDGWUDQVDFWLRQ 3.7.5. Delayed Transactions and Data Parity Errors 7KLVVHFWLRQSUHVHQWVDGGLWLRQDOUHTXLUHPHQWVIRUHUURUKDQGOLQJWKDWDUHXQLTXHWRD WDUJHWFRPSOHWLQJDWUDQVDFWLRQDVD'HOD\HG7UDQVDFWLRQ'DWDSDULW\HUURUUHTXLUHPHQWV SUHVHQWHGLQSUHYLRXVVHFWLRQVDSSO\WR'HOD\HG7UDQVDFWLRQVDVZHOO $GDWDSDULW\HUURUFDQRFFXUGXULQJDQ\RIWKHWKUHHVWHSVRID'HOD\HG7UDQVDFWLRQWKH PDVWHUUHTXHVWVWHSWKHWDUJHWFRPSOHWLRQVWHSRUWKHPDVWHUFRPSOHWLRQVWHS UHIHUWR 6HFWLRQ 7KHUHTXLUHPHQWVIRUKDQGOLQJWKHHUURUYDU\GHSHQGLQJXSRQWKH VWHSLQZKLFKWKHHUURURFFXUUHG(UURUVWKDWRFFXUGXULQJWKHWDUJHWFRPSOHWLRQSKDVH DUHVSHFLILFWRWKHWDUJHWGHYLFHDQGDUHKDQGOHGLQDGHYLFHVSHFLILFPDQQHU QRW Ã VSHFLILHGKHUH 'HYLFHEHKDYLRUIRUHUURUVWKDWRFFXUGXULQJWKHPDVWHUUHTXHVWVWHSRU PDVWHUFRPSOHWLRQVWHSGHSHQGXSRQZKHWKHUWKH'HOD\HG7UDQVDFWLRQLVDUHDG RUD ZULWH WUDQVDFWLRQ 22 If the actual target resides on a PCI bus segment generated by a PCI-to-PCI bridge, the target completion phase occurs across a PCI bus segment. In this case, the PCI-to-PCI Bridge Architecture Specification details additional requirements for error handling during the target completion phase of a read Delayed Transaction. 23 Memory Read, Memory Read Line, Memory Read Multiple, Configuration Read, I/O Read, or Interrupt Acknowledge. 24 Configuration Write or I/O Write, but never Memory Write and Invalidate or Memory Write. 98 Revision 2.2 'XULQJDUHDGWUDQVDFWLRQWKHWDUJHWGHYLFHVRXUFHVWKHGDWDDQGSDULW\LVQRWYDOLGXQWLO TRDY#LVDVVHUWHG7KHUHIRUHDGDWDSDULW\HUURUFDQQRWRFFXUGXULQJWKHPDVWHU UHTXHVWSKDVHRUDQ\VXEVHTXHQWUHDWWHPSWE\WKHPDVWHUWKDWLVWHUPLQDWHGZLWK5HWU\ 'XULQJWKHPDVWHUFRPSOHWLRQVWHSRIUHDGWUDQVDFWLRQWKHWDUJHWVRXUFHVGDWDDQGGDWD SDULW\DQGWKHPDVWHUFKHFNVSDULW\DQGFRQGLWLRQDOO\DVVHUWVPERR#DVIRUDQ\RWKHU QRWGHOD\HG WUDQVDFWLRQ UHIHUWR6HFWLRQ 'XULQJDZULWHWUDQVDFWLRQWKHPDVWHUVRXUFHVWKHZULWHGDWDDQGPXVWDVVHUWIRDY# ZKHQWKHGDWDLVYDOLGLQGHSHQGHQWRIWKHUHVSRQVHE\WKHWDUJHWGHYLFH UHIHUWR 6HFWLRQ 7KHUHIRUHDGDWDSDULW\HUURUPD\RFFXUERWKLQWKHPDVWHUUHTXHVWDQG WKHPDVWHUFRPSOHWLRQVWHSV,QDGGLWLRQLWLVSRVVLEOHIRUDGDWDSDULW\HUURUWREHHLWKHU FRQVWDQW LHWKHVDPHHUURURFFXUVHDFKWLPHWKHPDVWHUUHSHDWVWKHWUDQVDFWLRQ RU WUDQVLHQW LHWKHHUURURFFXUVRQVRPHEXWQRWRWKHUUHSHWLWLRQVRIWKHWUDQVDFWLRQE\WKH PDVWHU 7KHGDWDSDULW\HUURUUHSRUWLQJPHWKRGVIRUZULWH'HOD\HG7UDQVDFWLRQV GHVFULEHGLQWKHIROORZLQJVHFWLRQVDUHGHVLJQHGWRGHWHFWDQGUHSRUWERWKFRQVWDQWDQG WUDQVLHQWGDWDSDULW\HUURUVDQGWRSUHYHQWWUDQVLHQWGDWDSDULW\HUURUVIURPFDXVLQJD GHDGORFNFRQGLWLRQ ,IDWDUJHWGHWHFWVDGDWDSDULW\HUURURQDZULWHWUDQVDFWLRQWKDWZRXOGRWKHUZLVHKDYH EHHQKDQGOHGDVD'HOD\HG7UDQVDFWLRQWKHWDUJHWLVUHTXLUHGWRGRWKHIROORZLQJ &RPSOHWHWKHGDWDSKDVHLQZKLFKWKHHUURURFFXUUHGE\DVVHUWLQJTRDY#,IWKH PDVWHULVDWWHPSWLQJDEXUVWWKHWDUJHWPXVWDOVRDVVHUWSTOP# 5HSRUWWKHHUURUDVGHVFULEHGLQ6HFWLRQ 'LVFDUGWKHWUDQVDFWLRQ1R'HOD\HG:ULWH5HTXHVWLVHQTXHXHGDQGQR'HOD\HG :ULWH&RPSOHWLRQLVUHWLUHG ,IWKHWDUJHWGHWHFWVDGDWDSDULW\HUURUGXULQJWKHLQLWLDOUHTXHVWSKDVHRID'HOD\HG:ULWH 7UDQVDFWLRQQR'HOD\HG5HTXHVWLVHYHUHQTXHXHG ,IWKHWDUJHWHQTXHXHVDJRRG'HOD\HG:ULWH5HTXHVWDQGODWHUGHWHFWVDGDWDSDULW\HUURU GXULQJDVXEVHTXHQWUHSHWLWLRQRIWKHWUDQVDFWLRQWKHWDUJHWGRHVQRWUHWLUHDQ\'HOD\HG :ULWH&RPSOHWLRQVHYHQLIWKHWUDQVDFWLRQDSSHDUVWRPDWFKRQHSUHYLRXVO\HQTXHXHG ,WLVLPSRVVLEOHWRGHWHUPLQHZKHWKHUWKHWUDQVDFWLRQUHDOO\PDWFKHVDSUHYLRXVO\ HQTXHXHGRQHVLQFHDQHUURULVSUHVHQW 7KLVFDXVHVWKHWDUJHWWRKDYHDQRUSKDQ 'HOD\HG:ULWH&RPSOHWLRQEHFDXVHWKHPDVWHUEHOLHYHVWKHWUDQVDFWLRQKDVFRPSOHWHG EXWWKHWDUJHWLVZDLWLQJIRUWKHRULJLQDO HUURUIUHH UHTXHVWWREHUHSHDWHG7KHRUSKDQ FRPSOHWLRQLVGLVFDUGHGZKHQWKHWDUJHW¶V'LVFDUG7LPHUH[SLUHV UHIHUWR 6HFWLRQ :KLOHZDLWLQJIRUWKHGLVFDUGWLPHUWRH[SLUHVRPHWDUJHW LPSOHPHQWDWLRQVZLOOQRWEHDEOHWRDFFHSWDQHZ'HOD\HG7UDQVDFWLRQVLQFHWKHWDUJHWLV QRWUHTXLUHGWRKDQGOHPXOWLSOH'HOD\HG7UDQVDFWLRQVDWWKHVDPHWLPH+RZHYHUVLQFH WKLVFRQGLWLRQLVWHPSRUDU\DGHDGORFNFDQQRWRFFXU:KLOHLQWKLVFRQGLWLRQWKHGHYLFH LVUHTXLUHGWRFRPSOHWHWUDQVDFWLRQVWKDWXVHPHPRU\ZULWH FRPPDQGV UHIHUWR 6HFWLRQ 3.7.6. Error Recovery 7KHDFWLRQWKDWDV\VWHPWDNHVDVDUHVXOWRIWKHDVVHUWLRQRISERR#LVQRWFRQWUROOHGE\ WKLVVSHFLILFDWLRQ7KHDVVHUWLRQRISERR#E\DGHYLFHLQGLFDWHVWKDWWKHGHYLFHKDV HQFRXQWHUHGDQHUURUIURPZKLFKLWFDQQRWUHFRYHU7KHV\VWHPPD\RSWLRQDOO\VWRS 25 This includes two commands: Memory Write and Invalidate and Memory Write. 99 Revision 2.2 H[HFXWLRQDWWKDWSRLQWLILWGRHVQRWKDYHHQRXJKLQIRUPDWLRQWRFRQWDLQDQGUHFRYHU IURPWKHHUURUFRQGLWLRQ 7KH3&,SDULW\HUURUVLJQDOVDQGVWDWXVELWVDUHGHVLJQHGWRSURYLGHDPHWKRGIRUGDWD SDULW\HUURUVWREHGHWHFWHGDQGUHSRUWHG LIHQDEOHG 2QDZULWHWUDQVDFWLRQWKHWDUJHW DOZD\VVLJQDOVGDWDSDULW\HUURUVEDFNWRWKHPDVWHURQPERR#2QDUHDGWUDQVDFWLRQ WKHPDVWHUDVVHUWVPERR#WRLQGLFDWHWRWKHV\VWHPWKDWDQHUURUZDVGHWHFWHG,QERWK FDVHVWKHPDVWHUKDVWKHDELOLW\WRSURPRWHWKHHUURUWRLWVGHYLFHGULYHURUWKHRSHUDWLQJ V\VWHPRUWRDWWHPSWUHFRYHU\XVLQJKDUGZDUHDQGRUVRIWZDUHPHWKRGV 7KHV\VWHPGHVLJQHUPD\HOHFWWRUHSRUWDOOGDWDSDULW\HUURUVWRWKHRSHUDWLQJV\VWHPE\ DVVHUWLQJSERR#ZKHQWKHFHQWUDOUHVRXUFHVDPSOHVPERR#DVVHUWHG1RWHWKDWZKHQ WKLVRSWLRQLVXVHGUHFRYHU\LVQRWSRVVLEOH Implementation Note: Recovery from Data Parity Errors ,WLVRSWLRQDOIRU3&,PDVWHUVDQGV\VWHPVWRDWWHPSWUHFRYHU\IURPGDWDSDULW\HUURUV 7KHIROORZLQJDUHH[DPSOHVRIKRZGDWDSDULW\HUURUUHFRYHU\PD\EHDWWHPSWHG 5HFRYHU\E\WKHPDVWHU,IWKHPDVWHURIWKHWUDQVDFWLRQLQZKLFKWKHSDULW\HUURU ZDVGHWHFWHGKDVVXIILFLHQWNQRZOHGJHWKDWWKHWUDQVDFWLRQFDQEHUHSHDWHGZLWKRXW VLGHHIIHFWVWKHQWKHPDVWHUPD\VLPSO\UHSHDWWKHWUDQVDFWLRQ,IQRHUURURFFXUVRQ WKHUHSHDWHGWUDQVDFWLRQUHSRUWLQJRIWKHSDULW\HUURU WRWKHRSHUDWLQJV\VWHPRU GHYLFHGULYHU LVXQQHFHVVDU\,IWKHHUURUSHUVLVWVRULIWKHPDVWHULVQRWFDSDEOHRI UHFRYHULQJIURPWKHGDWDSDULW\HUURUWKHPDVWHUPXVWLQIRUPLWVGHYLFHGULYHU7KLV FDQEHDFFRPSOLVKHGE\JHQHUDWLQJDQLQWHUUXSWPRGLI\LQJDVWDWXVUHJLVWHUVHWWLQJD IODJRURWKHUVXLWDEOHPHDQV:KHQWKHPDVWHUGRHVQRWKDYHDGHYLFHGULYHULWPD\ UHSRUWWKHHUURUE\DVVHUWLQJSERR# 1RWH 0RVWGHYLFHVKDYHVLGHHIIHFWVZKHQDFFHVVHGDQGWKHUHIRUHLWLVXQOLNHO\ WKDWUHFRYHU\LVSRVVLEOHE\VLPSO\UHSHDWLQJDWUDQVDFWLRQ+RZHYHULQDSSOLFDWLRQV ZKHUHWKHPDVWHUXQGHUVWDQGVWKHEHKDYLRURIWKHWDUJHWLWPD\EHSRVVLEOHWRUHFRYHU IURPWKHHUURUE\UHSHWLWLRQRIWKHWUDQVDFWLRQ 5HFRYHU\E\WKHGHYLFHGULYHU7KHGHYLFHGULYHUPD\VXSSRUWDQHUURUUHFRYHU\ PHFKDQLVPVXFKWKDWWKHGDWDSDULW\HUURUFDQEHFRUUHFWHG,QWKLVFDVHWKH UHSRUWLQJRIWKHHUURUWRWKHRSHUDWLQJV\VWHPLVQRWUHTXLUHG)RUH[DPSOHWKHGULYHU PD\EHDEOHWRUHSHDWDQHQWLUHEORFNWUDQVIHUE\UHORDGLQJWKHPDVWHUZLWKWKH WUDQVIHUVL]HVRXUFHDQGGHVWLQDWLRQDGGUHVVHVRIWKHGDWD,IQRHUURURFFXUVRQWKH UHSHDWHGEORFNWUDQVIHUWKHQWKHHUURULVQRWUHSRUWHG:KHQWKHGHYLFHGULYHUGRHV QRWKDYHVXIILFLHQWNQRZOHGJHWKDWWKHDFFHVVFDQEHUHSHDWHGZLWKRXWVLGHHIIHFWVLW PXVWUHSRUWWKHHUURUWRWKHRSHUDWLQJV\VWHP 5HFRYHU\ RUHUURUKDQGOLQJ E\WKHRSHUDWLQJV\VWHP2QFHWKHGDWDSDULW\HUURU KDVEHHQUHSRUWHGWRWKHRSHUDWLQJV\VWHPQRRWKHUDJHQWRUPHFKDQLVPFDQUHFRYHU IURPWKHHUURU+RZWKHRSHUDWLQJV\VWHPKDQGOHVWKHGDWDSDULW\HUURULVRSHUDWLQJ V\VWHPGHSHQGHQW 3.8. 64-Bit Bus Extension 3&,VXSSRUWVDKLJKELWEXVUHIHUUHGWRDVWKHELWH[WHQVLRQWRWKHVWDQGDUGORZ ELWEXV7KHELWEXVSURYLGHVDGGLWLRQDOGDWDEDQGZLGWKIRUDJHQWVWKDWUHTXLUHLW 7KHKLJKELWH[WHQVLRQIRUELWGHYLFHVQHHGVDQDGGLWLRQDO VLJQDOSLQV REQ64#ACK64#AD[63::32]C/BE[7::4]#DQGPAR647KHVHVLJQDOVDUHGHILQHG LQ6HFWLRQ ELWDJHQWVZRUNXQPRGLILHGZLWKELWDJHQWVELWDJHQWVPXVW 100 Revision 2.2 GHIDXOWWRELWPRGHXQOHVVDELWWUDQVDFWLRQLVQHJRWLDWHG+HQFHELW WUDQVDFWLRQVDUHWRWDOO\WUDQVSDUHQWWRELWGHYLFHV1RWH ELWDGGUHVVLQJGRHVQRW UHTXLUHDELWGDWDSDWK UHIHUWR6HFWLRQ ELWWUDQVDFWLRQVRQ3&,DUHG\QDPLFDOO\QHJRWLDWHG RQFHSHUWUDQVDFWLRQ EHWZHHQWKH PDVWHUDQGWDUJHW7KLVLVDFFRPSOLVKHGE\WKHPDVWHUDVVHUWLQJREQ64#DQGWKHWDUJHW UHVSRQGLQJWRWKHDVVHUWHGREQ64#E\DVVHUWLQJACK64#2QFHDELWWUDQVDFWLRQLV QHJRWLDWHGLWKROGVXQWLOWKHHQGRIWKHWUDQVDFWLRQACK64# PXVWQRWEHDVVHUWHG XQOHVVREQ64#ZDVVDPSOHGDVVHUWHGGXULQJWKHVDPHWUDQVDFWLRQREQ64#DQG ACK64#DUHH[WHUQDOO\SXOOHGXSWRHQVXUHSURSHUEHKDYLRUZKHQPL[LQJDQGELW DJHQWV5HIHUWR6HFWLRQIRUWKHRSHUDWLRQRIELWGHYLFHVLQDELWV\VWHP 'XULQJDELWWUDQVDFWLRQDOO3&,SURWRFRODQGWLPLQJUHPDLQLQWDFW2QO\PHPRU\ WUDQVDFWLRQVPDNHVHQVHZKHQGRLQJELWGDWDWUDQVIHUV,QWHUUXSW$FNQRZOHGJHDQG 6SHFLDO&\FOH FRPPDQGVDUHEDVLFDOO\ELWWUDQVDFWLRQVDQGPXVWQRWEHXVHGZLWKD REQ64#7KHEDQGZLGWKUHTXLUHPHQWVIRU,2DQGFRQILJXUDWLRQWUDQVDFWLRQVFDQQRW MXVWLI\WKHDGGHGFRPSOH[LW\DQGWKHUHIRUHRQO\PHPRU\WUDQVDFWLRQVVXSSRUWELW GDWDWUDQVIHUV $OOPHPRU\WUDQVDFWLRQVDQGRWKHUEXVWUDQVIHUVRSHUDWHWKHVDPHZKHWKHUGDWDLV WUDQVIHUUHGRUELWVDWDWLPHELWDJHQWVFDQWUDQVIHUIURPRQHWRHLJKWE\WHVSHU GDWDSKDVHDQGDOOFRPELQDWLRQVRIE\WHHQDEOHVDUHOHJDO$VLQELWPRGHE\WH HQDEOHVPD\FKDQJHRQHYHU\GDWDSKDVH7KHPDVWHULQLWLDWLQJDELWGDWDWUDQVDFWLRQ PXVWXVHDGRXEOH':25' 4XDGZRUGRUE\WH UHIHUHQFHGDGGUHVV AD[2]PXVWEH GXULQJWKHDGGUHVVSKDVH :KHQDPDVWHUUHTXHVWVDELWGDWDWUDQVIHU REQ64#DVVHUWHG WKHWDUJHWKDVWKUHH EDVLFUHVSRQVHVDQGHDFKLVGLVFXVVHGLQWKHIROORZLQJSDUDJUDSKV &RPSOHWHWKHWUDQVDFWLRQXVLQJWKHELWGDWDSDWK ACK64#DVVHUWHG &RPSOHWHWKHWUDQVDFWLRQXVLQJWKHELWGDWDSDWK ACK64#GHDVVHUWHG &RPSOHWHDVLQJOHELWGDWDWUDQVIHU ACK64#GHDVVHUWHGSTOP#DVVHUWHG 7KHILUVWRSWLRQLVZKHUHWKHWDUJHWUHVSRQGVWRWKHPDVWHUWKDWLWFDQFRPSOHWHWKH WUDQVDFWLRQXVLQJWKHELWGDWDSDWKE\DVVHUWLQJACK64#7KHWUDQVDFWLRQWKHQ WUDQVIHUVGDWDXVLQJWKHHQWLUHGDWDEXVDQGXSWRE\WHVFDQEHWUDQVIHUUHGLQHDFKGDWD SKDVH,WEHKDYHVOLNHDELWEXVH[FHSWPRUHGDWDWUDQVIHUVHDFKGDWDSKDVH 7KHVHFRQGRSWLRQRFFXUVZKHQWKHWDUJHWFDQQRWSHUIRUPDELWGDWDWUDQVIHUWRWKH DGGUHVVHGORFDWLRQ LWPD\EHFDSDEOHLQDGLIIHUHQWVSDFH ,QWKLVFDVHWKHPDVWHULV UHTXLUHGWRFRPSOHWHWKHWUDQVDFWLRQDFWLQJDVDELWPDVWHUDQGQRWDVDELWPDVWHU 7KHPDVWHUKDVWZRRSWLRQVZKHQWKHWDUJHWGRHVQRWUHVSRQGE\DVVHUWLQJACK64# ZKHQWKHPDVWHUDVVHUWVREQ64#WRVWDUWDZULWHWUDQVDFWLRQ7KHILUVWRSWLRQLVWKDWWKH PDVWHUTXLWVGULYLQJWKHXSSHUADOLQHVDQGRQO\SURYLGHVGDWDRQWKHORZHUADOLQHV 7KHVHFRQGRSWLRQLVWKHPDVWHUFRQWLQXHVSUHVHQWLQJWKHIXOOELWVRIGDWDRQHDFKHYHQ ':25'DGGUHVVERXQGDU\2QWKHRGG':25'DGGUHVVERXQGDU\WKHPDVWHUGULYHV WKHVDPHGDWDRQERWKWKHXSSHUDQGORZHUSRUWLRQVRIWKHEXV 7KHWKLUGDQGODVWRSWLRQLVZKHUHWKHWDUJHWLVRQO\ELWVDQGFDQQRWVXVWDLQDEXUVWIRU WKLVWUDQVDFWLRQ,QWKLVFDVHWKHWDUJHWGRHVQRWUHVSRQGE\DVVHUWLQJACK64#EXW WHUPLQDWHVWKHWUDQVDFWLRQE\DVVHUWLQJSTOP#,IWKLVLVD5HWU\WHUPLQDWLRQ STOP# DVVHUWHGDQGTRDY#GHDVVHUWHG WKHPDVWHUUHSHDWVWKHVDPHUHTXHVW DVDELWUHTXHVW 26 Since no agent claims the access by asserting DEVSEL# and, therefore, cannot respond with ACK64#. 101 Revision 2.2 DWDODWHUWLPH,IWKLVLVD'LVFRQQHFWWHUPLQDWLRQ STOP#DQGTRDY#DVVHUWHG WKH PDVWHUPXVWUHSHDWWKHUHTXHVWDVDELWPDVWHUVLQFHWKHVWDUWLQJDGGUHVVLVQRZRQD RGG':25'ERXQGDU\,IWKHWDUJHWFRPSOHWHGWKHGDWDWUDQVIHUVXFKWKDWWKHQH[W VWDUWLQJDGGUHVVZRXOGEHDHYHQ':25'ERXQGDU\WKHPDVWHUZRXOGEHIUHHWRUHTXHVW DELWGDWDWUDQVIHU&DXWLRQVKRXOGEHXVHGZKHQDELWUHTXHVWLVSUHVHQWHGDQGWKH WDUJHWWUDQVIHUVDVLQJOH':25'DVDELWDJHQW,IWKHPDVWHUZHUHWRFRQWLQXHWKH EXUVWZLWKWKHVDPHDGGUHVVEXWZLWKWKHORZHUE\WHHQDEOHVGHDVVHUWHGQRIRUZDUG SURJUHVVZRXOGEHPDGHEHFDXVHWKHWDUJHWZRXOGQRWWUDQVIHUDQ\QHZGDWDVLQFHWKH ORZHUE\WHHQDEOHVDUHGHDVVHUWHG7KHUHIRUHWKHWUDQVDFWLRQZRXOGFRQWLQXHWREH UHSHDWHGIRUHYHUZLWKRXWPDNLQJSURJUHVV ELWSDULW\ PAR64) ZRUNVWKHVDPHIRUWKHKLJKELWVRIWKHELWEXVDVWKHELW SDULW\ PAR)ZRUNVIRUWKHORZELWEXVPAR64FRYHUVAD[63::32]DQG C/BE[7::4]#DQGKDVWKHVDPHWLPLQJDQGIXQFWLRQDVPAR. 7KHQXPEHURIVRQ AD[63::32]C/BE[7::4]#DQGPAR64HTXDODQHYHQQXPEHU PAR64PXVWEHYDOLG RQHFORFNDIWHUHDFKDGGUHVVSKDVHRQDQ\WUDQVDFWLRQLQZKLFKREQ64#LVDVVHUWHG $OOELWWDUJHWVTXDOLI\DGGUHVVSDULW\FKHFNLQJRIPAR64ZLWKREQ64#. ELW GHYLFHVDUHQRWDZDUHRIDFWLYLW\RQELWEXVH[WHQVLRQVLJQDOV )RUELWGHYLFHVFKHFNLQJSDULW\RQGDWDSKDVHVPAR64PXVWEHDGGLWLRQDOO\TXDOLILHG ZLWKWKHVXFFHVVIXOQHJRWLDWLRQRIDELWWUDQVDFWLRQPAR64LVUHTXLUHGIRUELW GDWDSKDVHV LWLVQRWRSWLRQDOIRUDELWDJHQW ,QWKHIROORZLQJWZRILJXUHVDELWPDVWHUUHTXHVWVDELWWUDQVDFWLRQXWLOL]LQJD VLQJOHDGGUHVVSKDVH7KLVLVWKHVDPHW\SHRIDGGUHVVLQJSHUIRUPHGE\DELWPDVWHU LQWKHORZ*%DGGUHVVVSDFH 7KHILUVW)LJXUHLVDUHDGZKHUHWKHWDUJHW UHVSRQGVZLWKACK64# DVVHUWHGDQGWKHGDWDLVWUDQVIHUUHGLQELWGDWDSKDVHV7KH VHFRQG)LJXUHLVDZULWHZKHUHWKHWDUJHWGRHVQRWUHVSRQGZLWKACK64# DVVHUWHG DQGWKHGDWDLVWUDQVIHUUHGLQELWGDWDSKDVHV WKHWUDQVDFWLRQGHIDXOWHGWRELW PRGH 7KHVHWZRILJXUHVDUHLGHQWLFDOWR)LJXUHVDQGH[FHSWWKDWELWVLJQDOV KDYHEHHQDGGHGDQGLQ)LJXUHGDWDLVWUDQVIHUUHGELWVSHUGDWDSKDVH7KHVDPH WUDQVDFWLRQVDUHXVHGWRLOOXVWUDWHWKDWWKHVDPHSURWRFROZRUNVIRUERWKDQGELW WUDQVDFWLRQV AD[63::32]DQGC/BE[7::4]#DUHUHVHUYHGGXULQJWKHDGGUHVVSKDVHRIDVLQJOHDGGUHVV SKDVHWUDQVDFWLRQAD[63::32]FRQWDLQGDWDDQGC/BE[7::4]#FRQWDLQE\WHHQDEOHVIRU WKHXSSHUIRXUE\WHVGXULQJELWGDWDSKDVHVRIWKHVHWUDQVDFWLRQVAD[63::32]DQG C/BE[7::4]# DUHGHILQHGGXULQJWKHWZRDGGUHVVSKDVHVRIDGXDODGGUHVVF\FOH '$& DQGGXULQJWKHELWGDWDSKDVHV UHIHUWR6HFWLRQ IRUGHWDLOV )LJXUHLOOXVWUDWHVDPDVWHUUHTXHVWLQJDELWUHDGWUDQVDFWLRQE\DVVHUWLQJ REQ64# ZKLFKH[DFWO\PLUURUVFRAME# 7KHWDUJHWDFNQRZOHGJHVWKHUHTXHVWE\ DVVHUWLQJACK64# ZKLFKPLUURUVDEVSEL# 'DWDSKDVHVDUHVWUHWFKHGE\ERWK DJHQWVGHDVVHUWLQJWKHLUUHDG\OLQHVELWVLJQDOVUHTXLUHWKHVDPHWXUQDURXQGF\FOHVDV WKHLUELWFRXQWHUSDUWV 102 Revision 2.2 CLK 1 2 3 4 5 6 7 8 9 FRAME# REQ64# AD[31::00] ADDRESS DATA-1 DATA-3 DATA-5 AD[63::32] DATA-2 DATA-4 DATA-6 C/BE[3::0]# BUS CMD BE#'s C/BE[7::4]# BE#'s IRDY# WAIT WAIT WAIT TRDY# WAIT DATA TRANSFER DATA TRANSFER DATA DATA TRANSFER DEVSEL# ACK64# ADDRESS DATA DATA DATA PHASE PHASE PHASE PHASE )LJXUH ELW5HDG5HTXHVW:LWKELW7UDQVIHU )LJXUHLOOXVWUDWHVDPDVWHUUHTXHVWLQJDELWWUDQVIHU7KHELWWDUJHWLVQRW FRQQHFWHGWRREQ64#RUACK64#DQGACK64#LVNHSWLQWKHGHDVVHUWHGVWDWHZLWKD SXOOXS$VIDUDVWKHWDUJHWLVFRQFHUQHGWKLVLVDELWWUDQVIHU7KHPDVWHUFRQYHUWV WKHWUDQVDFWLRQIURPWRELWV6LQFHWKHPDVWHULVFRQYHUWLQJELWGDWDWUDQVIHUV LQWRELWGDWDWUDQVIHUVWKHUHPD\RUPD\QRWEHDQ\E\WHHQDEOHVDVVHUWHGGXULQJDQ\ GDWDSKDVHRIWKHWUDQVDFWLRQ7KHUHIRUHDOOELWWDUJHWVPXVWEHDEOHWRKDQGOHGDWD SKDVHVZLWKQRE\WHHQDEOHVDVVHUWHG7KHWDUJHWVKRXOGQRWXVH'LVFRQQHFWRU5HWU\ EHFDXVHDGDWDSKDVHLVHQFRXQWHUHGWKDWKDVQRDVVHUWHGE\WHHQDEOHVEXWVKRXOGDVVHUW TRDY#DQGFRPSOHWHWKHGDWDSKDVH+RZHYHUWKHWDUJHWLVDOORZHGWRXVH5HWU\RU 'LVFRQQHFWEHFDXVHLWLVLQWHUQDOO\EXV\DQGXQDEOHWRFRPSOHWHWKHGDWDWUDQVIHU LQGHSHQGHQWRIZKLFKE\WHHQDEOHVDUHDVVHUWHG7KHPDVWHUUHVHQGVWKHGDWDWKDW RULJLQDOO\DSSHDUHGRQAD[63::32]GXULQJWKHILUVWGDWDSKDVHRQAD[31::00]GXULQJWKH VHFRQGGDWDSKDVH7KHVXEVHTXHQWGDWDSKDVHVDSSHDUH[DFWO\OLNHWKHELWWUDQVIHU ,IWKHELWVLJQDOVDUHUHPRYHG)LJXUHDQG)LJXUHDUHLGHQWLFDO 103 Revision 2.2 CLK 1 2 3 4 5 6 7 8 9 FRAME# REQ64# AD[31::00] ADDRESS DATA-1 DATA-2 DATA-3 AD[63::32] DATA-2 C/BE[3::0]# BUS CMD BE#'s-1 BE#'s-2 BE#'s-3 C/BE[7::4]# BE#'s-2 IRDY# WAIT WAIT TRDY# WAIT WAIT DATA TRANSFER DATA DATA TRANSFER DATA TRANSFER DEVSEL# ACK64# ADDRESS DATA DATA DATA PHASE PHASE PHASE PHASE )LJXUH ELW:ULWH5HTXHVW:LWKELW7UDQVIHU 8VLQJDVLQJOHGDWDSKDVHZLWKELWWUDQVIHUVPD\QRWEHYHU\HIIHFWLYH6LQFHWKH PDVWHUGRHVQRWNQRZKRZWKHWUDQVDFWLRQZLOOEHUHVROYHGZLWKACK64#XQWLO DEVSEL#LVUHWXUQHGLWGRHVQRWNQRZWKHFORFNRQZKLFKWRGHDVVHUWFRAME# IRUD ELWVLQJOHGDWDSKDVHWUDQVDFWLRQIRDY#PXVWUHPDLQGHDVVHUWHGXQWLOFRAME# VLJQDOLQJLVUHVROYHG7KHVLQJOHELWGDWDSKDVHPD\KDYHWREHVSOLWLQWRWZRELW GDWDSKDVHVZKHQWKHWDUJHWLVRQO\ELWVZKLFKPHDQVDWZRSKDVHELWWUDQVIHULVDW OHDVWDVIDVWDVDRQHSKDVHELWWUDQVIHU 3.8.1. Determining Bus Width During System Initialization REQ64#LVXVHGGXULQJUHVHWWRGLVWLQJXLVKEHWZHHQSDUWVWKDWDUHFRQQHFWHGWRDELW GDWDSDWKDQGWKRVHWKDWDUHQRW3&,H[SDQVLRQVORWVWKDWVXSSRUWRQO\DELWGDWDSDWK PXVWQRWFRQQHFWREQ64#WRDQ\RWKHUVORWVRUGHYLFHV 7KHREQ64#DQGACK64# SLQVDUHORFDWHGLQWKHELWSRUWLRQRIWKHFRQQHFWRU (DFKELWRQO\FRQQHFWRUPXVW KDYHDQLQGLYLGXDOSXOOXSUHVLVWRUIRUREQ64#RQWKHPRWKHUERDUGACK64#LVEXVHG WRDOOELWGHYLFHVDQGVORWVRQWKHPRWKHUERDUGDQGSXOOHGXSZLWKDVLQJOHUHVLVWRU ORFDWHGRQWKHPRWKHUERDUGACK64#IRUHDFKELWVORWVPXVWEHGHDVVHUWHGHLWKHUE\ FRQQHFWLQJLWWRWKHACK64#VLJQDOFRQQHFWLQJWKHELWGHYLFHVDQGVORWVRUE\ LQGLYLGXDOSXOOXSUHVLVWRUVRQWKHPRWKHUERDUG 104 Revision 2.2 REQ64#LVEXVHGWRDOOGHYLFHVRQWKHPRWKHUERDUG LQFOXGLQJ3&,FRQQHFWRUVORWV WKDW VXSSRUWDELWGDWDSDWK7KLVVLJQDOKDVDVLQJOHSXOOXSUHVLVWRURQWKHPRWKHUERDUG 7KHFHQWUDOUHVRXUFHPXVWGULYHREQ64#ORZ DVVHUWHG GXULQJWKHWLPHWKDWRST#LV DVVHUWHGDFFRUGLQJWRWKHWLPLQJVSHFLILFDWLRQLQ6HFWLRQ'HYLFHVWKDWVHH REQ64#DVVHUWHGRQWKHULVLQJHGJHRIRST#DUHFRQQHFWHGWRWKHELWGDWDSDWKDQG WKRVHWKDWGRQRWVHHREQ64#DVVHUWHGDUHQRWFRQQHFWHG7KLVLQIRUPDWLRQPD\EHXVHG E\WKHFRPSRQHQWWRVWDELOL]HIORDWLQJLQSXWVGXULQJUXQWLPHDVGHVFULEHGEHORZ REQ64#KDVVHWXSDQGKROGWLPHUHTXLUHPHQWVUHODWLYHWRWKHGHDVVHUWLQJ KLJKJRLQJ HGJHRIRST#:KLOHRST#LVDVVHUWHGREQ64#LVDV\QFKURQRXVZLWKUHVSHFWWR CLK :KHQDELWGDWDSDWKLVSURYLGHGAD[63::32]C/BE[7::4]#DQGPAR64UHTXLUH HLWKHUSXOOXSUHVLVWRUVRULQSXWNHHSHUVEHFDXVHWKH\DUHQRWXVHGLQWUDQVDFWLRQVZLWK ELWGHYLFHVDQGPD\WKHUHIRUHIORDWWRWKHWKUHVKROGOHYHOFDXVLQJRVFLOODWLRQRUKLJK SRZHUGUDLQWKURXJKWKHLQSXWEXIIHU7KLVSXOOXSRUNHHSHUIXQFWLRQPXVWEHSDUWRIWKH PRWKHUERDUGFHQWUDOUHVRXUFHQRWWKHH[SDQVLRQERDUG UHIHUWR6HFWLRQ WRHQVXUH DFRQVLVWHQWVROXWLRQDQGDYRLGSXOOXSFXUUHQWRYHUORDG :KHQWKHELWGDWDSDWKLVSUHVHQWRQDGHYLFHEXWQRWFRQQHFWHG DVLQDELWFDUG SOXJJHGLQWRDELW3&,VORW WKDW3&,GHYLFHPXVWLQVXUHWKDWLWVLQSXWVGRQRW RVFLOODWHDQGWKDWWKHUHLVQRWDVLJQLILFDQWSRZHUGUDLQWKURXJKWKHLQSXWEXIIHUERWK EHIRUHDQGDIWHUWKHULVLQJHGJHRIRST#7KLVFDQEHGRQHLQDYDULHW\RIZD\V HJ ELDVLQJWKHLQSXWEXIIHURUDFWLYHO\GULYLQJWKHRXWSXWVFRQWLQXRXVO\ VLQFHWKH\DUHQRW FRQQHFWHGWRDQ\WKLQJ ([WHUQDOUHVLVWRUVRQDQH[SDQVLRQERDUGRUDQ\VROXWLRQWKDW YLRODWHVWKHLQSXWOHDNDJHVSHFLILFDWLRQDUHSURKLELWHG :KLOHRST#LVDVVHUWHGWKH3&,GHYLFHIORDWVLWVRXWSXWEXIIHUVIRUWKHH[WHQGHGGDWD SDWKAD[63::32]C/BE[7::4]#DQGPAR64XQOHVVWKHGHYLFHLQSXWEXIIHUVFDQQRW WROHUDWHWKHLULQSXWVIORDWLQJIRUDQLQGHILQLWHO\ORQJRST#SHULRG,IWKHGHYLFHLQSXW EXIIHUVFDQQRWWROHUDWHWKLVWKHFRPSRQHQWPXVWFRQWUROLWVLQSXWVZKLOHRST#LV DVVHUWHG,QWKLVFDVHWKHGHYLFHLVSHUPLWWHGWRHQDEOHLWVRXWSXWVFRQWLQXRXVO\ZKLOH RST#LVDVVHUWHGDQGREQ64#LVGHDVVHUWHG LQGLFDWLQJDELWEXV EXWPXVWGULYH WKHPWRDORJLFORZOHYHO LQFDVHWKHEXVFRQQHFWLRQLVDFWXDOO\ELWVZLGHDQG REQ64#KDVQRW\HWVHWWOHGWRLWVILQDOYDOXH $IWHUWKHGHYLFHGHWHFWVWKDWREQ64#LV GHDVVHUWHGDWWKHULVLQJHGJHRIRST#WKHGHYLFHPXVWFRQWLQXHWRFRQWUROWKHH[WHQGHG EXVWRSURWHFWWKHGHYLFHLQSXWEXIIHUV 3.9. 64-bit Addressing 3&,VXSSRUWVPHPRU\DGGUHVVLQJEH\RQGWKHORZ*%E\GHILQLQJDPHFKDQLVPWR WUDQVIHUDELWDGGUHVVIURPWKHPDVWHURIWKHWUDQVDFWLRQWRWKHWDUJHW1RDGGLWLRQDO SLQVDUHUHTXLUHGIRUDRUELWGHYLFHWRVXSSRUWELWDGGUHVVLQJ'HYLFHVWKDW VXSSRUWRQO\ELWDGGUHVVHVDUHPDSSHGLQWRWKHORZ*%RIWKHDGGUHVVVSDFHDQG ZRUNWUDQVSDUHQWO\ZLWKGHYLFHVWKDWJHQHUDWHELWDGGUHVVHV2QO\PHPRU\ WUDQVDFWLRQVVXSSRUWELWDGGUHVVLQJ 7KHZLGWKRIWKHDGGUHVVLVLQGHSHQGHQWRIWKHZLGWKRIWKHEXVRQHLWKHUWKHPDVWHURU WKHWDUJHW,IERWKWKHPDVWHUDQGWDUJHWVXSSRUWDELWEXVWKHHQWLUHELWDGGUHVV FRXOGWKHRUHWLFDOO\EHSURYLGHGLQDVLQJOHFORFN+RZHYHUWKHPDVWHULVUHTXLUHGLQDOO FDVHVWRXVHWZRFORFNVWRFRPPXQLFDWHDELWDGGUHVVVLQFHWKHZLGWKRIWKHWDUJHW¶V EXVLVQRWNQRZQGXULQJWKHDGGUHVVSKDVH 7KHVWDQGDUG3&,EXVWUDQVDFWLRQVXSSRUWVDELWDGGUHVV6LQJOH$GGUHVV&\FOH 6$& ZKHUHWKHDGGUHVVLVYDOLGIRUDVLQJOHFORFNZKHQFRAME#LVILUVWVDPSOHGDVVHUWHG 105 Revision 2.2 7RVXSSRUWWKHWUDQVIHURIDELWDGGUHVVD'XDO$GGUHVV&\FOH '$& EXVFRPPDQGLV XVHGDFFRPSDQLHGZLWKRQHRIWKHGHILQHGEXVFRPPDQGVWRLQGLFDWHWKHGHVLUHGGDWD SKDVHDFWLYLW\IRUWKHWUDQVDFWLRQ7KH'$&XVHVWZRFORFNVWRWUDQVIHUWKHHQWLUHELW DGGUHVVRQWKHAD[31::00]VLJQDOV0DVWHUVWKDWXVHDGGUHVVVWHSSLQJFDQQRWLPSOHPHQW ELWDGGUHVVLQJVLQFHWKHUHLVQRPHFKDQLVPIRUGHOD\LQJRUH[WHQGLQJWKHVHFRQG DGGUHVVSKDVH:KHQDELWPDVWHUXVHV'$& ELWDGGUHVVLQJ LWPXVWSURYLGHWKH XSSHUELWVRIWKHDGGUHVVRQAD[63::32]DQGWKHDVVRFLDWHGFRPPDQGIRUWKH WUDQVDFWLRQRQC/BE[7::4]#GXULQJERWKDGGUHVVSKDVHVRIWKHWUDQVDFWLRQWRDOORZELW WDUJHWVDGGLWLRQDOWLPHWRGHFRGHWKHWUDQVDFWLRQ )LJXUHLOOXVWUDWHVD'$&IRUDUHDGWUDQVDFWLRQ,QDEDVLF6$&UHDGWUDQVDFWLRQD WXUQDURXQGF\FOHIROORZVWKHDGGUHVVSKDVH,QWKH'$&UHDGWUDQVDFWLRQDQDGGLWLRQDO DGGUHVVSKDVHLVLQVHUWHGEHWZHHQWKHVWDQGDUGDGGUHVVSKDVHDQGWKHWXUQDURXQGF\FOH ,QWKHILJXUHWKHILUVWDQGVHFRQGDGGUHVVSKDVHVRFFXURQFORFNDQGUHVSHFWLYHO\ 7KHWXUQDURXQGF\FOHEHWZHHQWKHDGGUHVVDQGGDWDSKDVHVLVGHOD\HGXQWLOFORFN 1RWH FRAME#PXVWEHDVVHUWHGGXULQJERWKDGGUHVVSKDVHVHYHQIRUQRQEXUVWLQJ VLQJOHGDWDSKDVHWUDQVDFWLRQV7RDGKHUHWRWKHFRAME#IRDY#UHODWLRQVKLS FRAME#FDQQRWEHGHDVVHUWHGXQWLOIRDY#LVDVVHUWHGIRDY#FDQQRWEHDVVHUWHGXQWLO WKHPDVWHUSURYLGHVGDWDRQDZULWHWUDQVDFWLRQRULVUHDG\WRDFFHSWGDWDRQDUHDG WUDQVDFWLRQ $'$&LVGHFRGHGE\DSRWHQWLDOWDUJHWZKHQDLVSUHVHQWRQC/BE[3::0]#GXULQJ WKHILUVWDGGUHVVSKDVH,IDELWWDUJHWVXSSRUWVELWDGGUHVVLQJLWVWRUHVWKHDGGUHVV WKDWZDVWUDQVIHUUHGRQAD[31::00]DQGSUHSDUHVWRODWFKWKHUHVWRIWKHDGGUHVVRQWKH QH[WFORFN7KHDFWXDOFRPPDQGXVHGIRUWKHWUDQVDFWLRQLVWUDQVIHUUHGGXULQJWKHVHFRQG DGGUHVVSKDVHRQC/BE[3::0]#$ELWWDUJHWLVSHUPLWWHGWRODWFKWKHHQWLUHDGGUHVVRQ WKHILUVWDGGUHVVSKDVH2QFHWKHHQWLUHDGGUHVVLVWUDQVIHUUHGDQGWKHFRPPDQGLV ODWFKHGWKHWDUJHWGHWHUPLQHVLIDEVSEL#LVWREHDVVHUWHG7KHWDUJHWFDQGRIDVW PHGLXPRUVORZGHFRGHRQHFORFNGHOD\HGIURP6$&GHFRGLQJ$VXEWUDFWLYHGHFRGH DJHQWDGMXVWVWRWKHGHOD\HGGHYLFHVHOHFWLRQWLPLQJHLWKHUE\LJQRULQJWKHHQWLUH WUDQVDFWLRQRUE\GHOD\LQJLWVRZQDVVHUWLRQRIDEVSEL#,IWKHEULGJHGRHVVXSSRUW ELWDGGUHVVLQJLWZLOOGHOD\DVVHUWLQJLWVDEVSEL# LILWGRHVVXSSRUWELW DGGUHVVLQJ 7KHPDVWHU RID'$& ZLOODOVRGHOD\WHUPLQDWLQJWKHWUDQVDFWLRQZLWK 0DVWHU$ERUWIRURQHDGGLWLRQDOFORFN 7KHH[HFXWLRQRIDQH[FOXVLYHDFFHVVLVWKHVDPHIRUHLWKHU'$&RU6$&,QHLWKHUFDVH LOCK#LVGHDVVHUWHGGXULQJWKHDGGUHVVSKDVH ILUVWFORFN DQGDVVHUWHGGXULQJWKH VHFRQGFORFN ZKLFKLVWKHILUVWGDWDSKDVHIRU6$&DQGWKHVHFRQGDGGUHVVSKDVHIRUD '$& $JHQWVPRQLWRULQJWKHWUDQVDFWLRQXQGHUVWDQGWKHORFNUHVRXUFHLVEXV\DQGWKH WDUJHWNQRZVWKHPDVWHULVUHTXHVWLQJDORFNHGRSHUDWLRQ)RUDWDUJHWWKDWVXSSRUWVERWK 6$&DQG'$&WKHORJLFWKDWKDQGOHVLOCK#LVWKHVDPH 106 Revision 2.2 CLK 1 2 3 4 5 6 7 8 FRAME# AD[31::00] LO - ADDR HI - ADDR DATA-1 DATA-3(2) C/BE[3::0]# DUAL AD BUS CMD BE#[3::0] AD[63::32] HI ADDR DATA-2 DATA-4 Optional C/BE[7::4]# BUS CMD BE#[7::4] IRDY# WAIT WAIT TRDY# WAIT DATA TRANSFER DATA TRANSFER DATA DEVSEL# F M S ADDRESS DATA DATA PHASE PHASE PHASE )LJXUH%LW'XDO$GGUHVV5HDG&\FOH 7KHPDVWHUFRPPXQLFDWHVDELWDGGUHVVDVVKRZQLQ)LJXUHUHJDUGOHVVRI ZKHWKHUWKHWDUJHWVXSSRUWVDELWRUELWEXV7KHVKDGHGDUHDLQ)LJXUHLVXVHG RQO\ZKHQWKHPDVWHURIWKHDFFHVVVXSSRUWVDELWEXV7KHPDVWHUGULYHVWKHHQWLUH DGGUHVV ORZHUDGGUHVVRQAD[31::00]DQGXSSHUDGGUHVVRQAD[63::32] DQGERWK FRPPDQGV '$&RQC/BE[3::0]#DQGWKHDFWXDOEXVFRPPDQGRQ C/BE[7::4]# DOOGXULQJWKHLQLWLDODGGUHVVSKDVH2QWKHVHFRQGDGGUHVVSKDVHWKH PDVWHUGULYHVWKHXSSHUDGGUHVVRQAD[31::00] DQGAD[63::32] ZKLOHWKHEXV FRPPDQGLVGULYHQRQC/BE[3::0]# DQGC/BE[7::4]# 7KHPDVWHUFDQQRWGHWHUPLQHLI WKHWDUJHWVXSSRUWVDELWGDWDSDWKXQWLOWKHHQWLUHDGGUHVVKDVEHHQWUDQVIHUUHGDQG WKHUHIRUHPXVWDVVXPHDELWWDUJHWZKLOHSURYLGLQJWKHDGGUHVV ,IERWKWKHPDVWHUDQGWDUJHWVXSSRUWDELWEXVWKHQELWDGGUHVVLQJFDXVHVQR DGGLWLRQDOODWHQF\ZKHQGHWHUPLQLQJDEVSEL#VLQFH DOOUHTXLUHGLQIRUPDWLRQIRU FRPPDQGGHFRGLQJLVVXSSOLHGLQWKHILUVWDGGUHVVSKDVH)RUH[DPSOHDELWWDUJHW WKDWQRUPDOO\SHUIRUPVDPHGLXPDEVSEL#GHFRGHIRUD6$&FDQGHFRGHWKHIXOO ELWDGGUHVVIURPDELWPDVWHUGXULQJWKHILUVWDGGUHVVSKDVHRIWKH'$&DQG SHUIRUPDIDVWDEVSEL#GHFRGH,IHLWKHUWKHPDVWHURUWKHWDUJHWGRHVQRWVXSSRUWD ELWGDWDSDWKRQHDGGLWLRQDOFORFNRIGHOD\ZLOOEHHQFRXQWHUHG $PDVWHUWKDWVXSSRUWVELWDGGUHVVLQJPXVWJHQHUDWHD6$&LQVWHDGRID'$&ZKHQ WKHXSSHUELWVRIWKHDGGUHVVDUH]HUR7KLVDOORZVPDVWHUVWKDWJHQHUDWHELW DGGUHVVHVWRFRPPXQLFDWHZLWKELWDGGUHVVDEOHWDUJHWVYLD6$&7KHW\SHRI DGGUHVVLQJ 6$&RU'$& GHSHQGVRQZKHWKHUWKHDGGUHVVLVLQWKHORZ*%DGGUHVV UDQJHRUQRWDQGQRWE\WKHWDUJHW VEXVZLGWKFDSDELOLWLHV 107 Revision 2.2 $ELWDGGUHVVDEOHWDUJHWPXVWDFWOLNHDELWDGGUHVVDEOHWDUJHW UHVSRQGWR6$& WUDQVDFWLRQV ZKHQPDSSHGLQWKHORZHU*%DGGUHVVVSDFH,IDELWPDVWHUPXVW DFFHVVWDUJHWVPDSSHGDERYHWKHORZHU*%DGGUHVVVSDFHWKDWPDVWHUPXVWVXSSRUW ELWDGGUHVVLQJXVLQJ'$& 3.10. Special Design Considerations 7KLVVHFWLRQGHVFULEHVWRSLFVWKDWPHULWDGGLWLRQDOFRPPHQWVRUDUHUHODWHGWR3&,EXWDUH QRWSDUWRIWKHEDVLFRSHUDWLRQRIWKHEXV 7KLUGSDUW\'0$ 7KLUGSDUW\'0$LVQRWVXSSRUWHGRQ3&,VLQFHVLGHEDQGVLJQDOVDUHQRWVXSSRUWHG RQWKHFRQQHFWRU7KHLQWHQWRI3&,LVWRJURXSWRJHWKHUWKH'0$IXQFWLRQLQ GHYLFHVWKDWQHHGPDVWHUFDSDELOLW\DQGWKHUHIRUHWKLUGSDUW\'0$LVQRWVXSSRUWHG 6QRRSLQJ3&,WUDQVDFWLRQV $Q\WUDQVDFWLRQJHQHUDWHGE\DQDJHQWRQ3&,PD\EHVQRRSHGE\DQ\RWKHUDJHQWRQ WKHVDPHEXVVHJPHQW6QRRSLQJGRHVQRWZRUNZKHQWKHDJHQWVDUHRQGLIIHUHQW3&, EXVVHJPHQWV,QJHQHUDOWKHVQRRSLQJDJHQWFDQQRWGULYHDQ\3&,VLJQDOEXWPXVW EHDEOHWRRSHUDWHLQGHSHQGHQWO\RIWKHEHKDYLRURIWKHFXUUHQWPDVWHURUWDUJHW ,OOHJDOSURWRFROEHKDYLRU $GHYLFHLVQRWHQFRXUDJHGDFWLYHO\WRFKHFNIRUSURWRFROHUURUV+RZHYHULID GHYLFHGRHVGHWHFWLOOHJDOSURWRFROHYHQWV DVDFRQVHTXHQFHRIWKHZD\LWLV GHVLJQHG WKHGHVLJQPD\UHWXUQLWVVWDWHPDFKLQHV WDUJHWRUPDVWHU WRDQ,GOHVWDWH DVTXLFNO\DVSRVVLEOHLQDFFRUGDQFHZLWKWKHSURWRFROUXOHVIRUGHDVVHUWLRQDQGWUL VWDWHRIVLJQDOVGULYHQE\WKHGHYLFH 9*$SDOHWWHVQRRS 7KHDFWLYH9*$GHYLFHDOZD\VUHVSRQGVWRDUHDGRIWKHFRORUSDOHWWHZKLOHHLWKHU WKH9*$RUJUDSKLFVDJHQWZLOOEHSURJUDPPHGWRUHVSRQGWRZULWHWUDQVDFWLRQVWR WKHFRORUSDOHWWHDQGWKHRWKHUZLOOVQRRSLW:KHQDGHYLFH 9*$RUJUDSKLFV KDV EHHQSURJUDPPHGWRVQRRSDZULWHWRWKH9*$SDOHWWHUHJLVWHULWPXVWRQO\ODWFKWKH GDWDZKHQIRDY#DQGTRDY#DUHERWKDVVHUWHGRQWKHVDPHULVLQJFORFNHGJHRU ZKHQD0DVWHU$ERUWRFFXUV7KHILUVWRSWLRQLVWKHQRUPDOFDVHZKHQD9*$DQG JUDSKLFVGHYLFHDUHSUHVHQWLQWKHVDPHV\VWHP7KHVHFRQGRSWLRQRFFXUVZKHQQR GHYLFHRQWKHFXUUHQWEXVKDVEHHQSURJUDPPHGWRSRVLWLYHO\UHVSRQGWRWKLVUDQJHRI DGGUHVVHV7KLVRFFXUVZKHQWKH3&,VHJPHQWLVJLYHQWKHILUVWULJKWRIUHIXVDODQGD VXEWUDFWLYHGHFRGHGHYLFHLVQRWSUHVHQW,QVRPHV\VWHPVWKLVDFFHVVLVVWLOO IRUZDUGHGWRDQRWKHUEXVZKLFKZLOOFRPSOHWHWKHDFFHVV,QWKLVW\SHRIV\VWHPD GHYLFHWKDWKDVEHHQSURJUDPPHGWRVQRRSZULWHVWRWKHSDOHWWHVKRXOGODWFKWKHGDWD ZKHQWKHWUDQVDFWLRQLVWHUPLQDWHGZLWK0DVWHU$ERUW 7KHSDOHWWHVQRRSELWZLOOEHVHWE\WKHV\VWHP%,26ZKHQLWGHWHFWVERWKD9*$ GHYLFHDQGDJUDSKLFVDFFHOHUDWRUGHYLFHWKDWDUHRQVHSDUDWHERDUGVRQWKHVDPHEXV RURQWKHVDPHSDWKEXWRQGLIIHUHQWEXVHV • :KHQERWKDJHQWVDUH3&,GHYLFHVWKDWUHVLGHRQWKHVDPHEXVHLWKHUGHYLFHFDQ EHVHWWRVQRRSDQGWKHRWKHUZLOOEHVHWWRSRVLWLYHO\UHVSRQG • :KHQERWKDUH3&,GHYLFHVWKDWUHVLGHRQGLIIHUHQWEXVHVEXWRQWKHVDPHSDWK WKHILUVWGHYLFHIRXQGLQWKHSDWKZLOOEHVHWWRVQRRSDQGWKHRWKHUGHYLFHPD\EH VHWWRSRVLWLYHO\UHVSRQGRUVQRRSWKHDFFHVV (LWKHURSWLRQZRUNVLQD3&$7 FRPSDWLEOHV\VWHPVLQFHDZULWHWUDQVDFWLRQRQD3&,VHJPHQWRWKHUWKDQWKH SULPDU\3&,EXVWKDWLVWHUPLQDWHGZLWK0DVWHU$ERUWLVVLPSO\WHUPLQDWHGDQG WKHGDWDLVGURSSHGDQG0DVWHU$ERUWVDUHQRWUHSRUWHG 108 Revision 2.2 • :KHQRQHGHYLFHLVRQ3&,DQGWKHRWKHULVEHKLQGWKHVXEWUDFWLYHGHFRGH GHYLFHVXFKDVDQ,6$(,6$RU0LFUR&KDQQHOEULGJHWKH3&,GHYLFHZLOOEH VHWWRVQRRSDQGWKHVXEWUDFWLYHGHFRGHGHYLFHZLOODXWRPDWLFDOO\FODLPWKH DFFHVVDQGIRUZDUGLW 7KHRQO\FDVHZKHUHSDOHWWHVQRRSLQJZRXOGEHWXUQHGRIILVZKHQRQO\D9*$ GHYLFH QRJUDSKLFVGHYLFH LVSUHVHQWLQWKHV\VWHPRUERWKWKH9*$DQGJUDSKLFV GHYLFHVDUHLQWHJUDWHGWRJHWKHULQWRVLQJOHGHYLFHRUFDUG 1RWH 3DOHWWHVQRRSLQJGRHVQRWZRUNZKHQWKH9*$DQGJUDSKLFVGHYLFHVUHVLGHRQ GLIIHUHQWEXVHVWKDWDUHQRWRQWKHVDPHSDWK7KLVRFFXUVEHFDXVHRQO\DVLQJOH DJHQWSHUEXVVHJPHQWPD\FODLPWKHDFFHVV7KHUHIRUHRQHDJHQWZLOOQHYHUVHHWKH DFFHVVEHFDXVHLWVEULGJHFDQQRWIRUZDUGWKHDFFHVV:KHQDGHYLFHKDVEHHQ SURJUDPPHGWRVQRRSWKHDFFHVVLWFDQQRWLQVHUWZDLWVWDWHVRUGHOD\WKHDFFHVVLQ DQ\ZD\DQGWKHUHIRUHPXVWEHDEOHWRODWFKDQGSURFHVVWKHGDWDZLWKRXWGHOD\ )RUPRUHLQIRUPDWLRQRQ3&,VXSSRUWRI9*$GHYLFHVUHIHUWR$SSHQGL[$RIWKH 3&,WR3&,%ULGJH$UFKLWHFWXUH6SHFLILFDWLRQ 3RWHQWLDOGHDGORFNVFHQDULRZKHQXVLQJ3&,WR3&,EULGJHV :DUQLQJ $SRWHQWLDOGHDGORFNZLOORFFXUZKHQDOOWKHIROORZLQJFRQGLWLRQVH[LVWLQ DV\VWHP :KHQ3&,WR3&,EULGJHVDUHVXSSRUWHGLQWKHV\VWHP 1RWH ,ID3&, H[SDQVLRQERDUGFRQQHFWRULVVXSSRUWHG3&,WR3&,EULGJHVPD\EHSUHVHQWLQ WKHV\VWHP $UHDGDFFHVVRULJLQDWHGE\WKHKRVWEULGJHWDUJHWVD3&,GHYLFHWKDWUHTXLUHV PRUHWKDQDVLQJOHGDWDSKDVHWRFRPSOHWH (LJKWE\WHWUDQVIHURUDQDFFHVVWKDW FURVVHVD':25'ERXQGDU\ZKHQWDUJHWLQJDQDJHQWWKDWUHVSRQGVWRWKLV UHTXHVWDVELWDJHQWRUUHVLGHVRQDELW3&,VHJPHQW The deadlock occurs when the following steps are met: $EXUVWUHDGLVLQLWLDWHGRQ3&,E\WKHKRVWEULGJHDQGRQO\WKHILUVWGDWDSKDVH FRPSOHWHV 7KLVRFFXUVEHFDXVHHLWKHUWKHWDUJHWRUWKH3&,WR3&,EULGJHLQWKH SDWKWHUPLQDWHVWKHUHTXHVWZLWK'LVFRQQHFW 7KHUHTXHVWSDVVHVWKURXJKD3&,WR3&,EULGJHDQGWKH3&,WR3&,EULGJH DOORZVSRVWHGZULWHGDWD PRYLQJWRZDUGPDLQPHPRU\ DIWHUWKHLQLWLDOUHDG FRPSOHWHV 7KHKRVWEULGJHWKDWRULJLQDWHGWKHUHDGUHTXHVWEORFNVWKHSDWKWRPDLQPHPRU\ 7KHGHDGORFNRFFXUVEHFDXVHWKH3&,WR3&,EULGJHFDQQRWDOORZDUHDGWRWUDQVYHUVH LWZKLOHKROGLQJSRVWHGZULWHGDWD7KHKRVWEULGJHWKDWLQLWLDWHGWKH3&,DFFHVV FDQQRWDOORZWKH3&,WR3&,EULGJHWRIOXVKGDWDXQWLOLWFRPSOHWHVWKHVHFRQGUHDG EHFDXVHWKHUHLVQRZD\WR³EDFNRII´WKHRULJLQDWLQJDJHQWZLWKRXWORVLQJGDWD,W PXVWEHDVVXPHGWKHUHDGGDWDZDVREWDLQHGIURPDGHYLFHWKDWKDVGHVWUXFWLYHUHDG VLGHHIIHFWV7KHUHIRUHGLVFDUGLQJWKHGDWDDQGUHSHDWLQJWKHDFFHVVLVQRWDQRSWLRQ ,IDOOWKHVHFRQGLWLRQVDUHPHWWKHGHDGORFNZLOORFFXU,IWKHV\VWHPDOORZVDOOWKH FRQGLWLRQVWRH[LVWWKHQWKHKRVWEULGJHLQLWLDWLQJWKHUHDGUHTXHVWPXVWXVHLOCK# WRJXDUDQWHHWKDWWKHUHDGDFFHVVZLOOFRPSOHWHZLWKRXWWKHGHDGORFNFRQGLWLRQVEHLQJ PHW7KHIDFWWKDWLOCK#LVDFWLYHIRUWKHWUDQVDFWLRQFDXVHVWKH3&,WR3&,EULGJH WRWXUQRIISRVWLQJXQWLOWKHORFNRSHUDWLRQFRPSOHWHV $ORFNHGRSHUDWLRQ FRPSOHWHVZKHQLOCK#LVGHDVVHUWHGZKLOHFRAME#LVGHDVVHUWHG 109 Revision 2.2 1RWH 7KHXVHRILOCK#LVRQO\VXSSRUWHGE\3&,WR3&,EULGJHVPRYLQJ GRZQVWUHDP DZD\IURPWKHSURFHVVRU 7KHUHIRUHWKLVVROXWLRQLVRQO\DSSOLFDEOHWR KRVWEXVEULGJHV $QRWKHUGHDGORFNWKDWLVVLPLODUWRWKHDERYHGHDGORFNRFFXUVGRLQJDQ,2:ULWH DFFHVVWKDWVWUDGGOHVDQRGG':25'ERXQGDU\7KHVDPHFRQGLWLRQRFFXUVDVWKH UHDGGHDGORFNZKHQWKHKRVWEULGJHFDQQRWDOORZDFFHVVWRPHPRU\XQWLOWKH,2 ZULWHFRPSOHWHV+RZHYHULOCK#FDQQRWEHXVHGWRSUHYHQWWKLVGHDGORFNVLQFH ORFNHGDFFHVVHVPXVWEHLQLWLDWHGZLWKDUHDGDFFHVV 3RWHQWLDOGDWDLQFRQVLVWHQF\ZKHQDQDJHQWXVHVGHOD\HGWUDQVDFWLRQ WHUPLQDWLRQ 'HOD\HG&RPSOHWLRQWUDQVDFWLRQVRQ3&,DUHPDWFKHGE\WKHWDUJHWZLWKWKHUHTXHVWHU E\FRPSDULQJDGGUHVVHVEXVFRPPDQGVDQGE\WHHQDEOHVDQGLIDZULWHZULWHGDWD $VDUHVXOWZKHQWZRPDVWHUVDFFHVVWKHVDPHDGGUHVVZLWKWKHVDPHEXVFRPPDQG DQGE\WHHQDEOHVLWLVSRVVLEOHWKDWRQHPDVWHUZLOOREWDLQWKHGDWDDVVXPLQJWKDWLWLV DUHDGZKLFKZDVDFWXDOO\UHTXHVWHGE\WKHRWKHUPDVWHU,QDSUHIHWFKDEOHUHJLRQ WKLVFRQGLWLRQFDQRFFXUHYHQLIWKHE\WHHQDEOHVDQGLQVRPHFDVHVWKHFRPPDQGV RIWKHWZRWUDQVDFWLRQVGRQRWPDWFK$SUHIHWFKDEOHUHJLRQFDQEHGHILQHGE\WKH WDUJHWXVLQJUDQJHUHJLVWHUVRUE\WKHPDVWHUXVLQJWKH0HPRU\5HDG/LQHRU 0HPRU\5HDG0XOWLSOHFRPPDQGV7DUJHWVFRPSOHWLQJUHDGDFFHVVHVLQD SUHIHWFKDEOHPHPRU\UDQJHLJQRUHWKHE\WHHQDEOHVDQGFDQDOVRDOLDVWKHPHPRU\ UHDGFRPPDQGVZKHQFRPSOHWLQJWKHGHOD\HGUHDGUHTXHVW ,IQRLQWHUYHQLQJZULWHRFFXUVEHWZHHQWKHUHDGLVVXHGE\WKHWZRPDVWHUVWKHUHLVQR GDWDFRQVLVWHQF\LVVXH+RZHYHULIDPDVWHUFRPSOHWHVDPHPRU\ZULWHDQGWKHQ UHTXHVWVDUHDGRIWKHVDPHORFDWLRQWKHUHLVDSRVVLELOLW\WKDWWKHUHDGZLOOUHWXUQD VQDSVKRWRIWKDWORFDWLRQZKLFKDFWXDOO\RFFXUUHGSULRUWRWKHZULWH GXHWRD'HOD\HG 5HDG5HTXHVWE\DQRWKHUPDVWHUTXHXHGSULRUWRWKHZULWH 7KLVLVRQO\DSUREOHPZKHQPXOWLSOHPDVWHUVRQRQHVLGHRIDEULGJHDUHSROOLQJWKH VDPHORFDWLRQRQWKHRWKHUVLGHRIWKHEULGJHDQGRQHRIWKHPDVWHUVDOVRZULWHVWKH ORFDWLRQ$OWKRXJKLWLVGLIILFXOWWRHQYLVLRQDUHDODSSOLFDWLRQZLWKWKHVH FKDUDFWHULVWLFVFRQVLGHUWKHVHTXHQFHEHORZ 0DVWHU$DWWHPSWVDUHDGWRORFDWLRQ;DQGDEULGJHUHVSRQGVWRWKHUHTXHVW XVLQJ'HOD\HG7UDQVDFWLRQVHPDQWLFV TXHXHVD'HOD\HG5HDG5HTXHVW 7KHEULGJHREWDLQVWKHUHTXHVWHGUHDGGDWDDQGWKH'HOD\HG5HTXHVWLVQRZ VWRUHGDVD'HOD\HG&RPSOHWLRQLQWKHEULGJH %HIRUH0DVWHU$LVDEOHWRFRPSOHWHWKHUHDGUHTXHVW REWDLQWKHUHVXOWVVWRUHGLQ WKH'HOD\HG&RPSOHWLRQLQWKHEULGJH 0DVWHU%GRHVDPHPRU\ZULWHWR /RFDWLRQ;DQGWKHEULGJHSRVWVWKHPHPRU\ZULWHWUDQVDFWLRQ 0DVWHU%WKHQUHDGVORFDWLRQ;XVLQJWKHVDPHDGGUHVVE\WHHQDEOHVDQGEXV FRPPDQGDV0DVWHU$¶VRULJLQDOUHTXHVW1RWHWKDWLIWKHWUDQVDFWLRQUHDGVIURP DSUHIHWFKDEOHORFDWLRQWKHWZRFRPPDQGVFDQEHFRQIXVHGE\WKHEULGJHHYHQLI WKHE\WHHQDEOHSDWWHUQVDQGUHDGFRPPDQGVDUHGLIIHUHQW 7KHEULGJHFRPSOHWHV0DVWHU%¶VUHDGDFFHVVDQGGHOLYHUVUHDGGDWDZKLFKLVD VQDSVKRWRI/RFDWLRQ;SULRUWRWKHPHPRU\ZULWHRI/RFDWLRQ;E\0DVWHU% 6LQFHERWKWUDQVDFWLRQVDUHLGHQWLFDOWKHEULGJHSURYLGHVWKHGDWDWRWKHZURQJ PDVWHU,I0DVWHU%WDNHVDFWLRQRQWKHUHDGGDWDWKHQDQHUURUPD\RFFXUVLQFH 0DVWHU%ZLOOVHHWKHYDOXHEHIRUHWKHZULWH+RZHYHULIWKHSXUSRVHRIWKHUHDGE\ 0DVWHU%ZDVWRHQVXUHWKDWWKHZULWHKDGFRPSOHWHGDWWKHGHVWLQDWLRQQRHUURU 110 Revision 2.2 RFFXUVDQGWKHV\VWHPLVFRKHUHQWVLQFHWKHUHDGGDWDLVQRWXVHG GXPP\UHDG ,I WKHSXUSRVHRIWKHUHDGLVRQO\WRIOXVKWKHZULWHSRVWHGGDWDLWLVUHFRPPHQGHGWKDW WKHUHDGEHWRDGLIIHUHQW':25'ORFDWLRQRIWKHVDPHGHYLFH7KHQWKHUHDGLQJRI VWDOHGDWDGRHVQRWH[LVW,IWKHUHDGLVWREHFRPSDUHGWRGHFLGHZKDWWRGRLWLV UHFRPPHQGHGWKDWWKHILUVWUHDGEHGLVFDUGHGDQGWKHGHFLVLRQEHEDVHGRQWKH VHFRQGUHDG 7KHDERYHH[DPSOHDSSOLHVHTXDOO\WRDQ,2FRQWUROOHUWKDWXVHV'HOD\HG 7UDQVDFWLRQWHUPLQDWLRQ,QWKHDERYHH[DPSOHUHSODFHWKHZRUGEULGJHZLWK,2 FRQWUROOHUDQGWKHVDPHSRWHQWLDOSUREOHPH[LVWV $VLPLODUSUREOHPFDQRFFXULIWKHWZRPDVWHUVDUHQRWVKDULQJWKHVDPHORFDWLRQEXW ORFDWLRQVFORVHWRHDFKRWKHUDQGRQHPDVWHUEHJLQVUHDGLQJDWDVPDOOHUDGGUHVVWKDQ WKHRQHDFWXDOO\QHHGHG,IWKHVPDOOHUDGGUHVVFRLQFLGHVH[DFWO\ZLWKWKHDGGUHVVRI WKHRWKHUPDVWHU¶VUHDGIURPWKHQHDUORFDWLRQWKHQWKHWZRPDVWHUV¶UHDGVFDQEH VZDSSHGE\DGHYLFHXVLQJ'HOD\HG7UDQVDFWLRQWHUPLQDWLRQ,IWKHUHLVDQ LQWHUYHQLQJZULWHF\FOHWKHQWKHVHFRQGPDVWHUPD\UHFHLYHVWDOHGDWD LHWKH UHVXOWVIURPWKHUHDGZKLFKRFFXUUHGEHIRUHWKHZULWHF\FOH7KHUHVXOWRIWKLV H[DPSOHLVWKHVDPHDVWKHILUVWH[DPSOHVLQFHWKHVWDUWDGGUHVVHVDUHWKHVDPH7R DYRLGWKLVSUREOHPWKHPDVWHUPXVWDGGUHVVWKHGDWDDFWXDOO\UHTXLUHGDQGQRWVWDUWDW DVPDOOHUDGGUHVV ,QVXPPDU\WKLVSUREOHPFDQRQO\RFFXULIWZRPDVWHUVRQRQHVLGHRIDEULGJHDUH VKDULQJORFDWLRQVRQWKHRWKHUVLGHRIWKHEULGJH$OWKRXJKW\SLFDODSSOLFDWLRQVDUH QRWFRQILJXUHGWKLVZD\WKHSUREOHPFDQEHDYRLGHGLIDPDVWHUGRLQJDUHDGIHWFKHV RQO\WKHDFWXDOGDWDLWQHHGVDQGGRHVQRWSUHIHWFKGDWDEHIRUHWKHGHVLUHGGDWDRULI WKHPDVWHUGRHVDGXPP\UHDGDIWHUWKHZULWHWRJXDUDQWHHWKDWWKHZULWHFRPSOHWHV $QRWKHUGDWDLQFRQVLVWHQF\VLWXDWLRQFDQRFFXUZKHQDVLQJOHPDVWHUFKDQJHVLWV EHKDYLRUEDVHGRQDQHZWUDQVDFWLRQLWUHFHLYHVDIWHUKDYLQJDUHTXHVWWHUPLQDWHG ZLWK5HWU\7KHIROORZLQJVHTXHQFHLOOXVWUDWHVWKHGDWDLQFRQVLVWHQF\ $PDVWHULVLQIRUPHGWKDWSRLQWHUDW':25'/RFDWLRQ;LVYDOLG 3RLQWHU DW/RFDWLRQ<WKHQH[WVHTXHQWLDO':25'ORFDWLRQLVQRWYDOLG 7KHPDVWHULQLWLDWHVDPHPRU\UHDGWR/RFDWLRQ;DQGLVWHUPLQDWHGZLWK5HWU\ 7KHPDVWHULQWHQGVWRUHDGRQO\SRLQWHUVLQFHSRLQWHULVLQYDOLG 7KHKRVWEULGJHEHJLQVWRIHWFKWKHFRQWHQWVRI/RFDWLRQ;DVD'HOD\HG 7UDQVDFWLRQ 7KHKRVWEULGJHFRPSOHWHVWKHUHDGUHTXHVWSUHIHWFKLQJEH\RQG/RFDWLRQ;WR LQFOXGH/RFDWLRQ<DQGSODFHVWKH'HOD\HG5HDG&RPSOHWLRQLQWKHRXWERXQG TXHXH 7KH&38XSGDWHVSRLQWHULQ/RFDWLRQ<LQPHPRU\ 7KH&38XVHVDPHPRU\ZULWHWRLQIRUPWKHPDVWHUWKDWSRLQWHULVYDOLG7KH KRVWEULGJHSRVWVWKHPHPRU\ZULWH2UGHULQJUXOHQXPEHULQ$SSHQGL[( UHTXLUHVWKHKRVWEULGJHWRDOORZWKHSRVWHGPHPRU\ZULWHWUDQVDFWLRQWRSDVVWKH 'HOD\HG5HDG&RPSOHWLRQRI/RFDWLRQ; LQFOXGLQJWKHVWDOHYDOXHIURP /RFDWLRQ< 7KHKRVWEULGJHH[HFXWHVWKHSRVWHGPHPRU\ZULWHRQWKH3&,EXVLQIRUPLQJWKH PDVWHUWKDWSRLQWHULQQRZYDOLG 7KHPDVWHUUHSHDWVWKHRULJLQDOPHPRU\UHDGWR/RFDWLRQ;EXWEHFDXVHSRLQWHU LQQRZYDOLGLWH[WHQGVWKHWUDQVDFWLRQDQGREWDLQVWZR':25'6LQFOXGLQJ /RFDWLRQ< 111 Revision 2.2 7KHGDWDWKHPDVWHUUHFHLYHGIURP/RFDWLRQ<LVVWDOH7RSUHYHQWWKLVGDWD LQFRQVLVWHQF\IURPRFFXUULQJWKHPDVWHULVQRWDOORZHGWRH[WHQGDPHPRU\UHDG WUDQVDFWLRQEH\RQGLWVRULJLQDOLQWHQGHGOLPLWVDIWHULWKDVEHHQWHUPLQDWHGZLWK5HWU\ 3HHUWRSHHUWUDQVDFWLRQVFURVVLQJPXOWLSOHKRVWEULGJHV 3&,KRVWEULGJHVPD\EXWDUHQRWUHTXLUHGWRVXSSRUW3&,SHHUWRSHHUWUDQVDFWLRQV WKDWWUDYHUVHPXOWLSOH3&,KRVWEULGJHV 7KHHIIHFWRI3&,WR3&,EULGJHVRQWKH3&,FORFNVSHFLILFDWLRQ 7KHWLPLQJSDUDPHWHUVIRUCLKIRU3&,H[SDQVLRQFRQQHFWRUVDUHVSHFLILHGDWWKH LQSXWRIWKHGHYLFHLQWKHVORW5HIHUWR6HFWLRQDQG6HFWLRQIRUPRUH LQIRUPDWLRQ/LNHDOOVLJQDOVRQWKHFRQQHFWRURQO\DVLQJOHORDGLVSHUPLWWHGRQ CLKLQHDFKVORW$QH[SDQVLRQERDUGWKDWXVHVVHYHUDOGHYLFHVEHKLQGD3&,WR3&, EULGJHPXVWDFFRPPRGDWHWKHFORFNEXIIHULQJUHTXLUHPHQWVRIWKDWEULGJH)RU H[DPSOHLIWKHEULGJH¶VFORFNEXIIHUDIIHFWVWKHGXW\F\FOHRICLKWKHUHVWRIWKH GHYLFHVRQWKHH[SDQVLRQERDUGPXVWDFFHSWWKHGLIIHUHQWGXW\F\FOH,WLVWKH UHVSRQVLELOLW\RIWKHH[SDQVLRQERDUGGHVLJQHUWRFKRRVHFRPSRQHQWVZLWK FRPSDWLEOHCLKVSHFLILFDWLRQV 7KHV\VWHPPXVWDOZD\VJXDUDQWHHWKHWLPLQJSDUDPHWHUVIRUCLKVSHFLILHGLQ 6HFWLRQDQG6HFWLRQDWWKHLQSXWRIWKHGHYLFHLQD3&,H[SDQVLRQ VORWHYHQLIWKHPRWKHUERDUGSODFHV3&,H[SDQVLRQVORWVRQWKHVHFRQGDU\VLGHRID 3&,WR3&,EULGJH,WLVWKHUHVSRQVLELOLW\RIWKHPRWKHUERDUGGHVLJQHUWRFKRRVH FORFNVRXUFHVDQG3&,WR3&,EULGJHVWKDWZLOOJXDUDQWHHWKLVVSHFLILFDWLRQIRUDOO VORWV 'HYLFHVFDQQRWGULYHDQGUHFHLYHVLJQDOVDWWKHVDPHWLPH %XVWLPLQJUHTXLUHVWKDWQRGHYLFHERWKGULYHDQGUHFHLYHDVLJQDORQWKHEXVDWWKH VDPHWLPH6\VWHPWLPLQJDQDO\VLVFRQVLGHUVWKHZRUVWVLJQDOSURSDJDWLRQFDVHWREH ZKHQRQHGHYLFHGULYHVDVLJQDODQGWKHVLJQDOVHWWOHVDWWKHLQSXWRIDOORWKHUGHYLFHV RQWKHEXV,QPRVWFDVHVWKHVLJQDOZLOOQRWVHWWOHDWWKHGULYLQJGHYLFHXQWLOVRPH WLPHDIWHULWKDVVHWWOHGDWDOORWKHUGHYLFHV5HIHUWR6HFWLRQDQG6HFWLRQ IRUDGHVFULSWLRQRI7SURS Logic internal to a device must never use the signal received from the bus while that device is driving the bus. If internal logic requires the state of a bus signal while the device is driving the bus, that logic must use the internal signal (the one going to the output buffer of the device) rather than the signal received from the device input buffer. For example, if logic internal to a device continuously monitors the state of FRAME# on the bus, that logic must use the signal from the device input buffer when the device is not the current bus master, and it must use the internally generated FRAME# when the device is the current bus master. 112 Revision 2.2 Chapter 4 Electrical Specification 4.1. Overview 7KLVFKDSWHUGHILQHVDOOWKHHOHFWULFDOFKDUDFWHULVWLFVDQGFRQVWUDLQWVRI3&,FRPSRQHQWV V\VWHPVDQGH[SDQVLRQERDUGVLQFOXGLQJSLQDVVLJQPHQWRQWKHH[SDQVLRQERDUG FRQQHFWRUZKHQWKHRSHUDWLQJIUHTXHQF\LVDWRUEHORZ0+]5HIHUWR&KDSWHUIRU UHTXLUHPHQWVZKHQWKHRSHUDWLQJIUHTXHQF\LVDERYH0+]7KLVFKDSWHULVGLYLGHG LQWRPDMRUVHFWLRQVFRYHULQJLQWHJUDWHGFLUFXLWFRPSRQHQWV 6HFWLRQ V\VWHPVRU PRWKHUERDUGV 6HFWLRQ DQGH[SDQVLRQERDUGV 6HFWLRQ (DFKVHFWLRQFRQWDLQV WKHUHTXLUHPHQWVWKDWPXVWEHPHWE\WKHUHVSHFWLYHSURGXFWDVZHOODVWKHDVVXPSWLRQVLW PD\PDNHDERXWWKHHQYLURQPHQWSURYLGHG:KLOHHYHU\DWWHPSWZDVPDGHWRPDNH WKHVHVHFWLRQVVHOIFRQWDLQHGWKHUHDUHLQYDULDEO\GHSHQGHQFLHVEHWZHHQVHFWLRQVVRWKDW LWLVQHFHVVDU\WKDWDOOYHQGRUVEHIDPLOLDUZLWKDOOWKUHHDUHDV7KH3&,HOHFWULFDO GHILQLWLRQSURYLGHVIRUERWK9DQG9VLJQDOLQJHQYLURQPHQWV7KHVHVKRXOGQRWEH FRQIXVHGZLWK9DQG9FRPSRQHQWWHFKQRORJLHV$9FRPSRQHQWFDQEH GHVLJQHGWRZRUNLQD9VLJQDOLQJHQYLURQPHQWDQGYLFHYHUVD FRPSRQHQW WHFKQRORJLHVFDQEHPL[HGLQHLWKHUVLJQDOLQJHQYLURQPHQW7KHVLJQDOLQJHQYLURQPHQWV FDQQRWEHPL[HG DOOFRPSRQHQWVRQDJLYHQ3&,EXVPXVWXVHWKHVDPHVLJQDOLQJ FRQYHQWLRQRI9RU9 4.1.1. 5V to 3.3V Transition Road Map 2QHJRDORIWKH3&,HOHFWULFDOVSHFLILFDWLRQLVWRSURYLGHDTXLFNDQGHDV\WUDQVLWLRQIURP 9WR9FRPSRQHQWWHFKQRORJ\,QRUGHUWRIDFLOLWDWHWKLVWUDQVLWLRQ3&,GHILQHVWZR H[SDQVLRQERDUGFRQQHFWRUV−RQHIRUWKH9VLJQDOLQJHQYLURQPHQWDQGRQHIRUWKH9 VLJQDOLQJHQYLURQPHQW−DQGWKUHHERDUGHOHFWULFDOW\SHVDVVKRZQLQ)LJXUH$ FRQQHFWRUNH\LQJV\VWHPSUHYHQWVDERDUGIURPEHLQJLQVHUWHGLQWRDQLQDSSURSULDWHVORW 7KHPRWKHUERDUG LQFOXGLQJFRQQHFWRUV GHILQHVWKHVLJQDOLQJHQYLURQPHQWIRUWKHEXV ZKHWKHULWEH9RU97KH9H[SDQVLRQERDUGLVGHVLJQHGWRZRUNRQO\LQD9 VLJQDOLQJHQYLURQPHQWDQGWKHUHIRUHFDQRQO\EHSOXJJHGLQWRWKH9FRQQHFWRU 6LPLODUO\WKH9H[SDQVLRQERDUGLVGHVLJQHGWRZRUNRQO\LQWKH9VLJQDOLQJ HQYLURQPHQW+RZHYHUWKH8QLYHUVDOH[SDQVLRQERDUGLVFDSDEOHRIGHWHFWLQJWKH VLJQDOLQJHQYLURQPHQWLQXVHDQGDGDSWLQJLWVHOIWRWKDWHQYLURQPHQW,WFDQWKHUHIRUH EHSOXJJHGLQWRHLWKHUFRQQHFWRUW\SH$OOWKUHHERDUGW\SHVGHILQHFRQQHFWLRQVWRERWK 9DQG9SRZHUVXSSOLHVDQGPD\FRQWDLQHLWKHU9DQGRU9FRPSRQHQWV7KH GLVWLQFWLRQEHWZHHQERDUGW\SHVLVWKHVLJQDOLQJSURWRFROWKH\XVHQRWWKHSRZHUUDLOV WKH\FRQQHFWWRQRUWKHFRPSRQHQWWHFKQRORJ\WKH\FRQWDLQ 113 Revision 2.2 "5 volt" Board "3.3 volt" Board I/O buffers powered on I/O buffers powered on 5 volt rail 3.3 volt rail Dual Voltage Signaling Board I/O buffers powered on connector dependent rail "5 volt" Connector "3.3 volt" Connector )LJXUH 3&,%RDUG&RQQHFWRUV 3&,FRPSRQHQWVRQWKH8QLYHUVDOERDUGPXVWXVH,2EXIIHUVWKDWFDQEHFRPSOLDQWZLWK HLWKHUWKH9RU9VLJQDOLQJHQYLURQPHQW:KLOHWKHUHDUHPXOWLSOHEXIIHU LPSOHPHQWDWLRQVWKDWFDQDFKLHYHWKLVGXDOHQYLURQPHQWFRPSOLDQFHLWLVLQWHQGHGWKDW WKH\EHGXDOYROWDJHEXIIHUV LHFDSDEOHRIRSHUDWLQJIURPHLWKHUSRZHUUDLO7KH\ VKRXOGEHSRZHUHGIURP,2GHVLJQDWHGSRZHUSLQV RQ3&,FRQQHFWRUVWKDWZLOO DOZD\VEHFRQQHFWHGWRWKHSRZHUUDLODVVRFLDWHGZLWKWKHVLJQDOLQJHQYLURQPHQWLQXVH 7KLVPHDQVWKDWLQWKH9VLJQDOLQJHQYLURQPHQWWKHVHEXIIHUVDUHSRZHUHGRQWKH9 UDLO:KHQWKHVDPHERDUGLVSOXJJHGLQWRD9FRQQHFWRUWKHVHEXIIHUVDUHSRZHUHG RQWKH9UDLO7KLVHQDEOHVWKH8QLYHUVDOERDUGWREHFRPSOLDQWZLWKHLWKHUVLJQDOLQJ HQYLURQPHQW 7KHLQWHQWRIWKLVWUDQVLWLRQDSSURDFKLVWRPRYH9FRPSRQHQWWHFKQRORJ\LQWRWKH9 VLJQDOLQJHQYLURQPHQWUDWKHUWKDQIRUFLQJ9FRPSRQHQWWHFKQRORJ\WRRSHUDWHLQD 9VLJQDOLQJHQYLURQPHQW:KLOHWKHODWWHUFDQEHGRQHLWLVPRUHGLIILFXOWDQGPRUH H[SHQVLYHHVSHFLDOO\LQDQXQWHUPLQDWHGPRGXODUEXVHQYLURQPHQW7KHSUHIHUUHG DOWHUQDWLYHPRYLQJ9FRPSRQHQWVLQWRD9VLJQDOLQJHQYLURQPHQWFDQEHGRQH ZLWKRXWDQ\LQFUHPHQWDOFRVWDQGKDVLQDGGLWLRQVRPHVLJQDOSHUIRUPDQFHEHQHILWV $OOQHZFRPSRQHQWGHVLJQVDUHUHFRPPHQGHGWRXVHWKHGXDOYROWDJHEXIIHUV$OOQHZ H[SDQVLRQERDUGVDUHUHFRPPHQGHGWREH8QLYHUVDOERDUGV7KLVDOORZVH[SDQVLRQ ERDUGVEDVHGRQ9FRPSRQHQWWHFKQRORJ\WREHXVHGLQERWK9DQG9V\VWHPVWKXV HQDEOLQJWKHPRYHWR9V\VWHPV 27 While the primary goal of the PCI 5V to 3.3V transition strategy is to spare vendors the burden and expense of implementing 3.3V parts that are "5V tolerant," such parts are not excluded. If a PCI component of this type is used on the Universal board, its I/O buffers may optionally be connected to the 3.3V rail rather than the "I/O" designated power pins; but high clamp diodes must still be connected to the "I/O" designated power pins. (Refer to the last paragraph of Section 4.2.1.2. - "Clamping directly to the 3.3V rail with a simple diode must never be used in the 5V signaling environment.") Since the effective operation of these high clamp diodes may be critical to both signal quality and device reliability, the designer must provide enough extra "I/O" designated power pins on a component to handle the current spikes associated with the 5V maximum AC waveforms (Section 4.2.1.3.). 114 Revision 2.2 4.1.2. Dynamic vs. Static Drive Specification 7KH3&,EXVKDVWZRHOHFWULFDOFKDUDFWHULVWLFVWKDWPRWLYDWHDGLIIHUHQWDSSURDFKWR VSHFLI\LQJ,2EXIIHUFKDUDFWHULVWLFV)LUVW3&,LVD&026EXVZKLFKPHDQVWKDWVWHDG\ VWDWHFXUUHQWV DIWHUVZLWFKLQJWUDQVLHQWVKDYHGLHGRXW DUHPLQLPDO,QIDFWWKHPDMRULW\ RIWKH'&GULYHFXUUHQWLVVSHQWRQSXOOXSUHVLVWRUV6HFRQG3&,LVEDVHGRQUHIOHFWHG ZDYHUDWKHUWKDQLQFLGHQWZDYHVLJQDOLQJ7KLVPHDQVWKDWEXVGULYHUVDUHVL]HGWRRQO\ VZLWFKWKHEXVKDOIZD\WRWKHUHTXLUHGKLJKRUORZYROWDJH7KHHOHFWULFDOZDYH SURSDJDWHVGRZQWKHEXVUHIOHFWVRIIWKHXQWHUPLQDWHGHQGDQGEDFNWRWKHSRLQWRI RULJLQWKHUHE\GRXEOLQJWKHLQLWLDOYROWDJHH[FXUVLRQWRDFKLHYHWKHUHTXLUHGYROWDJH OHYHO7KHEXVGULYHULVDFWXDOO\LQWKHPLGGOHRILWVVZLWFKLQJUDQJHGXULQJWKLV SURSDJDWLRQWLPHZKLFKODVWVXSWRQVRQHWKLUGRIWKHEXVF\FOHWLPHDW0+] 3&,EXVGULYHUVVSHQGWKLVUHODWLYHO\ODUJHSURSRUWLRQRIWLPHLQWUDQVLHQWVZLWFKLQJDQG WKH'&FXUUHQWLVPLQLPDOVRWKHW\SLFDODSSURDFKRIVSHFLI\LQJEXIIHUVEDVHGRQWKHLU '&FXUUHQWVRXUFLQJFDSDELOLW\LVQRWXVHIXO3&,EXVGULYHUVDUHVSHFLILHGLQWHUPVRI WKHLU$&VZLWFKLQJFKDUDFWHULVWLFVUDWKHUWKDQ'&GULYH6SHFLILFDOO\WKHYROWDJHWR FXUUHQWUHODWLRQVKLS 9,FXUYH RIWKHGULYHUWKURXJKLWVDFWLYHVZLWFKLQJUDQJHLVWKH SULPDU\PHDQVRIVSHFLILFDWLRQ7KHVH9,FXUYHVDUHWDUJHWHGDWDFKLHYLQJDFFHSWDEOH VZLWFKLQJEHKDYLRULQW\SLFDOFRQILJXUDWLRQVRIVL[ORDGVRQWKHPRWKHUERDUGDQGWZR H[SDQVLRQFRQQHFWRUVRUWZRORDGVRQWKHPRWKHUERDUGDQGIRXUH[SDQVLRQFRQQHFWRUV +RZHYHULWLVSRVVLEOHWRDFKLHYHGLIIHUHQWRUODUJHUFRQILJXUDWLRQVGHSHQGLQJRQWKH DFWXDOHTXLSPHQWSUDFWLFHOD\RXWDUUDQJHPHQWORDGHGLPSHGDQFHRIWKHPRWKHUERDUG HWF 4.2. Component Specification 7KLVVHFWLRQVSHFLILHVWKHHOHFWULFDODQGWLPLQJSDUDPHWHUVIRU3&,FRPSRQHQWV LH LQWHJUDWHGFLUFXLWGHYLFHV%RWK9DQG9UDLOWRUDLOVLJQDOLQJHQYLURQPHQWVDUH GHILQHG7KH9HQYLURQPHQWLVEDVHGRQDEVROXWHVZLWFKLQJYROWDJHVLQRUGHUWREH FRPSDWLEOHZLWK77/VZLWFKLQJOHYHOV7KH9HQYLURQPHQWRQWKHRWKHUKDQGLV EDVHGRQ9FFUHODWLYHVZLWFKLQJYROWDJHVDQGLVDQRSWLPL]HG&026DSSURDFK7KH LQWHQWRIWKHHOHFWULFDOVSHFLILFDWLRQLVWKDWFRPSRQHQWVFRQQHFWGLUHFWO\WRJHWKHU ZKHWKHURQWKHSODQDURUDQH[SDQVLRQERDUGZLWKRXWDQ\H[WHUQDOEXIIHUVRURWKHU JOXH 7KHVHVSHFLILFDWLRQVDUHLQWHQGHGWRSURYLGHDGHVLJQGHILQLWLRQRI3&,FRPSRQHQW HOHFWULFDOFRPSOLDQFHDQGDUHQRWLQJHQHUDOLQWHQGHGDVDFWXDOWHVWVSHFLILFDWLRQV 6RPHRIWKHHOHPHQWVRIWKLVGHVLJQGHILQLWLRQFDQQRWEHWHVWHGLQDQ\SUDFWLFDOZD\EXW PXVWEHJXDUDQWHHGE\GHVLJQFKDUDFWHUL]DWLRQ,WLVWKHUHVSRQVLELOLW\RIFRPSRQHQW GHVLJQHUVDQG$6,&YHQGRUVWRGHYLVHDQDSSURSULDWHFRPELQDWLRQRIGHYLFH FKDUDFWHUL]DWLRQDQGSURGXFWLRQWHVWVFRUUHODWHGWRWKHSDUDPHWHUVKHUHLQLQRUGHUWR JXDUDQWHHWKH3&,FRPSRQHQWFRPSOLHVZLWKWKLVGHVLJQGHILQLWLRQ$OOFRPSRQHQW VSHFLILFDWLRQVKDYHUHIHUHQFHWRDSDFNDJHGFRPSRQHQWDQGWKHUHIRUHLQFOXGHSDFNDJH SDUDVLWLFV8QOHVVVSHFLILFDOO\VWDWHGRWKHUZLVHFRPSRQHQWSDUDPHWHUVDSSO\DWWKH SDFNDJHSLQVQRWDWEDUHVLOLFRQSDGV QRUDWH[SDQVLRQERDUGHGJHFRQQHFWRUV 28 It may be desirable to perform some production tests at bare silicon pads. Such tests may have different parameters than those specified here and must be correlated back to this specification. 115 Revision 2.2 7KHLQWHQWRIWKLVVSHFLILFDWLRQLVWKDWFRPSRQHQWVRSHUDWHZLWKLQWKHFRPPHUFLDO UDQJHRIHQYLURQPHQWDOSDUDPHWHUV+RZHYHUWKLVGRHVQRWSUHFOXGHWKHRSWLRQRIRWKHU RSHUDWLQJHQYLURQPHQWVDWWKHYHQGRU VGLVFUHWLRQ 3&,RXWSXWEXIIHUVDUHVSHFLILHGLQWHUPVRIWKHLU9,FXUYHV/LPLWVRQDFFHSWDEOH9, FXUYHVSURYLGHIRUDPD[LPXPRXWSXWLPSHGDQFHWKDWFDQDFKLHYHDQDFFHSWDEOHILUVWVWHS YROWDJHLQW\SLFDOFRQILJXUDWLRQVDQGIRUDPLQLPXPRXWSXWLPSHGDQFHWKDWNHHSVWKH UHIOHFWHGZDYHZLWKLQUHDVRQDEOHERXQGV3XOOXSDQGSXOOGRZQVLGHVRIWKHEXIIHUKDYH VHSDUDWH9,FXUYHVZKLFKDUHSURYLGHGZLWKWKHSDUDPHWULFVSHFLILFDWLRQ7KHHIIHFWLYH EXIIHUVWUHQJWKLVSULPDULO\VSHFLILHGE\DQ$&GULYHSRLQWZKLFKGHILQHVDQDFFHSWDEOH ILUVWVWHSYROWDJHERWKKLJKJRLQJDQGORZJRLQJWRJHWKHUZLWKUHTXLUHGFXUUHQWVWR DFKLHYHWKDWYROWDJHLQW\SLFDOFRQILJXUDWLRQV7KH'&GULYHSRLQWVSHFLILHVVWHDG\VWDWH FRQGLWLRQVWKDWPXVWEHPDLQWDLQHGEXWLQD&026HQYLURQPHQWWKHVHDUHPLQLPDODQG GRQRWLQGLFDWHUHDORXWSXWGULYHVWUHQJWK7KHVKDGHGDUHDVRQWKH9,FXUYHVVKRZQLQ )LJXUHVDQGGHILQHWKHDOORZDEOHUDQJHIRURXWSXWFKDUDFWHULVWLFV ,WLVSRVVLEOHWRXVHZHDNHURXWSXWGULYHUVWKDWGRQRWFRPSO\ZLWKWKH9,FXUYHVRUPHHW WKHWLPLQJSDUDPHWHUVLQWKLVFKDSWHULIWKH\DUHVHWXSWRGRFRQWLQXRXVVWHSSLQJDV GHVFULEHGLQ6HFWLRQ+RZHYHUWKLVSUDFWLFHLVVWURQJO\GLVFRXUDJHGDVLWFUHDWHV YLRODWLRQVRIWKHLQSXWVHWXSWLPHDWDOOLQSXWVDVZHOODVKDYLQJVLJQLILFDQWQHJDWLYH SHUIRUPDQFHLPSDFWV,QDQ\FDVHDOORXWSXWGULYHUVPXVWPHHWWKHWXUQRII IORDW WLPLQJ VSHFLILFDWLRQ '&SDUDPHWHUVPXVWEHVXVWDLQDEOHXQGHUVWHDG\VWDWH '& FRQGLWLRQV$&SDUDPHWHUV PXVWEHJXDUDQWHHGXQGHUWUDQVLHQWVZLWFKLQJ $& FRQGLWLRQVZKLFKPD\UHSUHVHQWXS WRRIWKHFORFNF\FOH7KHVLJQRQDOOFXUUHQWSDUDPHWHUV GLUHFWLRQRIFXUUHQWIORZ LVUHIHUHQFHGWRDJURXQGLQVLGHWKHFRPSRQHQW WKDWLVSRVLWLYHFXUUHQWVIORZLQWRWKH FRPSRQHQWZKLOHQHJDWLYHFXUUHQWVIORZRXWRIWKHFRPSRQHQW7KHEHKDYLRURIUHVHW RST# LVGHVFULEHGLQ6HFWLRQ V\VWHPVSHFLILFDWLRQ UDWKHUWKDQLQWKLV FRPSRQHQW VHFWLRQ 7KHRSWLRQDOPME# VLJQDOLVXQLTXHEHFDXVHRILWVXVHZKHQWKHV\VWHPLVLQDORZ SRZHUVWDWHLQZKLFKWKH3&,EXVDQGDOOWKHSHULSKHUDOVDWWDFKHGWRLWZLOOVRPHWLPHV KDYHSRZHUUHPRYHG7KLVUHTXLUHVFDUHIXOGHVLJQWRHQVXUHWKDWDYROWDJHDSSOLHGWRWKH PME# SLQZLOOQHYHUFDXVHGDPDJHWRWKHSDUWHYHQLIWKHFRPSRQHQW¶V9FFSLQVDUHQRW SRZHUHG$GGLWLRQDOO\WKHGHYLFHPXVWHQVXUHWKDWLWGRHVQRWSXOOWKHVLJQDOWRJURXQG XQOHVVWKHPME#VLJQDOLVEHLQJLQWHQWLRQDOO\DVVHUWHG6HHWKH3&,3RZHU0DQDJHPHQW ,QWHUIDFH6SHFLILFDWLRQIRUUHTXLUHPHQWVIRUPME#LQV\VWHPVWKDWVXSSRUWLW 116 Revision 2.2 4.2.1. 5V Signaling Environment 4.2.1.1. DC Specifications 7DEOHVXPPDUL]HVWKH'&VSHFLILFDWLRQVIRU9VLJQDOLQJ 7DEOH '&6SHFLILFDWLRQVIRU96LJQDOLQJ Symbol Parameter Condition Min Max Units Notes Vcc Supply Voltage 4.75 5.25 V Vih Input High Voltage 2.0 Vcc+0.5 V Vil Input Low Voltage -0.5 0.8 V µ Iih Input High Leakage Vin = 2.7 70 A1 Current µ Iil Input Low Leakage Vin = 0.5 -70 A1 Current Voh Output High Voltage Iout = -2 mA 2.4 V Vol Output Low Voltage Iout = 3 mA, 6 mA 0.55 V 2 Cin Input Pin Capacitance 10 pF 3 Cclk CLK Pin Capacitance 5 12 pF CIDSEL IDSEL Pin Capacitance 8 pF 4 Lpin Pin Inductance 20 nH 5 ≤ µ IOff PME# input leakage Vo 5.25 V –1 A6 Vcc off or floating NOTES: 1. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs. 2. Signals without pull-up resistors must have 3 mA low output current. Signals requiring pull up must have 6 mA; the latter include, FRAME#, TRDY#, IRDY#, DEVSEL#, STOP#, SERR#, PERR#, LOCK#, INTA#, INTB#, INTC#, INTD#, and, when used, AD[63::32], C/BE[7::4]#, PAR64, REQ64#, and ACK64#. 3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK) with an exception granted to motherboard-only devices up to 16 pF, in order to accommodate PGA packaging. This means, in general, that components for expansion boards need to use alternatives to ceramic PGA packaging (i.e., PQFP, SGA, etc.). 4. Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx]. 5. This is a recommendation, not an absolute requirement. The actual value should be provided with the component data sheet. 6. This input leakage is the maximum allowable leakage into the PME# open drain driver when power is removed from Vcc of the component. This assumes that no event has occurred to cause the device to attempt to assert PME#. 5HIHUWR6HFWLRQIRUVSHFLDOUHTXLUHPHQWVIRUAD[63::32]C/BE[7::4]#DQG PAR64ZKHQWKH\DUHQRWFRQQHFWHG DVLQDELWH[SDQVLRQERDUGLQVWDOOHGLQDELW FRQQHFWRU 117 Revision 2.2 4.2.1.2. AC Specifications 7DEOHVXPPDUL]HVWKH$&VSHFLILFDWLRQVIRU9VLJQDOLQJ 7DEOH $&6SHFLILFDWLRQVIRU96LJQDOLQJ Symbol Parameter Condition Min Max Units Notes I 0 Current High 1.4 3.1 (Test Point) Vout = 3.1 -142 mA 3 I V > 2.2 95 mA 1 ol(AC) Switching out Current Low 2.2>Vout>0.55 Vout/0.023 mA 1 0.71>Vout>0 Eqt'n B 1, 3 (Test Point) Vout = 0.71 206 mA 3 ≤ Icl Low Clamp -5 < Vin -1 -25+(Vin+1)/0.015 mA Current slewr Output Rise Slew 0.4V to 2.4V load 1 5 V / ns 4 Rate slewf Output Fall Slew 2.4V to 0.4V load 1 5 V / ns 4 Rate NOTES: 1. Refer to the V/I curves in Figure 4-2. Switching current characteristics for REQ# and GNT# are permitted to be one half of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST# which are system outputs. "Switching Current High" specifications are not relevant to SERR#, PME#, INTA#, INTB#, INTC#, and INTD# which are open drain outputs. 2. Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive point rather than toward the voltage rail (as is done in the pull-down curve). This difference is intended to allow for an optional N-channel pull-up. 3. Maximum current requirements must be met as drivers pull beyond the first step voltage. Equations defining these maximums (A and B) are provided with the respective diagrams in Figure 4-3. The equation-defined maximums should be met by design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver. 118 Revision 2.2 4. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an unloaded output per revision 2.0 of the PCI Local Bus Specification. However, adherence to both maximum and minimum parameters is required (the maximum is not simply a guideline). Since adherence to the maximum slew rate was not required prior to revision 2.1 of the specification, there may be components in the market for some time that have faster edge rates; therefore, motherboard designers must bear in mind that rise and fall times faster than this specification could occur and should ensure that signal integrity modeling accounts for this. Rise slew rate does not apply to open drain outputs. pin 1/2 in. max. output buffer Vcc 10 pF 1K Ω 1K Ω 7KHPLQLPXPDQGPD[LPXPGULYHFKDUDFWHULVWLFVRI3&,RXWSXWEXIIHUVDUHGHILQHGE\ 9,FXUYHV7KHVHFXUYHVVKRXOGEHLQWHUSUHWHGDVWUDGLWLRQDO³'&´WUDQVLVWRUFXUYHVZLWK WKHIROORZLQJH[FHSWLRQV WKH³'&'ULYH3RLQW´LVWKHRQO\SRVLWLRQRQWKHFXUYHVDW ZKLFKVWHDG\VWDWHRSHUDWLRQLVLQWHQGHGZKLOHWKHKLJKHUFXUUHQWSDUWVRIWKHFXUYHVDUH RQO\UHDFKHGPRPHQWDULO\GXULQJEXVVZLWFKLQJWUDQVLHQWV7KH³$&'ULYH3RLQW´ WKH UHDOGHILQLWLRQRIEXIIHUVWUHQJWK GHILQHVWKHPLQLPXPLQVWDQWDQHRXVFXUUHQWFXUYH UHTXLUHGWRVZLWFKWKHEXVZLWKDVLQJOHUHIOHFWLRQ)URPDTXLHVFHQWRUVWHDG\VWDWHWKH FXUUHQWDVVRFLDWHGZLWKWKH$&GULYHSRLQWPXVWEHUHDFKHGZLWKLQWKHRXWSXWGHOD\WLPH 7YDO1RWHKRZHYHUWKDWWKLVGHOD\WLPHDOVRLQFOXGHVQHFHVVDU\ORJLFWLPH7KH SDUWLWLRQLQJRI7YDOEHWZHHQFORFNGLVWULEXWLRQORJLFDQGRXWSXWEXIIHULVQRWVSHFLILHG EXWWKHIDVWHUWKHEXIIHU DVORQJDVLWGRHVQRWH[FHHGWKHPD[LPXPULVHIDOOVOHZUDWH VSHFLILFDWLRQ WKHPRUHWLPHLVDOORZHGIRUORJLFGHOD\LQVLGHWKHSDUW7KH³7HVW3RLQW´ GHILQHVWKHPD[LPXPDOORZDEOHLQVWDQWDQHRXVFXUUHQWFXUYHLQRUGHUWROLPLWVZLWFKLQJ QRLVHDQGLVVHOHFWHGURXJKO\RQDΩORDGOLQH 119 Revision 2.2 Pull Up Pull Down Vcc Vcc AC drive point test Voltage Voltage point 2.4 2.2 DC drive point DC drive 1.4 point AC drive 0.55 test point point -2 -44Current (mA) -176 3, 6 95 Current (mA) 380 Equation A: Equation B: ,RK 9RXW 9RXW ,RO 9RXW 9RXW IRU9FF!9RXW!Y IRUY 9RXW Y )LJXUH 9,&XUYHVIRU96LJQDOLQJ $GKHUHQFHWRWKHVHFXUYHVLVHYDOXDWHGDWZRUVWFDVHFRQGLWLRQV7KHPLQLPXPSXOOXS FXUYHLVHYDOXDWHGDWPLQLPXP9FFDQGKLJKWHPSHUDWXUH7KHPLQLPXPSXOOGRZQ FXUYHLVHYDOXDWHGDWPD[LPXP9FFDQGKLJKWHPSHUDWXUH7KHPD[LPXPFXUYHWHVW SRLQWVDUHHYDOXDWHGDWPD[LPXP9FFDQGORZWHPSHUDWXUH ,QSXWVDUHUHTXLUHGWREHFODPSHGWRJURXQG&ODPSVWRWKH9UDLODUHRSWLRQDOEXWPD\ EHQHHGHGWRSURWHFW9LQSXWGHYLFHV UHIHUWR6HFWLRQ &ODPSLQJGLUHFWO\WR WKH9UDLOZLWKDVLPSOHGLRGHPXVWQHYHUEHXVHGLQWKH9VLJQDOLQJHQYLURQPHQW :KHQGXDOSRZHUUDLOVDUHXVHGSDUDVLWLFGLRGHSDWKVFDQH[LVWIURPRQHVXSSO\WR DQRWKHU7KHVHGLRGHSDWKVFDQEHFRPHVLJQLILFDQWO\IRUZDUGELDVHG FRQGXFWLQJ LIRQH RIWKHSRZHUUDLOVJRHVRXWRIVSHFLILFDWLRQPRPHQWDULO\'LRGHFODPSVWRDSRZHUUDLO DVZHOODVWRRXWSXWSXOOXSGHYLFHVPXVWEHDEOHWRZLWKVWDQGVKRUWFLUFXLWFXUUHQWXQWLO GULYHUVFDQEHWULVWDWHG5HIHUWR6HFWLRQIRUPRUHLQIRUPDWLRQ 4.2.1.3. Maximum AC Ratings and Device Protection 0D[LPXP$&ZDYHIRUPVDUHLQFOXGHGKHUHDVH[DPSOHVRIZRUVWFDVH$&RSHUDWLQJ FRQGLWLRQV,WLVUHFRPPHQGHGWKDWWKHVHZDYHIRUPVEHXVHGDVTXDOLILFDWLRQFULWHULD DJDLQVWZKLFKWKHORQJWHUPUHOLDELOLW\RIDGHYLFHLVHYDOXDWHG7KLVLVQRWLQWHQGHGWREH XVHGDVDSURGXFWLRQWHVW LWLVLQWHQGHGWKDWWKLVOHYHORIUREXVWQHVVEHJXDUDQWHHGE\ GHVLJQ7KLVVHFWLRQFRYHUV$&RSHUDWLQJFRQGLWLRQVRQO\ '&FRQGLWLRQVDUHVSHFLILHGLQ 6HFWLRQ 7KH3&,HQYLURQPHQWFRQWDLQVPDQ\UHDFWLYHHOHPHQWVDQGLQJHQHUDOPXVWEHWUHDWHGDV DQRQWHUPLQDWHGWUDQVPLVVLRQOLQHHQYLURQPHQW7KHEDVLFSUHPLVHRIWKHHQYLURQPHQW UHTXLUHVWKDWDVLJQDOUHIOHFWDWWKHHQGRIWKHOLQHDQGUHWXUQWRWKHGULYHUEHIRUHWKH VLJQDOLVFRQVLGHUHGVZLWFKHG$VDFRQVHTXHQFHRIWKLVHQYLURQPHQWXQGHUFHUWDLQ FRQGLWLRQVRIGULYHUVGHYLFHWRSRORJ\ERDUGLPSHGDQFHHWFWKHRSHQFLUFXLWYROWDJH DWWKHSLQVRI3&,GHYLFHVZLOOH[FHHGWKHH[SHFWHGJURXQGWR9FFYROWDJHUDQJHE\D 120 Revision 2.2 FRQVLGHUDEOHDPRXQW7KHWHFKQRORJ\XVHGWRLPSOHPHQW3&,FDQYDU\IURPYHQGRUWR YHQGRUVRLWFDQQRWEHDVVXPHGWKDWWKHWHFKQRORJ\LVQDWXUDOO\LPPXQHWRWKHVHHIIHFWV 7KLVXQGHURYHUYROWDJHVSHFLILFDWLRQSURYLGHVDV\QWKHWLFZRUVWFDVH$&HQYLURQPHQW DJDLQVWZKLFKWKHORQJWHUPUHOLDELOLW\RIDGHYLFHFDQEHHYDOXDWHG $OOLQSXWELGLUHFWLRQDODQGWULVWDWHRXWSXWVXVHGRQHDFK3&,GHYLFHPXVWEHFDSDEOHRI FRQWLQXRXVH[SRVXUHWRWKHIROORZLQJV\QWKHWLFZDYHIRUPZKLFKLVDSSOLHGZLWKWKH HTXLYDOHQWRID]HURLPSHGDQFHYROWDJHVRXUFHGULYLQJDVHULHVUHVLVWRUGLUHFWO\LQWRHDFK LQSXWRUWULVWDWHGRXWSXWSLQRIWKH3&,GHYLFH7KHZDYHIRUPSURYLGHGE\WKHYROWDJH VRXUFH RURSHQFLUFXLWYROWDJH DQGWKHUHVLVWRUYDOXHDUHVKRZQLQ)LJXUH7KHRSHQ FLUFXLWZDYHIRUPLVDFRPSRVLWHRIVLPXODWHGZRUVWFDVHV VRPHKDGQDUURZHUSXOVH ZLGWKVZKLOHRWKHUVKDGORZHUYROWDJHSHDNV7KHUHVLVWRULVFDOFXODWHGWRSURYLGHD ZRUVWFDVHFXUUHQWLQWRDQHIIHFWLYH LQWHUQDO FODPSGLRGH1RWHWKDW • 7KHYROWDJHZDYHIRUPLVVXSSOLHGDWWKHUHVLVWRUVKRZQLQWKHHYDOXDWLRQVHWXSQRW WKHSDFNDJHSLQ • :LWKHIIHFWLYHFODPSLQJWKHZDYHIRUPDWWKHSDFNDJHSLQZLOOEHJUHDWO\UHGXFHG • 7KHXSSHUFODPSLVRSWLRQDOEXWLIXVHGLWPXVWEHFRQQHFWHGWRWKH9VXSSO\RUWKH 9,2SODQHRIWKHH[SDQVLRQERDUGEXWQHYHU WKH9VXSSO\ • )RUGHYLFHVEXLOWLQ³YROWWHFKQRORJ\´WKHXSSHUFODPSLVLQSUDFWLFHUHTXLUHGIRU GHYLFHSURWHFWLRQ • ,QRUGHUWROLPLWVLJQDOULQJLQJLQV\VWHPVWKDWWHQGWRJHQHUDWHODUJHRYHUVKRRWV PRWKHUERDUGYHQGRUVPD\ZLVKWRXVHOD\RXWWHFKQLTXHVWRORZHUFLUFXLWLPSHGDQFH Overvoltage Waveform 11 nSec Voltage Source Impedance (min) R = 55 Ω + 11 v 11 v, p-to-p (minimum) 5v. supply 0 v 4 nSec (max) R Input Buffer 62.5 nSec V (16 MHz) Evaluation + 5.25 v Setup 10.75 v, p-to-p (minimum) - 5.5 v Undervoltage Waveform Voltage Source Impedance R = 25 Ω )LJXUH 0D[LPXP$&:DYHIRUPVIRU96LJQDOLQJ 29 Waveforms based on worst case (strongest) driver, maximum and minimum system configurations, with no internal clamp diodes. 30 It is possible to use alternative clamps, such as a diode stack to the 3.3V rail or a circuit to ground, if it can be insured that the I/O pin will never be clamped below the 5V level. 121 Revision 2.2 4.2.2. 3.3V Signaling Environment 4.2.2.1. DC Specifications 7DEOHVXPPDUL]HVWKH'&VSHFLILFDWLRQVIRU9VLJQDOLQJ 7DEOH '&6SHFLILFDWLRQVIRU96LJQDOLQJ Symbol Parameter Condition Min Max Units Notes Vcc Supply Voltage 3.0 3.6 V Vih Input High Voltage 0.5Vcc Vcc + 0.5 V Vil Input Low Voltage -0.5 0.3Vcc V Vipu Input Pull-up Voltage 0.7Vcc V1 µ Iil Input Leakage Current 0 < Vin < Vcc +10 A2 µ Voh Output High Voltage Iout = -500 A 0.9Vcc V µ Vol Output Low Voltage Iout = 1500 A 0.1Vcc V Cin Input Pin Capacitance 10 pF 3 Cclk CLK Pin Capacitance 5 12 pF CIDSEL IDSEL Pin Capacitance 8 pF 4 Lpin Pin Inductance 20 nH 5 ≤ µ IOff PME# input leakage Vo 3.6 V –1 A6 Vcc off or floating NOTES: 1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated network. Applications sensitive to static power utilization must assure that the input buffer is conducting minimum current at this input voltage. 2. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs. 3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK) with an exception granted to motherboard-only devices up to 16 pF in order to accommodate PGA packaging. This would mean in general that components for expansion boards need to use alternatives to ceramic PGA packaging; i.e., PQFP, SGA, etc. 4. Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx]. 5. This is a recommendation, not an absolute requirement. The actual value should be provided with the component data sheet. 6. This input leakage is the maximum allowable leakage into the PME# open drain driver when power is removed from Vccof the component. This assumes that no event has occurred to cause the device to attempt to assert PME#. 5HIHUWR6HFWLRQIRUVSHFLDOUHTXLUHPHQWVIRUAD[63::32]C/BE[7::4]#DQG PAR64ZKHQWKH\DUHQRWFRQQHFWHG DVLQDELWH[SDQVLRQERDUGLQVWDOOHGLQDELW FRQQHFWRU 122 Revision 2.2 4.2.2.2. AC Specifications 7DEOHVXPPDUL]HVWKH$&VSHFLILFDWLRQVIRU9VLJQDOLQJ 7DEOH $&6SHFLILFDWLRQVIRU96LJQDOLQJ Symbol Parameter Condition Min Max Units Notes I 0 Current High 0.3Vcc Current Low 0.6Vcc>Vout>0.1Vcc 26.7Vout mA 1 0.18Vcc>Vout>0 Eqt'n D 1, 2 (Test Point) Vout = 0.18Vcc 38Vcc mA 2 ≤ Icl Low Clamp -3 NOTES: 1. Refer to the V/I curves in Figure 4-4. Switching current characteristics for REQ# and GNT# are permitted to be one half of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST# which are system outputs. "Switching Current High" specifications are not relevant to SERR#, PME#, INTA#, INTB#, INTC#, and INTD# which are open drain outputs. 2. Maximum current requirements must be met as drivers pull beyond the first step voltage. Equations defining these maximums (C and D) are provided with the respective diagrams in Figure 4-5. The equation-defined maximums should be met by design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver. 3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an unloaded output per revision 2.0 of the PCI Local Bus Specification. However, adherence to both maximum and minimum parameters is required (the maximum is not simply a guideline). Rise slew rate does not apply to open drain outputs. pin 1/2 in. max. output buffer Vcc 10 pF 1K Ω 1K Ω 7KHPLQLPXPDQGPD[LPXPGULYHFKDUDFWHULVWLFVRI3&,RXWSXWEXIIHUVDUHGHILQHGE\ 9,FXUYHV7KHVHFXUYHVVKRXOGEHLQWHUSUHWHGDVWUDGLWLRQDO³'&´WUDQVLVWRUFXUYHVZLWK WKHIROORZLQJH[FHSWLRQV WKH³'&'ULYH3RLQW´LVWKHRQO\SRVLWLRQRQWKHFXUYHVDW ZKLFKVWHDG\VWDWHRSHUDWLRQLVLQWHQGHGZKLOHWKHKLJKHUFXUUHQWSDUWVRIWKHFXUYHVDUH 123 Revision 2.2 RQO\UHDFKHGPRPHQWDULO\GXULQJEXVVZLWFKLQJWUDQVLHQWV7KH³$&'ULYH3RLQW´ WKH UHDOGHILQLWLRQRIEXIIHUVWUHQJWK GHILQHVWKHPLQLPXPLQVWDQWDQHRXVFXUUHQWFXUYH UHTXLUHGWRVZLWFKWKHEXVZLWKDVLQJOHUHIOHFWLRQ)URPDTXLHVFHQWRUVWHDG\VWDWHWKH FXUUHQWDVVRFLDWHGZLWKWKH$&GULYHSRLQWPXVWEHUHDFKHGZLWKLQWKHRXWSXWGHOD\WLPH 7YDO1RWHKRZHYHUWKDWWKLVGHOD\WLPHDOVRLQFOXGHVQHFHVVDU\ORJLFWLPH7KH SDUWLWLRQLQJRI7YDOEHWZHHQFORFNGLVWULEXWLRQORJLFDQGRXWSXWEXIIHULVQRWVSHFLILHG EXWWKHIDVWHUWKHEXIIHU DVORQJDVLWGRHVQRWH[FHHGWKHPD[LPXPULVHIDOOVOHZUDWH VSHFLILFDWLRQ WKHPRUHWLPHLVDOORZHGIRUORJLFGHOD\LQVLGHWKHSDUW7KH³7HVW3RLQW´ GHILQHVWKHPD[LPXPDOORZDEOHLQVWDQWDQHRXVFXUUHQWFXUYHLQRUGHUWROLPLWVZLWFKLQJ QRLVHDQGLVVHOHFWHGURXJKO\RQDΩORDGOLQH $GKHUHQFHWRWKHVHFXUYHVLVHYDOXDWHGDWZRUVWFDVHFRQGLWLRQV7KHPLQLPXPSXOOXS FXUYHLVHYDOXDWHGDWPLQLPXP9FFDQGKLJKWHPSHUDWXUH7KHPLQLPXPSXOOGRZQ FXUYHLVHYDOXDWHGDWPD[LPXP9FFDQGKLJKWHPSHUDWXUH7KHPD[LPXPFXUYHWHVW SRLQWVDUHHYDOXDWHGDWPD[LPXP9FFDQGORZWHPSHUDWXUH Pull Up Pull Down Vcc Vcc AC drive point 0.9 test Voltage Vcc point 0.6 Vcc DC 0.5 Vcc Voltage drive point 0.3 DC drive Vcc point 0.1 AC drive Vcc test point point Current (mA) Current (mA) -0.5 -12 -48 1.5 16 64 (TXDWLRQ& (TXDWLRQ' ,RK 9FF 9RXW9FF 9RXW9FF ,RO 9FF 9RXW 9FF9RXW IRU9FF!9RXW!9FF IRUY 9RXW 9FF )LJXUH 9,&XUYHVIRU96LJQDOLQJ ,QSXWVDUHUHTXLUHGWREHFODPSHGWRERWKJURXQGDQG9FF 9 UDLOV:KHQGXDO SRZHUUDLOVDUHXVHGSDUDVLWLFGLRGHSDWKVFRXOGH[LVWIURPRQHVXSSO\WRDQRWKHU7KHVH GLRGHSDWKVFDQEHFRPHVLJQLILFDQWO\IRUZDUGELDVHG FRQGXFWLQJ LIRQHRIWKHSRZHU UDLOVJRHVRXWRIVSHFLILFDWLRQPRPHQWDULO\'LRGHFODPSVWRDSRZHUUDLODVZHOODV RXWSXWSXOOXSGHYLFHVPXVWEHDEOHWRZLWKVWDQGVKRUWFLUFXLWFXUUHQWXQWLOGULYHUVFDQEH WULVWDWHG5HIHUWR6HFWLRQIRUPRUHLQIRUPDWLRQ 124 Revision 2.2 4.2.2.3. Maximum AC Ratings and Device Protection 5HIHUWRWKH0D[LPXP$&5DWLQJVVHFWLRQLQWKH9VLJQDOLQJHQYLURQPHQW 0D[LPXP$&ZDYHIRUPVDUHLQFOXGHGKHUHDVH[DPSOHVRIZRUVWFDVH$&RSHUDWLQJ FRQGLWLRQV,WLVUHFRPPHQGHGWKDWWKHVHZDYHIRUPVEHXVHGDVTXDOLILFDWLRQFULWHULD DJDLQVWZKLFKWKHORQJWHUPUHOLDELOLW\RIDGHYLFHLVHYDOXDWHG7KLVLVQRWLQWHQGHGWREH XVHGDVDSURGXFWLRQWHVW LWLVLQWHQGHGWKDWWKLVOHYHORIUREXVWQHVVEHJXDUDQWHHGE\ GHVLJQ7KLVVHFWLRQFRYHUV$&RSHUDWLQJFRQGLWLRQVRQO\ '&FRQGLWLRQVDUHVSHFLILHG LQ6HFWLRQ $OOLQSXWELGLUHFWLRQDODQGWULVWDWHRXWSXWVXVHGRQHDFK3&,GHYLFHPXVWEHFDSDEOHRI FRQWLQXRXVH[SRVXUHWRWKHIROORZLQJV\QWKHWLFZDYHIRUPZKLFKLVDSSOLHGZLWKWKH HTXLYDOHQWRID]HURLPSHGDQFHYROWDJHVRXUFHGULYLQJDVHULHVUHVLVWRUGLUHFWO\LQWRHDFK LQSXWRUWULVWDWHGRXWSXWSLQRIWKH3&,GHYLFH7KHZDYHIRUPSURYLGHGE\WKHYROWDJH VRXUFH RURSHQFLUFXLWYROWDJH DQGWKHUHVLVWRUYDOXHDUHVKRZQLQ)LJXUH7KHRSHQ FLUFXLWZDYHIRUPLVDFRPSRVLWHRIVLPXODWHGZRUVWFDVHV VRPHKDGQDUURZHUSXOVH ZLGWKVZKLOHRWKHUVKDGORZHUYROWDJHSHDNV7KHUHVLVWRULVFDOFXODWHGWRSURYLGHD ZRUVWFDVHFXUUHQWLQWRDQHIIHFWLYH LQWHUQDO FODPSGLRGH1RWHWKDW • 7KHYROWDJHZDYHIRUPLVVXSSOLHGDWWKHUHVLVWRUVKRZQLQWKHHYDOXDWLRQVHWXS127 WKHSDFNDJHSLQ • :LWKHIIHFWLYHFODPSLQJWKHZDYHIRUPDWWKHSDFNDJHSLQZLOOEHJUHDWO\UHGXFHG • ,QRUGHUWROLPLWVLJQDOULQJLQJLQV\VWHPVWKDWWHQGWRJHQHUDWHODUJHRYHUVKRRWV PRWKHUERDUGYHQGRUVPD\ZLVKWRXVHOD\RXWWHFKQLTXHVWRORZHUFLUFXLWLPSHGDQFH Overvoltage Waveform 11 nSec Voltage Source Impedance (min) R = 29 Ω + 7.1 v 7.1 v, p-to-p (minimum) 3.3v. supply 0 v 4 nSec (max) R Input Buffer 62.5 nSec V (16 MHz) Evaluation Setup + 3.6 v 7.1 v, p-to-p (minimum) - 3.5 v Undervoltage Waveform Voltage Source Impedance R = 28 Ω )LJXUH 0D[LPXP$&:DYHIRUPVIRU96LJQDOLQJ 125 Revision 2.2 4.2.3. Timing Specification 4.2.3.1. Clock Specification 7KHFORFNZDYHIRUPPXVWEHGHOLYHUHGWRHDFK3&,FRPSRQHQWLQWKHV\VWHP,QWKHFDVH RIH[SDQVLRQERDUGVFRPSOLDQFHZLWKWKHFORFNVSHFLILFDWLRQLVPHDVXUHGDWWKH H[SDQVLRQERDUGFRPSRQHQWQRWDWWKHFRQQHFWRUVORW)LJXUHVKRZVWKHFORFN ZDYHIRUPDQGUHTXLUHGPHDVXUHPHQWSRLQWVIRUERWK9DQG9VLJQDOLQJ HQYLURQPHQWV7DEOHVXPPDUL]HVWKHFORFNVSHFLILFDWLRQV5HIHUWRLWHPLQ 6HFWLRQIRUVSHFLDOFRQVLGHUDWLRQVZKHQXVLQJ3&,WR3&,EULGJHVRQH[SDQVLRQ ERDUGVRUZKHQH[SDQVLRQERDUGVORWVDUHORFDWHGGRZQVWUHDPRID3&,WR3&,EULGJH 5 volt Clock 2.4 v 2.0 v 1.5 v 2 v, p-to-p (minimum) 0.8 v 0.4 v T_cyc T_high T_low 3.3 volt Clock 0.6 Vcc 0.5 Vcc 0.4 Vcc 0.4 Vcc, p-to-p (minimum) 0.3 Vcc 0.2 Vcc )LJXUH &ORFN:DYHIRUPV 126 Revision 2.2 7DEOH &ORFNDQG5HVHW6SHFLILFDWLRQV Symbol Parameter Min Max Units Notes Tcyc CLK Cycle Time 30 ∞ ns 1 Thigh CLK High Time 11 ns Tlow CLK Low Time 11 ns - CLK Slew Rate 1 4 V/ns 2 - RST# Slew Rate 50 - mV/ns 3 NOTES: 1. In general, all PCI components must work with any clock frequency between nominal DC and 33 MHz. Device operational parameters at frequencies under 16 MHz may be guaranteed by design rather than by testing. The clock frequency may be changed at any time during the operation of the system so long as the clock edges remain "clean" (monotonic) and the minimum cycle and high and low times are not violated. For example, the use of spread spectrum techniques to reduce EMI emissions is included in this requirement. Refer to Section 7.6.41. for the spread spectrum requirements for 66 MHz. The clock may only be stopped in a low state. A variance on this specification is allowed for components designed for use on the system motherboard only. These components may operate at any single fixed frequency up to 33 MHz and may enforce a policy of no frequency changes. 2. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in Figure 4-6. 3. The minimum RST# slew rate applies only to the rising (deassertion) edge of the reset signal and ensures that system noise cannot render an otherwise monotonic signal to appear to bounce in the switching range. RST# waveforms and timing are discussed in Section 4.3.2. 127 Revision 2.2 4.2.3.2. Timing Parameters 7DEOHSURYLGHVWKHWLPLQJSDUDPHWHUVIRU9DQG9VLJQDOLQJHQYLURQPHQWV 7DEOH 9DQG97LPLQJ3DUDPHWHUV Symbol Parameter Min Max Units Notes Tval CLK to Signal Valid Delay - bused signals 2 11 ns 1, 2, 3 Tval(ptp) CLK to Signal Valid Delay - point to point 2 12 ns 1, 2, 3 Ton Float to Active Delay 2 ns 1, 7 Toff Active to Float Delay 28 ns 1, 7 Tsu Input Setup Time to CLK - bused signals 7 ns 3, 4, 8 Tsu(ptp) Input Setup Time to CLK - point to point 10, 12 ns 3, 4 Th Input Hold Time from CLK 0ns4 Trst Reset active time after power stable 1 ms 5 µ Trst-clk Reset active time after CLK STABLE 100 s5 Trst-off Reset Active to Output Float delay 40 ns 5, 6,7 Trrsu REQ64# to RST# Setup time 10*Tcyc ns Trrh RST# to REQ64# Hold time 0 50 ns 25 Trhfa RST# High to First configuration Access 2 clocks Trhff RST# High to First FRAME# assertion 5 clocks NOTES: 1. See the timing measurement conditions in Figure 4-7. 2. For parts compliant to the 5V signaling environment: Minimum times are evaluated with 0 pF equivalent load; maximum times are evaluated with 50 pF equivalent load. Actual test capacitance may vary, but results must be correlated to these specifications. Note that faster buffers may exhibit some ring back when attached to a 50 pF lump load which should be of no consequence as long as the output buffers are in full compliance with slew rate and V/I curve specifications. For parts compliant to the 3.3V signaling environment: Minimum times are evaluated with same load used for slew rate measurement (as shown in Table 4-4, note 3); maximum times are evaluated with the following load circuits, for high-going and low-going edges respectively. Tval(max) Rising Edge Tval(max) Falling Edge pin 1/2 in. max. output 1/2 in. max. buffer 25 Ω 10 pF Vcc 25 Ω 10 pF 3. REQ# and GNT# are point-to-point signals and have different output valid delay and input setup times than do bused signals. GNT# has a setup of 10; REQ# has a setup of 12. All other signals are bused. 4. See the timing measurement conditions in Figure 4-8. 5. CLK is stable when it meets the requirements in Section 4.2.3.1. RST# is asserted and deasserted asynchronously with respect to CLK. Refer to Section 4.3.2. for more information. 128 Revision 2.2 6. All output drivers must be asynchronously floated when RST# is active. Refer to Section 3.10.2. for special requirements for AD[63::32], C/BE[7::4]#, and PAR64 when they are not connected (as in a 64-bit expansion board installed in a 32-bit connector). 7. For purposes of Active/Float timing measurements, the Hi-Z or “off” state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 8. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at the same time. Refer to Section 3.10., item 9, for additional details. 4.2.3.3. Measurement and Test Conditions )LJXUHVDQG GHILQHWKHFRQGLWLRQVXQGHUZKLFKWLPLQJPHDVXUHPHQWVDUHPDGH 7KHFRPSRQHQWWHVWJXDUDQWHHVWKDWDOOWLPLQJVDUHPHWZLWKPLQLPXPFORFNVOHZUDWH VORZHVWHGJH DQGYROWDJHVZLQJ7KHGHVLJQPXVWJXDUDQWHHWKDWPLQLPXPWLPLQJVDUH DOVRPHWZLWKPD[LPXPFORFNVOHZUDWH IDVWHVWHGJH DQGYROWDJHVZLQJ,QDGGLWLRQ WKHGHVLJQPXVWJXDUDQWHHSURSHULQSXWRSHUDWLRQIRULQSXWYROWDJHVZLQJVDQGVOHZUDWHV WKDWH[FHHGWKHVSHFLILHGWHVWFRQGLWLRQV V_th CLK V_test V_tl T_val OUTPUT V_test (5v. signaling) DELAY V_trise, V_tfall (3.3v. signaling) output current leakage current Tri-State OUTPUT T_on T_off )LJXUH 2XWSXW7LPLQJ0HDVXUHPHQW&RQGLWLRQV V_th CLK V_test V_tl T_su T_h V_th inputs V_test V_test V_max INPUT valid V_tl )LJXUH ,QSXW7LPLQJ0HDVXUHPHQW&RQGLWLRQV 129 Revision 2.2 7DEOH 0HDVXUH&RQGLWLRQ3DUDPHWHUV Symbol 5V Signaling 3.3V Signaling Units Vth 2.4 0.6Vcc V (Note) Vtl 0.4 0.2Vcc V (Note) Vtest 1.5 0.4Vcc V Vtrise n/a 0.285Vcc V Vtfall n/a 0.615Vcc V Vmax 2.0 0.4Vcc V (Note) Input Signal 1 V / ns Edge Rate NOTE: The input test for the 5V environment is done with 400 mV of overdrive (over Vih and Vil); the test for the 3.3V environment is done with 0.1Vcc of overdrive. Timing parameters must be met with no more overdrive than this. Vmax specifies the maximum peak-to-peak waveform allowed for measuring input timing. Production testing may use different voltage values, but must correlate results back to these parameters. 4.2.4. Indeterminate Inputs and Metastability $WWLPHVYDULRXVLQSXWVPD\EHLQGHWHUPLQDWH&RPSRQHQWVPXVWDYRLGORJLFDO RSHUDWLRQDOHUURUVDQGPHWDVWDELOLW\E\VDPSOLQJLQSXWVRQO\RQTXDOLILHGFORFNHGJHV ,QJHQHUDOV\QFKURQRXVVLJQDOVDUHDVVXPHGWREHYDOLGDQGGHWHUPLQDWHRQO\DWWKHFORFN HGJHRQZKLFKWKH\DUH³TXDOLILHG´ UHIHUWR6HFWLRQ 6\VWHPGHVLJQVPXVWDVVXUHWKDWIORDWLQJLQSXWVDUHELDVHGDZD\IURPWKHVZLWFKLQJ UHJLRQLQRUGHUWRDYRLGORJLFDOHOHFWULFDOWKHUPDORUUHOLDELOLW\SUREOHPV,QJHQHUDOLW LVQRWSRVVLEOHWRDYRLGVLWXDWLRQVZKHUHORZVOHZUDWHVLJQDOV HJUHVLVWLYHO\FRXSOHG IDSEL SDVVWKURXJKWKHVZLWFKLQJUHJLRQDWWKHWLPHRIDFORFNHGJHEXWWKH\PXVWQRW EHDOORZHGWRUHPDLQDWWKHWKUHVKROGSRLQWIRUPDQ\FORFNSHULRGV)UHTXHQWO\DSUH FKDUJHGEXVPD\EHDVVXPHGWRUHWDLQLWVVWDWHZKLOHQRWGULYHQIRUDIHZFORFNSHULRGV GXULQJEXVWXUQDURXQG 7KHUHDUHVSHFLILFLQVWDQFHVZKHQVLJQDOVDUHNQRZQWREHLQGHWHUPLQDWH7KHVHPXVWEH FDUHIXOO\FRQVLGHUHGLQDQ\GHVLJQ $OOAD[31::00]C/BE[3::0]#DQGPARSLQVDUHLQGHWHUPLQDWHZKHQWULVWDWHGIRUEXV WXUQDURXQG7KLVZLOOVRPHWLPHVODVWIRUVHYHUDOF\FOHVZKLOHZDLWLQJIRUDGHYLFHWR UHVSRQGDWWKHEHJLQQLQJRIDWUDQVDFWLRQ 7KHIDSELSLQLVLQGHWHUPLQDWHDWDOOWLPHVH[FHSWGXULQJFRQILJXUDWLRQF\FOHV,ID UHVLVWLYHFRQQHFWLRQWRDQADOLQHLVXVHGLWPD\WHQGWRIORDWDURXQGWKHVZLWFKLQJ UHJLRQPXFKRIWKHWLPH 130 Revision 2.2 7KHPME#DQGSERR#SLQVPXVWEHFRQVLGHUHGLQGHWHUPLQDWHIRUDQXPEHURIF\FOHV DIWHUWKH\KDYHEHHQGHDVVHUWHG 1HDUO\DOOVLJQDOVZLOOEHLQGHWHUPLQDWHIRUDVORQJDVRST#LVDVVHUWHGDQGIRUDSHULRG RIWLPHDIWHULWLVUHOHDVHG3LQVZLWKSXOOXSUHVLVWRUVZLOOHYHQWXDOO\UHVROYHKLJK 4.2.5. Vendor Provided Specification 7KHYHQGRURID3&,V\VWHPLVUHVSRQVLEOHIRUHOHFWULFDOVLPXODWLRQRIWKH3&,EXVDQG FRPSRQHQWVWRJXDUDQWHHSURSHURSHUDWLRQ7RKHOSIDFLOLWDWHWKLVHIIRUWFRPSRQHQW YHQGRUVDUHHQFRXUDJHGWRPDNHWKHIROORZLQJLQIRUPDWLRQDYDLODEOH ,WLV UHFRPPHQGHGWKDWFRPSRQHQWYHQGRUVPDNHWKLVLQIRUPDWLRQHOHFWURQLFDOO\DYDLODEOHLQ WKH,%,6PRGHOIRUPDW • 3LQFDSDFLWDQFHIRUDOOSLQV • 3LQLQGXFWDQFHIRUDOOSLQV • 2XWSXW9,FXUYHVXQGHUVZLWFKLQJFRQGLWLRQV7ZRFXUYHVVKRXOGEHJLYHQIRUHDFK RXWSXWW\SHXVHG RQHIRUGULYLQJKLJKWKHRWKHUIRUGULYLQJORZ%RWKVKRXOGVKRZ EHVWW\SLFDOZRUVWFXUYHV$OVREH\RQGWKHUDLOUHVSRQVHLVFULWLFDOVRWKHYROWDJH UDQJHVKRXOGVSDQ9WR9IRU9VLJQDOLQJDQG9WR9IRU9VLJQDOLQJ • ,QSXW9,FXUYHVXQGHUVZLWFKLQJFRQGLWLRQV$9,FXUYHRIWKHLQSXWVWUXFWXUHZKHQ WKHRXWSXWLVWULVWDWHGLVDOVRLPSRUWDQW7KLVSORWVKRXOGDOVRVKRZEHVWW\SLFDO ZRUVWFXUYHVRYHUWKHUDQJHRIWR9FF • 5LVHIDOOVOHZUDWHVIRUHDFKRXWSXWW\SH • &RPSOHWHDEVROXWHPD[LPXPGDWDLQFOXGLQJRSHUDWLQJDQGQRQRSHUDWLQJ WHPSHUDWXUH'&PD[LPXPVHWF ,QDGGLWLRQWRWKLVFRPSRQHQWLQIRUPDWLRQFRQQHFWRUYHQGRUVDUHHQFRXUDJHGWRPDNH DYDLODEOHDFFXUDWHVLPXODWLRQPRGHOVRI3&,FRQQHFWRUV 4.2.6. Pinout Recommendation 7KLVVHFWLRQSURYLGHVDUHFRPPHQGHGSLQRXWIRU3&,FRPSRQHQWV6LQFHH[SDQVLRQ ERDUGVWXEVDUHVROLPLWHGOD\RXWLVVXHVDUHJUHDWO\PLQLPL]HGLIWKHFRPSRQHQWSLQRXW DOLJQVH[DFWO\ZLWKWKHERDUG FRQQHFWRU SLQRXW&RPSRQHQWVIRUXVHRQO\RQ PRWKHUERDUGVDUHHQFRXUDJHGDOVRWRIROORZWKLVVDPHVLJQDORUGHULQJWRDOORZOD\RXWV ZLWKPLQLPXPVWXEV)LJXUH VKRZVWKHUHFRPPHQGHGSLQRXWIRUDW\SLFDO34)33&, FRPSRQHQW1RWHWKDWWKHSLQRXWLVH[DFWO\DOLJQHGZLWKWKHVLJQDORUGHURQWKHERDUG FRQQHFWRU3ODFHPHQWDQGQXPEHURISRZHUDQGJURXQGSLQVLVGHYLFHGHSHQGHQW 7KHDGGLWLRQDOVLJQDOVQHHGHGLQELWYHUVLRQVRIWKHEXVFRQWLQXHZUDSSLQJDURXQGWKH FRPSRQHQWLQDFRXQWHUFORFNZLVHGLUHFWLRQLQWKHVDPHRUGHUWKH\DSSHDURQWKHELW FRQQHFWRUH[WHQVLRQ 131 Revision 2.2 PAR64 AD[32] { PCI Component . JTAG . AD[63] RST# C/BE4# CLK C/BE5# GNT C/BE6# REQ C/BE7# AD[31] All PCI Shared Signals REQ64# . Below this Line ACK64# . AD[0] AD[24] . C/BE3# AD[7] IDSEL C/BE0# . . . PAR AD[8] IRDY# AD[23] AD[16] AD[15] TRDY# STOP# LOCK# PERR# SERR# C/BE2# C/BE1# FRAME# DEVSEL# PCI Card Edge )LJXUH 6XJJHVWHG3LQRXWIRU34)33&,&RPSRQHQW 3ODFLQJWKHIDSELLQSXWDVFORVHDVSRVVLEOHWRAD[31::11]DOORZVWKHRSWLRQIRUDQRQ UHVLVWLYH FRQQHFWLRQRIIDSELWRWKHDSSURSULDWHDGGUHVVOLQHZLWKDVPDOODGGLWLRQDO ORDG1RWHWKDWWKLVSLQKDVDORZHUFDSDFLWDQFHVSHFLILFDWLRQWKDWLQVRPHFDVHVZLOO FRQVWUDLQLWVSODFHPHQWLQWKHSDFNDJH 4.3. System (Motherboard) Specification 4.3.1. Clock Skew 7KHPD[LPXPDOORZDEOHFORFNVNHZLVQV7KLVVSHFLILFDWLRQDSSOLHVQRWRQO\DWD VLQJOHWKUHVKROGSRLQWEXWDWDOOSRLQWVRQWKHFORFNHGJHWKDWIDOOLQWKHVZLWFKLQJUDQJH GHILQHGLQ7DEOHDQG)LJXUH7KHPD[LPXPVNHZLVPHDVXUHGEHWZHHQDQ\WZR FRPSRQHQWV UDWKHUWKDQEHWZHHQFRQQHFWRUV7RFRUUHFWO\HYDOXDWHFORFNVNHZWKH V\VWHPGHVLJQHUPXVWWDNHLQWRDFFRXQWFORFNGLVWULEXWLRQRQWKHH[SDQVLRQERDUGZKLFK LVVSHFLILHGLQ6HFWLRQ 31 Non-resistive connections of IDSEL to one of the AD[xx] lines create a technical violation of the single load per expansion board rule. PCI protocol provides for pre-driving of address lines in configuration cycles, and it is recommended that this be done in order to allow a resistive coupling of IDSEL. In absence of this, signal performance must be derated for the extra IDSEL load. 32 The system designer must address an additional source of skew. This clock skew occurs between two components that have clock input trip points at opposite ends of the Vil - Vih range. In certain circumstances, this can add to the clock skew measurement as described here. In all cases, total clock skew must be limited to the specified number. 132 Revision 2.2 7DEOH &ORFN6NHZ3DUDPHWHUV Symbol 5V Signaling 3.3V Signaling Units Vtest 1.5 0.4 Vcc V Tskew 2 (max) 2 (max) ns V_ih V_test CLK V_il (@Device #1) T_skew T_skew T_skew V_ih CLK V_test (@Device #2) V_il )LJXUH &ORFN6NHZ'LDJUDP 4.3.2. Reset 7KHDVVHUWLRQDQGGHDVVHUWLRQRIWKH3&,UHVHWVLJQDO RST# LVDV\QFKURQRXVZLWK UHVSHFWWRCLK7KHULVLQJ GHDVVHUWLRQ HGJHRIWKHRST#VLJQDOPXVWEHPRQRWRQLF ERXQFHIUHH WKURXJKWKHLQSXWVZLWFKLQJUDQJHDQGPXVWPHHWWKHPLQLPXPVOHZUDWH VSHFLILHGLQ7DEOH7KH3&,VSHFLILFDWLRQGRHVQRWSUHFOXGHWKHLPSOHPHQWDWLRQRID V\QFKURQRXVRST#LIGHVLUHG7KHWLPLQJSDUDPHWHUVIRUUHVHWDUHOLVWHGLQ7DEOH ZLWKWKHH[FHSWLRQRIWKH7IDLOSDUDPHWHU7KLVSDUDPHWHUSURYLGHVIRUV\VWHPUHDFWLRQ WRRQHRUERWKRIWKHSRZHUUDLOVJRLQJRXWRIVSHFLILFDWLRQ,IWKLVRFFXUVSDUDVLWLFGLRGH SDWKVFRXOGVKRUWFLUFXLWDFWLYHRXWSXWEXIIHUV7KHUHIRUHRST#LVDVVHUWHGXSRQSRZHU IDLOXUHLQRUGHUWRIORDWWKHRXWSXWEXIIHUV 7KHYDOXHRI7IDLOLVWKHPLQLPXPRI • QV PD[LPXP IURPHLWKHUSRZHUUDLOJRLQJRXWRIVSHFLILFDWLRQ H[FHHGLQJ VSHFLILHGWROHUDQFHVE\PRUHWKDQP9 • QV PD[LPXP IURPWKH9UDLOIDOOLQJEHORZWKH9UDLOE\PRUHWKDQ P9 7KHV\VWHPPXVWDVVHUWRST#GXULQJSRZHUXSRULQWKHHYHQWRIDSRZHUIDLOXUH,Q RUGHUWRPLQLPL]HSRVVLEOHYROWDJHFRQWHQWLRQEHWZHHQ9DQG9SDUWVRST#PXVW EHDVVHUWHGDVVRRQDVSRVVLEOHGXULQJWKHSRZHUXSVHTXHQFH)LJXUHVKRZVD ZRUVWFDVHDVVHUWLRQRIRST#DV\QFKURQRXVO\IROORZLQJWKHSRZHUJRRGVLJQDO $IWHURST#LV DVVHUWHG3&,FRPSRQHQWVPXVWDV\QFKURQRXVO\GLVDEOH IORDW WKHLU RXWSXWVEXWDUHQRWFRQVLGHUHGUHVHWXQWLOERWK7UVWDQG7UVWFONSDUDPHWHUVKDYHEHHQ PHW)LJXUHVKRZVRST#VLJQDOWLPLQJ 7KHV\VWHPPXVWJXDUDQWHHWKDWWKHEXVUHPDLQVLQWKHLGOHVWDWHIRUDPLQLPXPWLPH GHOD\IROORZLQJWKHGHDVVHUWLRQRIRST#WRDGHYLFHEHIRUHWKHV\VWHPZLOOSHUPLWWKH 33 Component vendors should note that a fixed timing relationship between RST# and power sequencing cannot be guaranteed in all cases. 133 Revision 2.2 ILUVWDVVHUWLRQRIFRAME#7KLVWLPHGHOD\LVLQFOXGHGLQ7DEOHDV5HVHW+LJKWR FRAME# )LUVW DVVHUWLRQ 7UKII ,IDGHYLFHUHTXLUHVORQJHUWKDQWKHVSHFLILHGWLPH RST# 7UKII DIWHUWKHGHDVVHUWLRQRI EHIRUHLWLVUHDG\WRSDUWLFLSDWHLQWKHEXVVLJQDOLQJ SURWRFROWKHQWKHGHYLFH VVWDWHPDFKLQHVPXVWUHPDLQLQWKHUHVHWVWDWHXQWLODOORIWKH IROORZLQJDUHVLPXOWDQHRXVO\WUXH • RST# LVGHDVVHUWHG • 7KHGHYLFHLVUHDG\WRSDUWLFLSDWHLQWKHEXVVLJQDOLQJSURWRFRO • 7KHEXVLVLQWKHLGOHVWDWH Implementation Note: Reset $QH[DPSOHRIDGHYLFHWKDWFRXOGUHTXLUHPRUHWKDQ7UKIIWREHUHDG\WRSDUWLFLSDWHLQ WKHEXVVLJQDOLQJSURWRFROLVD0+]GHYLFHWKDWLQFOXGHVD3KDVH/RFNHG/RRS 3// IRUGLVWULEXWLRQRIWKH3&,FORFNLQWHUQDOO\WRWKHGHYLFH7KHGHYLFHPD\LQKLELWFORFNV WRWKH3&,LQWHUIDFHXQWLOWKH3//KDVORFNHG6LQFHWKH3//FRXOGHDVLO\UHTXLUHPRUH WKDQ7UKIIWRORFNWKLVFRXOGUHVXOWLQWKHFORFNVEHLQJHQDEOHGWRWKH3&,LQWHUIDFHRI WKLVGHYLFHLQWKHPLGGOHRIDEXUVWWUDQVIHUEHWZHHQWZRRWKHUGHYLFHV:KHQWKLV RFFXUVWKH0+]GHYLFHZRXOGKDYHWRGHWHFWDQLGOHEXVFRQGLWLRQEHIRUHHQDEOLQJ WKHWDUJHWVHOHFWLRQIXQFWLRQ RST# 6RPH3&,GHYLFHVPXVWEHSUHSDUHGWRUHVSRQGDVDWDUJHW7UKIIWLPHDIWHU GHDVVHUWV)RUH[DPSOHGHYLFHVLQWKHSDWKEHWZHHQWKH&38DQGWKHERRW520 QRW RST# H[SDQVLRQ520 PXVWEHSUHSDUHGWRUHVSRQGDVDWDUJHW7UKIIWLPHDIWHU GHDVVHUWV $OORWKHUGHYLFHVPXVWEHSUHSDUHGWRUHVSRQGDVDWDUJHWQRWPRUHWKDQ7UKIDDIWHUWKH RST# GHDVVHUWLRQRI ,WLVUHFRPPHQGHGWKDWWKHV\VWHPZDLWDWOHDVW7UKIDIROORZLQJ WKHGHDVVHUWLRQRIRST#WRDGHYLFHEHIRUHWKHILUVWDFFHVVWRWKDWGHYLFHXQOHVVWKH GHYLFHLVLQWKHSDWKEHWZHHQWKH&38DQGWKHERRW520RUWKHV\VWHPNQRZVWKDWWKH GHYLFHLVUHDG\VRRQHU 6RIWZDUHWKDWDFFHVVHVGHYLFHVSULRUWRWKHH[SLUDWLRQRI7UKIDPXVWEHSUHSDUHGIRUWKH GHYLFHVHLWKHUQRWWRUHVSRQGDWDOO UHVXOWLQJLQ0DVWHU$ERUW RUIRUWKHGHYLFHVWR UHVSRQGZLWK5HWU\XQWLOWKHH[SLUDWLRQRI7UKID$WQRWLPHFDQDGHYLFHUHWXUQLQYDOLG GDWD'HYLFHVDUHH[HPSWIURPWKH0D[LPXP5HWU\7LPHVSHFLILFDWLRQDQGWKHWDUJHW LQLWLDOODWHQF\UHTXLUHPHQWXQWLOWKHH[SLUDWLRQRI7UKID 134 Revision 2.2 Implementation Note: Trhfa 'HYLFHVDUHHQFRXUDJHGWRFRPSOHWHWKHLULQLWLDOL]DWLRQDQGEHUHDG\WRDFFHSWWKHLUILUVW F\FOH JHQHUDOO\D&RQILJXUDWLRQ5HDGF\FOH DVVRRQDVSRVVLEOHDIWHUWKHGHDVVHUWLRQRI RST#6RPHV\VWHPLPSOHPHQWDWLRQVZLOODFFHVVGHYLFHVSULRUWRZDLWLQJWKHIXOOYDOXH RI7UKIDLIWKH\NQRZLQDGYDQFHWKDWDOOGHYLFHVDUHUHDG\VRRQHU)RUH[DPSOHD V\VWHPZLWKQR3&,VORWVZRXOGRQO\QHHGWRZDLWIRUWKHLQLWLDOL]DWLRQUHTXLUHPHQWVRI WKHHPEHGGHGGHYLFHV6LPLODUO\DQLQWHOOLJHQWH[SDQVLRQERDUGWKDWLQLWLDOL]HGLWVRZQ HPEHGGHG3&,GHYLFHVZRXOGRQO\QHHGWRZDLWIRUWKHLQLWLDOL]DWLRQUHTXLUHPHQWVRI WKRVHGHYLFHV ,QVRPHFDVHVVXFKDVLQWHOOLJHQWH[SDQVLRQERDUGVWKHH[SDQVLRQERDUGGHVLJQHUPXVW VHOHFWGHYLFHVWKDWLQLWLDOL]HLQOHVVWKDQWKHIXOOYDOXHRI7UKID)RUH[DPSOHVXSSRVHDQ LQWHOOLJHQWH[SDQVLRQERDUGLVQRWUHDG\WRUHVSRQGDVDWDUJHWWRWKHILUVW&RQILJXUDWLRQ WUDQVDFWLRQIURPWKHKRVW&38XQWLODIWHUWKHORFDO&38KDVFRQILJXUHGWKHORFDOGHYLFHV ,QWKLVFDVHWKHORFDOGHYLFHVPXVWLQLWLDOL]HIDVWHQRXJKWRHQDEOHWKHORFDO&38WR FRPSOHWHLWVLQLWLDOL]DWLRQLQWLPHIRUWKHILUVWDFFHVVIURPWKHKRVW&38 32:(5 9QRPLQDOÃÃ;È 7BIDLO 3&,B&/. PVÃ W\S 3:5B*22' 7BUVW 567Æ 7BUVWFON 7BUUK 5(4Æ 7BUVWRII 7BUUVX 3&, WULVWDWH 6LJQDOV 7BUKII 7BUKID )LJXUH 5HVHW7LPLQJ 5HIHUWR6HFWLRQIRUVSHFLDOUHTXLUHPHQWVIRUAD[63::32]C/BE[7::4]#DQG PAR64ZKHQWKH\DUHQRWFRQQHFWHG DVLQDELWH[SDQVLRQERDUGLQVWDOOHGLQDELW FRQQHFWRU 34 This reset timing figure optionally shows the "PWR_GOOD" signal as a pulse which is used to time the RST# pulse. In many systems, "PWR_GOOD" may be a level, in which case the RST# pulse must be timed in another way. 135 Revision 2.2 4.3.3. Pull-ups 3&,FRQWUROVLJQDOVDOZD\VUHTXLUHSXOOXSUHVLVWRUVRQWKHPRWKHUERDUG QRWWKH H[SDQVLRQERDUG WRHQVXUHWKDWWKH\FRQWDLQVWDEOHYDOXHVZKHQQRDJHQWLVDFWLYHO\ GULYLQJWKHEXV7KLVLQFOXGHVFRAME#TRDY#IRDY#DEVSEL#STOP# SERR#PERR#LOCK#, INTA#, INTB#, INTC#, INTD#,REQ64#DQG ACK64# 7KHSRLQWWRSRLQWDQGVKDUHGELWVLJQDOVGRQRWUHTXLUHSXOOXSV EXVSDUNLQJHQVXUHV WKHLUVWDELOLW\5HIHUWR6HFWLRQIRUVSHFLDOUHTXLUHPHQWVIRUWHUPLQDWLQJ AD[63::32]C/BE[7::4]#DQGPAR64.5HIHUWR6HFWLRQIRUSXOOXSDQG GHFRXSOLQJUHTXLUHPHQWVIRUPRSNT1#DQGPRSNT2#5HIHUWR6HFWLRQIRUSXOO XSDQGGHFRXSOLQJUHTXLUHPHQWVIRUM66EN 5HVHUYHGSLQV$DQG$PXVWEHVHSDUDWHO\SXOOHGXSZLWKDQ∼.ΩUHVLVWRUWREH FRQVLVWHQWZLWKSUHYLRXVYHUVLRQVRIWKLVVSHFLILFDWLRQ 3UHYLRXVYHUVLRQVRIWKLV VSHFLILFDWLRQDVVLJQHGIXQFWLRQVWRWKHVHSLQV $OVRLIERXQGDU\VFDQLVQRW LPSOHPHQWHGRQWKHSODQDUTMSDQGTDIPXVWEHLQGHSHQGHQWO\EXVHGDQGSXOOHGXS HDFKZLWKa.ΩUHVLVWRUVDQGTRST#DQGTCKPXVWEHLQGHSHQGHQWO\EXVHGDQG SXOOHGGRZQHDFKZLWKa.ΩUHVLVWRUVTDOPXVWEHOHIWRSHQ 7KHIRUPXODVIRUPLQLPXPDQGPD[LPXPSXOOXSUHVLVWRUVDUHSURYLGHGEHORZ5PLQLV SULPDULO\GULYHQE\,ROWKH'&ORZRXWSXWFXUUHQWZKHUHDVWKHQXPEHURIORDGVRQO\KDV DVHFRQGDU\HIIHFW2QWKHRWKHUKDQG5PD[LVSULPDULO\GULYHQE\WKHQXPEHURIORDGV SUHVHQW7KHVSHFLILFDWLRQSURYLGHVIRUDPLQLPXP5YDOXHWKDWLVFDOFXODWHGEDVHGRQ ORDGV EHOLHYHGWREHDZRUVWFDVH DQGDW\SLFDO5YDOXHWKDWLVFDOFXODWHGDVWKH PD[LPXP5YDOXHZLWKORDGV7KHPD[LPXP5YDOXHLVSURYLGHGE\IRUPXODRQO\ DQGZLOOEHWKHKLJKHVWLQDV\VWHPZLWKWKHVPDOOHVWQXPEHURIORDGV PLQ=−+⋅ PD[ RO RO LO where 16 = max number of loads 5>@> @ 9FF 9 , , , =− × 5PD[>@>B@ 9FF PLQ 9[ QXP ORDGV ,LK , = [ = where: 9[ Y for 5V signaling, and 9 9FF for 3.3V signaling. 7DEOH SURYLGHVPLQLPXPDQGW\SLFDOYDOXHVIRUERWK9DQG9VLJQDOLQJ HQYLURQPHQWV7KHW\SLFDOYDOXHVKDYHEHHQGHUDWHGIRUUHVLVWRUVDWQRPLQDOYDOXHV 7DEOH 0LQLPXPDQG7\SLFDO3XOOXS5HVLVWRU9DOXHV Signaling Rail Rmin Rtypical Rmax 5V 963 Ω 2.7 KΩ @ 10% see formula 3.3V 2.42 KΩ 8.2 KΩ @ 10% see formula 7KHFHQWUDOUHVRXUFHRUDQ\FRPSRQHQWFRQWDLQLQJDQDUELWUDWLRQXQLWPD\UHTXLUHD ZHDNSXOOXSRQHDFKXQFRQQHFWHGREQ#SLQDQGHDFKREQ#SLQFRQQHFWHGWRD3&, H[SDQVLRQVORWLQRUGHUWRLQVXUHWKDWWKHVHVLJQDOVGRQRWIORDW9DOXHVIRUWKLVSXOOXS VKDOOEHVSHFLILHGE\WKHFHQWUDOUHVRXUFHYHQGRU 6\VWHPVXWLOL]LQJPME#PXVWSURYLGHDSXOOXSRQWKDWVLJQDO7KHUHVLVWRUYDOXHXVHGLV FDOFXODWHGXVLQJWKHIRUPXODVDERYHEXWVXEVWLWXWLQJ,2IIÃIRU,LK 136 Revision 2.2 4.3.4. Power 4.3.4.1. Power Requirements $OO3&,FRQQHFWRUVUHTXLUHIRXUSRZHUUDLOV 999DQG96\VWHPV WKDWSURYLGH3&,FRQQHFWRUVDUHUHTXLUHGWRSURYLGHDOOIRXUUDLOVLQHYHU\V\VWHPZLWKWKH FXUUHQWEXGJHWVSHFLILHGLQ7DEOH6\VWHPVPD\RSWLRQDOO\VXSSO\9DX[SRZHU DVVSHFLILHGLQWKH3&,%XV3RZHU0DQDJHPHQW,QWHUIDFH6SHFLILFDWLRQ6\VWHPVWKDWGR QRWVXSSRUW3&,EXVSRZHUPDQDJHPHQWPXVWWUHDWWKH9DX[SLQDVUHVHUYHG &XUUHQWUHTXLUHPHQWVSHUFRQQHFWRUIRUWKHWZR9UDLOVDUHSURYLGHGLQ7DEOH 7KHUHDUHQRVSHFLILFV\VWHPUHTXLUHPHQWVIRUFXUUHQWSHUFRQQHFWRURQWKH9DQG9 UDLOV WKLVLVV\VWHPGHSHQGHQW1RWHWKDW6HFWLRQUHTXLUHVWKDWDQH[SDQVLRQFDUG PXVWOLPLWLWVWRWDOSRZHUFRQVXPSWLRQWRZDWWV IURPDOOSRZHUUDLOV 7KHV\VWHP SURYLGHVDWRWDOSRZHUEXGJHWIRU3&,H[SDQVLRQERDUGVWKDWFDQEHGLVWULEXWHGEHWZHHQ FRQQHFWRUVLQDQDUELWUDU\ZD\7KHPRSNTn#SLQVRQWKHFRQQHFWRUDOORZWKHV\VWHP WRRSWLRQDOO\DVVHVVWKHSRZHUGHPDQGRIHDFKH[SDQVLRQERDUGDQGGHWHUPLQHLIWKH LQVWDOOHGFRQILJXUDWLRQZLOOUXQZLWKLQWKHWRWDOSRZHUEXGJHW5HIHUWR6HFWLRQIRU IXUWKHUGHWDLOV 7DEOHVSHFLILHVWKHWROHUDQFHVRIVXSSO\UDLOV1RWHWKDWWKHVHWROHUDQFHVDUHWREH JXDUDQWHHGDWWKHFRPSRQHQWVQRWWKHVXSSO\ 7DEOH 3RZHU6XSSO\5DLO7ROHUDQFHV Power Rail Expansion Boards (Short and Long) 5 V ±5% 5 A max. (system dependent) 3.3 V ±0.3 V 7.6 A max. (system dependent) 12 V ±5% 500 mA -12 V ±10% 100 mA 4.3.4.2. Sequencing 7KHUHLVQRVSHFLILHGVHTXHQFHLQZKLFKWKHIRXUSRZHUUDLOVDUHDFWLYDWHGRUGHDFWLYDWHG 7KH\PD\FRPHXSDQGJRGRZQLQDQ\RUGHU7KHV\VWHPPXVWDVVHUWRST#ERWKDW SRZHUXSDQGZKHQHYHUHLWKHUWKH9RU9UDLOVJRRXWRIVSHFLILFDWLRQ SHU 6HFWLRQ 'XULQJUHVHWDOO3&,VLJQDOVDUHGULYHQWRDVDIHVWDWHDVGHVFULEHGLQ 6HFWLRQ 137 Revision 2.2 4.3.4.3. Decoupling $OOSRZHUSODQHVPXVWEHGHFRXSOHGWRJURXQGWRSURYLGH • UHDVRQDEOHPDQDJHPHQWRIWKHVZLWFKLQJFXUUHQWV G,GW WRZKLFKWKHSODQHDQGLWV VXSSO\SDWKDUHVXEMHFWHG • DQ$&UHWXUQSDWKLQDPDQQHUFRQVLVWHQWZLWKKLJKVSHHGVLJQDOLQJWHFKQLTXHV 7KLVLVSODWIRUPGHSHQGHQWDQGQRWGHWDLOHGLQWKHVSHFLILFDWLRQ 4.3.5. System Timing Budget :KHQFRPSXWLQJDWRWDO3&,ORDGPRGHOFDUHIXODWWHQWLRQPXVWEHSDLGWRPD[LPXP WUDFHOHQJWKDQGORDGLQJRIH[SDQVLRQERDUGVDVVSHFLILHGLQ6HFWLRQ$OVRWKH PD[LPXPSLQFDSDFLWDQFHRIS)PXVWEHDVVXPHGIRUH[SDQVLRQERDUGVZKHUHDVWKH DFWXDOSLQFDSDFLWDQFHPD\EHXVHGIRUSODQDUGHYLFHV 7KHWRWDOFORFNSHULRGFDQEHGLYLGHGLQWRIRXUVHJPHQWV9DOLGRXWSXWGHOD\ 7YDO DQG LQSXWVHWXSWLPH 7VX DUHVSHFLILHGE\WKHFRPSRQHQWVSHFLILFDWLRQ7RWDOFORFNVNHZ 7VNHZ DQGPD[LPXPEXVSURSDJDWLRQWLPH 7SURS DUHV\VWHPSDUDPHWHUV7SURSLV VSHFLILHGDVQVEXWPD\EHLQFUHDVHGWRQVE\ORZHULQJFORFNVNHZ WKDWLV7SURS SOXV7VNHZWRJHWKHUPD\QRWH[FHHGQV KRZHYHUXQGHUQRFLUFXPVWDQFHPD\7VNHZ H[FHHGQV)XUWKHUPRUHE\XVLQJFORFNUDWHVVORZHUWKDQ0+]VRPHV\VWHPVPD\ EXLOGODUJHU3&,WRSRORJLHVKDYLQJ7SURSYDOXHVODUJHUWKDQWKRVHVSHFLILHGKHUH6LQFH FRPSRQHQWWLPHV 7YDODQG7VX DQGFORFNVNHZDUHIL[HGDQ\LQFUHDVHLQFORFNF\FOH WLPHDOORZVDQHTXLYDOHQWLQFUHDVHLQ7SURS)RUH[DPSOHDW0+] QVFORFN SHULRG 7SURSPD\EHLQFUHDVHGWRQV1RWHWKDWWKLVWUDGHRIIDIIHFWVV\VWHPV PRWKHUERDUGV RQO\ DOODGGLQERDUGGHVLJQVPXVWDVVXPH0+]RSHUDWLRQ ,Q9VLJQDOLQJHQYLURQPHQWV7SURSLVPHDVXUHGDVVKRZQLQ)LJXUH,WEHJLQVDW WKHWLPHWKHVLJQDODWWKHRXWSXWEXIIHUZRXOGKDYHFURVVHGWKHWKUHVKROGSRLQW 9WHVWLQ )LJXUH KDGWKHRXWSXWEHHQGULYLQJWKHS)OXPSORDGVSHFLILHGIRU7YDO PHDVXUHPHQW7KHHQGRI7SURSIRUDQ\SDUWLFXODULQSXWLVGHWHUPLQHGE\RQHRIWKH IROORZLQJWZRPHDVXUHPHQWPHWKRGV7KHPHWKRGWKDWSURGXFHVWKHORQJHUYDOXHIRU 7SURSPXVWEHXVHG 0HWKRG 7KHHQGRI7SURSLVWKHWLPHZKHQWKHVLJQDODWWKHLQSXWFURVVHV9WHVWIRUWKH ODVWWLPH 6HH)LJXUHDG 0HWKRG &RQVWUXFWDOLQHZLWKDVORSHHTXDOWRWKH,QSXW6LJQDO(GJH5DWHVKRZQLQ 7DEOHDQGFURVVLQJWKURXJKWKHSRLQWZKHUHWKHVLJQDODWWKHLQSXW FURVVHV9LK KLJKJRLQJ RU9LO ORZJRLQJ IRUWKHODVWWLPH7KHHQGRI 7SURSLVWKHWLPHZKHQWKHFRQVWUXFWHGOLQHFURVVHV9WHVW 6HH)LJXUH EFHI 138 Revision 2.2 Implementation Note: Determining the End of Tprop 7KHHQGRI7SURSLVDOZD\VGHWHUPLQHGE\WKHFDOFXODWLRQPHWKRGWKDWSURGXFHVWKH ORQJHUYDOXHRI7SURS7KHVKDSHRIWKHZDYHIRUPDWWKHLQSXWEXIIHUZLOOGHWHUPLQH ZKLFKPHDVXUHPHQWPHWKRGZLOOSURGXFHWKHORQJHUYDOXH :KHQWKHVLJQDOULVHVRUIDOOVIURP9WHVWWRWKHODVWFURVVLQJRU9LK KLJKJRLQJ RU9LO ORZJRLQJ IDVWHUWKDQWKH,QSXW6LJQDO(GJH5DWHVKRZQLQ7DEOH0HWKRGZLOO SURGXFHWKHORQJHUYDOXH 6HH)LJXUHDG :KHQWKHVLJQDOULVHVRUIDOOVIURP9WHVWWRWKHODVWFURVVLQJRU9LK KLJKJRLQJ RU9LO ORZJRLQJ VORZHUWKDQWKH,QSXW6LJQDO(GJH5DWH0HWKRGZLOOSURGXFHWKHORQJHU YDOXH,QRWKHUZRUGVLIWKHVLJQDOSODWHDXVRUULVHV KLJKJRLQJ RUIDOOV ORZJRLQJ VORZO\DIWHUFURVVLQJ9WHVWRUULQJVEDFNDFURVV9LK KLJKJRLQJ RU9LO ORZJRLQJ VLJQLILFDQWO\DIWHUFURVVLQJ9WHVW0HWKRGZLOOSURGXFHWKHORQJHUYDOXH 6HH )LJXUHEFHI )RU9VLJQDOLQJHQYLURQPHQWV VKRZQLQ)LJXUH 7SURSLVPHDVXUHGLQDVLPLODU Ω ZD\H[FHSWWKDWWKHRXWSXWEXIIHUGULYHVWKH OXPSORDGVSHFLILHGIRU7YDO PHDVXUHPHQW,QWKLVFDVHWKHPHDVXUHPHQWRI7SURSEHJLQVDWWKHWLPHWKHRXWSXW EXIIHUZRXOGKDYHUHDFKHGWKH7YDOPHDVXUHPHQWVSHFLILFDWLRQ7DEOHVSHFLILHVWKLV SRLQWDVHLWKHU³9WULVH´IRUDULVLQJVLJQDORU³9WIDOO´IRUDIDOOLQJVLJQDO7KHHQGRIWKH 7SURSSHULRGLVPHDVXUHGXVLQJWKHVDPHWKUHVKROG 9WHVW DQGPHWKRGVDVLQWKH9 FDVH 5HIHUWR7DEOH7DEOHDQG7DEOHIRUWKHYDOXHVRISDUDPHWHUVLQ)LJXUH DQG)LJXUHLQ0+]PRGH5HIHUWR&KDSWHUIRUDGHVFULSWLRQRI0+] RSHUDWLRQ )RUDJLYHQGULYHUORFDWLRQWKHZRUVWFDVHWKDWPXVWEHFRQVLGHUHGZKHQGHWHUPLQLQJWKH YDOXHRI7SURSLVZKHQWKHVLJQDOVHWWOHVDWDOORWKHUGHYLFHVRQWKHEXV7KHYDOXHRI 7SURSLVQRWDIIHFWHGE\WKHWLPHWKHVLJQDOVHWWOHVDWWKHGULYHURXWSXWVLQFHGHYLFHVDUH QRWSHUPLWWHGWRGULYHDQGUHFHLYHDVLJQDODWWKHVDPHWLPH5HIHUWR6HFWLRQLWHP IRUDGGLWLRQDOGHWDLOV ,QPDQ\V\VWHPOD\RXWVFRUUHFW3&,VLJQDOSURSDJDWLRQUHOLHVRQGLRGHVHPEHGGHGLQ 3&,FRPSRQHQWVWROLPLWUHIOHFWLRQVDQGVXFFHVVIXOO\PHHW7SURS,QFRQILJXUDWLRQV ZKHUHXQWHUPLQDWHGWUDFHHQGVSURSDJDWHDVLJQLILFDQWGLVWDQFHIURPD3&,FRPSRQHQW HJDVHFWLRQRIXQSRSXODWHGH[SDQVLRQFRQQHFWRUV LWPD\EHQHFHVVDU\WRDGGDFWLYH HJGLRGH WHUPLQDWLRQDWWKHXQORDGHGHQGRIWKHEXVLQRUGHUWRLQVXUHDGHTXDWHVLJQDO TXDOLW\1RWHWKDWVLQFHWKHVLJQDOLQJSURWRFROGHSHQGVRQWKHLQLWLDOUHIOHFWLRQSDVVLYH WHUPLQDWLRQGRHVQRWZRUN 139 Revision 2.2 Driving Input Signal Test Load Edge Rate Vth Vth Driving Test Load Vih Vih Driving 2.0V 2.0V Bus Driving Bus Vtest Vtest 1.0V 1.0V Tprop Tprop (a) (b) Driving Vth Test Load Tprop Driving Vih 2.0V Bus 2.0V Input Vtest Signal Vtest Edge Rate Driving Bus 1.0V 1.0V Vil Tprop Vtl Driving Test Load (c) (d) Tprop Tprop 2.0V 2.0V Vtest Vtest Input Signal Input Signal Edge Rate Edge Rate Driving Test Load 1.0V 1.0V Vil Vil Driving Bus Vtl Vtl Driving Bus Driving Test Load (e) (f) )LJXUH 0HDVXUHPHQWRI7SURS9ROW6LJQDOLQJ 140 Revision 2.2 4.3.6. Physical Requirements 4.3.6.1. Routing and Layout Recommendations for Four-Layer Motherboards 7KHSRZHUSLQVKDYHEHHQDUUDQJHGRQWKHFRQQHFWRUWRIDFLOLWDWHOD\RXWVRQIRXUOD\HU PRWKHUERDUGV$VSOLWSRZHUSODQHLVSHUPLWWHGFUHDWLQJD9LVODQGLQWKH9 SODQHZKLFKFRQQHFWVDOOWKH93&,FRQQHFWRUSLQVDQGPD\RSWLRQDOO\KDYHDSRZHU GLVWULEXWLRQILQJHUUHDFKLQJWRWKHSRZHUVXSSO\FRQQHFWRU$OWKRXJKWKLVLVDVWDQGDUG WHFKQLTXHURXWLQJKLJKVSHHGVLJQDOVGLUHFWO\RYHUWKLVSODQHVSOLWFDQFDXVHVLJQDO LQWHJULW\SUREOHPV7KHVSOLWLQWKHSODQHGLVUXSWVWKH$&UHWXUQSDWKIRUWKHVLJQDO FUHDWLQJDQLPSHGDQFHGLVFRQWLQXLW\ $UHFRPPHQGHGVROXWLRQLVWRDUUDQJHWKHVLJQDOOHYHOOD\RXWVVRWKDWQRKLJKVSHHG VLJQDO HJ0+] LVUHIHUHQFHGWRERWKSODQHV6LJQDOWUDFHVVKRXOGHLWKHUUHPDLQ HQWLUHO\RYHUWKH9SODQHRUHQWLUHO\RYHUWKH9SODQH6LJQDOVWKDWPXVWFURVVIURP RQHGRPDLQWRWKHRWKHUVKRXOGEHURXWHGRQWKHRSSRVLWHVLGHRIWKHPRWKHUERDUGVRWKDW WKH\DUHUHIHUHQFHGWRWKHJURXQGSODQHZKLFKLVQRWVSOLW,IWKLVLVQRWSRVVLEOHDQG VLJQDOVPXVWEHURXWHGRYHUWKHSODQHVSOLWWKHWZRSODQHVVKRXOGEHFDSDFLWLYHO\WLHG WRJHWKHU 9SODQHGHFRXSOHGGLUHFWO\WR9SODQH ZLWKµ)KLJKVSHHGFDSDFLWRUV IRUHDFKIRXUVLJQDOVFURVVLQJWKHVSOLWDQGWKHFDSDFLWRUVKRXOGEHSODFHGQRWPRUHWKDQ LQFKHVIURPWKHSRLQWWKHVLJQDOVFURVVWKHVSOLW 7KLVUHFRPPHQGDWLRQGRHVQRWDSSO\WRVORZHUVSHHGVLJQDOVVXFKDV,6$EXVVLJQDOV 4.3.6.2. Motherboard Impedance 7KHUHLVQREDUHERDUGLPSHGDQFHVSHFLILFDWLRQIRUPRWKHUERDUGV7KHV\VWHPGHVLJQHU KDVWZRSULPDU\FRQVWUDLQWVLQZKLFKWRZRUN • 7KHOHQJWKDQGVLJQDOYHORFLW\PXVWDOORZDIXOOURXQGWULSWLPHRQWKHEXVZLWKLQWKH VSHFLILHGSURSDJDWLRQGHOD\RIQV 5HIHUWR6HFWLRQ • 7KHORDGHGLPSHGDQFHVHHQDWDQ\GULYHSRLQWRQWKHQHWZRUNPXVWEHVXFKWKDWD 3&,RXWSXWGHYLFH DVVSHFLILHGE\LWV9,FXUYH FDQPHHWLQSXWGHYLFHVSHFLILFDWLRQV ZLWKDVLQJOHUHIOHFWLRQRIWKHVLJQDO7KLVLQFOXGHVORDGVSUHVHQWHGE\H[SDQVLRQ ERDUGV 2SHUDWLQJIUHTXHQF\PD\EHWUDGHGRIIIRUDGGLWLRQDOURXQGWULSVRQWKHEXVWREXLOG FRQILJXUDWLRQVWKDWPLJKWQRWFRPSO\ZLWKWKHWZRFRQVWUDLQWVPHQWLRQHGDERYH7KLV RSWLRQLVQHLWKHUUHFRPPHQGHGQRUVSHFLILFDOO\SUHFOXGHG 141 Revision 2.2 4.3.7. Connector Pin Assignments 7KH3&,FRQQHFWRUFRQWDLQVDOOWKHVLJQDOVGHILQHGIRU3&,FRPSRQHQWVSOXVWZRSLQV WKDWDUHUHODWHGWRWKHFRQQHFWRURQO\7KHVHSLQVPRSNT1#DQGPRSNT2#DUH GHVFULEHGLQ6HFWLRQ0RWKHUERDUGVPXVWGHFRXSOHERWKRIWKHVHSLQVLQGLYLGXDOO\ WRJURXQGZLWKµ)KLJKVSHHGFDSDFLWRUVEHFDXVHRQHRUERWKRIWKHSLQVDOVR SURYLGHDQ$&UHWXUQSDWK7KHVHSLQVPD\QRWEHEXVHGRURWKHUZLVHFRQQHFWHGWRHDFK RWKHURQWKHPRWKHUERDUG)XUWKHUXVHRIWKHVHSLQVRQWKHPRWKHUERDUGLVRSWLRQDO,I WKHPRWKHUERDUGGHVLJQDFFHVVHVWKHVHSLQVWRREWDLQERDUGLQIRUPDWLRQHDFKSLQPXVW KDYHDQDSSURSULDWHSXOOXSUHVLVWRU RIDSSUR[LPDWHO\.Ω RQWKHPRWKHUERDUG7KH FRQQHFWRUSLQDVVLJQPHQWVDUHVKRZQLQ7DEOH3LQVODEHOHG³5HVHUYHG´PXVWEH OHIWXQFRQQHFWHGRQDOOFRQQHFWRUV 3LQ %LVDVSHFLDOSXUSRVHSLQWKDWKDVORJLFDOVLJQLILFDQFHLQ0+]FDSDEOH V\VWHPVDQGLQVXFKV\VWHPVLWPXVWEHVHSDUDWHO\EXVHGSXOOHGXSDQGGHFRXSOHGDV GHVFULEHGLQ6HFWLRQ)RUDOORWKHU3&,FRQQHFWRUVWKLVSLQPXVWEHWUHDWHGLQDOO UHVSHFWVDVDVWDQGDUGJURXQGSLQ LHWKHFRQQHFWRUSLQPXVWEHFRQQHFWHGWRWKHJURXQG SODQH 142 Revision 2.2 7DEOH 3&,&RQQHFWRU3LQRXW 5V System Environment 3.3V System Environment Pin Side B Side A Side B Side A Comments 1 -12V TRST# -12V TRST# 32-bit connector start 2 TCK +12V TCK +12V 3 Ground TMS Ground TMS 4 TDO TDI TDO TDI 5 +5V +5V +5V +5V 6 +5V INTA# +5V INTA# 7 INTB# INTC# INTB# INTC# 8 INTD# +5V INTD# +5V 9 PRSNT1# Reserved PRSNT1# Reserved 10 Reserved +5V (I/O) Reserved +3.3V (I/O) 11 PRSNT2# Reserved PRSNT2# Reserved 12 Ground Ground CONNECTOR KEY 3.3 volt key 13 Ground Ground CONNECTOR KEY 3.3 volt key 14 Reserved 3.3Vaux Reserved 3.3Vaux 15 Ground RST# Ground RST# 16 CLK +5V (I/O) CLK +3.3V (I/O) 17 Ground GNT# Ground GNT# 18 REQ# Ground REQ# Ground 19 +5V (I/O) PME# +3.3V (I/O) PME# 20 AD[31] AD[30] AD[31] AD[30] 21 AD[29] +3.3V AD[29] +3.3V 22 Ground AD[28] Ground AD[28] 23 AD[27] AD[26] AD[27] AD[26] 24 AD[25] Ground AD[25] Ground 25 +3.3V AD[24] +3.3V AD[24] 26 C/BE[3]# IDSEL C/BE[3]# IDSEL 27 AD[23] +3.3V AD[23] +3.3V 28 Ground AD[22] Ground AD[22] 29 AD[21] AD[20] AD[21] AD[20] 30 AD[19] Ground AD[19] Ground 31 +3.3V AD[18] +3.3V AD[18] 32 AD[17] AD[16] AD[17] AD[16] 33 C/BE[2]# +3.3V C/BE[2]# +3.3V 34 Ground FRAME# Ground FRAME# 35 IRDY# Ground IRDY# Ground 36 +3.3V TRDY# +3.3V TRDY# 37 DEVSEL# Ground DEVSEL# Ground 38 Ground STOP# Ground STOP# 39 LOCK# +3.3V LOCK# +3.3V 40 PERR# Reserved* PERR# Reserved* 41 +3.3V Reserved* +3.3V Reserved* 42 SERR# Ground SERR# Ground 7KLVSLQZDVXVHGLQSUHYLRXVYHUVLRQVRIWKLVVSHFLILFDWLRQDQGPD\KDYHEHHQEXVHGWRRWKHU FRQQHFWRUVDQGSXOOHGXS7REHFRPSODLQWZLWKWKLVYHUVLRQRIWKHVSHFLILFDWLRQWKLVSLQPXVWEH OHIWXQFRQQHFWHG HJQRWEXVHGRUSXOOHGXS 143 Revision 2.2 7DEOH 3&,&RQQHFWRU3LQRXW FRQWLQXHG 5V System Environment 3.3V System Environment Pin Side B Side A Side B Side A Comments 43 +3.3V PAR +3.3V PAR 44 C/BE[1]# AD[15] C/BE[1]# AD[15] 45 AD[14] +3.3V AD[14] +3.3V 46 Ground AD[13] Ground AD[13] 47 AD[12] AD[11] AD[12] AD[11] 48 AD[10] Ground AD[10] Ground 49 Ground AD[09] M66EN AD[09] 66 MHz / gnd 50 CONNECTOR KEY Ground Ground 5 volt key 51 CONNECTOR KEY Ground Ground 5 volt key 52 AD[08] C/BE[0]# AD[08] C/BE[0]# 53 AD[07] +3.3V AD[07] +3.3V 54 +3.3V AD[06] +3.3V AD[06] 55 AD[05] AD[04] AD[05] AD[04] 56 AD[03] Ground AD[03] Ground 57 Ground AD[02] Ground AD[02] 58 AD[01] AD[00] AD[01] AD[00] 59 +5V (I/O) +5V (I/O) +3.3V (I/O) +3.3V (I/O) 60 ACK64# REQ64# ACK64# REQ64# 61 +5V +5V +5V +5V 62 +5V +5V +5V +5V 32-bit connector end CONNECTOR KEY CONNECTOR KEY 64-bit spacer CONNECTOR KEY CONNECTOR KEY 64-bit spacer 63 Reserved Ground Reserved Ground 64-bit connector start 64 Ground C/BE[7]# Ground C/BE[7]# 65 C/BE[6]# C/BE[5]# C/BE[6]# C/BE[5]# 66 C/BE[4]# +5V (I/O) C/BE[4]# +3.3V (I/O) 67 Ground PAR64 Ground PAR64 68 AD[63] AD[62] AD[63] AD[62] 69 AD[61] Ground AD[61] Ground 70 +5V (I/O) AD[60] +3.3V (I/O) AD[60] 71 AD[59] AD[58] AD[59] AD[58] 72 AD[57] Ground AD[57] Ground 73 Ground AD[56] Ground AD[56] 74 AD[55] AD[54] AD[55] AD[54] 75 AD[53] +5V (I/O) AD[53] +3.3V (I/O) 76 Ground AD[52] Ground AD[52] 77 AD[51] AD[50] AD[51] AD[50] 78 AD[49] Ground AD[49] Ground 79 +5V (I/O) AD[48] +3.3V (I/O) AD[48] 80 AD[47] AD[46] AD[47] AD[46] 81 AD[45] Ground AD[45] Ground 82 Ground AD[44] Ground AD[44] 144 Revision 2.2 7DEOH 3&,&RQQHFWRU3LQRXW FRQWLQXHG 5V System Environment 3.3V System Environment Pin Side B Side A Side B Side A Comments 83 AD[43] AD[42] AD[43] AD[42] 84 AD[41] +5V (I/O) AD[41] +3.3V (I/O) 85 Ground AD[40] Ground AD[40] 86 AD[39] AD[38] AD[39] AD[38] 87 AD[37] Ground AD[37] Ground 88 +5V (I/O) AD[36] +3.3V (I/O) AD[36] 89 AD[35] AD[34] AD[35] AD[34] 90 AD[33] Ground AD[33] Ground 91 Ground AD[32] Ground AD[32] 92 Reserved Reserved Reserved Reserved 93 Reserved Ground Reserved Ground 94 Ground Reserved Ground Reserved 64-bit connector end ,2 ,2 3LQVODEHOHG9 DQG9 DUHVSHFLDOSRZHUSLQVIRUGHILQLQJDQGGULYLQJ WKH3&,VLJQDOLQJUDLORQWKH8QLYHUVDO%RDUG2QWKHPRWKHUERDUGWKHVHSLQVDUH FRQQHFWHGWRWKHPDLQ9RU9SODQHUHVSHFWLYHO\ 5HIHUWR6HFWLRQIRUVSHFLDOUHTXLUHPHQWVIRUWKHFRQQHFWLRQRIREQ64#RQ ELWRQO\H[SDQVLRQVORWFRQQHFWRUV 145 Revision 2.2 4.4. Expansion Board Specification 4.4.1. Board Pin Assignment 7KH3&,FRQQHFWRUFRQWDLQVDOOWKHVLJQDOVGHILQHGIRU3&,FRPSRQHQWVSOXVWZRSLQV WKDWDUHUHODWHGWRWKHFRQQHFWRURQO\7KHVHDUHPRSNT1#DQGPRSNT2#7KH\DUH XVHGIRUWZRSXUSRVHV LQGLFDWLQJWKDWDQH[SDQVLRQERDUGLVSK\VLFDOO\SUHVHQWLQWKH VORWDQGSURYLGLQJLQIRUPDWLRQDERXWWKHWRWDOSRZHUUHTXLUHPHQWVRIWKHERDUG 7DEOHGHILQHVWKHUHTXLUHGVHWWLQJRIWKHPRSNT#SLQVIRUH[SDQVLRQERDUGV 7DEOH 3UHVHQW6LJQDO'HILQLWLRQV PRSNT1# PRSNT2# Expansion Configuration Open Open No expansion board present Ground Open Expansion board present, 25 W maximum Open Ground Expansion board present, 15 W maximum Ground Ground Expansion board present, 7.5 W maximum ,QSURYLGLQJDSRZHUOHYHOLQGLFDWLRQWKHH[SDQVLRQERDUGPXVWLQGLFDWHWRWDOPD[LPXP SRZHUFRQVXPSWLRQIRUWKHERDUGLQFOXGLQJDOOVXSSO\YROWDJHV7KHH[SDQVLRQERDUGV PD\RSWLRQDOO\GUDZDOOWKLVSRZHUIURPHLWKHUWKH9RU9SRZHUUDLO)XUWKHUPRUH LIWKHH[SDQVLRQERDUGLVFRQILJXUDEOH HJVRFNHWVIRUPHPRU\H[SDQVLRQHWF WKHSLQ VWUDSSLQJPXVWLQGLFDWHWKHWRWDOSRZHUFRQVXPHGE\DIXOO\FRQILJXUHGERDUGZKLFK PD\EHPRUHWKDQWKDWFRQVXPHGLQLWVVKLSSLQJFRQILJXUDWLRQ ([SDQVLRQERDUGVWKDWGRQRWLPSOHPHQW-7$*%RXQGDU\6FDQDUHUHTXLUHGWRFRQQHFW TDIDQGTDO SLQV$DQG% VRWKHVFDQFKDLQLVQRWEURNHQ 3LQ %LVDVSHFLDOSXUSRVHSLQWKDWKDVORJLFDOVLJQLILFDQFHLQ0+]FDSDEOH H[SDQVLRQERDUGVDQGLQVXFKERDUGVLWPXVWEHFRQQHFWHGDQGGHFRXSOHGDVGHVFULEHG LQ6HFWLRQ)RUDOORWKHUH[SDQVLRQERDUGVWKLVSLQPXVWEHWUHDWHGLQDOOUHVSHFWVDV DVWDQGDUGJURXQGSLQ LHWKHHGJHILQJHUPXVWEHSODWHGDQGFRQQHFWHGWRWKHJURXQG SODQHRIWKHH[SDQVLRQERDUG 146 Revision 2.2 7DEOH 3&,([SDQVLRQ%RDUG3LQRXW 5V Board Universal Board 3.3V Board Pin Side B Side A Side B Side A Side B Side A Comments 1 -12V TRST# -12V TRST# -12V TRST# 32-bit start 2 TCK +12V TCK +12V TCK +12V 3 Ground TMS Ground TMS Ground TMS 4 TDO TDI TDO TDI TDO TDI 5 +5V +5V +5V +5V +5V +5V 6 +5V INTA# +5V INTA# +5V INTA# 7 INTB# INTC# INTB# INTC# INTB# INTC# 8 INTD# +5V INTD# +5V INTD# +5V 9 PRSNT1# Reserved PRSNT1# Reserved PRSNT1# Reserved 10 Reserved +5V Reserved +VI/O Reserved +3.3V 11 PRSNT2# Reserved PRSNT2# Reserved PRSNT2# Reserved 12 Ground Ground KEYWAY KEYWAY 3.3V key 13 Ground Ground KEYWAY KEYWAY 3.3V key 14 Reserved 3.3Vaux Reserved 3.3Vaux Reserved 3.3Vaux 15 Ground RST# Ground RST# Ground RST# 16 CLK +5V CLK +VI/O CLK +3.3V 17 Ground GNT# Ground GNT# Ground GNT# 18 REQ# Ground REQ# Ground REQ# Ground 19 +5V PME# +VI/O PME# +3.3V PME# 20 AD[31] AD[30] AD[31] AD[30] AD[31] AD[30] 21 AD[29] +3.3V AD[29] +3.3V AD[29] +3.3V 22 Ground AD[28] Ground AD[28] Ground AD[28] 23 AD[27] AD[26] AD[27] AD[26] AD[27] AD[26] 24 AD[25] Ground AD[25] Ground AD[25] Ground 25 +3.3V AD[24] +3.3V AD[24] +3.3V AD[24] 26 C/BE[3]# IDSEL C/BE[3]# IDSEL C/BE[3]# IDSEL 27 AD[23] +3.3V AD[23] +3.3V AD[23] +3.3V 28 Ground AD[22] Ground AD[22] Ground AD[22] 29 AD[21] AD[20] AD[21] AD[20] AD[21] AD[20] 30 AD[19] Ground AD[19] Ground AD[19] Ground 31 +3.3V AD[18] +3.3V AD[18] +3.3V AD[18] 32 AD[17] AD[16] AD[17] AD[16] AD[17] AD[16] 33 C/BE[2]# +3.3V C/BE[2]# +3.3V C/BE[2]# +3.3V 34 Ground FRAME# Ground FRAME# Ground FRAME# 35 IRDY# Ground IRDY# Ground IRDY# Ground 36 +3.3V TRDY# +3.3V TRDY# +3.3V TRDY# 37 DEVSEL# Ground DEVSEL# Ground DEVSEL# Ground 38 Ground STOP# Ground STOP# Ground STOP# 39 LOCK# +3.3V LOCK# +3.3V LOCK# +3.3V 40 PERR# Reserved PERR# Reserved PERR# Reserved 41 +3.3V Reserved +3.3V Reserved +3.3V Reserved 42 SERR# Ground SERR# Ground SERR# Ground 147 Revision 2.2 7DEOH 3&,([SDQVLRQ%RDUG3LQRXW FRQWLQXHG 5V Board Universal Board 3.3V Board Pin Side B Side A Side B Side A Side B Side A Comments 43 +3.3V PAR +3.3V PAR +3.3V PAR 44 C/BE[1]# AD[15] C/BE[1]# AD[15] C/BE[1]# AD[15] 45 AD[14] +3.3V AD[14] +3.3V AD[14] +3.3V 46 Ground AD[13] Ground AD[13] Ground AD[13] 47 AD[12] AD[11] AD[12] AD[11] AD[12] AD[11] 48 AD[10] Ground AD[10] Ground AD[10] Ground 49 Ground AD[09] M66EN AD[09] M66EN AD[09] 66 MHz /gnd 50 KEYWAY KEYWAY Ground Ground 5V key 51 KEYWAY KEYWAY Ground Ground 5V key 52 AD[08] C/BE[0]# AD[08] C/BE[0]# AD[08] C/BE[0]# 53 AD[07] +3.3V AD[07] +3.3V AD[07] +3.3V 54 +3.3V AD[06] +3.3V AD[06] +3.3V AD[06] 55 AD[05] AD[04] AD[05] AD[04] AD[05] AD[04] 56 AD[03] Ground AD[03] Ground AD[03] Ground 57 Ground AD[02] Ground AD[02] Ground AD[02] 58 AD[01] AD[00] AD[01] AD[00] AD[01] AD[00] 59 +5V +5V +VI/O +VI/O +3.3V +3.3V 60 ACK64# REQ64# ACK64# REQ64# ACK64# REQ64# 61 +5V +5V +5V +5V +5V +5V 62 +5V +5V +5V +5V +5V +5V 32-bit end KEYWAY KEYWAY KEYWAY 64-bit spacer KEYWAY KEYWAY KEYWAY 64-bit spacer 63 Reserved Ground Reserved Ground Reserved Ground 64-bit start 64 Ground C/BE[7]# Ground C/BE[7]# Ground C/BE[7]# 65 C/BE[6]# C/BE[5]# C/BE[6]# C/BE[5]# C/BE[6]# C/BE[5]# 66 C/BE[4]# +5V C/BE[4]# +VI/O C/BE[4]# +3.3V 67 Ground PAR64 Ground PAR64 Ground PAR64 68 AD[63] AD[62] AD[63] AD[62] AD[63] AD[62] 69 AD[61] Ground AD[61] Ground AD[61] Ground 70 +5V AD[60] +VI/O AD[60] +3.3V AD[60] 71 AD[59] AD[58] AD[59] AD[58] AD[59] AD[58] 72 AD[57] Ground AD[57] Ground AD[57] Ground 73 Ground AD[56] Ground AD[56] Ground AD[56] 74 AD[55] AD[54] AD[55] AD[54] AD[55] AD[54] 75 AD[53] +5V AD[53] +VI/O AD[53] +3.3V 76 Ground AD[52] Ground AD[52] Ground AD[52] 77 AD[51] AD[50] AD[51] AD[50] AD[51] AD[50] 78 AD[49] Ground AD[49] Ground AD[49] Ground 79 +5V AD[48] +VI/O AD[48] +3.3V AD[48] 80 AD[47] AD[46] AD[47] AD[46] AD[47] AD[46] 81 AD[45] Ground AD[45] Ground AD[45] Ground 82 Ground AD[44] Ground AD[44] Ground AD[44] 148 Revision 2.2 7DEOH 3&,([SDQVLRQ%RDUG3LQRXW FRQWLQXHG 5V Board Universal Board 3.3V Board Pin Side B Side A Side B Side A Side B Side A Comments 83 AD[43] AD[42] AD[43] AD[42] AD[43] AD[42] 84 AD[41] +5V AD[41] +VI/O AD[41] +3.3V 85 Ground AD[40] Ground AD[40] Ground AD[40] 86 AD[39] AD[38] AD[39] AD[38] AD[39] AD[38] 87 AD[37] Ground AD[37] Ground AD[37] Ground 88 +5V AD[36] +VI/O AD[36] +3.3V AD[36] 89 AD[35] AD[34] AD[35] AD[34] AD[35] AD[34] 90 AD[33] Ground AD[33] Ground AD[33] Ground 91 Ground AD[32] Ground AD[32] Ground AD[32] 92 Reserved Reserved Reserved Reserved Reserved Reserved 93 Reserved Ground Reserved Ground Reserved Ground 94 Ground Reserved Ground Reserved Ground Reserved 64-bit end 7DEOH 3LQ6XPPDU\ELW([SDQVLRQ%RDUG Pin Type 5V Board Universal Board 3.3V Board Ground 22 18 (Note) 22 (Note) +5 V 13 8 8 +3.3 V 12 12 17 I/O pwr 0 5 0 Reserv'd 4 4 4 NOTE: If the M66EN pin is implemented, the number of ground pins for a Universal board is 17 and the number of ground pins for a 3.3V board is 21. 7DEOH 3LQ6XPPDU\ELW%RDUG LQFUHPHQWDOSLQV Pin Type 5V Board Universal Board 3.3V Board Ground 16 16 16 +5 V 6 0 0 +3.3 V 0 0 6 I/O pwr 0 6 0 Reserv'd 5 5 5 149 Revision 2.2 3LQVODEHOHG9,2DUHVSHFLDOSRZHUSLQVIRUGHILQLQJDQGGULYLQJWKH3&,VLJQDOLQJ UDLORQWKH8QLYHUVDO%RDUG2QWKLVERDUGWKH3&,FRPSRQHQW V,2EXIIHUVPXVWEH SRZHUHGIURPWKHVHVSHFLDOSRZHUSLQVRQO\ ²QRWIURPWKHRWKHU9RU9SRZHU SLQV 4.4.2. Power Requirements 4.4.2.1. Decoupling 8QGHUW\SLFDOFRQGLWLRQVWKH9FFSODQHWRJURXQGSODQHFDSDFLWDQFHZLOOSURYLGH DGHTXDWHGHFRXSOLQJIRUWKH9FFFRQQHFWRUSLQV7KHPD[LPXPWUDFHOHQJWKIURPD FRQQHFWRUSDGWRWKH9FF*1'SODQHYLDVKDOOEHLQFKHV DVVXPHVDPLOWUDFH ZLGWK +RZHYHURQWKH8QLYHUVDOERDUGLWLVOLNHO\WKDWWKH,2EXIIHUSRZHUUDLOZLOOQRWKDYH DGHTXDWHFDSDFLWDQFHWRWKHJURXQGSODQHWRSURYLGHWKHQHFHVVDU\GHFRXSOLQJ3LQV ODEHOHG9,2VKRXOGEHGHFRXSOHGWRJURXQGZLWKDQDYHUDJHRIµ)SHUSLQ $GGLWLRQDOO\DOO9SLQV HYHQLIWKH\DUHQRWDFWXDOO\GHOLYHULQJSRZHU DQGDQ\ XQXVHG9DQG9,2SLQVRQWKH3&,HGJHFRQQHFWRUSURYLGHDQ$&UHWXUQSDWKDQG PXVWKDYHSODWHGHGJHILQJHUVDQGEHFRXSOHGWRWKHJURXQGSODQHRQWKHH[SDQVLRQERDUG DVGHVFULEHGEHORZWRHQVXUHWKH\FRQWLQXHWRIXQFWLRQDVHIILFLHQW$&UHIHUHQFHSRLQWV µ 7KHGHFRXSOLQJPXVWDYHUDJHDWOHDVW ) KLJKVSHHG SHU9FFSLQ 7KHWUDFHOHQJWKIURPSLQSDGWRFDSDFLWRUSDGVKDOOEHQRJUHDWHUWKDQLQFKHV XVLQJDWUDFHZLGWKRIDWOHDVWLQFKHV 7KHUHLVQROLPLWWRWKHQXPEHURISLQVWKDWFDQVKDUHWKHVDPHFDSDFLWRUSURYLGHG WKDWUHTXLUHPHQWVDQGDUHPHW 4.4.2.2. Power Consumption 7KHPD[LPXPSRZHUDOORZHGIRUDQ\3&,ERDUGLVZDWWVDQGUHSUHVHQWVWKHWRWDO SRZHUGUDZQIURPDOOSRZHUUDLOVSURYLGHGDWWKHFRQQHFWRU 999,29 99DX[ 7KHH[SDQVLRQERDUGPD\RSWLRQDOO\GUDZDOOWKLVSRZHUIURPHLWKHU WKH9RU9UDLO ,WLVDQWLFLSDWHGWKDWPDQ\V\VWHPVZLOOQRWSURYLGHDIXOOZDWWVSHUFRQQHFWRUIRUHDFK SRZHUUDLOEHFDXVHPRVWERDUGVZLOOW\SLFDOO\GUDZPXFKOHVVWKDQWKLVDPRXQW)RUWKLV UHDVRQLWLVUHFRPPHQGHGWKDW3&,ERDUGVWKDWFRQVXPHPRUHWKDQZDWWVSRZHUXSLQ 35 While the primary goal of the PCI 5V to 3.3V transition strategy is to spare vendors the burden and expense of implementing 3.3V parts that are "5V tolerant," such parts are not excluded. If a PCI component of this type is used on the Universal Board, its I/O buffers may optionally be connected to the 3.3V rail rather than the "I/O" designated power pins; but high clamp diodes must still be connected to the "I/O" designated power pins. (Refer to the last paragraph of Section 4.2.1.2. - "Clamping directly to the 3.3V rail with a simple diode must never be used in the 5V signaling environment.") Since the effective operation of these high clamp diodes may be critical to both signal quality and device reliability, the designer must provide enough extra "I/O" designated power pins on a component to handle the current spikes associated with the 5V maximum AC waveforms (Section 4.2.1.3.). 150 Revision 2.2 DQGUHVHWWRDUHGXFHGSRZHUVWDWHWKDWFRQVXPHVZDWWVRUOHVV:KLOHLQWKLVVWDWHWKH ERDUGPXVWSURYLGHIXOODFFHVVWRLWV3&,&RQILJXUDWLRQ6SDFHDQGPXVWSHUIRUPUHTXLUHG ERRWVWUDSIXQFWLRQVVXFKDVEDVLFWH[WPRGHRQDYLGHRERDUG$OORWKHUERDUGIXQFWLRQV FDQEHVXVSHQGHGLIQHFHVVDU\7KLVSRZHUVDYLQJVWDWHFDQEHDFKLHYHGLQDYDULHW\RI ZD\V)RUH[DPSOH • &ORFNUDWHVRQWKHERDUGFDQEHUHGXFHGZKLFKUHGXFHVSHUIRUPDQFHEXWGRHVQRW OLPLWIXQFWLRQDOLW\ • 3RZHUSODQHVWRQRQFULWLFDOSDUWVFRXOGEHVKXWRIIZLWKD)(7ZKLFKFRXOGOLPLW IXQFWLRQDOFDSDELOLW\ $IWHUWKHGULYHUIRUWKHERDUGKDVEHHQLQLWLDOL]HGLWPD\SODFHWKHERDUGLQWRDIXOO\ SRZHUHGIXOOIXQFWLRQSHUIRUPDQFHVWDWHXVLQJDGHYLFHGHSHQGHQWPHFKDQLVPRIFKRLFH SUREDEO\UHJLVWHUEDVHG ,QDGYDQFHGSRZHUPDQDJHGV\VWHPVWKHGHYLFHGULYHUPD\ EHUHTXLUHGWRUHSRUWWKHWDUJHWSRZHUFRQVXPSWLRQEHIRUHIXOO\HQDEOLQJWKHERDUGLQ RUGHUWRDOORZWKHV\VWHPWRGHWHUPLQHLILWKDVDVXIILFLHQWSRZHUEXGJHWIRUDOOERDUGVLQ WKHFXUUHQWFRQILJXUDWLRQ7KHGULYHUPXVWEHDEOHWRDFFXUDWHO\GHWHUPLQHWKHPD[LPXP SRZHUUHTXLUHPHQWVIRULWVERDUGDVFXUUHQWO\FRQILJXUHGDQGIURPZKLFKUDLO V WKLV SRZHUZLOOEHGUDZQ ([SDQVLRQERDUGVPXVWQHYHUVRXUFHDQ\SRZHUEDFNWRWKHV\VWHPERDUGH[FHSWLQWKH FDVHZKHUHDQH[SDQVLRQERDUGKDVEHHQVSHFLILFDOO\GHVLJQHGWRSURYLGHDJLYHQ V\VWHP¶VSRZHU,QVRPHFDVHVERDUGVFDSDEOHRI93&,VLJQDOLQJKDYHPXOWLSOH PHFKDQLVPVWKDWLQGLUHFWO\VRXUFHSRZHUEDFNWRWKHV\VWHPDQGZLOOYLRODWHWKLV UHTXLUHPHQWLIQRWSURSHUO\FRQWUROOHG)RUH[DPSOHERDUGVFRQWDLQLQJFRPSRQHQWVZLWK EXVFODPSVWRWKH9UDLOPD\FUHDWHD³FKDUJHSXPS´ZKLFKGLUHFWVH[FHVVEXV VZLWFKLQJHQHUJ\EDFNLQWRWKHV\VWHPERDUG$OWHUQDWHO\,2RXWSXWEXIIHUVRSHUDWLQJ RQWKH9UDLOEXWXVHGLQD9VLJQDOLQJHQYLURQPHQWPD\EOHHGWKHH[FHVVFKDUJH RIIWKHEXVDQGLQWRWKH9SRZHUQHWZKHQWKH\GULYHWKHEXV³KLJK´DIWHULWZDV SUHYLRXVO\GULYHQWRWKH9UDLO8QLQWHQWLRQDOSRZHUVRXUFLQJE\DQ\VXFKPHFKDQLVP PXVWEHPDQDJHGE\SURSHUGHFRXSOLQJDQGVXIILFLHQWORFDOORDGRQWKHVXSSO\ EOHHG UHVLVWRURURWKHUZLVH WRGLVVLSDWHDQ\SRZHU³JHQHUDWHG´RQWKHH[SDQVLRQERDUG7KLV UHTXLUHPHQWGRHVQRWDSSO\WRQRLVHJHQHUDWHGRQWKHSRZHUUDLODVORQJDVWKHQHW'& FXUUHQWDFFXPXODWHGRYHUDQ\WZRFORFNSHULRGVLV]HUR 4.4.3. Physical Requirements 4.4.3.1. Trace Length Limits 7UDFHOHQJWKVIURPWKHWRSRIWKHH[SDQVLRQERDUG¶VHGJHFRQQHFWRUWRWKH3&,GHYLFHDUH DVIROORZV • 7KHPD[LPXPWUDFHOHQJWKVIRUDOOELWLQWHUIDFHVLJQDOVDUHOLPLWHGWRLQFKHV IRUELWDQGELWH[SDQVLRQERDUGV7KLVLQFOXGHVDOOVLJQDOJURXSV UHIHUWR 6HFWLRQ H[FHSWWKRVHOLVWHGDV6\VWHP3LQV,QWHUUXSW3LQVDQG-7$* 3LQV • 7KHWUDFHOHQJWKVRIWKHDGGLWLRQDOVLJQDOVXVHGLQWKHELWH[WHQVLRQDUHOLPLWHGWR LQFKHVRQDOOELWH[SDQVLRQERDUGV • 7KHWUDFHOHQJWKIRUWKH3&,CLKVLJQDOLVLQFKHVLQFKHVIRUELWDQG ELWH[SDQVLRQERDUGVDQGPXVWEHURXWHGWRRQO\RQHORDG 151 Revision 2.2 4.4.3.2. Routing Recommendations for Four-Layer Expansion Boards 7KHSRZHUSLQVKDYHEHHQDUUDQJHGRQWKHFRQQHFWRUWRIDFLOLWDWHOD\RXWVRQIRXUOD\HU ERDUGV$VSOLWSRZHUSODQHLVSHUPLWWHGDVGHVFULEHGLQ6HFWLRQ$OWKRXJK WKLVLVDVWDQGDUGWHFKQLTXHURXWLQJKLJKVSHHGVLJQDOVGLUHFWO\RYHUWKLVSODQHVSOLWFDQ FDXVHVLJQDOLQWHJULW\SUREOHPV7KHVSOLWLQWKHSODQHGLVUXSWVWKH$&UHWXUQSDWKIRUWKH VLJQDOFUHDWLQJDQLPSHGDQFHGLVFRQWLQXLW\ $UHFRPPHQGHGVROXWLRQLVWRDUUDQJHWKHVLJQDOOHYHOOD\RXWVVRWKDWQRKLJKVSHHG VLJQDO HJ0+] LVUHIHUHQFHGWRERWKSODQHV6LJQDOWUDFHVVKRXOGHLWKHUUHPDLQ HQWLUHO\RYHUWKH9SODQHRUHQWLUHO\RYHUWKH9SODQH6LJQDOVWKDWPXVWFURVVIURP RQHGRPDLQWRWKHRWKHUVKRXOGEHURXWHGRQWKHRSSRVLWHVLGHRIWKHERDUGVRWKDWWKH\ DUHUHIHUHQFHGWRWKHJURXQGSODQHZKLFKLVQRWVSOLW,IWKLVLVQRWSRVVLEOHDQGVLJQDOV PXVWEHURXWHGRYHUWKHSODQHVSOLWWKHWZRSODQHVVKRXOGEHFDSDFLWLYHO\WLHGWRJHWKHU 9SODQHGHFRXSOHGGLUHFWO\WR9SODQH ZLWKµ)KLJKVSHHGFDSDFLWRUVIRUHDFK IRXUVLJQDOVFURVVLQJWKHVSOLWDQGWKHFDSDFLWRUVKRXOGEHSODFHGQRWPRUHWKDQ LQFKHVIURPWKHSRLQWWKHVLJQDOVFURVVWKHVSOLW 4.4.3.3. Impedance 7KHXQORDGHGFKDUDFWHULVWLFLPSHGDQFH = RIWKHVKDUHG3&,VLJQDOWUDFHVRQWKH H[SDQVLRQERDUGVKDOOEHFRQWUROOHGWREHLQWKHΩΩUDQJH7KHWUDFHYHORFLW\ PXVWEHEHWZHHQSVLQFKDQG SVLQFK 4.4.3.4. Signal Loading 6KDUHG3&,VLJQDOVPXVWEHOLPLWHGWRRQHORDGRQWKHH[SDQVLRQERDUG9LRODWLRQRI H[SDQVLRQERDUGWUDFHOHQJWKRUORDGLQJOLPLWVZLOOFRPSURPLVHV\VWHPVLJQDOLQWHJULW\ ,WLVVSHFLILFDOO\DYLRODWLRQRIWKLVVSHFLILFDWLRQIRUH[SDQVLRQERDUGVWR • $WWDFKDQH[SDQVLRQ520GLUHFWO\ RUYLDEXVWUDQVFHLYHUV RQDQ\3&,SLQV • $WWDFKWZRRUPRUH3&,GHYLFHVRQDQH[SDQVLRQERDUGXQOHVVWKH\DUHSODFHG EHKLQGD3&,WR3&,EULGJH • $WWDFKDQ\ORJLF RWKHUWKDQDVLQJOH3&,GHYLFH WKDWVQRRSV3&,SLQV • 8VH3&,FRPSRQHQWVHWVWKDWSODFHPRUHWKDQRQHORDGRQHDFK3&,SLQ HJ VHSDUDWHDGGUHVVDQGGDWDSDWKFRPSRQHQWV • 8VHD3&,FRPSRQHQWWKDWKDVPRUHWKDQS)FDSDFLWDQFHSHUSLQ • $WWDFKDQ\SXOOXSUHVLVWRUVRURWKHUGLVFUHWHGHYLFHVWRWKH3&,VLJQDOVXQOHVVWKH\ DUHSODFHGEHKLQGD3&,WR3&,EULGJH 152 Revision 2.2 Chapter 5 Mechanical Specification 5.1. Overview 7KH3&,H[SDQVLRQFDUGLVEDVHGRQDUDZFDUGGHVLJQ VHH)LJXUHVWR WKDWLV HDVLO\LPSOHPHQWHGLQH[LVWLQJFKDVVLVGHVLJQVIURPPXOWLSOHPDQXIDFWXUHUV7KHFDUG GHVLJQDGDSWVWR,6$(,6$DQG0&V\VWHPV3&,H[SDQVLRQFDUGVKDYHWZREDVLFIRUP IDFWRUV VWDQGDUGOHQJWKDQGVKRUWOHQJWK7KHVWDQGDUGOHQJWKFDUGSURYLGHV VTXDUH LQFKHVRIUHDOHVWDWH7KHIL[HGDQGYDULDEOHKHLJKWVKRUWOHQJWKFDUGVZHUHFKRVHQIRU SDQHORSWLPL]DWLRQWRSURYLGHWKHORZHVWFRVWIRUDIXQFWLRQ7KHIL[HGDQGYDULDEOH KHLJKWVKRUWFDUGVDOVRSURYLGHWKHORZHVWFRVWWRLPSOHPHQWLQDV\VWHPWKHORZHVW HQHUJ\FRQVXPSWLRQDQGDOORZWKHGHVLJQRIVPDOOHUV\VWHPV7KHLQWHUFRQQHFWIRUWKH 3&,H[SDQVLRQFDUGKDVEHHQGHILQHGIRUERWKWKHELWDQGELWLQWHUIDFHV 3&,FDUGVDQGFRQQHFWRUVDUHNH\HGWRPDQDJHWKH9WR9WUDQVLWLRQ7KHEDVLF ELWFRQQHFWRUFRQWDLQVSLQV7KHORJLFDOQXPEHULQJRISLQVVKRZVSLQ LGHQWLILFDWLRQQXPEHUVEXWIRXUSLQVDUHQRWSUHVHQWDQGDUHUHSODFHGE\WKHNH\LQJ ORFDWLRQ,QRQHRULHQWDWLRQWKHFRQQHFWRULVNH\HGWRDFFHSW9V\VWHPVLJQDOLQJ HQYLURQPHQWERDUGV WXUQHGGHJUHHVWKHNH\LVORFDWHGWRDFFHSW9V\VWHP VLJQDOLQJHQYLURQPHQWERDUGV8QLYHUVDODGGLQFDUGVFDUGVEXLOWWRZRUNLQERWK9 DQG9V\VWHPVLJQDOLQJHQYLURQPHQWVKDYHWZRNH\VORWVVRWKDWWKH\FDQSOXJLQWR HLWKHUFRQQHFWRU$ELWH[WHQVLRQEXLOWRQWRWKHVDPHFRQQHFWRUPROGLQJH[WHQGVWKH WRWDOQXPEHURISLQVWR7KHELWFRQQHFWRUVXEVHWGHILQHVWKHV\VWHPVLJQDOLQJ HQYLURQPHQWELWFDUGVDQGELWFDUGVDUHLQWHURSHUDEOHZLWKLQWKHV\VWHP V VLJQDOLQJYROWDJHFODVVHVGHILQHGE\WKHNH\LQJLQWKHELWFRQQHFWRUVXEVHW$ELW FDUGLGHQWLILHVLWVHOIIRUELWWUDQVIHUVRQWKHELWFRQQHFWRU$ELWFDUGLQDELW FRQQHFWRUPXVWFRQILJXUHIRUELWWUDQVIHUV 0D[LPXPFDUGSRZHUGLVVLSDWLRQLVHQFRGHGRQWKHPRSNT1#DQGPRSNT2#SLQVRI WKHH[SDQVLRQFDUG7KLVKDUGHQFRGLQJFDQEHUHDGE\V\VWHPVRIWZDUHXSRQ LQLWLDOL]DWLRQ7KHV\VWHP VVRIWZDUHFDQWKHQPDNHDGHWHUPLQDWLRQZKHWKHUDGHTXDWH FRROLQJDQGVXSSO\FXUUHQWLVDYDLODEOHLQWKDWV\VWHPIRUUHOLDEOHRSHUDWLRQDWVWDUWXS DQGLQLWLDOL]DWLRQWLPH6XSSRUWHGSRZHUOHYHOVDQGWKHLUHQFRGLQJDUHGHILQHGLQ &KDSWHU 7KH3&,H[SDQVLRQFDUGLQFOXGHVDPRXQWLQJEUDFNHWIRUFDUGORFDWLRQDQGUHWHQWLRQ 7KHEDFNSODWHLVWKHLQWHUIDFHEHWZHHQWKHFDUGDQGWKHV\VWHPWKDWSURYLGHVIRUFDEOH HVFDSHPHQW7KHFDUGKDVEHHQGHVLJQHGWRDFFRPPRGDWH3&,EUDFNHWVIRUERWK ,6$(,6$DQG0&V\VWHPV6HH)LJXUHVDQG IRUWKH,6$(,6$DVVHPEOLHVDQG )LJXUHVDQGIRUWKH0&DVVHPEOLHV7KH,6$(,6$NLWFRQWDLQVD3&,EUDFNHW IRXUVFUHZVDQGDFDUGUHWDLQHU7KHDVVHPEOHGOHQJWKRIWKH3&,H[SDQVLRQERDUG 153 Revision 2.2 LVWKDWRIDQ0&FDUG7KHUHWDLQHUIDVWHQVWRWKHIURQWHGJHRIWKH3&,FDUGWRSURYLGH VXSSRUWYLDDVWDQGDUG,6$FDUGJXLGH7KH0&EUDFNHWNLWFRQWDLQVDULYHWHG0& EUDFNHWEUDFNHWEUDFHDVVHPEO\DQGWZRSDQKHDGVFUHZV 7KHFRPSRQHQWVLGHRID3&,H[SDQVLRQFDUGLVWKHRSSRVLWHRI,6$(,6$DQG0&FDUGV 7KH3&,FDUGLVDPLUURULPDJHRI,6$(,6$DQG0&FDUGV$JRDORI3&,LVWRHQDEOH LWVLPSOHPHQWDWLRQLQV\VWHPVZLWKDOLPLWHGQXPEHURIH[SDQVLRQFDUGVORWV,QWKHVH V\VWHPVWKH3&,H[SDQVLRQERDUGFRQQHFWRUFDQFRH[LVWZLWKLQDVLQJOHVORWZLWKDQ ,6$(,6$RU0&H[SDQVLRQFRQQHFWRU7KHVHVORWVDUHUHIHUUHGWRDVVKDUHGVORWV 6KDUHGVORWVDOORZWKHHQGXVHUWRLQVWDOOD3&,,6$(,6$RU0&FDUG+RZHYHURQO\ RQHH[SDQVLRQERDUGFDQEHLQVWDOOHGLQDVKDUHGVORWDWDWLPH)RUH[DPSOHVKDUHGVORWV LQ3&,V\VWHPVZLWKDQ,6$H[SDQVLRQEXVFDQDFFRPPRGDWHDQ,6$RUD3&,H[SDQVLRQ ERDUG VKDUHGVORWVLQ3&,V\VWHPVZLWKDQ0&H[SDQVLRQEXVFDQDFFRPPRGDWHDQ0& RUD3&,H[SDQVLRQERDUG HWF 5.2. Expansion Card Physical Dimensions and Tolerances 7KHPD[LPXPFRPSRQHQWKHLJKWRQWKHSULPDU\FRPSRQHQWVLGHRIWKH3&,H[SDQVLRQ FDUGLVQRWWRH[FHHGLQFKHV PP 7KHPD[LPXPFRPSRQHQWKHLJKWRQWKH EDFNVLGHRIWKHFDUGLVQRWWRH[FHHGLQFKHV PP 'DWXP$RQWKH LOOXVWUDWLRQVLVXVHGWRORFDWHWKH3&,FDUGWRWKHSODQDUDQGWRWKHIUDPHLQWHUIDFHV WKH EDFNRIWKHIUDPHDQGWKHFDUGJXLGH'DWXP$LVFDUULHGWKURXJKWKHORFDWLQJNH\RQWKH FDUGHGJHDQGWKHORFDWLQJNH\RQWKHFRQQHFWRU 6HH)LJXUHVWKURXJKIRU3&,H[SDQVLRQFDUGSK\VLFDOGLPHQVLRQV 154 Revision 2.2 )LJXUH 3&,5DZ&DUG 9 )LJXUH 3&,5DZ&DUG 9DQG8QLYHUVDO 155 Revision 2.2 )LJXUH 3&,5DZ9DULDEOH+HLJKW6KRUW&DUG 9ELW )LJXUH 3&,5DZ9DULDEOH+HLJKW6KRUW&DUG 9ELW 156 Revision 2.2 )LJXUH 3&,5DZ9DULDEOH+HLJKW6KRUW&DUG 9ELW 157 Revision 2.2 )LJXUH 3&,5DZ9DULDEOH+HLJKW6KRUW&DUG 9ELW 158 Revision 2.2 )LJXUH 3&,&DUG(GJH&RQQHFWRU%HYHO 159 Revision 2.2 )LJXUH ,6$$VVHPEO\ 9 )LJXUH ,6$$VVHPEO\ 9DQG8QLYHUVDO 160 Revision 2.2 )LJXUH 0&$VVHPEO\ 9 )LJXUH 0&$VVHPEO\ 9 161 Revision 2.2 )LJXUH ,6$%UDFNHW 36 It is highly recommended that adapter card designers implement I/O brackets which mount on the backside of PCI cards as soon as possible to reduce their exposure to causing EMC leakage in systems. 37 It is highly recommended that system designers initiate requirements which include the use of this new design by their adapter card suppliers. 162 Revision 2.2 )LJXUH ,6$5HWDLQHU 163 Revision 2.2 )LJXUH ,2:LQGRZ+HLJKW 164 Revision 2.2 )LJXUH $GDSWHU,QVWDOODWLRQ:LWK/DUJH,2&RQQHFWRU 165 Revision 2.2 )LJXUH 0&%UDFNHW%UDFH 166 Revision 2.2 )LJXUH 0&%UDFNHW 167 Revision 2.2 )LJXUH 0&%UDFNHW'HWDLOV 5.2.1. Connector Physical Description 7KHFRQQHFWRUVWKDWVXSSRUW3&,H[SDQVLRQFDUGVDUHGHULYHGIURPWKRVHRQWKH0&EXV 7KH0&FRQQHFWRUVDUHZHOOGHILQHGDQGKDYHSURYHQYDOXHDQGUHOLDELOLW\7KHUHDUH IRXUFRQQHFWRUVWKDWFDQEHXVHGGHSHQGLQJRQWKH3&,LPSOHPHQWDWLRQ7KHGLIIHUHQFHV EHWZHHQFRQQHFWRUVDUHELWDQGELWDQGWKH9DQG9VLJQDOLQJHQYLURQPHQWV $NH\GLIIHUHQWLDWHVWKHVLJQDOLQJHQYLURQPHQWYROWDJHV7KHVDPHSK\VLFDOFRQQHFWRULV XVHGIRUWKHELWVLJQDOLQJHQYLURQPHQWV,QRQHRULHQWDWLRQWKHNH\DFFHSWV9 ERDUGV5RWDWHGGHJUHHVWKHFRQQHFWRUDFFHSWV9VLJQDOLQJERDUGV7KHSLQ QXPEHULQJRIWKHFRQQHFWRUFKDQJHVIRUWKHGLIIHUHQWVLJQDOLQJHQYLURQPHQWVWRPDLQWDLQ WKHVDPHUHODWLYHSRVLWLRQRIVLJQDOVRQWKHFRQQHFWRU VHH)LJXUHVDQG IRUERDUGOD\RXWGHWDLOV ,QWKHFRQQHFWRUGUDZLQJVWKHUHFRPPHQGHGERDUGOD\RXWGHWDLOVDUHJLYHQDVQRPLQDO GLPHQVLRQV/D\RXWGHWDLOWROHUDQFLQJVKRXOGEHFRQVLVWHQWZLWKWKHFRQQHFWRUVXSSOLHU V UHFRPPHQGDWLRQVDQGJRRGHQJLQHHULQJSUDFWLFH 168 Revision 2.2 6HH)LJXUHV WKURXJKIRUFRQQHFWRUGLPHQVLRQVDQGOD\RXWUHFRPPHQGDWLRQV 6HH)LJXUHVWKURXJKIRUFDUGHGJHFRQQHFWRUGLPHQVLRQVDQGWROHUDQFHV 7ROHUDQFHVIRUFDUGVDUHJLYHQVRWKDWLQWHUFKDQJHDEOHFDUGVFDQEHPDQXIDFWXUHG )LJXUH ELW&RQQHFWRU )LJXUH 9ELW&RQQHFWRU/D\RXW5HFRPPHQGDWLRQ 169 Revision 2.2 )LJXUH 9ELW&RQQHFWRU/D\RXW5HFRPPHQGDWLRQ )LJXUH 9ELW&RQQHFWRU )LJXUH 9ELW&RQQHFWRU/D\RXW5HFRPPHQGDWLRQ 170 Revision 2.2 )LJXUH 9ELW&RQQHFWRU )LJXUH 9ELW&RQQHFWRU/D\RXW5HFRPPHQGDWLRQ 171 Revision 2.2 )LJXUH 9ELW&DUG(GJH&RQQHFWRU'LPHQVLRQVDQG7ROHUDQFHV )LJXUH 9ELW&DUG(GJH&RQQHFWRU'LPHQVLRQVDQG7ROHUDQFHV 172 Revision 2.2 )LJXUH 9ELW&DUG(GJH&RQQHFWRU'LPHQVLRQVDQG7ROHUDQFHV )LJXUH 9ELW&DUG(GJH&RQQHFWRU'LPHQVLRQVDQG7ROHUDQFHV 173 Revision 2.2 )LJXUH 8QLYHUVDOELW&DUG(GJH&RQQHFWRU'LPHQVLRQVDQG7ROHUDQFHV 174 Revision 2.2 )LJXUH 8QLYHUVDOELW&DUG(GJH&RQQHFWRU'LPHQVLRQVDQG7ROHUDQFHV 175 Revision 2.2 )LJXUH 3&,&DUG(GJH&RQQHFWRU&RQWDFWV 5.2.1.1. Connector Physical Requirements 7DEOH &RQQHFWRU3K\VLFDO5HTXLUHPHQWV Part Materials Connector Housing High-temperature thermoplastic, UL flammability rating 94V-0, color: white. Contacts Phosphor bronze. Contact Finish 0.000030 inch minimum gold over 0.000050 inch minimum nickel in the contact area. Alternate finish: gold flash over 0.000040 inch (1 micron) minimum palladium or palladium-nickel over nickel in the contact area. 176 Revision 2.2 5.2.1.2. Connector Performance Specification 7DEOH &RQQHFWRU0HFKDQLFDO3HUIRUPDQFH5HTXLUHPHQWV Parameter Specification Durability 100 mating cycles without physical damage or exceeding low level contact resistance requirement when mated with the recommended card edge. Mating Force 6 oz. (1.7N) max. avg. per opposing contact pair using MIL-STD-1344, Method 2013.1 and gauge per MIL-C-21097 with profile as shown in add-in board specification. Contact Normal Force 75 grams minimum. 7DEOH &RQQHFWRU(OHFWULFDO3HUIRUPDQFH5HTXLUHPHQWV Parameter Specification Contact Resistance (low signal level) 30 mΩ max. initial, 10 mΩ max. increase through testing. Contact resistance, test per MIL-STD-1344, Method 3002.1. Insulation Resistance 1000 MΩ min. per MIL STD 202, Method 302, Condition B. Dielectric Withstand 500 VAC RMS. per MIL-STD-1344, Method D3001.1 Voltage Condition 1. Capacitance 2 pF max. @ 1 MHz. Current Rating 1A, 30 °C rise above ambient. Voltage Rating 125V. Certification UL Recognition and CSA Certification required. 7DEOH &RQQHFWRU(QYLURQPHQWDO3HUIRUPDQFH5HTXLUHPHQWV Parameter Specification Operating Temperature -40 °C to 105 °C Thermal Shock -55 °C to 85 °C, 5 cycles per MIL-STD-1344, Method 1003.1. Flowing Mixed Gas Test Battelle, Class II. Connector mated with board and tested per Battelle method. 177 Revision 2.2 5.2.2. Planar Implementation 7ZRW\SHVRISODQDULPSOHPHQWDWLRQVDUHVXSSRUWHGE\WKH3&,H[SDQVLRQFDUGGHVLJQ H[SDQVLRQFRQQHFWRUVPRXQWHGRQWKHSODQDUDQGH[SDQVLRQFRQQHFWRUVPRXQWHGRQD ULVHUFDUG 6HH)LJXUHVDQGIRUSODQDUGHWDLOVIRU,6$(,6$DQG0&FDUGV UHVSHFWLYHO\7KHSODQDUGUDZLQJVVKRZWKHUHODWLYHORFDWLRQVRIWKH3&,9DQG9 FRQQHFWRUGDWXPVWRWKH,6$(,6$DQG0&FRQQHFWRUGDWXPV%RWK9DQG9 FRQQHFWRUVDUHVKRZQRQWKHSODQDUWRFRQFLVHO\FRQYH\WKHGLPHQVLRQDOLQIRUPDWLRQ 1RUPDOO\DJLYHQV\VWHPZRXOGLQFRUSRUDWHHLWKHUWKH9RUWKH93&,FRQQHFWRUEXW QRWERWK6WDQGDUGFDUGVSDFLQJRILQFKHVIRU,6$(,6$DQGLQFKHVIRU0& DOORZVIRURQO\RQHVKDUHGVORWSHUV\VWHP,IPRUH3&,H[SDQVLRQVORWVDUHUHTXLUHG ZKLOHXVLQJH[LVWLQJFDUGVSDFLQJDGGLWLRQDOVORWVPXVWEHGHGLFDWHGWR3&,9LHZLQJ WKHSODQDUIURPWKHEDFNRIWKHV\VWHPWKHVKDUHGVORWLVORFDWHGVXFKWKDWGHGLFDWHG,6$ (,6$RU0&VORWVDUHORFDWHGWRWKHULJKWDQGGHGLFDWHG3&,VORWVDUHORFDWHGWRWKHOHIW 6HH)LJXUHV DQGIRUULVHUFDUGGHWDLOV 178 Revision 2.2 )LJXUH 3&,&RQQHFWRU/RFDWLRQRQ3ODQDU5HODWLYHWR'DWXPRQWKH,6$&RQQHFWRU )LJXUH 3&,&RQQHFWRU/RFDWLRQRQ3ODQDU5HODWLYHWR'DWXPRQWKH(,6$&RQQHFWRU 179 Revision 2.2 )LJXUH 3&,&RQQHFWRU/RFDWLRQRQ3ODQDU5HODWLYHWR'DWXPRQWKH0&&RQQHFWRU 180 Revision 2.2 )LJXUH ELW3&,5LVHU&RQQHFWRU 38 It is highly recommended that LPX system chassis designers utilize the PCI riser connector when implementing riser cards on LPX systems and using adapter cards slots on 0.800” spacing. 39 It is highly recommended that LPX system chassis designers utilize the taller riser style of ISA and EISA connectors when combining PCI and ISA/EISA. 181 Revision 2.2 )LJXUH ELW93&,5LVHU&RQQHFWRU)RRWSULQW 182 Revision 2.2 )LJXUH ELW93&,5LVHU&RQQHFWRU)RRWSULQW 183 Revision 2.2 Ã )LJXUH ELW93&,5LVHU&RQQHFWRU 184 Revision 2.2 )LJXUH ELW93&,5LVHU&RQQHFWRU)RRWSULQW 185 Revision 2.2 Ã )LJXUH ELW93&,5LVHU&RQQHFWRU 186 Revision 2.2 )LJXUH ELW93&,5LVHU&RQQHFWRU)RRWSULQW 187 Revision 2.2 188 Revision 2.2 Chapter 6 Configuration Space 7KLVFKDSWHUGHILQHVWKHSURJUDPPLQJPRGHODQGXVDJHUXOHVIRUWKHFRQILJXUDWLRQ UHJLVWHUVSDFHLQ3&,FRPSOLDQWGHYLFHV7KLVFKDSWHULVOLPLWHGWRWKHGHILQLWLRQRI3&, FRPSOLDQWFRPSRQHQWVIRUDZLGHYDULHW\RIV\VWHPW\SHV6\VWHPGHSHQGHQWLVVXHVIRU VSHFLILFSODWIRUPVVXFKDVPDSSLQJYDULRXV3&,DGGUHVVVSDFHVLQWRKRVW&38DGGUHVV VSDFHVDFFHVVRUGHULQJUXOHVUHTXLUHPHQWVIRUKRVWWR3&,EXVEULGJHVHWFDUHQRW GHVFULEHGLQWKLVFKDSWHU 7KHLQWHQWRIWKH3&,&RQILJXUDWLRQ6SDFHGHILQLWLRQLVWRSURYLGHDQDSSURSULDWHVHWRI FRQILJXUDWLRQKRRNVZKLFKVDWLVILHVWKHQHHGVRIFXUUHQWDQGDQWLFLSDWHGV\VWHP FRQILJXUDWLRQPHFKDQLVPVZLWKRXWVSHFLI\LQJWKRVHPHFKDQLVPVRURWKHUZLVHSODFLQJ FRQVWUDLQWVRQWKHLUXVH7KHFULWHULDIRUWKHVHFRQILJXUDWLRQKRRNVDUH • 6XIILFLHQWVXSSRUWWRDOORZIXWXUHFRQILJXUDWLRQPHFKDQLVPVWRSURYLGH • )XOOGHYLFHUHORFDWLRQLQFOXGLQJLQWHUUXSWELQGLQJ • ,QVWDOODWLRQFRQILJXUDWLRQDQGERRWLQJZLWKRXWXVHULQWHUYHQWLRQ • 6\VWHPDGGUHVVPDSFRQVWUXFWLRQE\GHYLFHLQGHSHQGHQWVRIWZDUH • (IIHFWLYHVXSSRUWRIH[LVWLQJFRQILJXUDWLRQPHFKDQLVPV HJ(,6$&RQILJXUDWLRQ 8WLOLW\ • 0LQLPL]HWKHVLOLFRQEXUGHQFUHDWHGE\UHTXLUHGIXQFWLRQV • /HYHUDJHFRPPRQDOLW\ZLWKDWHPSODWHDSSURDFKWRFRPPRQIXQFWLRQVZLWKRXW SUHFOXGLQJGHYLFHVZLWKXQLTXHUHTXLUHPHQWV $OO3&,GHYLFHV H[FHSWKRVWEXVEULGJHV PXVWLPSOHPHQW&RQILJXUDWLRQ6SDFH 0XOWLIXQFWLRQGHYLFHVPXVWSURYLGHD&RQILJXUDWLRQ6SDFHIRUHDFKIXQFWLRQ LPSOHPHQWHG UHIHUWR6HFWLRQ 189 Revision 2.2 6.1. Configuration Space Organization 7KLVVHFWLRQGHILQHVWKHRUJDQL]DWLRQRI&RQILJXUDWLRQ6SDFHUHJLVWHUVDQGLPSRVHVD VSHFLILFUHFRUGVWUXFWXUHRUWHPSODWHRQWKHE\WHVSDFH7KLVVSDFHLVGLYLGHGLQWRD SUHGHILQHGKHDGHUUHJLRQDQGDGHYLFHGHSHQGHQWUHJLRQ 'HYLFHVLPSOHPHQWRQO\WKH QHFHVVDU\DQGUHOHYDQWUHJLVWHUVLQHDFKUHJLRQ$GHYLFH V&RQILJXUDWLRQ6SDFHPXVWEH DFFHVVLEOHDWDOOWLPHVQRWMXVWGXULQJV\VWHPERRW 7KHSUHGHILQHGKHDGHUUHJLRQFRQVLVWVRIILHOGVWKDWXQLTXHO\LGHQWLI\WKHGHYLFHDQG DOORZWKHGHYLFHWREHJHQHULFDOO\FRQWUROOHG7KHSUHGHILQHGKHDGHUSRUWLRQRIWKH &RQILJXUDWLRQ6SDFHLVGLYLGHGLQWRWZRSDUWV7KHILUVWE\WHVDUHGHILQHGWKHVDPH IRUDOOW\SHVRIGHYLFHV7KHUHPDLQLQJE\WHVFDQKDYHGLIIHUHQWOD\RXWVGHSHQGLQJRQWKH EDVHIXQFWLRQWKDWWKHGHYLFHVXSSRUWV7KH+HDGHU7\SHILHOG ORFDWHGDWRIIVHW(K GHILQHVZKDWOD\RXWLVSURYLGHG&XUUHQWO\WKUHH+HDGHU7\SHVDUHGHILQHGKZKLFK KDVWKHOD\RXWVKRZQLQ)LJXUHKZKLFKLVGHILQHGIRU3&,WR3&,EULGJHVDQGLV GRFXPHQWHGLQWKH3&,WR3&,%ULGJH$UFKLWHFWXUH6SHFLILFDWLRQDQGKZKLFKLV GHILQHGIRU&DUG%XVEULGJHVDQGLVGRFXPHQWHGLQWKH3&&DUG6WDQGDUG 6\VWHPVRIWZDUHPD\QHHGWRVFDQWKH3&,EXVWRGHWHUPLQHZKDWGHYLFHVDUHDFWXDOO\ SUHVHQW7RGRWKLVWKHFRQILJXUDWLRQVRIWZDUHPXVWUHDGWKH9HQGRU,'LQHDFKSRVVLEOH 3&,VORW7KHKRVWEXVWR3&,EULGJHPXVWXQDPELJXRXVO\UHSRUWDWWHPSWVWRUHDGWKH 9HQGRU,'RIQRQH[LVWHQWGHYLFHV6LQFH))))KLVDQLQYDOLG9HQGRU,'LWLVDGHTXDWH IRUWKHKRVWEXVWR3&,EULGJHWRUHWXUQDYDOXHRIDOO VRQUHDGDFFHVVHVWR &RQILJXUDWLRQ6SDFHUHJLVWHUVRIQRQH[LVWHQWGHYLFHV 1RWHWKDWWKHVHDFFHVVHVZLOOEH WHUPLQDWHGZLWKD0DVWHU$ERUW $OO3&,GHYLFHVPXVWWUHDW&RQILJXUDWLRQ6SDFHZULWHRSHUDWLRQVWRUHVHUYHGUHJLVWHUVDV QRRSV WKDWLVWKHDFFHVVPXVWEHFRPSOHWHGQRUPDOO\RQWKHEXVDQGWKHGDWDGLVFDUGHG 5HDGDFFHVVHVWRUHVHUYHGRUXQLPSOHPHQWHGUHJLVWHUVPXVWEHFRPSOHWHGQRUPDOO\DQGD GDWDYDOXHRIUHWXUQHG )LJXUHGHSLFWVWKHOD\RXWRID7\SHKSUHGHILQHGKHDGHUSRUWLRQRIWKHE\WH &RQILJXUDWLRQ6SDFH'HYLFHVPXVWSODFHDQ\QHFHVVDU\GHYLFHVSHFLILFUHJLVWHUVDIWHU WKHSUHGHILQHGKHDGHULQ&RQILJXUDWLRQ6SDFH$OOPXOWLE\WHQXPHULFILHOGVIROORZ OLWWOHHQGLDQRUGHULQJ WKDWLVORZHUDGGUHVVHVFRQWDLQWKHOHDVWVLJQLILFDQWSDUWVRIWKH ILHOG6RIWZDUHPXVWWDNHFDUHWRGHDOFRUUHFWO\ZLWKELWHQFRGHGILHOGVWKDWKDYHVRPH ELWVUHVHUYHGIRUIXWXUHXVH2QUHDGVVRIWZDUHPXVWXVHDSSURSULDWHPDVNVWRH[WUDFW WKHGHILQHGELWVDQGPD\QRWUHO\RQUHVHUYHGELWVEHLQJDQ\SDUWLFXODUYDOXH2QZULWHV VRIWZDUHPXVWHQVXUHWKDWWKHYDOXHVRIUHVHUYHGELWSRVLWLRQVDUHSUHVHUYHG WKDWLVWKH YDOXHVRIUHVHUYHGELWSRVLWLRQVPXVWILUVWEHUHDGPHUJHGZLWKWKHQHZYDOXHVIRURWKHU ELWSRVLWLRQVDQGWKHGDWDWKHQZULWWHQEDFN6HFWLRQGHVFULEHVWKHUHJLVWHUVLQWKH 7\SHKSUHGHILQHGKHDGHUSRUWLRQRIWKH&RQILJXUDWLRQ6SDFH 40 The device dependent region contains device specific information and is not described in this document. 41 The PC Card Standard is available from PCMCIA and contact information can be found at http://www.pc-card.com 190 Revision 2.2 )LJXUH 7\SHK&RQILJXUDWLRQ6SDFH+HDGHU $OO3&,FRPSOLDQWGHYLFHVPXVWVXSSRUWWKH9HQGRU,''HYLFH,'&RPPDQG6WDWXV 5HYLVLRQ,'&ODVV&RGHDQG+HDGHU7\SHILHOGVLQWKHKHDGHU5HIHUWR6HFWLRQ IRUWKHUHTXLUHPHQWVIRU6XEV\VWHP,'DQG6XEV\VWHP9HQGRU,',PSOHPHQWDWLRQRIWKH RWKHUUHJLVWHUVLQD7\SHKSUHGHILQHGKHDGHULVRSWLRQDO LHWKH\FDQEHWUHDWHGDV UHVHUYHGUHJLVWHUV GHSHQGLQJRQGHYLFHIXQFWLRQDOLW\,IDGHYLFHVXSSRUWVWKHIXQFWLRQ WKDWWKHUHJLVWHULVFRQFHUQHGZLWKWKHGHYLFHPXVWLPSOHPHQWLWLQWKHGHILQHGORFDWLRQ DQGZLWKWKHGHILQHGIXQFWLRQDOLW\ 191 Revision 2.2 6.2. Configuration Space Functions 3&,KDVWKHSRWHQWLDOIRUJUHDWO\LQFUHDVLQJWKHHDVHZLWKZKLFKV\VWHPVPD\EH FRQILJXUHG7RUHDOL]HWKLVSRWHQWLDODOO3&,GHYLFHVPXVWSURYLGHFHUWDLQIXQFWLRQVWKDW V\VWHPFRQILJXUDWLRQVRIWZDUHFDQXWLOL]H7KLVVHFWLRQDOVROLVWVWKHIXQFWLRQVWKDWQHHG WREHVXSSRUWHGE\3&,GHYLFHVYLDUHJLVWHUVGHILQHGLQWKHSUHGHILQHGKHDGHUSRUWLRQRI WKH&RQILJXUDWLRQ6SDFH7KHH[DFWIRUPDWRIWKHVHUHJLVWHUV LHQXPEHURIELWV LPSOHPHQWHG LVGHYLFHVSHFLILF+RZHYHUVRPHJHQHUDOUXOHVPXVWEHIROORZHG$OO UHJLVWHUVPXVWEHFDSDEOHRIEHLQJUHDGDQGWKHGDWDUHWXUQHGPXVWLQGLFDWHWKHYDOXHWKDW WKHGHYLFHLVDFWXDOO\XVLQJ &RQILJXUDWLRQ6SDFHLVLQWHQGHGIRUFRQILJXUDWLRQLQLWLDOL]DWLRQDQGFDWDVWURSKLFHUURU KDQGOLQJIXQFWLRQV,WVXVHVKRXOGEHUHVWULFWHGWRLQLWLDOL]DWLRQVRIWZDUHDQGHUURU KDQGOLQJVRIWZDUH$OORSHUDWLRQDOVRIWZDUHPXVWFRQWLQXHWRXVH,2DQGRU0HPRU\ 6SDFHDFFHVVHVWRPDQLSXODWHGHYLFHUHJLVWHUV 6.2.1. Device Identification )LYHILHOGVLQWKHSUHGHILQHGKHDGHUGHDOZLWKGHYLFHLGHQWLILFDWLRQ$OO3&,GHYLFHVDUH UHTXLUHGWRLPSOHPHQWWKHVHILHOGV*HQHULFFRQILJXUDWLRQVRIWZDUHZLOOEHDEOHWRHDVLO\ GHWHUPLQHZKDWGHYLFHVDUHDYDLODEOHRQWKHV\VWHP V3&,EXV HV $OORIWKHVHUHJLVWHUV DUHUHDGRQO\ Vendor ID This field identifies the manufacturer of the device. Valid vendor identifiers are allocated by the PCI SIG to ensure uniqueness. 0FFFFh is an invalid value for Vendor ID. Device ID This field identifies the particular device. This identifier is allocated by the vendor. Revision ID This register specifies a device specific revision identifier. The value is chosen by the vendor. Zero is an acceptable value. This field should be viewed as a vendor defined extension to the Device ID. Header Type This byte identifies the layout of the second part of the predefined header (beginning at byte 10h in Configuration Space) and also whether or not the device contains multiple functions. Bit 7 in this register is used to identify a multi- function device. If the bit is 0, then the device is single function. If the bit is 1, then the device has multiple functions. Bits 6 through 0 identify the layout of the second part of the predefined header. The encoding 00h specifies the layout shown in Figure 6-1. The encoding 01h is defined for PCI-to-PCI bridges and is defined in the document PCI to PCI Bridge Architecture Specification. The encoding 02h is defined for a CardBus bridge and is documented in the PC Card Standard. All other encodings are reserved. 192 Revision 2.2 Class Code The Class Code register is read-only and is used to identify the generic function of the device and, in some cases, a specific register-level programming interface. The register is broken into three byte-size fields. The upper byte (at offset 0Bh) is a base class code which broadly classifies the type of function the device performs. The middle byte (at offset 0Ah) is a sub-class code which identifies more specifically the function of the device. The lower byte (at offset 09h) identifies a specific register-level programming interface (if any) so that device independent software can interact with the device. Encodings for base class, sub-class, and programming interface are provided in Appendix D. All unspecified encodings are reserved. 6.2.2. Device Control 7KH&RPPDQGUHJLVWHUSURYLGHVFRDUVHFRQWURORYHUDGHYLFH VDELOLW\WRJHQHUDWHDQG UHVSRQGWR3&,F\FOHV:KHQDLVZULWWHQWRWKLVUHJLVWHUWKHGHYLFHLVORJLFDOO\ GLVFRQQHFWHGIURPWKH3&,EXVIRUDOODFFHVVHVH[FHSWFRQILJXUDWLRQDFFHVVHV$OO GHYLFHVDUHUHTXLUHGWRVXSSRUWWKLVEDVHOHYHORIIXQFWLRQDOLW\,QGLYLGXDOELWVLQWKH &RPPDQGUHJLVWHUPD\RUPD\QRWEHLPSOHPHQWHGGHSHQGLQJRQDGHYLFH¶V IXQFWLRQDOLW\)RULQVWDQFHGHYLFHVWKDWGRQRWLPSOHPHQWDQ,26SDFHZLOOQRW LPSOHPHQWDZULWDEOHHOHPHQWDWELWORFDWLRQRIWKH&RPPDQGUHJLVWHU'HYLFHV W\SLFDOO\SRZHUXSZLWKDOO VLQWKLVUHJLVWHUEXW6HFWLRQH[SODLQVVRPHH[FHSWLRQV )LJXUHVKRZVWKHOD\RXWRIWKHUHJLVWHUDQG7DEOHH[SODLQVWKHPHDQLQJVRIWKH GLIIHUHQWELWVLQWKH&RPPDQGUHJLVWHU 1510 9 8 7 6 5 4 3 2 1 0 Reserved )DVW%DFNWR%DFN(QDEOH 6(55(QDEOH 6WHSSLQJ&RQWURO 3DULW\(UURU5HVSRQVH 9*$3DOHWWH6QRRS 0HPRU\:ULWHDQG,QYDOLGDWH(QDEOH 6SHFLDO&\FOHV %XV0DVWHU 0HPRU\6SDFH ,26SDFH )LJXUH &RPPDQG5HJLVWHU/D\RXW 193 Revision 2.2 7DEOH &RPPDQG5HJLVWHU%LWV Bit Location Description 0 Controls a device's response to I/O Space accesses. A value of 0 disables the device response. A value of 1 allows the device to respond to I/O Space accesses. State after RST# is 0. 1 Controls a device's response to Memory Space accesses. A value of 0 disables the device response. A value of 1 allows the device to respond to Memory Space accesses. State after RST# is 0. 2 Controls a device's ability to act as a master on the PCI bus. A value of 0 disables the device from generating PCI accesses. A value of 1 allows the device to behave as a bus master. State after RST# is 0. 3 Controls a device's action on Special Cycle operations. A value of 0 causes the device to ignore all Special Cycle operations. A value of 1 allows the device to monitor Special Cycle operations. State after RST# is 0. 4 This is an enable bit for using the Memory Write and Invalidate command. When this bit is 1, masters may generate the command. When it is 0, Memory Write must be used instead. State after RST# is 0. This bit must be implemented by master devices that can generate the Memory Write and Invalidate command. 5 This bit controls how VGA compatible and graphics devices handle accesses to VGA palette registers. When this bit is 1, palette snooping is enabled (i.e., the device does not respond to palette register writes and snoops the data). When the bit is 0, the device should treat palette write accesses like all other accesses. VGA compatible devices should implement this bit. Refer to Section 3.10. for more details on VGA palette snooping. 194 Revision 2.2 7DEOH &RPPDQG5HJLVWHU%LWV FRQWLQXHG Bit Location Description 6 This bit controls the device's response to parity errors. When the bit is set, the device must take its normal action when a parity error is detected. When the bit is 0, the device sets its Detected Parity Error status bit (bit 15 in the Status register) when an error is detected, but does not assert PERR# and continues normal operation. This bit's state after RST# is 0. Devices that check parity must implement this bit. Devices are still required to generate parity even if parity checking is disabled. 7 This bit is used to control whether or not a device does address/data stepping. Devices that never do stepping must hardwire this bit to 0. Devices that always do stepping must hardwire this bit to 1. Devices that can do either, must make this bit read/write and have it initialize to 1 after RST#. 8 This bit is an enable bit for the SERR# driver. A value of 0 disables the SERR# driver. A value of 1 enables the SERR# driver. This bit's state after RST# is 0. All devices that have an SERR# pin must implement this bit. Address parity errors are reported only if this bit and bit 6 are 1. 9 This optional read/write bit controls whether or not a master can do fast back-to-back transactions to different devices. Initialization software will set the bit if all targets are fast back-to-back capable. A value of 1 means the master is allowed to generate fast back-to-back transactions to different agents as described in Section 3.4.2. A value of 0 means fast back-to-back transactions are only allowed to the same agent. This bit's state after RST# is 0. 10-15 Reserved. 195 Revision 2.2 6.2.3. Device Status 7KH6WDWXVUHJLVWHULVXVHGWRUHFRUGVWDWXVLQIRUPDWLRQIRU3&,EXVUHODWHGHYHQWV7KH GHILQLWLRQRIHDFKRIWKHELWVLVJLYHQLQ7DEOHDQGWKHOD\RXWRIWKHUHJLVWHULVVKRZQ LQ)LJXUH'HYLFHVPD\QRWQHHGWRLPSOHPHQWDOOELWVGHSHQGLQJRQGHYLFH IXQFWLRQDOLW\)RULQVWDQFHDGHYLFHWKDWDFWVDVDWDUJHWEXWZLOOQHYHUVLJQDO7DUJHW $ERUWZRXOGQRWLPSOHPHQWELW5HVHUYHGELWVVKRXOGEHUHDGRQO\DQGUHWXUQ]HUR ZKHQUHDG 5HDGVWRWKLVUHJLVWHUEHKDYHQRUPDOO\:ULWHVDUHVOLJKWO\GLIIHUHQWLQWKDWELWVFDQEH UHVHWEXWQRWVHW$RQHELWLVUHVHWZKHQHYHUWKHUHJLVWHULVZULWWHQDQGWKHZULWHGDWDLQ WKHFRUUHVSRQGLQJELWORFDWLRQLVD)RULQVWDQFHWRFOHDUELWDQGQRWDIIHFWDQ\ RWKHUELWVZULWHWKHYDOXHBBBEWRWKHUHJLVWHU 15 14 13 1211 10 9 8765 4 0 5HVHUYHG Capabilities List 66 MHz Capable Reserved Fast Back-to-Back Capable Master Data Parity Error DEVSEL timing 00 - fast 01 - medium 10 - slow Signaled Target Abort Received Target Abort Received Master Abort Signaled System Error Detected Parity Error )LJXUH 6WDWXV5HJLVWHU/D\RXW 196 Revision 2.2 7DEOH 6WDWXV5HJLVWHU%LWV Bit Location Description 0-3 Reserved. 4 This optional read-only bit indicates whether or not this device implements the pointer for a New Capabilities linked list at offset 34h. A value of zero indicates that no New Capabilities linked list is available. A value of one indicates that the value read at offset 34h is a pointer in Configuration Space to a linked list of new capabilities. Refer to Section 6.7. for details on New Capabilities. 5 This optional read-only bit indicates whether or not this device is capable of running at 66 MHz as defined in Chapter 7. A value of zero indicates 33 MHz. A value of 1 indicates that the device is 66 MHz capable. 6 This bit is reserved42. 7 This optional read-only bit indicates whether or not the target is capable of accepting fast back-to-back transactions when the transactions are not to the same agent. This bit can be set to 1 if the device can accept these transactions and must be set to 0 otherwise. Refer to Section 3.4.2. for a complete description of requirements for setting this bit. 8 This bit is only implemented by bus masters. It is set when three conditions are met: 1) the bus agent asserted PERR# itself (on a read) or observed PERR# asserted (on a write); 2) the agent setting the bit acted as the bus master for the operation in which the error occurred; and 3) the Parity Error Response bit (Command register) is set. 9-10 These bits encode the timing of DEVSEL#. Section 3.6.1. specifies three allowable timings for assertion of DEVSEL#. These are encoded as 00b for fast, 01b for medium, and 10b for slow (11b is reserved). These bits are read-only and must indicate the slowest time that a device asserts DEVSEL# for any bus command except Configuration Read and Configuration Write. 42 In Revision 2.1 of this specification, this bit was used to indicate whether or not a device supported User Definable Features. 197 Revision 2.2 7DEOH 6WDWXV5HJLVWHU%LWV FRQWLQXHG Bit Location Description 11 This bit must be set by a target device whenever it terminates a transaction with Target-Abort. Devices that will never signal Target- Abort do not need to implement this bit. 12 This bit must be set by a master device whenever its transaction is terminated with Target-Abort. All master devices must implement this bit. 13 This bit must be set by a master device whenever its transaction (except for Special Cycle) is terminated with Master-Abort. All master devices must implement this bit. 14 This bit must be set whenever the device asserts SERR#. Devices who will never assert SERR# do not need to implement this bit. 15 This bit must be set by the device whenever it detects a parity error, even if parity error handling is disabled (as controlled by bit 6 in the Command register). 6.2.4. Miscellaneous Registers 7KLVVHFWLRQGHVFULEHVWKHUHJLVWHUVWKDWDUHGHYLFHLQGHSHQGHQWDQGRQO\QHHGWREH LPSOHPHQWHGE\GHYLFHVWKDWSURYLGHWKHGHVFULEHGIXQFWLRQ &DFKH/LQH6L]H 7KLVUHDGZULWHUHJLVWHUVSHFLILHVWKHV\VWHPFDFKHOLQHVL]HLQXQLWVRI':25'V7KLV UHJLVWHUPXVWEHLPSOHPHQWHGE\PDVWHUGHYLFHVWKDWFDQJHQHUDWHWKH0HPRU\:ULWHDQG ,QYDOLGDWHFRPPDQG UHIHUWR6HFWLRQ 7KHYDOXHLQWKLVUHJLVWHULVDOVRXVHGE\ PDVWHUGHYLFHVWRGHWHUPLQHZKHWKHUWRXVH5HDG5HDG/LQHRU5HDG0XOWLSOH FRPPDQGVIRUDFFHVVLQJPHPRU\ UHIHUWR6HFWLRQ 6ODYHGHYLFHVWKDWZDQWWRDOORZPHPRU\EXUVWLQJXVLQJFDFKHOLQHZUDSDGGUHVVLQJPRGH UHIHUWR6HFWLRQ PXVWLPSOHPHQWWKLVUHJLVWHUWRNQRZZKHQDEXUVWVHTXHQFH ZUDSVWRWKHEHJLQQLQJRIWKHFDFKHOLQH 7KLVILHOGPXVWEHLQLWLDOL]HGWRDWRST# $GHYLFHPD\OLPLWWKHQXPEHURIFDFKHOLQHVL]HVWKDWLWFDQVXSSRUW)RUH[DPSOHLW PD\DFFHSWRQO\SRZHUVRIOHVVWKDQ,IDQXQVXSSRUWHGYDOXHLVZULWWHQWRWKH &DFKH/LQH6L]HUHJLVWHUWKHGHYLFHVKRXOGEHKDYHDVLIDYDOXHRIZDVZULWWHQ /DWHQF\7LPHU 7KLVUHJLVWHUVSHFLILHVLQXQLWVRI3&,EXVFORFNVWKHYDOXHRIWKH/DWHQF\7LPHUIRUWKLV 3&,EXVPDVWHU UHIHUWR6HFWLRQ 7KLVUHJLVWHUPXVWEHLPSOHPHQWHGDVZULWDEOHE\ DQ\PDVWHUWKDWFDQEXUVWPRUHWKDQWZRGDWDSKDVHV7KLVUHJLVWHUPD\EHLPSOHPHQWHG DVUHDGRQO\IRUGHYLFHVWKDWEXUVWWZRRUIHZHUGDWDSKDVHVEXWWKHKDUGZLUHGYDOXH PXVWEHOLPLWHGWRRUOHVV$W\SLFDOLPSOHPHQWDWLRQZRXOGEHWREXLOGWKHILYHKLJK RUGHUELWV OHDYLQJWKHERWWRPWKUHHDVUHDGRQO\ UHVXOWLQJLQDWLPHUJUDQXODULW\RIHLJKW FORFNV$WRST#WKHUHJLVWHUPXVWEHLQLWLDOL]HGWR LISURJUDPPDEOH 198 Revision 2.2 %XLOWLQ6HOI7HVW %,67 7KLVRSWLRQDOUHJLVWHULVXVHGIRUFRQWURODQGVWDWXVRI%,67'HYLFHVWKDWGRQRWVXSSRUW %,67PXVWDOZD\VUHWXUQDYDOXHRI LHWUHDWLWDVDUHVHUYHGUHJLVWHU $GHYLFH ZKRVH%,67LVLQYRNHGPXVWQRWSUHYHQWQRUPDORSHUDWLRQRIWKH3&,EXV)LJXUH VKRZVWKHUHJLVWHUOD\RXWDQG7DEOHGHVFULEHVWKHELWVLQWKHUHJLVWHU 7654321 0 Rsvd Start BIST BIST capable )LJXUH %,675HJLVWHU/D\RXW 7DEOH %,675HJLVWHU%LWV Bit Location Description 7 Return 1 if device supports BIST. Return 0 if the device is not BIST capable. 6 Write a 1 to invoke BIST. Device resets the bit when BIST is complete. Software should fail the device if BIST is not complete after 2 seconds. 5-4 Reserved. Device returns 0. 3-0 A value of 0 means the device has passed its test. Non-zero values mean the device failed. Device-specific failure codes can be encoded in the non-zero value. &DUG%XV&,63RLQWHU 7KLVRSWLRQDOUHJLVWHULVXVHGE\WKRVHGHYLFHVWKDWZDQWWRVKDUHVLOLFRQEHWZHHQ &DUG%XVDQG3&,7KHILHOGLVXVHGWRSRLQWWRWKH&DUG,QIRUPDWLRQ6WUXFWXUH &,6 IRU WKH&DUG%XVFDUG )RUDGHWDLOHGH[SODQDWLRQRIWKH&,6UHIHUWRWKH3&0&,$YVSHFLILFDWLRQ7KH VXEMHFWLVFRYHUHGXQGHUWKHKHDGLQJ&DUG0HWDIRUPDWDQGGHVFULEHVWKHW\SHVRI LQIRUPDWLRQSURYLGHGDQGWKHRUJDQL]DWLRQRIWKLVLQIRUPDWLRQ ,QWHUUXSW/LQH 7KH,QWHUUXSW/LQHUHJLVWHULVDQHLJKWELWUHJLVWHUXVHGWRFRPPXQLFDWHLQWHUUXSWOLQH URXWLQJLQIRUPDWLRQ7KHUHJLVWHULVUHDGZULWHDQGPXVWEHLPSOHPHQWHGE\DQ\GHYLFH RUGHYLFHIXQFWLRQ WKDWXVHVDQLQWHUUXSWSLQ3267VRIWZDUHZLOOZULWHWKHURXWLQJ LQIRUPDWLRQLQWRWKLVUHJLVWHUDVLWLQLWLDOL]HVDQGFRQILJXUHVWKHV\VWHP 7KHYDOXHLQWKLVUHJLVWHUWHOOVZKLFKLQSXWRIWKHV\VWHPLQWHUUXSWFRQWUROOHU V WKH GHYLFH VLQWHUUXSWSLQLVFRQQHFWHGWR7KHGHYLFHLWVHOIGRHVQRWXVHWKLVYDOXHUDWKHULW LVXVHGE\GHYLFHGULYHUVDQGRSHUDWLQJV\VWHPV'HYLFHGULYHUVDQGRSHUDWLQJV\VWHPV 199 Revision 2.2 FDQXVHWKLVLQIRUPDWLRQWRGHWHUPLQHSULRULW\DQGYHFWRULQIRUPDWLRQ9DOXHVLQWKLV UHJLVWHUDUHV\VWHPDUFKLWHFWXUHVSHFLILF ,QWHUUXSW3LQ 7KH,QWHUUXSW3LQUHJLVWHUWHOOVZKLFKLQWHUUXSWSLQWKHGHYLFH RUGHYLFHIXQFWLRQ XVHV $YDOXHRIFRUUHVSRQGVWRINTA#$YDOXHRIFRUUHVSRQGVWRINTB#$YDOXHRI FRUUHVSRQGVWRINTC#$YDOXHRIFRUUHVSRQGVWRINTD#'HYLFHV RUGHYLFH IXQFWLRQV WKDWGRQRWXVHDQLQWHUUXSWSLQPXVWSXWDLQWKLVUHJLVWHU7KHYDOXHVK WKURXJK))KDUHUHVHUYHG7KLVUHJLVWHULVUHDGRQO\5HIHUWR6HFWLRQIRUIXUWKHU GHVFULSWLRQRIWKHXVDJHRIWKHINTx#SLQV 0,1B*17DQG0$;B/$7 7KHVHUHDGRQO\E\WHUHJLVWHUVDUHXVHGWRVSHFLI\WKHGHYLFH¶VGHVLUHGVHWWLQJVIRU /DWHQF\7LPHUYDOXHV)RUERWKUHJLVWHUVWKHYDOXHVSHFLILHVDSHULRGRIWLPHLQXQLWVRI óPLFURVHFRQG9DOXHVRILQGLFDWHWKDWWKHGHYLFHKDVQRPDMRUUHTXLUHPHQWVIRUWKH VHWWLQJVRI/DWHQF\7LPHUV 0,1B*17LVXVHGIRUVSHFLI\LQJKRZORQJDEXUVWSHULRGWKHGHYLFHQHHGVDVVXPLQJD FORFNUDWHRI0+]0$;B/$7LVXVHGIRUVSHFLI\LQJKRZRIWHQWKHGHYLFHQHHGVWR JDLQDFFHVVWRWKH3&,EXV 'HYLFHVVKRXOGVSHFLI\YDOXHVWKDWZLOODOORZWKHPWRPRVWHIIHFWLYHO\XVHWKH3&,EXVDV ZHOODVWKHLULQWHUQDOUHVRXUFHV9DOXHVVKRXOGEHFKRVHQDVVXPLQJWKDWWKHWDUJHWGRHV QRWLQVHUWDQ\ZDLWVWDWHV Implementation Example: Choosing MIN_GNT and MAX_LAT $IDVW(WKHUQHWFRQWUROOHU 0EV KDVDE\WHEXIIHUIRUHDFKWUDQVIHUGLUHFWLRQ 2SWLPDOXVDJHRIWKHVHLQWHUQDOUHVRXUFHVLVDFKLHYHGZKHQWKHGHYLFHWUHDWVHDFKEXIIHU DVWZRE\WHSLQJSRQJEXIIHUV(DFKE\WHEXIIHUKDVHLJKW':25'6RIGDWDWREH WUDQVIHUUHGUHVXOWLQJLQHLJKWGDWDSKDVHVRQWKH3&,EXV7KHVHHLJKWGDWDSKDVHV WUDQVODWHWRóPLFURVHFRQGDW0+]VRWKH0,1B*17YDOXHIRUWKLVGHYLFHLV³´ :KHQPRYLQJGDWDWKHGHYLFHZLOOQHHGWRHPSW\RUILOODE\WHEXIIHUHYHU\µV DVVXPLQJDWKURXJKSXWRI0%V 7KLVZRXOGFRUUHVSRQGWRD0$;B/$7YDOXHRI 6XEV\VWHP9HQGRU,'DQG6XEV\VWHP,' 7KHVHUHJLVWHUVDUHXVHGWRXQLTXHO\LGHQWLI\WKHH[SDQVLRQERDUGRUVXEV\VWHPZKHUHWKH 3&,GHYLFHUHVLGHV7KH\SURYLGHDPHFKDQLVPIRUH[SDQVLRQERDUGYHQGRUVWR GLVWLQJXLVKWKHLUERDUGVIURPRQHDQRWKHUHYHQWKRXJKWKHERDUGVPD\KDYHWKHVDPH3&, FRQWUROOHURQWKHP DQGWKHUHIRUHWKHVDPH9HQGRU,'DQG'HYLFH,' 43 For x86 based PCs, the values in this register correspond to IRQ numbers (0-15) of the standard dual 8259 configuration. The value 255 is defined as meaning "unknown" or "no connection" to the interrupt controller. Values between 15 and 254 are reserved. 200 Revision 2.2 ,PSOHPHQWDWLRQRIWKHVHUHJLVWHUVLVUHTXLUHGIRUDOO3&,GHYLFHVH[FHSWWKRVHWKDWKDYHD EDVHFODVVZLWKVXEFODVV RUDEDVHFODVVZLWKVXEFODVV 6XEV\VWHP9HQGRU,'VFDQEHREWDLQHGIURPWKH3&,6,*DQGDUHXVHGWRLGHQWLI\WKH YHQGRURIWKHH[SDQVLRQERDUGRUVXEV\VWHP 9DOXHVIRUWKH6XEV\VWHP,'DUHYHQGRU VSHFLILF 9DOXHVLQWKHVHUHJLVWHUVPXVWEHORDGHGDQGYDOLGSULRUWRWKHV\VWHP%,26RUDQ\ V\VWHPVRIWZDUHDFFHVVLQJWKH3&,&RQILJXUDWLRQ6SDFH+RZWKHVHYDOXHVDUHORDGHGLV QRWVSHFLILHGEXWFRXOGEHGRQHGXULQJWKHPDQXIDFWXULQJSURFHVVRUORDGHGIURP H[WHUQDOORJLF HJVWUDSSLQJRSWLRQVVHULDO520VHWF 7KHVHYDOXHVPXVWQRWEH ORDGHGXVLQJH[SDQVLRQ520VRIWZDUHEHFDXVHH[SDQVLRQ520VRIWZDUHLVQRW JXDUDQWHHGWREHUXQGXULQJ3267LQDOOV\VWHPV'HYLFHVDUHUHVSRQVLEOHIRU JXDUDQWHHLQJWKHGDWDLVYDOLGEHIRUHDOORZLQJUHDGVWRWKHVHUHJLVWHUVWRFRPSOHWH7KLV FDQEHGRQHE\UHVSRQGLQJWRDQ\DFFHVVHVZLWK5HWU\XQWLOWKHGDWDLVYDOLG ,IDGHYLFHLVGHVLJQHGWREHXVHGH[FOXVLYHO\RQWKHPRWKHUERDUGWKHV\VWHPYHQGRUPD\ XVHV\VWHPVSHFLILFVRIWZDUHWRLQLWLDOL]HWKHVHUHJLVWHUVDIWHUHDFKSRZHURQ &DSDELOLWLHV3RLQWHU 7KLVRSWLRQDOUHJLVWHULVXVHGWRSRLQWWRDOLQNHGOLVWRIQHZFDSDELOLWLHVLPSOHPHQWHGE\ WKLVGHYLFH7KLVUHJLVWHULVRQO\YDOLGLIWKH³&DSDELOLWLHV/LVW´ELWLQWKH6WDWXV5HJLVWHU LVVHW,ILPSOHPHQWHGWKHERWWRPWZRELWVDUHUHVHUYHGDQGVKRXOGEHVHWWRE 6RIWZDUHVKRXOGPDVNWKHVHELWVRIIEHIRUHXVLQJWKLVUHJLVWHUDVDSRLQWHULQ &RQILJXUDWLRQ6SDFHWRWKHILUVWHQWU\RIDOLQNHGOLVWRIQHZFDSDELOLWLHV5HIHUWR 6HFWLRQIRUDGHVFULSWLRQRIWKLVGDWDVWUXFWXUH 6.2.5. Base Addresses 2QHRIWKHPRVWLPSRUWDQWIXQFWLRQVIRUHQDEOLQJVXSHULRUFRQILJXUDELOLW\DQGHDVHRIXVH LVWKHDELOLW\WRUHORFDWH3&,GHYLFHVLQWKHDGGUHVVVSDFHV$WV\VWHPSRZHUXSGHYLFH LQGHSHQGHQWVRIWZDUHPXVWEHDEOHWRGHWHUPLQHZKDWGHYLFHVDUHSUHVHQWEXLOGD FRQVLVWHQWDGGUHVVPDSDQGGHWHUPLQHLIDGHYLFHKDVDQH[SDQVLRQ520(DFKRIWKHVH DUHDVLVFRYHUHGLQWKHIROORZLQJVHFWLRQV 6.2.5.1. Address Maps 3RZHUXSVRIWZDUHQHHGVWREXLOGDFRQVLVWHQWDGGUHVVPDSEHIRUHERRWLQJWKHPDFKLQH WRDQRSHUDWLQJV\VWHP7KLVPHDQVLWKDVWRGHWHUPLQHKRZPXFKPHPRU\LVLQWKH V\VWHPDQGKRZPXFKDGGUHVVVSDFHWKH,2FRQWUROOHUVLQWKHV\VWHPUHTXLUH$IWHU GHWHUPLQLQJWKLVLQIRUPDWLRQSRZHUXSVRIWZDUHFDQPDSWKH,2FRQWUROOHUVLQWR UHDVRQDEOHORFDWLRQVDQGSURFHHGZLWKV\VWHPERRW,QRUGHUWRGRWKLVPDSSLQJLQD GHYLFHLQGHSHQGHQWPDQQHUWKHEDVHUHJLVWHUVIRUWKLVPDSSLQJDUHSODFHGLQWKH SUHGHILQHGKHDGHUSRUWLRQRI&RQILJXUDWLRQ6SDFH %LWLQDOO%DVH$GGUHVVUHJLVWHUVLVUHDGRQO\DQGXVHGWRGHWHUPLQHZKHWKHUWKH UHJLVWHUPDSVLQWR0HPRU\RU,26SDFH%DVH$GGUHVVUHJLVWHUVWKDWPDSWR0HPRU\ 44 A company has only one Vendor ID. That value can be used in either the Vendor ID field of configuration space (offset 00h) or the Subsystem Vendor ID field of configuration space (offset 2Ch). It is used in the Vendor ID field (offset 00h) if the company built the silicon. It is used in the Subsystem Vendor ID field (offset 2Ch) if the company built the add-in card. If a company builds both the silicon and the add- in card, then the same value would be used in both fields. 201 Revision 2.2 6SDFHPXVWUHWXUQDLQELW VHH)LJXUH %DVH$GGUHVVUHJLVWHUVWKDWPDSWR,2 6SDFHPXVWUHWXUQDLQELW VHH)LJXUH )LJXUH %DVH$GGUHVV5HJLVWHUIRU0HPRU\ 31 2 1 0 Base Address 0 1 Reserved IO space indicator )LJXUH %DVH$GGUHVV5HJLVWHUIRU,2 %DVH$GGUHVVUHJLVWHUVWKDWPDSLQWR,26SDFHDUHDOZD\VELWVZLGHZLWKELW KDUGZLUHGWRD%LWLVUHVHUYHGDQGPXVWUHWXUQRQUHDGVDQGWKHRWKHUELWVDUHXVHG WRPDSWKHGHYLFHLQWR,26SDFH %DVH$GGUHVVUHJLVWHUVWKDWPDSLQWR0HPRU\6SDFHFDQEHELWVRUELWVZLGH WR VXSSRUWPDSSLQJLQWRDELWDGGUHVVVSDFH ZLWKELWKDUGZLUHGWRD)RU0HPRU\ %DVH$GGUHVVUHJLVWHUVELWVDQGKDYHDQHQFRGHGPHDQLQJDVVKRZQLQ7DEOH %LWVKRXOGEHVHWWRLIWKHGDWDLVSUHIHWFKDEOHDQGUHVHWWRRWKHUZLVH$GHYLFHFDQ PDUNDUDQJHDVSUHIHWFKDEOHLIWKHUHDUHQRVLGHHIIHFWVRQUHDGVWKHGHYLFHUHWXUQVDOO E\WHVRQUHDGVUHJDUGOHVVRIWKHE\WHHQDEOHVDQGKRVWEULGJHVFDQPHUJHSURFHVVRU ZULWHV UHIHUWR6HFWLRQ LQWRWKLVUDQJH ZLWKRXWFDXVLQJHUURUV%LWVDUHUHDG RQO\ 45 Any device that has a range that behaves like normal memory should mark the range as prefetchable. A linear frame buffer in a graphics device is an example of a range that should be marked prefetchable. 202 Revision 2.2 7DEOH 0HPRU\%DVH$GGUHVV5HJLVWHU%LWV(QFRGLQJ Bits 2/1 Meaning 00 Base register is 32 bits wide and mapping can be done anywhere in the 32-bit Memory Space. 01 Reserved46 10 Base register is 64 bits wide and can be mapped anywhere in the 64-bit address space. 11 Reserved 7KHQXPEHURIXSSHUELWVWKDWDGHYLFHDFWXDOO\LPSOHPHQWVGHSHQGVRQKRZPXFKRIWKH DGGUHVVVSDFHWKHGHYLFHZLOOUHVSRQGWR$ELWUHJLVWHUFDQEHLPSOHPHQWHGWR VXSSRUWDVLQJOHPHPRU\VL]HWKDWLVDSRZHURIIURPE\WHVWR*%$GHYLFHWKDW ZDQWVD0%PHPRU\DGGUHVVVSDFH XVLQJDELWEDVHDGGUHVVUHJLVWHU ZRXOGEXLOG WKHWRSELWVRIWKHDGGUHVVUHJLVWHUKDUGZLULQJWKHRWKHUELWVWR 3RZHUXSVRIWZDUHFDQGHWHUPLQHKRZPXFKDGGUHVVVSDFHWKHGHYLFHUHTXLUHVE\ZULWLQJ DYDOXHRIDOO VWRWKHUHJLVWHUDQGWKHQUHDGLQJWKHYDOXHEDFN7KHGHYLFHZLOOUHWXUQ VLQDOOGRQ WFDUHDGGUHVVELWVHIIHFWLYHO\VSHFLI\LQJWKHDGGUHVVVSDFHUHTXLUHG 8QLPSOHPHQWHG%DVH$GGUHVVUHJLVWHUVDUHKDUGZLUHGWR]HUR 7KLVGHVLJQLPSOLHVWKDWDOODGGUHVVVSDFHVXVHGDUHDSRZHURIWZRLQVL]HDQGDUH QDWXUDOO\DOLJQHG'HYLFHVDUHIUHHWRFRQVXPHPRUHDGGUHVVVSDFHWKDQUHTXLUHGEXW GHFRGLQJGRZQWRD.%VSDFHIRUPHPRU\LVVXJJHVWHGIRUGHYLFHVWKDWQHHGOHVVWKDQ WKDWDPRXQW)RULQVWDQFHDGHYLFHWKDWKDVE\WHVRIUHJLVWHUVWREHPDSSHGLQWR 0HPRU\6SDFHPD\FRQVXPHXSWR.%RIDGGUHVVVSDFHLQRUGHUWRPLQLPL]HWKH QXPEHURIELWVLQWKHDGGUHVVGHFRGHU'HYLFHVWKDWGRFRQVXPHPRUHDGGUHVVVSDFHWKDQ WKH\XVHDUHQRWUHTXLUHGWRUHVSRQGWRWKHXQXVHGSRUWLRQRIWKDWDGGUHVVVSDFH'HYLFHV WKDWPDSFRQWUROIXQFWLRQVLQWR,26SDFHPXVWQRWFRQVXPHPRUHWKDQE\WHVSHU,2 %DVH$GGUHVVUHJLVWHU7KHXSSHUELWVRIWKH,2%DVH$GGUHVVUHJLVWHUPD\EH KDUGZLUHGWR]HURIRUGHYLFHVLQWHQGHGIRUELW,2V\VWHPVVXFKDV3&FRPSDWLEOHV +RZHYHUDIXOOELWGHFRGHRI,2DGGUHVVHVPXVWVWLOOEHGRQH 46 The encoding to support memory space below 1M was supported in previous versions of the specification. System software should recognize this encoding and handle appropriately. 203 Revision 2.2 Implementation Note: Sizing a 32 bit Base Address Register Example 'HFRGH ,2RUPHPRU\ RIDUHJLVWHULVGLVDEOHGYLDWKHFRPPDQGUHJLVWHUEHIRUHVL]LQJ D%DVH$GGUHVVUHJLVWHU6RIWZDUHVDYHVWKHRULJLQDOYDOXHRIWKH%DVH$GGUHVVUHJLVWHU ZULWHV))))))))KWRWKHUHJLVWHUWKHQUHDGVLWEDFN6L]HFDOFXODWLRQFDQEHGRQHIURP WKHELWYDOXHUHDGE\ILUVWFOHDULQJHQFRGLQJLQIRUPDWLRQELWV ELWIRU,2ELWVIRU PHPRU\ LQYHUWLQJDOOELWV ORJLFDO127 WKHQLQFUHPHQWLQJE\7KHUHVXOWDQW ELWYDOXHLVWKHPHPRU\,2UDQJHVL]HGHFRGHGE\WKHUHJLVWHU1RWHWKDWWKHXSSHU ELWVRIWKHUHVXOWLVLJQRUHGLIWKH%DVH$GGUHVVUHJLVWHULVIRU,2DQGELWVUHWXUQHG ]HURXSRQUHDG7KHRULJLQDOYDOXHLQWKH%DVH$GGUHVVUHJLVWHULVUHVWRUHGEHIRUHUH HQDEOLQJGHFRGHLQWKHFRPPDQGUHJLVWHURIWKHGHYLFH ELW PHPRU\ %DVH$GGUHVVUHJLVWHUVFDQEHKDQGOHGWKHVDPHH[FHSWWKDWWKHVHFRQG ELWUHJLVWHULVFRQVLGHUHGDQH[WHQVLRQRIWKHILUVW LHELWV6RIWZDUHZULWHV ))))))))KWRERWKUHJLVWHUVUHDGVWKHPEDFNDQGFRPELQHVWKHUHVXOWLQWRDELW YDOXH6L]HFDOFXODWLRQLVGRQHRQWKHELWYDOXH $W\SHKSUHGHILQHGKHDGHUKDVVL[':25'ORFDWLRQVDOORFDWHGIRU%DVH$GGUHVV UHJLVWHUVVWDUWLQJDWRIIVHWKLQ&RQILJXUDWLRQ6SDFH$GHYLFHPD\XVHDQ\RIWKH ORFDWLRQVWRLPSOHPHQW%DVH$GGUHVVUHJLVWHUV$QLPSOHPHQWHGELW%DVH$GGUHVV UHJLVWHUFRQVXPHVWZRFRQVHFXWLYH':25'ORFDWLRQV6RIWZDUHORRNLQJIRU LPSOHPHQWHG%DVH$GGUHVVUHJLVWHUVPXVWVWDUWDWRIIVHWKDQGFRQWLQXHXSZDUGV WKURXJKRIIVHWK$W\SLFDOGHYLFHZLOOUHTXLUHRQHPHPRU\UDQJHIRULWVFRQWURO IXQFWLRQV6RPHJUDSKLFVGHYLFHVPD\XVHWZRUDQJHVRQHIRUFRQWUROIXQFWLRQVDQG DQRWKHUIRUDIUDPHEXIIHU$GHYLFHWKDWZDQWVWRPDSFRQWUROIXQFWLRQVLQWRERWK PHPRU\DQG,26SDFHVDWWKHVDPHWLPHPXVWLPSOHPHQWWZR%DVH$GGUHVVUHJLVWHUV RQHPHPRU\DQGRQH,2 7KHGULYHUIRUWKDWGHYLFHPLJKWRQO\XVHRQHVSDFHLQZKLFK FDVHWKHRWKHUVSDFHZLOOEHXQXVHG'HYLFHVDUHUHFRPPHQGHGDOZD\VWRPDSFRQWURO IXQFWLRQVLQWR0HPRU\6SDFH 6.2.5.2. Expansion ROM Base Address Register 6RPH3&,GHYLFHVHVSHFLDOO\WKRVHWKDWDUHLQWHQGHGIRUXVHRQH[SDQVLRQERDUGVLQ3& DUFKLWHFWXUHVUHTXLUHORFDO(3520VIRUH[SDQVLRQ520 UHIHUWR6HFWLRQIRUD GHILQLWLRQRI520FRQWHQWV 7KHIRXUE\WHUHJLVWHUDWRIIVHWKLQDW\SHK SUHGHILQHGKHDGHULVGHILQHGWRKDQGOHWKHEDVHDGGUHVVDQGVL]HLQIRUPDWLRQIRUWKLV H[SDQVLRQ520)LJXUHVKRZVKRZWKLVZRUGLVRUJDQL]HG7KHUHJLVWHUIXQFWLRQV H[DFWO\OLNHDELW%DVH$GGUHVVUHJLVWHUH[FHSWWKDWWKHHQFRGLQJ DQGXVDJH RIWKH ERWWRPELWVLVGLIIHUHQW7KHXSSHUELWVFRUUHVSRQGWRWKHXSSHUELWVRIWKH ([SDQVLRQ520EDVHDGGUHVV7KHQXPEHURIELWV RXWRIWKHVH WKDWDGHYLFH DFWXDOO\LPSOHPHQWVGHSHQGVRQKRZPXFKDGGUHVVVSDFHWKHGHYLFHUHTXLUHV)RU LQVWDQFHDGHYLFHWKDWUHTXLUHVD.%DUHDWRPDSLWVH[SDQVLRQ520ZRXOG LPSOHPHQWWKHWRSELWVLQWKHUHJLVWHUOHDYLQJWKHERWWRP RXWRIWKHVH KDUGZLUHGWR'HYLFHVWKDWVXSSRUWDQH[SDQVLRQ520PXVWLPSOHPHQWWKLVUHJLVWHU 'HYLFHLQGHSHQGHQWFRQILJXUDWLRQVRIWZDUHFDQGHWHUPLQHKRZPXFKDGGUHVVVSDFHWKH GHYLFHUHTXLUHVE\ZULWLQJDYDOXHRIDOO VWRWKHDGGUHVVSRUWLRQRIWKHUHJLVWHUDQGWKHQ UHDGLQJWKHYDOXHEDFN7KHGHYLFHZLOOUHWXUQ VLQDOOGRQ WFDUHELWVHIIHFWLYHO\ VSHFLI\LQJWKHVL]HDQGDOLJQPHQWUHTXLUHPHQWV7KHDPRXQWRIDGGUHVVVSDFHDGHYLFH UHTXHVWVPXVWQRWEHJUHDWHUWKDQ0% 204 Revision 2.2 31 11 10 1 0 Expansion ROM Base Address Reserved (Upper 21 bits) Expansion ROM Enable )LJXUH ([SDQVLRQ520%DVH$GGUHVV5HJLVWHU/D\RXW %LWLQWKHUHJLVWHULVXVHGWRFRQWUROZKHWKHURUQRWWKHGHYLFHDFFHSWVDFFHVVHVWRLWV H[SDQVLRQ520:KHQWKLVELWLVWKHGHYLFH¶VH[SDQVLRQ520DGGUHVVVSDFHLV GLVDEOHG:KHQWKHELWLVDGGUHVVGHFRGLQJLVHQDEOHGXVLQJWKHSDUDPHWHUVLQWKH RWKHUSDUWRIWKHEDVHUHJLVWHU7KLVDOORZVDGHYLFHWREHXVHGZLWKRUZLWKRXWDQ H[SDQVLRQ520GHSHQGLQJRQV\VWHPFRQILJXUDWLRQ7KH0HPRU\6SDFHELWLQWKH &RPPDQGUHJLVWHUKDVSUHFHGHQFHRYHUWKH([SDQVLRQ520HQDEOHELW$GHYLFHPXVW UHVSRQGWRDFFHVVHVWRLWVH[SDQVLRQ520RQO\LIERWKWKH0HPRU\6SDFHELWDQGWKH ([SDQVLRQ520%DVH$GGUHVV(QDEOHELWDUHVHWWR7KLVELW VVWDWHDIWHURST#LV ,QRUGHUWRPLQLPL]HWKHQXPEHURIDGGUHVVGHFRGHUVQHHGHGDGHYLFHPD\VKDUHD GHFRGHUEHWZHHQWKH([SDQVLRQ520%DVH$GGUHVVUHJLVWHUDQGRWKHU%DVH$GGUHVV UHJLVWHUV :KHQH[SDQVLRQ520GHFRGHLVHQDEOHGWKHGHFRGHULVXVHGIRUDFFHVVHVWR WKHH[SDQVLRQ520DQGGHYLFHLQGHSHQGHQWVRIWZDUHPXVWQRWDFFHVVWKHGHYLFHWKURXJK DQ\RWKHU%DVH$GGUHVVUHJLVWHUV 6.3. PCI Expansion ROMs 7KH3&,VSHFLILFDWLRQSURYLGHVDPHFKDQLVPZKHUHGHYLFHVFDQSURYLGHH[SDQVLRQ520 FRGHWKDWFDQEHH[HFXWHGIRUGHYLFHVSHFLILFLQLWLDOL]DWLRQDQGSRVVLEO\DV\VWHPERRW IXQFWLRQ UHIHUWR6HFWLRQ 7KHPHFKDQLVPDOORZVWKH520WRFRQWDLQVHYHUDO GLIIHUHQWLPDJHVWRDFFRPPRGDWHGLIIHUHQWPDFKLQHDQGSURFHVVRUDUFKLWHFWXUHV7KLV VHFWLRQVSHFLILHVWKHUHTXLUHGLQIRUPDWLRQDQGOD\RXWRIFRGHLPDJHVLQWKHH[SDQVLRQ 5201RWHWKDW3&,GHYLFHVWKDWVXSSRUWDQH[SDQVLRQ520PXVWDOORZWKDW520WR EHDFFHVVHGZLWKDQ\FRPELQDWLRQRIE\WHHQDEOHV7KLVVSHFLILFDOO\PHDQVWKDW ':25'DFFHVVHVWRWKHH[SDQVLRQ520PXVWEHVXSSRUWHG 7KHLQIRUPDWLRQLQWKH520VLVODLGRXWWREHFRPSDWLEOHZLWKH[LVWLQJ,QWHO[ ([SDQVLRQ520KHDGHUVIRU,6$(,6$DQG0&DGDSWHUVEXWLWZLOODOVRVXSSRUWRWKHU PDFKLQHDUFKLWHFWXUHV7KHLQIRUPDWLRQDYDLODEOHLQWKHKHDGHUKDVEHHQH[WHQGHGVRWKDW PRUHRSWLPXPXVHFDQEHPDGHRIWKHIXQFWLRQSURYLGHGE\WKHDGDSWHUDQGVRWKDWWKH PLQLPXPDPRXQWRI0HPRU\6SDFHLVXVHGE\WKHUXQWLPHSRUWLRQRIWKHH[SDQVLRQ 520FRGH 7KH3&,([SDQVLRQ520KHDGHULQIRUPDWLRQVXSSRUWVWKHIROORZLQJIXQFWLRQV • $OHQJWKFRGHLVSURYLGHGWRLGHQWLI\WKHWRWDOFRQWLJXRXVDGGUHVVVSDFHQHHGHGE\ WKH3&,GHYLFH520LPDJHDWLQLWLDOL]DWLRQ • $QLQGLFDWRULGHQWLILHVWKHW\SHRIH[HFXWDEOHRULQWHUSUHWLYHFRGHWKDWH[LVWVLQWKH 520DGGUHVVVSDFHLQHDFK520LPDJH • $UHYLVLRQOHYHOIRUWKHFRGHDQGGDWDRQWKH520LVSURYLGHG • 7KH9HQGRU,'DQG'HYLFH,'RIWKHVXSSRUWHG3&,GHYLFHDUHLQFOXGHGLQWKH520 47Note that it is the address decoder that is shared, not the registers themselves. The Expansion ROM Base Address register and other Base Address registers must be able to hold unique values at the same time. 205 Revision 2.2 2QHPDMRUGLIIHUHQFHLQWKHXVDJHPRGHOEHWZHHQ3&,H[SDQVLRQ520VDQGVWDQGDUG ,6$(,6$DQG0&520VLVWKDWWKH520FRGHLVQHYHUH[HFXWHGLQSODFH,WLVDOZD\V FRSLHGIURPWKH520GHYLFHWR5$0DQGH[HFXWHGIURP5$07KLVHQDEOHVG\QDPLF VL]LQJRIWKHFRGH IRULQLWLDOL]DWLRQDQGUXQWLPH DQGSURYLGHVVSHHGLPSURYHPHQWVZKHQ H[HFXWLQJUXQWLPHFRGH 6.3.1. PCI Expansion ROM Contents 3&,GHYLFHH[SDQVLRQ520VPD\FRQWDLQFRGH H[HFXWDEOHRULQWHUSUHWLYH IRUPXOWLSOH SURFHVVRUDUFKLWHFWXUHV7KLVPD\EHLPSOHPHQWHGLQDVLQJOHSK\VLFDO520ZKLFKFDQ FRQWDLQDVPDQ\FRGHLPDJHVDVGHVLUHGIRUGLIIHUHQWV\VWHPDQGSURFHVVRUDUFKLWHFWXUHV VHH)LJXUH (DFKLPDJHPXVWVWDUWRQDE\WHERXQGDU\DQGPXVWFRQWDLQWKH 3&,H[SDQVLRQ520KHDGHU7KHVWDUWLQJSRLQWRIHDFKLPDJHGHSHQGVRQWKHVL]HRI SUHYLRXVLPDJHV7KHODVWLPDJHLQD520KDVDVSHFLDOHQFRGLQJLQWKHKHDGHUWR LGHQWLI\LWDVWKHODVWLPDJH Image 0 Image 1 Image N )LJXUH 3&,([SDQVLRQ5206WUXFWXUH 6.3.1.1. PCI Expansion ROM Header Format 7KHLQIRUPDWLRQUHTXLUHGLQHDFK520LPDJHLVVSOLWLQWRWZRGLIIHUHQWDUHDV2QHDUHD WKH520KHDGHULVUHTXLUHGWREHORFDWHGDWWKHEHJLQQLQJRIWKH520LPDJH7KH VHFRQGDUHDWKH3&,'DWD6WUXFWXUHPXVWEHORFDWHGLQWKHILUVW.%RIWKHLPDJH 7KHIRUPDWIRUWKH3&,([SDQVLRQ520+HDGHULVJLYHQEHORZ7KHRIIVHWLVD KH[DGHFLPDOQXPEHUIURPWKHEHJLQQLQJRIWKHLPDJHDQGWKHOHQJWKRIHDFKILHOGLV JLYHQLQE\WHV ([WHQVLRQVWRWKH3&,([SDQVLRQ520+HDGHUDQGRUWKH3&,'DWD6WUXFWXUHPD\EH GHILQHGE\VSHFLILFV\VWHPDUFKLWHFWXUHV([WHQVLRQVIRU3&$7FRPSDWLEOHV\VWHPVDUH GHVFULEHGLQ6HFWLRQ 206 Revision 2.2 Offset Length Value Description 0h 1 55h ROM Signature, byte 1 1h 1 AAh ROM Signature, byte 2 2h-17h 16h xx Reserved (processor architecture unique data) 18h-19h 2 xx Pointer to PCI Data Structure ROM Signature The ROM Signature is a two-byte field containing a 55h in the first byte and AAh in the second byte. This signature must be the first two bytes of the ROM address space for each image of the ROM. Pointer to PCI Data The Pointer to the PCI Data Structure is a two-byte pointer in Structure little endian format that points to the PCI Data Structure. The reference point for this pointer is the beginning of the ROM image. 6.3.1.2. PCI Data Structure Format 7KH3&,'DWD6WUXFWXUHPXVWEHORFDWHGZLWKLQWKHILUVW.%RIWKH520LPDJHDQG PXVWEH':25'DOLJQHG7KH3&,'DWD6WUXFWXUHFRQWDLQVWKHIROORZLQJLQIRUPDWLRQ Offset Length Description 0 4 Signature, the string "PCIR" 4 2 Vendor Identification 6 2 Device Identification 8 2 Reserved A 2 PCI Data Structure Length C 1 PCI Data Structure Revision D 3 Class Code 10 2 Image Length 12 2 Revision Level of Code/Data 14 1 Code Type 15 1 Indicator 16 2 Reserved Signature These four bytes provide a unique signature for the PCI Data Structure. The string "PCIR" is the signature with "P" being at offset 0, "C" at offset 1, etc. Vendor Identification The Vendor Identification field is a 16-bit field with the same definition as the Vendor Identification field in the Configuration Space for this device. Device Identification The Device Identification field is a 16-bit field with the same definition as the Device Identification field in the Configuration Space for this device. 207 Revision 2.2 Resvd Reserved 16-bit field. Note that in earlier versions of the PCI Local Bus Specification this field pointed to ROM located Vital Product Data. This has been superseded by Vital Product Data as described in Section 6.4. PCI Data Structure The PCI Data Structure Length is a 16-bit field that defines Length the length of the data structure from the start of the data structure (the first byte of the Signature field). This field is in little-endian format and is in units of bytes. PCI Data Structure The PCI Data Structure Revision field is an eight-bit field that Revision identifies the data structure revision level. This revision level is 0. Class Code The Class Code field is a 24-bit field with the same fields and definition as the class code field in the Configuration Space for this device. Image Length The Image Length field is a two-byte field that represents the length of the image. This field is in little-endian format, and the value is in units of 512 bytes. Revision Level The Revision Level field is a two-byte field that contains the revision level of the code in the ROM image. Code Type The Code Type field is a one-byte field that identifies the type of code contained in this section of the ROM. The code may be executable binary for a specific processor and system architecture or interpretive code. The following code types are assigned: 7\SH 'HVFULSWLRQ ,QWHO[3&$7FRPSDWLEOH 2SHQ)LUPZDUHVWDQGDUGIRU3&, +HZOHWW3DFNDUG3$5,6& )) 5HVHUYHG Indicator Bit 7 in this field tells whether or not this is the last image in the ROM. A value of 1 indicates "last image;" a value of 0 indicates that another image follows. Bits 0-6 are reserved. 48 Open Firmware is a processor architecture and system architecture independent standard for dealing with device specific option ROM code. Documentation for Open Firmware is available in the IEEE 1275-1994 Standard for Boot (Initialization, Configuration) Firmware Core Requirements and Practices. A related document, PCI Bus Binding to IEEE 1275-1994, specifies the application of Open Firmware to the PCI local bus, including PCI-specific requirements and practices. This document may be obtained using anonymous FTP to the machine playground.sun.com with the filename /pub/p1275/bindings/postscript/PCI.ps. 208 Revision 2.2 6.3.2. Power-on Self Test (POST) Code )RUWKHPRVWSDUWV\VWHP3267FRGHWUHDWVDGGLQ3&,GHYLFHVLGHQWLFDOO\WRWKRVHWKDW DUHVROGHUHGRQWRWKHPRWKHUERDUG7KHRQHH[FHSWLRQLVWKHKDQGOLQJRIH[SDQVLRQ 520V3267FRGHGHWHFWVWKHSUHVHQFHRIDQRSWLRQ520LQWZRVWHSV)LUVWWKHFRGH GHWHUPLQHVLIWKHGHYLFHKDVLPSOHPHQWHGDQ([SDQVLRQ520%DVH$GGUHVVUHJLVWHULQ &RQILJXUDWLRQ6SDFH,IWKHUHJLVWHULVLPSOHPHQWHGWKH3267PXVWPDSDQGHQDEOHWKH 520LQDQXQXVHGSRUWLRQRIWKHDGGUHVVVSDFHDQGFKHFNWKHILUVWWZRE\WHVIRUWKH $$KVLJQDWXUH,IWKDWVLJQDWXUHLVIRXQGWKHUHLVD520SUHVHQW RWKHUZLVHQR520 LVDWWDFKHGWRWKHGHYLFH ,ID520LVDWWDFKHGWKH3267PXVWVHDUFKWKH520IRUDQLPDJHWKDWKDVWKHSURSHU FRGHW\SHDQGZKRVH9HQGRU,'DQG'HYLFH,'ILHOGVPDWFKWKHFRUUHVSRQGLQJILHOGVLQ WKHGHYLFH $IWHUILQGLQJWKHSURSHULPDJHWKH3267FRSLHVWKHDSSURSULDWHDPRXQWRIGDWDLQWR 5$07KHQWKHGHYLFH VLQLWLDOL]DWLRQFRGHLVH[HFXWHG'HWHUPLQLQJWKHDSSURSULDWH DPRXQWRIGDWDWRFRS\DQGKRZWRH[HFXWHWKHGHYLFH VLQLWLDOL]DWLRQFRGHZLOOGHSHQGRQ WKHFRGHW\SHIRUWKHILHOG 6.3.3. PC-compatible Expansion ROMs 7KLVVHFWLRQGHVFULEHVIXUWKHUUHTXLUHPHQWVRQ520LPDJHVDQGWKHKDQGOLQJRI520 LPDJHVWKDWDUHXVHGLQ3&FRPSDWLEOHV\VWHPV7KLVDSSOLHVWRDQ\LPDJHWKDWVSHFLILHV ,QWHO[3&$7FRPSDWLEOHLQWKH&RGH7\SHILHOGRIWKH3&,'DWD6WUXFWXUHDQGDQ\ SODWIRUPWKDWLV3&FRPSDWLEOH 6.3.3.1. ROM Header Extensions 7KHVWDQGDUGKHDGHUIRU3&,([SDQVLRQ520LPDJHVLVH[SDQGHGVOLJKWO\IRU3& FRPSDWLELOLW\7ZRILHOGVDUHDGGHGRQHDWRIIVHWKSURYLGHVWKHLQLWLDOL]DWLRQVL]HIRU WKHLPDJH2IIVHWKLVWKHHQWU\SRLQWIRUWKHH[SDQVLRQ520,1,7IXQFWLRQ Offset Length Value Description 0h 1 55h ROM Signature byte 1 1h 1 AAh ROM Signature byte 2 2h 1 xx Initialization Size - size of the code in units of 512 bytes 3h 3 xx Entry point for INIT function. POST does a FAR CALL to this location. 6h-17h 12h xx Reserved (application unique data) 18h-19h 2 xx Pointer to PCI Data Structure 6.3.3.1.1. POST Code Extensions 3267FRGHLQWKHVHV\VWHPVFRSLHVWKHQXPEHURIE\WHVVSHFLILHGE\WKH,QLWLDOL]DWLRQ 6L]HILHOGLQWR5$0DQGWKHQFDOOVWKH,1,7IXQFWLRQZKRVHHQWU\SRLQWLVDWRIIVHWK 3267FRGHLVUHTXLUHGWROHDYHWKH5$0DUHDZKHUHWKHH[SDQVLRQ520FRGHZDV FRSLHGWRDVZULWDEOHXQWLODIWHUWKH,1,7IXQFWLRQKDVUHWXUQHG7KLVDOORZVWKH,1,7 209 Revision 2.2 FRGHWRVWRUHVRPHVWDWLFGDWDLQWKH5$0DUHDDQGWRDGMXVWWKHUXQWLPHVL]HRIWKHFRGH VRWKDWLWFRQVXPHVOHVVVSDFHZKLOHWKHV\VWHPLVUXQQLQJ 7KH3&FRPSDWLEOHVSHFLILFVHWRIVWHSVIRUWKHV\VWHP3267FRGHZKHQKDQGOLQJHDFK H[SDQVLRQ520DUH 0DSDQGHQDEOHWKHH[SDQVLRQ520WRDQXQRFFXSLHGDUHDRIWKHPHPRU\DGGUHVV VSDFH )LQGWKHSURSHULPDJHLQWKH520DQGFRS\LWIURP520LQWRWKHFRPSDWLELOLW\DUHD RI5$0 W\SLFDOO\&KWR'))))KK XVLQJWKHQXPEHURIE\WHVVSHFLILHGE\ ,QLWLDOL]DWLRQ6L]H 'LVDEOHWKH([SDQVLRQ520%DVH$GGUHVVUHJLVWHU /HDYHWKH5$0DUHDZULWDEOHDQGFDOOWKH,1,7IXQFWLRQ 8VHWKHE\WHDWRIIVHWK ZKLFKPD\KDYHEHHQPRGLILHG WRGHWHUPLQHKRZPXFK PHPRU\LVXVHGDWUXQWLPH %HIRUHV\VWHPERRWWKH3267FRGHPXVWPDNHWKH5$0DUHDFRQWDLQLQJH[SDQVLRQ 520FRGHUHDGRQO\ 3267FRGHPXVWKDQGOH9*$GHYLFHVZLWKH[SDQVLRQ520VLQDVSHFLDOZD\7KH 9*$GHYLFH VH[SDQVLRQ%,26PXVWEHFRSLHGWR&K9*$GHYLFHVFDQEH LGHQWLILHGE\H[DPLQLQJWKH&ODVV&RGHILHOGLQWKHGHYLFH V&RQILJXUDWLRQ6SDFH 6.3.3.1.2. INIT Function Extensions 3&FRPSDWLEOHH[SDQVLRQ520VFRQWDLQDQ,1,7IXQFWLRQWKDWLVUHVSRQVLEOHIRU LQLWLDOL]LQJWKH,2GHYLFHDQGSUHSDULQJIRUUXQWLPHRSHUDWLRQ,1,7IXQFWLRQVLQ3&, H[SDQVLRQ520VDUHDOORZHGVRPHH[WHQGHGFDSDELOLWLHVEHFDXVHWKH5$0DUHDZKHUH WKHFRGHLVORFDWHGLVOHIWZULWDEOHZKLOHWKH,1,7IXQFWLRQH[HFXWHV 7KH,1,7IXQFWLRQFDQVWRUHVWDWLFSDUDPHWHUVLQVLGHLWV5$0DUHDGXULQJWKH,1,7 IXQFWLRQ7KLVGDWDFDQWKHQEHXVHGE\WKHUXQWLPH%,26RUGHYLFHGULYHUV7KLVDUHDRI 5$0ZLOOQRWEHZULWDEOHGXULQJUXQWLPH 7KH,1,7IXQFWLRQFDQDOVRDGMXVWWKHDPRXQWRI5$0WKDWLWFRQVXPHVGXULQJUXQWLPH 7KLVLVGRQHE\PRGLI\LQJWKHVL]HE\WHDWRIIVHWKLQWKHLPDJH7KLVKHOSVFRQVHUYH WKHOLPLWHGPHPRU\UHVRXUFHLQWKHH[SDQVLRQ520DUHD &K'))))K )RUH[DPSOHDGHYLFHH[SDQVLRQ520PD\UHTXLUH.%IRULWVLQLWLDOL]DWLRQDQG UXQWLPHFRGHEXWRQO\.%IRUWKHUXQWLPHFRGH7KHLPDJHLQWKH520ZLOOVKRZD VL]HRI.%VRWKDWWKH3267FRGHFRSLHVWKHZKROHWKLQJLQWR5$07KHQZKHQWKH ,1,7IXQFWLRQLVUXQQLQJLWFDQDGMXVWWKHVL]HE\WHGRZQWR.%:KHQWKH,1,7 IXQFWLRQUHWXUQVWKH3267FRGHVHHVWKDWWKHUXQWLPHVL]HLV.%DQGFDQFRS\WKHQH[W H[SDQVLRQ%,26WRWKHRSWLPXPORFDWLRQ 7KH,1,7IXQFWLRQLVUHVSRQVLEOHIRUJXDUDQWHHLQJWKDWWKHFKHFNVXPDFURVVWKHVL]HRI WKHLPDJHLVFRUUHFW,IWKH,1,7IXQFWLRQPRGLILHVWKH5$0DUHDLQDQ\ZD\DQHZ FKHFNVXPPXVWEHFDOFXODWHGDQGVWRUHGLQWKHLPDJH7KH,1,7IXQFWLRQVKRXOGQRW PRGLI\V\VWHPPHPRU\ H[FHSWIRUWKH,1,7IXQFWLRQ5$0DUHD LQDQ\ZD\XQOHVVLW XVHVDSSURSULDWHSURWRFRORU%,26VHUYLFHVWRDOORFDWHPHPRU\,WLVQRWXQFRPPRQIRU 3267VRIWZDUHWRXVHV\VWHPPHPRU\IRUFULWLFDOGDWDRUFRGHDQGLWVGHVWUXFWLRQRU PRGLILFDWLRQPD\SUHYHQWV\VWHPERRW 210 Revision 2.2 ,IWKH,1,7IXQFWLRQZDQWVWRFRPSOHWHO\UHPRYHLWVHOIIURPWKHH[SDQVLRQ520DUHDLW GRHVVRE\ZULWLQJD]HURWRWKH,QLWLDOL]DWLRQ6L]HILHOG WKHE\WHDWRIIVHWK ,QWKLV FDVHQRFKHFNVXPKDVWREHJHQHUDWHG VLQFHWKHUHLVQROHQJWKWRFKHFNVXPDFURVV 2QHQWU\WKH,1,7IXQFWLRQLVSDVVHGWKUHHSDUDPHWHUV WKHEXVQXPEHUGHYLFHQXPEHU DQGIXQFWLRQQXPEHURIWKHGHYLFHWKDWVXSSOLHGWKHH[SDQVLRQ5207KHVHSDUDPHWHUV FDQEHXVHGWRDFFHVVWKHGHYLFHEHLQJLQLWLDOL]HG7KH\DUHSDVVHGLQ[UHJLVWHUV>$+@ FRQWDLQVWKHEXVQXPEHUWKHXSSHUILYHELWVRI>$/@FRQWDLQWKHGHYLFHQXPEHUDQGWKH ORZHUWKUHHELWVRI>$/@FRQWDLQWKHIXQFWLRQQXPEHU 3ULRUWRFDOOLQJWKH,1,7IXQFWLRQWKH3267FRGHZLOODOORFDWHUHVRXUFHVWRWKHGHYLFH YLDWKH%DVH$GGUHVVDQG,QWHUUXSW/LQHUHJLVWHUV 6.3.3.1.3. Image Structure $3&FRPSDWLEOHLPDJHKDVWKUHHOHQJWKVDVVRFLDWHGZLWKLW DUXQWLPHOHQJWKDQ LQLWLDOL]DWLRQOHQJWKDQGDQLPDJHOHQJWK7KHLPDJHOHQJWKLVWKHWRWDOOHQJWKRIWKH LPDJHDQGLWPXVWEHJUHDWHUWKDQRUHTXDOWRWKHLQLWLDOL]DWLRQOHQJWK 7KHLQLWLDOL]DWLRQOHQJWKVSHFLILHVWKHDPRXQWRIWKHLPDJHWKDWFRQWDLQVERWKWKH LQLWLDOL]DWLRQDQGUXQWLPHFRGH7KLVLVWKHDPRXQWRIGDWDWKDW3267FRGHZLOOFRS\ LQWR5$0EHIRUHH[HFXWLQJWKHLQLWLDOL]DWLRQURXWLQH,QLWLDOL]DWLRQOHQJWKPXVWEH JUHDWHUWKDQRUHTXDOWRUXQWLPHOHQJWK7KHLQLWLDOL]DWLRQGDWDWKDWLVFRSLHGLQWR5$0 PXVWFKHFNVXPWR XVLQJWKHVWDQGDUGDOJRULWKP 7KHUXQWLPHOHQJWKVSHFLILHVWKHDPRXQWRIWKHLPDJHWKDWFRQWDLQVWKHUXQWLPHFRGH 7KLVLVWKHDPRXQWRIGDWDWKH3267FRGHZLOOOHDYHLQ5$0ZKLOHWKHV\VWHPLV RSHUDWLQJ$JDLQWKLVDPRXQWRIWKHLPDJHPXVWFKHFNVXPWR 7KH3&,'DWDVWUXFWXUHPXVWEHFRQWDLQHGZLWKLQWKHUXQWLPHSRUWLRQRIWKHLPDJH LI WKHUHLVDQ\ RWKHUZLVHLWPXVWEHFRQWDLQHGZLWKLQWKHLQLWLDOL]DWLRQSRUWLRQ)LJXUH VKRZVWKHW\SLFDOOD\RXWRIDQLPDJHLQWKHH[SDQVLRQ520 Header Runtime size PCI Data structure Initialization size Checksum byte Image size Checksum byte )LJXUH 7\SLFDO,PDJH/D\RXW 211 Revision 2.2 6.4. Vital Product Data 9LWDO3URGXFW'DWD 93' LVWKHLQIRUPDWLRQWKDWXQLTXHO\GHILQHVLWHPVVXFKDVWKH KDUGZDUHVRIWZDUHDQGPLFURFRGHHOHPHQWVRIDV\VWHP7KH93'SURYLGHVWKHV\VWHP ZLWKLQIRUPDWLRQRQYDULRXV)58V )LHOG5HSODFHDEOH8QLW LQFOXGLQJ3DUW1XPEHU 6HULDO1XPEHUDQGRWKHUGHWDLOHGLQIRUPDWLRQ93'DOVRSURYLGHVDPHFKDQLVPIRU VWRULQJLQIRUPDWLRQVXFKDVSHUIRUPDQFHDQGIDLOXUHGDWDRQWKHGHYLFHEHLQJPRQLWRUHG 7KHREMHFWLYHIURPDV\VWHPSRLQWRIYLHZLVWRFROOHFWWKLVLQIRUPDWLRQE\UHDGLQJLW IURPWKHKDUGZDUHVRIWZDUHDQGPLFURFRGHFRPSRQHQWV 6XSSRUWRI93'ZLWKLQ3&,DGDSWHUVLVRSWLRQDOGHSHQGLQJRQWKHPDQXIDFWXUHU7KH GHILQLWLRQRI3&,93'SUHVHQWVQRLPSDFWWRH[LVWLQJ3&,GHYLFHVDQGPLQLPDOLPSDFWWR IXWXUH3&,GHYLFHVZKLFKRSWLRQDOO\LQFOXGH93'7KRXJKVXSSRUWRI93'LVRSWLRQDO DGDSWHUPDQXIDFWXUHUVDUHHQFRXUDJHGWRSURYLGH93'GXHWRLWVLQKHUHQWEHQHILWVIRUWKH DGDSWHUV\VWHPPDQXIDFWXUHUVDQGIRU3OXJDQG3OD\ 7KHPHFKDQLVPIRUDFFHVVLQJ93'DQGWKHGHVFULSWLRQRI93'GDWDVWUXFWXUHVLV GRFXPHQWHGLQ$SSHQGL[, 6.5. Device Drivers 7KHUHDUHWZRFKDUDFWHULVWLFVRI3&,GHYLFHVWKDWPD\PDNH3&,GHYLFHGULYHUVGLIIHUHQW IURPVWDQGDUGRUH[LVWLQJGHYLFHGULYHUV7KHILUVWFKDUDFWHULVWLFLVWKDW3&,GHYLFHVDUH UHORFDWDEOH LHQRWKDUGZLUHG LQWKHDGGUHVVVSDFHV3&,GHYLFHGULYHUV DQGRWKHU FRQILJXUDWLRQVRIWZDUH VKRXOGXVHWKHPDSSLQJLQIRUPDWLRQVWRUHGLQWKHGHYLFH V &RQILJXUDWLRQ6SDFHUHJLVWHUVWRGHWHUPLQHZKHUHWKHGHYLFHZDVPDSSHG7KLVDOVR DSSOLHVWRGHWHUPLQLQJLQWHUUXSWOLQHXVDJH 7KHVHFRQGFKDUDFWHULVWLFLVWKDW3&,LQWHUUXSWVDUHVKDUHDEOH3&,GHYLFHGULYHUVDUH UHTXLUHGWRVXSSRUWVKDUHGLQWHUUXSWVVLQFHLWLVYHU\OLNHO\WKDWV\VWHPLPSOHPHQWDWLRQV ZLOOFRQQHFWPRUHWKDQRQHGHYLFHWRDVLQJOHLQWHUUXSWOLQH7KHH[DFWPHWKRGIRU LQWHUUXSWVKDULQJLVRSHUDWLQJV\VWHPVSHFLILFDQGLVQRWHODERUDWHGKHUH 6RPHV\VWHPVPD\QRWJXDUDQWHHWKDWGDWDLVGHOLYHUHGWRPDLQPHPRU\EHIRUHLQWHUUXSWV DUHGHOLYHUHGWRWKH&38,IQRWKDQGOHGSURSHUO\WKLVFDQOHDGWRGDWDFRQVLVWHQF\ SUREOHPV ORVVRIGDWD 7KLVVLWXDWLRQLVPRVWRIWHQDVVRFLDWHGZLWKWKHLPSOHPHQWDWLRQ RISRVWLQJEXIIHUVLQEULGJHVEHWZHHQWKH3&,EXVDQGRWKHUEXVHV 7KHUHDUHWKUHHZD\VWKDWGDWDDQGLQWHUUXSWFRQVLVWHQF\FDQEHJXDUDQWHHG 7KHV\VWHPKDUGZDUHFDQJXDUDQWHHWKDWSRVWLQJEXIIHUVDUHIOXVKHGEHIRUHLQWHUUXSWV DUHGHOLYHUHGWRWKHSURFHVVRU 7KHGHYLFHVLJQDOLQJWKHLQWHUUXSWFDQSHUIRUPDUHDGRIWKHMXVWZULWWHQGDWDEHIRUH VLJQDOLQJWKHLQWHUUXSW7KLVFDXVHVSRVWLQJEXIIHUVWREHIOXVKHG 7KHGHYLFHGULYHUFDQSHUIRUPDUHDGWRDQ\UHJLVWHULQWKHGHYLFHEHIRUHDFFHVVLQJ WKHGDWDZULWWHQE\WKHGHYLFH7KLVUHDGFDXVHVSRVWLQJEXIIHUVWREHIOXVKHG 'HYLFHGULYHUVDUHXOWLPDWHO\UHVSRQVLEOHIRUJXDUDQWHHLQJFRQVLVWHQF\RILQWHUUXSWVDQG GDWDE\DVVXULQJWKDWDWOHDVWRQHRIWKHWKUHHPHWKRGVGHVFULEHGDERYHLVSHUIRUPHGLQ WKHV\VWHP7KLVPHDQVDGHYLFHGULYHUPXVWGR0HWKRGXQOHVVLWLPSOLFLWO\NQRZV 0HWKRGLVGRQHE\LWVGHYLFHRULWLVLQIRUPHG E\VRPHPHDQVRXWVLGHWKHVFRSHRI WKLVVSHFLILFDWLRQ WKDW0HWKRGLVGRQHE\WKHV\VWHPKDUGZDUH 212 Revision 2.2 6.6. System Reset $IWHUV\VWHPUHVHWWKHSURFHVVRU V PXVWEHDEOHWRDFFHVVERRWFRGHDQGDQ\GHYLFHV QHFHVVDU\WRERRWWKHPDFKLQH'HSHQGLQJRQWKHV\VWHPDUFKLWHFWXUHEULGJHVPD\QHHG WRFRPHXSHQDEOHGWRSDVVWKHVHDFFHVVHVWKURXJKWRWKHUHPRWHEXV 6LPLODUO\GHYLFHVRQ3&,PD\QHHGWRFRPHXSHQDEOHGWRUHFRJQL]HIL[HGDGGUHVVHVWR VXSSRUWWKHERRWVHTXHQFHLQDV\VWHPDUFKLWHFWXUH6XFKGHYLFHVDUHUHTXLUHGWRVXSSRUW WKH&RPPDQGUHJLVWHUGLVDEOLQJIXQFWLRQGHVFULEHGLQ6HFWLRQ7KH\VKRXOGDOVR SURYLGHDPHFKDQLVP LQYRNHGWKURXJKWKH&RQILJXUDWLRQ6SDFH WRUHHQDEOHWKH UHFRJQLWLRQRIIL[HGDGGUHVVHV 6.7. Capabilities List &HUWDLQFDSDELOLWLHVDGGHGWR3&,DIWHUWKHSXEOLFDWLRQRIUHYLVLRQDUHVXSSRUWHGE\ DGGLQJDVHWRIUHJLVWHUVWRDOLQNHGOLVWFDOOHGWKH&DSDELOLWLHV/LVW7KLVRSWLRQDOGDWD VWUXFWXUHLVLQGLFDWHGLQWKH3&,6WDWXV5HJLVWHUE\VHWWLQJWKH&DSDELOLWLHV/LVWELW ELW WRLQGLFDWHWKDWWKH&DSDELOLWLHV3RLQWHULVORFDWHGDWRIIVHWK7KLVUHJLVWHUSRLQWVWR WKHILUVWLWHPLQWKHOLVWRIFDSDELOLWLHV (DFKFDSDELOLW\LQWKHOLVWFRQVLVWVRIDQELW,'ILHOGDVVLJQHGE\WKH3&,6,*DQELW SRLQWHULQFRQILJXUDWLRQVSDFHWRWKHQH[WFDSDELOLW\DQGVRPHQXPEHURIDGGLWLRQDO UHJLVWHUVLPPHGLDWHO\IROORZLQJWKHSRLQWHUWRLPSOHPHQWWKDWFDSDELOLW\(DFKFDSDELOLW\ PXVWEH':25'DOLJQHG7KHERWWRPWZRELWVRIDOOSRLQWHUV LQFOXGLQJWKHLQLWLDO SRLQWHUDWK DUHUHVHUYHGDQGPXVWEHLPSOHPHQWHGDVEDOWKRXJKVRIWZDUHPXVW PDVNWKHPWRDOORZIRUIXWXUHXVHVRIWKHVHELWV$SRLQWHUYDOXHRIKLVXVHGWR LQGLFDWHWKHODVWFDSDELOLW\LQWKHOLVW)LJXUHVKRZVKRZWKLVOLVWLVFRQVWUXFWHG )LJXUH ([DPSOH&DSDELOLWLHV/LVW (DFKGHILQHGFDSDELOLW\PXVWKDYHD6,*DVVLJQHG,'FRGH7KHVHFRGHVDUHDVVLJQHGDQG KDQGOHGPXFKOLNHWKH&ODVV&RGHV5HIHUWR$SSHQGL[+IRUDOLVWRIFXUUHQWO\GHILQHG &DSDELOLWLHV(DFK&DSDELOLW\PXVWGHILQHWKHGHWDLOHGUHJLVWHUPDSIRUWKDWFDSDELOLW\ 7KHVHUHJLVWHUVPXVWLPPHGLDWHO\IROORZWKHSRLQWHUWRWKHQH[WFDSDELOLW\ 213 Revision 2.2 6.8. Message Signaled Interrupts 0HVVDJH6LJQDOHG,QWHUUXSWV 06, LVDQRSWLRQDOIHDWXUHWKDWHQDEOHVDGHYLFHWRUHTXHVW VHUYLFHE\ZULWLQJDV\VWHPVSHFLILHGPHVVDJHWRDV\VWHPVSHFLILHGDGGUHVV 3&, ':25'PHPRU\ZULWHWUDQVDFWLRQ 7KHWUDQVDFWLRQDGGUHVVVSHFLILHVWKHPHVVDJH GHVWLQDWLRQDQGWKHWUDQVDFWLRQGDWDVSHFLILHVWKHPHVVDJH6\VWHPVRIWZDUHLQLWLDOL]HV WKHPHVVDJHGHVWLQDWLRQDQGPHVVDJHGXULQJGHYLFHFRQILJXUDWLRQDOORFDWLQJRQHRUPRUH QRQVKDUHGPHVVDJHVWRHDFK06,FDSDEOHIXQFWLRQ 6LQFHWKHWDUJHWRIWKHWUDQVDFWLRQFDQQRWGLVWLQJXLVKEHWZHHQDQ06,ZULWHWUDQVDFWLRQ DQGDQ\RWKHUZULWHWUDQVDFWLRQDOOWUDQVDFWLRQWHUPLQDWLRQFRQGLWLRQVDUHVXSSRUWHG 7KHUHIRUHD06,ZULWHWUDQVDFWLRQFDQEHWHUPLQDWHGZLWKD5HWU\0DVWHU$ERUW7DUJHW $ERUWRUQRUPDOFRPSOHWLRQ UHIHUWR6HFWLRQ ,WLVUHFRPPHQGHGWKDWGHYLFHVLPSOHPHQWLQWHUUXSWSLQVWRSURYLGHFRPSDWLELOLW\LQ V\VWHPVWKDWGRQRWVXSSRUW06, GHYLFHVGHIDXOWWRLQWHUUXSWSLQV +RZHYHULWLV H[SHFWHGWKDWWKHQHHGIRULQWHUUXSWSLQVZLOOGLPLQLVKRYHUWLPH'HYLFHVWKDWGRQRW VXSSRUWLQWHUUXSWSLQVGXHWRSLQFRQVWUDLQWV UHO\RQSROOLQJIRUGHYLFHVHUYLFH PD\ LPSOHPHQWPHVVDJHVWRLQFUHDVHSHUIRUPDQFHZLWKRXWDGGLQJDGGLWLRQDOSLQV7KHUHIRUH V\VWHPFRQILJXUDWLRQVRIWZDUHPXVWQRWDVVXPHWKDWDPHVVDJHFDSDEOHGHYLFHKDVDQ LQWHUUXSWSLQ ,QWHUUXSWODWHQF\ WKHWLPHIURPLQWHUUXSWVLJQDOLQJWRLQWHUUXSWVHUYLFLQJ LVV\VWHP GHSHQGHQW&RQVLVWHQWZLWKFXUUHQWLQWHUUXSWDUFKLWHFWXUHVPHVVDJHVLJQDOHGLQWHUUXSWV GRQRWSURYLGHLQWHUUXSWODWHQF\WLPHJXDUDQWHHV 6.8.1. Message Capability Structure 7KHFDSDELOLWLHVPHFKDQLVP UHIHUWR6HFWLRQ LVXVHGWRLGHQWLI\DQGFRQILJXUHD 06,FDSDEOHGHYLFH7KHPHVVDJHFDSDELOLW\VWUXFWXUHLVLOOXVWUDWHGLQ)LJXUH(DFK GHYLFHIXQFWLRQWKDWVXSSRUWV06, LQDPXOWLIXQFWLRQGHYLFH PXVWLPSOHPHQWLWVRZQ 06,FDSDELOLW\VWUXFWXUH0RUHWKHQRQH06,FDSDELOLW\VWUXFWXUHSHUIXQFWLRQLV SURKLELWHG &DSDELOLW\Ã6WUXFWXUHÃIRUÃELWÃ0HVVDJHÃ$GGUHVV ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ ÃÃÃÃÃÃÃÃÃÃÃÃÃ0HVVDJHÃ&RQWUROÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ1H[WÃ3RLQWHUÃÃÃÃÃÃ&DSDELOLW\Ã,' &DSDELOLW\Ã3RLQWHU 0HVVDJHÃ$GGUHVV &DSDELOLW\Ã3RLQWHUÃÃK 0HVVDJHÃ'DWD &DSDELOLW\Ã3RLQWHUÃÃK &DSDELOLW\Ã6WUXFWXUHÃIRUÃELWÃ0HVVDJHÃ$GGUHVV ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ ÃÃÃÃÃÃÃÃÃÃÃ0HVVDJHÃ&RQWUROÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ1H[WÃ3RLQWHUÃÃÃÃÃÃ&DSDELOLW\Ã,' &DSDELOLW\Ã3RLQWHU 0HVVDJHÃ$GGUHVV &DSDELOLW\Ã3RLQWHUÃÃK 0HVVDJHÃ8SSHUÃ$GGUHVV &DSDELOLW\Ã3RLQWHUÃÃK 0HVVDJHÃ'DWD &DSDELOLW\Ã3RLQWHUÃÃ&K )LJXUH 0HVVDJH6LJQDOHG,QWHUUXSW&DSDELOLW\6WUXFWXUH 214 Revision 2.2 7RUHTXHVWVHUYLFHDQ06,IXQFWLRQZULWHVWKHFRQWHQWVRIWKH0HVVDJH'DWDUHJLVWHUWR WKHDGGUHVVVSHFLILHGE\WKHFRQWHQWVRIWKH0HVVDJH$GGUHVVUHJLVWHU DQGRSWLRQDOO\ WKH0HVVDJH8SSHU$GGUHVVUHJLVWHUIRUDELWPHVVDJHDGGUHVV $UHDGRIWKHDGGUHVV VSHFLILHGE\WKHFRQWHQWVRIWKH0HVVDJH$GGUHVVUHJLVWHUSURGXFHVXQGHILQHGUHVXOWV 7KHFDSDELOLW\VWUXFWXUHIRUDELWPHVVDJHDGGUHVV LOOXVWUDWHGLQ)LJXUH LV LPSOHPHQWHGLIWKHIXQFWLRQVXSSRUWVDELWPHVVDJHDGGUHVV7KHFDSDELOLW\VWUXFWXUH IRUDELWPHVVDJHDGGUHVV LOOXVWUDWHGLQ)LJXUH LVLPSOHPHQWHGLIWKHIXQFWLRQ VXSSRUWVDELWPHVVDJHDGGUHVV,IDGHYLFHVXSSRUWV06,DQGWKHGHYLFHVXSSRUWV ELWDGGUHVVLQJ '$& ZKHQDFWLQJDVDPDVWHUWKHGHYLFHLVUHTXLUHGWRLPSOHPHQWWKH ELWPHVVDJHDGGUHVVVWUXFWXUH 7KHPHVVDJHFRQWUROUHJLVWHULQGLFDWHVWKHIXQFWLRQ¶VFDSDELOLWLHVDQGSURYLGHVV\VWHP VRIWZDUHFRQWURORYHU06, (DFKILHOGLVIXUWKHUGHVFULEHGLQWKHIROORZLQJVXEVHFWLRQV5HVHUYHGUHJLVWHUVDQGELWV DOZD\VUHWXUQZKHQUHDGDQGZULWHRSHUDWLRQVKDYHQRHIIHFW5HDGRQO\UHJLVWHUV UHWXUQYDOLGGDWDZKHQUHDGDQGZULWHRSHUDWLRQVKDYHQRHIIHFW 6.8.1.1. Capability ID 7::0 CAP_ID The value of 05h in this field identifies the function as message signaled interrupt capable. This field is read only. 6.8.1.2. Next Pointer 7::0 NXT_PTR Pointer to the next item in the capabilities list. Must be NULL for the final item in the list. This field is read only. 6.8.1.3. Message Control 7KLVUHJLVWHUSURYLGHVV\VWHPVRIWZDUHFRQWURORYHU06,$IWHUUHVHW06,LVGLVDEOHG ELWLVFOHDUHG DQGWKHIXQFWLRQUHTXHVWVVHUYLFLQJYLDLWVINTx#SLQ LIVXSSRUWHG 6\VWHPVRIWZDUHFDQHQDEOH06,E\VHWWLQJELWRIWKLVUHJLVWHU6\VWHPVRIWZDUHLV SHUPLWWHGWRPRGLI\WKH0HVVDJH&RQWUROUHJLVWHU¶VUHDGZULWHELWVDQGILHOGV$GHYLFH GULYHULVQRWSHUPLWWHGWRPRGLI\WKH0HVVDJH&RQWUROUHJLVWHU¶VUHDGZULWHELWVDQG ILHOGV Bits Field Description Always returns 0 on a read and a write operation has 15::08 Reserved no effect. If 1, the function is capable of generating a 64-bit 7 64 bit address message address. capable If 0, the function is not capable of generating a 64-bit message address. This bit is read only. 215 Revision 2.2 Bits Field Description 6::4 Multiple Message System software writes to this field to indicate the Enable number of allocated messages (equal to or less than the number of requested messages). The number of allocated messages is aligned to a power of two. If a function requests four messages (indicated by a Multiple Message Capable encoding of “010”), system software can allocate either four, two, or one message by writing a “010”, “001, or “000” to this field, respectively. When MSI is enabled, a device will be allocated at least 1 message. The encoding is defined as: Encoding # of messages allocated 000 1 001 2 010 4 011 8 100 16 101 32 110 Reserved 111 Reserved This field’s state after reset is “000”. This field is read/write. 3::1 Multiple Message System software reads this field to determine the Capable number of requested messages. The number of requested messages must be aligned to a power of two (if a function requires three messages, it requests four by initializing this field to “010”). The encoding is defined as: Encoding # of messages requested 000 1 001 2 010 4 011 8 100 16 101 32 110 Reserved 111 Reserved This field is read/only. 216 Revision 2.2 Bits Field Description If 1, the function is permitted to use MSI to request 0 MSI Enable service and is prohibited from using its INTx# pin (if implemented). System configuration software sets this bit to enable MSI. A device driver is prohibited from writing this bit to mask a function’s service request. If 0, the function is prohibited from using MSI to request service. This bit’s state after reset is 0 (MSI is disabled). This bit is read/write. 6.8.1.4. Message Address Bits Field Description 31::02 Message System-specified message address. Address If the Message Enable bit (bit 0 of the Message Control register) is set, the contents of this register specify the DWORD aligned address (AD[31::02]) for the MSI memory write transaction. AD[1::0] are driven to zero during the address phase. This field is read/write. 01::00 Reserved Always returns 0 on read. Write operations have no effect. 6.8.1.5. Message Upper Address (Optional) Bits Field Description System-specified message upper address. 31::00 Message Upper Address This register is optional and is implemented only if the device supports a 64-bit message address (bit 7 in Message Control register set)49. If the Message Enable bit (bit 0 of the Message Control register) is set, the contents of this register (if non-zero) specify the upper 32-bits of a 64-bit message address (AD[63::32]). If the contents of this register are zero, the device uses the 32 bit address specified by the message address register. This field is read/write. 49 This register is required when the device supports 64-bit addressing (DAC) when acting as a master. 217 Revision 2.2 6.8.1.6. Message Data Bits Field Description 15::00 Message Data System-specified message. Each MSI function is allocated up to 32 unique messages. System architecture specifies the number of unique messages supported by the system. If the Message Enable bit (bit 0 of the Message Control register) is set, the message data is driven onto the lower word (AD[15::00]) of the memory write transaction’s data phase. AD[31::16] are driven to zero during the memory write transaction’s data phase. C/BE[3::0]# are asserted during the data phase of the memory write transaction. The Multiple Message Enable field (bits 6-4 of the Message Control register) defines the number of low order message data bits the function is permitted to modify to generate its system software allocated messages. For example, a Multiple Message Enable encoding of “010” indicates the function has been allocated four messages and is permitted to modify message data bits 1 and 0 (a function modifies the lower message data bits to generate the allocated number of messages). If the Multiple Message Enable field is “000”, the function is not permitted to modify the message data. This field is read/write. 6.8.2. MSI Operation $WFRQILJXUDWLRQWLPHV\VWHPVRIWZDUHWUDYHUVHVWKHIXQFWLRQ¶VFDSDELOLW\OLVW,ID FDSDELOLW\,'RIKLVIRXQGWKHIXQFWLRQLPSOHPHQWV06,6\VWHPVRIWZDUHUHDGVWKH 06,FDSDELOLW\VWUXFWXUH¶V0HVVDJH&RQWUROUHJLVWHUWRGHWHUPLQHWKHIXQFWLRQ¶V FDSDELOLWLHV 6\VWHPVRIWZDUHUHDGVWKH0XOWLSOH0HVVDJH&DSDEOHILHOG ELWVRIWKH0HVVDJH &RQWUROUHJLVWHU WRGHWHUPLQHWKHQXPEHURIUHTXHVWHGPHVVDJHV6\VWHPVRIWZDUH ZULWHVWRWKH0XOWLSOH0HVVDJH(QDEOHILHOG ELWVRIWKH0HVVDJH&RQWUROUHJLVWHU WR DOORFDWHHLWKHUDOORUDVXEVHWRIWKHUHTXHVWHGPHVVDJHV)RUH[DPSOHDIXQFWLRQFDQ UHTXHVWIRXUPHVVDJHVDQGEHDOORFDWHGHLWKHUIRXUWZRRURQHPHVVDJH7KHQXPEHURI PHVVDJHVUHTXHVWHGDQGDOORFDWHGDUHDOLJQHGWRDSRZHURIWZR DIXQFWLRQWKDWUHTXLUHV WKUHHPHVVDJHVPXVWUHTXHVWIRXU ,IWKHELW$GGUHVV&DSDEOHELW ELWRIWKH0HVVDJH&RQWUROUHJLVWHU LVVHWV\VWHP VRIWZDUHLQLWLDOL]HVWKH06,FDSDELOLW\VWUXFWXUH¶V0HVVDJH$GGUHVVUHJLVWHU VSHFLI\LQJ WKHORZHUELWVRIWKHPHVVDJHDGGUHVV DQGWKH0HVVDJH8SSHU$GGUHVVUHJLVWHU VSHFLI\LQJWKHXSSHUELWVRIWKHPHVVDJHDGGUHVV ZLWKDV\VWHPVSHFLILHGPHVVDJH 218 Revision 2.2 GHVWLQDWLRQDGGUHVV6\VWHPVRIWZDUHPD\SURJUDPWKH0HVVDJH8SSHU$GGUHVVUHJLVWHU WR]HURVRWKDWWKHIXQFWLRQJHQHUDWHVDELWDGGUHVVIRUWKH06,ZULWHWUDQVDFWLRQ,I WKLVELWLVFOHDUV\VWHPVRIWZDUHLQLWLDOL]HVWKH06,FDSDELOLW\VWUXFWXUH¶V0HVVDJH $GGUHVVUHJLVWHU VSHFLI\LQJDELWPHVVDJHDGGUHVV ZLWKDV\VWHPVSHFLILHGPHVVDJH GHVWLQDWLRQDGGUHVV 6\VWHPVRIWZDUHLQLWLDOL]HVWKH06,FDSDELOLW\VWUXFWXUH¶V0HVVDJH'DWDUHJLVWHUZLWKD V\VWHPVSHFLILHGPHVVDJH&DUHPXVWEHWDNHQWRLQLWLDOL]HRQO\WKH0HVVDJH'DWD UHJLVWHU LHDE\WHYDOXH DQGQRWPRGLI\WKHXSSHUWZRE\WHVRIWKDW':25' ORFDWLRQ 7RPDLQWDLQEDFNZDUGFRPSDWLELOLW\WKH06,(QDEOHELW ELWRIWKH0HVVDJH&RQWURO UHJLVWHU LVFOHDUHGDIWHUUHVHW 06,LVGLVDEOHG 6\VWHPFRQILJXUDWLRQVRIWZDUHVHWVWKLV ELWWRHQDEOH06,$GHYLFHGULYHULVSURKLELWHGIURPZULWLQJWKLVELWWRPDVND IXQFWLRQ¶VVHUYLFHUHTXHVW2QFHHQDEOHGDIXQFWLRQLVSURKLELWHGIURPXVLQJLWVINTx# SLQ LILPSOHPHQWHG WRUHTXHVWVHUYLFH 06,DQGINTx#DUHPXWXDOO\H[FOXVLYH 2QFH06,LVHQDEOHG ELWRIWKH0HVVDJH&RQWURO5HJLVWHULVVHW WKHIXQFWLRQPD\ VHQGPHVVDJHV7RVHQGDPHVVDJHDIXQFWLRQGRHVD':25'PHPRU\ZULWHWRWKH DGGUHVVVSHFLILHGE\WKHFRQWHQWVRIWKH0HVVDJH$GGUHVVUHJLVWHU DQGRSWLRQDOO\WKH 0HVVDJH8SSHU$GGUHVVUHJLVWHUIRUDELWPHVVDJHDGGUHVV 7KH':25'WKDWLV ZULWWHQLVPDGHXSRIWKHYDOXHLQWKH0HVVDJH'DWDUHJLVWHULQWKHORZHUWZRE\WHVDQG ]HURHVLQWKHXSSHUWZRE\WHV,IWKH0XOWLSOH0HVVDJH(QDEOHILHOG ELWVRIWKH 0HVVDJH&RQWUROUHJLVWHU LVQRQ]HURWKHGHYLFHLVSHUPLWWHGWRPRGLI\WKHORZRUGHU ELWVRIWKHPHVVDJHGDWDWRJHQHUDWHPXOWLSOHPHVVDJHV)RUH[DPSOHD0XOWLSOH 0HVVDJH(QDEOHHQFRGLQJRI³´LQGLFDWHVWKHIXQFWLRQLVSHUPLWWHGWRPRGLI\PHVVDJH GDWDELWVDQGWRJHQHUDWHXSWRIRXUXQLTXHPHVVDJHV,IWKH0XOWLSOH0HVVDJH(QDEOH ILHOGLV³´WKHIXQFWLRQLVQRWSHUPLWWHGWRPRGLI\WKHPHVVDJHGDWD+RZDIXQFWLRQ XVHVPXOWLSOHPHVVDJHV ZKHQDOORFDWHG LVGHYLFHGHSHQGHQW$IXQFWLRQPXVWKDQGOH EHLQJDOORFDWHGOHVVPHVVDJHVWKDQUHTXHVWHG ,IDGHYLFHVLJQDOVWKHVDPHPHVVDJHPDQ\WLPHVRQO\RQHPHVVDJHLVJXDUDQWHHGWREH VHUYLFHG,IDOOPHVVDJHVPXVWEHVHUYLFHGDGHYLFHGULYHUKDQGVKDNHLVUHTXLUHG,Q RWKHUZRUGVRQFHDIXQFWLRQVLJQDOV0HVVDJH$LWFDQQRWVLJQDO0HVVDJH$DJDLQXQWLOLW LVH[SOLFLWO\HQDEOHGWRGRVRE\LWVGHYLFHGULYHU SURYLGHGDOOPHVVDJHVPXVWEH VHUYLFHG ,IVRPHPHVVDJHVFDQEHORVWDGHYLFHGULYHUKDQGVKDNHLVQRWUHTXLUHG)RU IXQFWLRQVWKDWVXSSRUWPXOWLSOHPHVVDJHVDIXQFWLRQFDQVLJQDOPXOWLSOHXQLTXHPHVVDJHV DQGLVJXDUDQWHHGWKDWHDFKXQLTXHPHVVDJHZLOOEHVHUYLFHG)RUH[DPSOHDGHYLFHFDQ VLJQDO0HVVDJH$IROORZHGE\0HVVDJH%ZLWKRXWDQ\GHYLFHGULYHUKDQGVKDNH ERWK 0HVVDJH$DQG0HVVDJH%ZLOOEHVHUYLFHG $Q06,LVE\GHILQLWLRQDQRQVKDUHGLQWHUUXSWWKDWHQIRUFHVGDWDFRQVLVWHQF\ HQVXUHV WKHLQWHUUXSWVHUYLFHURXWLQHDFFHVVHVWKHPRVWUHFHQWGDWD 7KHV\VWHPJXDUDQWHHVWKDW DQ\GDWDZULWWHQE\WKHGHYLFHSULRUWRVHQGLQJWKH06,KDVUHDFKHGLWVILQDOGHVWLQDWLRQ EHIRUHWKHLQWHUUXSWVHUYLFHURXWLQHDFFHVVHVWKDWGDWD7KHUHIRUHDGHYLFHGULYHULVQRW UHTXLUHGWRUHDGLWVGHYLFHEHIRUHVHUYLFLQJLWV06, 219 Revision 2.2 6.8.2.1. MSI Transaction Termination 7KHWDUJHWRIDQ06,FDQQRWGLVWLQJXLVKEHWZHHQDQ06,ZULWHWUDQVDFWLRQDQGDQ\RWKHU PHPRU\ZULWHWUDQVDFWLRQ7KHWHUPLQDWLRQUHTXLUHPHQWVIRUDQ06,DUHWKHVDPHDVIRU DQ\RWKHUPHPRU\ZULWHWUDQVDFWLRQH[FHSWDVQRWHGEHORZ ,IWKH06,ZULWHWUDQVDFWLRQLVWHUPLQDWHGZLWKD0DVWHU$ERUWRUD7DUJHW$ERUWWKH PDVWHUWKDWRULJLQDWHGWKH06,ZULWHWUDQVDFWLRQLVUHTXLUHGWRUHSRUWWKHHUURUE\ DVVHUWLQJSERR# LIELWLQWKH&RPPDQGUHJLVWHULVVHW DQGWRVHWWKHDSSURSULDWHELWV LQWKH6WDWXVUHJLVWHU UHIHUWR6HFWLRQ 7KH06,ZULWHWUDQVDFWLRQLVLJQRUHGE\ WKHWDUJHWLILWLVWHUPLQDWHGZLWKD0DVWHU$ERUWRU7DUJHW$ERUW If the MSI write transaction results in a data parity error, the master that originated the MSI write transaction is required to assert SERR# (if bit 8 in the Command register is set) and to set the appropriated bits in the Status register (refer to Section 3.7.4.). 6.8.2.2. MSI Transaction Reception and Ordering Requirements $VZLWKDOOPHPRU\ZULWHWUDQVDFWLRQVWKHGHYLFHWKDWLQFOXGHVWKHWDUJHWRIWKHLQWHUUXSW PHVVDJH WKHLQWHUUXSWUHFHLYHU LVUHTXLUHGWRFRPSOHWHDOOLQWHUUXSWPHVVDJHWUDQVDFWLRQV DVDWDUJHWZLWKRXWUHTXLULQJRWKHUWUDQVDFWLRQVWRFRPSOHWHILUVWDVDPDVWHU 5HIHUWR 6HFWLRQ,QJHQHUDOWKLVPHDQVWKDWWKHPHVVDJHUHFHLYHUPXVWFRPSOHWHWKH LQWHUUXSWPHVVDJHWUDQVDFWLRQLQGHSHQGHQWRIZKHQWKH&38VHUYLFHVWKHLQWHUUXSW)RU H[DPSOHHDFKWLPHWKHLQWHUUXSWUHFHLYHUUHFHLYHVDQLQWHUUXSWPHVVDJHLWFRXOGVHWDELW LQDQLQWHUQDOUHJLVWHULQGLFDWLQJWKDWWKLVPHVVDJHKDGEHHQUHFHLYHGDQGWKHQFRPSOHWH WKHWUDQVDFWLRQRQWKHEXV7KHDSSURSULDWHLQWHUUXSWVHUYLFHURXWLQHZRXOGODWHUEH GLVSDWFKHGEHFDXVHWKLVELWZDVVHW7KHPHVVDJHUHFHLYHUZRXOGQRWEHDOORZHGWRGHOD\ WKHFRPSOHWLRQRIWKHLQWHUUXSWPHVVDJHRQWKHEXVSHQGLQJDFNQRZOHGJHPHQWIURPWKH SURFHVVRUWKDWWKHLQWHUUXSWZDVEHLQJVHUYLFHG6XFKGHSHQGHQFLHVFDQOHDGWRGHDGORFN ZKHQPXOWLSOHGHYLFHVJHQHUDWHLQWHUUXSWPHVVDJHVVLPXOWDQHRXVO\ $OWKRXJKLQWHUUXSWPHVVDJHVUHPDLQVWULFWO\RUGHUHGWKURXJKRXWWKH3&,EXVKLHUDUFK\ WKHRUGHURIUHFHLSWRIWKHLQWHUUXSWPHVVDJHVGRHVQRWJXDUDQWHHDQ\RUGHULQZKLFKWKH LQWHUUXSWVZLOOEHVHUYLFHG6LQFHWKHPHVVDJHUHFHLYHUPXVWFRPSOHWHDOOLQWHUUXSW PHVVDJHWUDQVDFWLRQVZLWKRXWUHJDUGWRZKHQWKHLQWHUUXSWZDVDFWXDOO\VHUYLFHGWKH PHVVDJHUHFHLYHUZLOOJHQHUDOO\QRWPDLQWDLQDQ\LQIRUPDWLRQDERXWWKHRUGHULQZKLFK WKHLQWHUUXSWVZHUHUHFHLYHG7KLVLVWUXHERWKRILQWHUUXSWPHVVDJHVUHFHLYHGIURP GLIIHUHQWGHYLFHVDQGPXOWLSOHPHVVDJHVUHFHLYHGIURPWKHVDPHGHYLFH,IDGHYLFH UHTXLUHVRQHLQWHUUXSWPHVVDJHWREHVHUYLFHGEHIRUHDQRWKHUWKHQWKHGHYLFHPXVWQRW VHQGWKHVHFRQGLQWHUUXSWPHVVDJHXQWLOWKHILUVWRQHKDVEHHQVHUYLFHG 220 Revision 2.2 Chapter 7 66 MHz PCI Specification 7.1. Introduction 7KH0+]3&,EXVLVDFRPSDWLEOHVXSHUVHWRI3&,GHILQHGWRRSHUDWHXSWRD PD[LPXPFORFNVSHHGRI0+]7KH0+]3&,EXVLVLQWHQGHGWREHXVHGE\ORZ ODWHQF\KLJKEDQGZLGWKEULGJHVDQGSHULSKHUDOV6\VWHPVPD\DXJPHQWWKH0+] 3&,EXVZLWKDVHSDUDWH0+]3&,EXVWRKDQGOHORZHUVSHHGSHULSKHUDOV 'LIIHUHQFHVEHWZHHQ0+]3&,DQG0+]3&,DUHPLQLPDO%RWKVKDUHWKHVDPH SURWRFROVLJQDOGHILQLWLRQVDQGFRQQHFWRUOD\RXW7RLGHQWLI\0+]3&,GHYLFHVRQH VWDWLFVLJQDOLVDGGHGE\UHGHILQLQJDQH[LVWLQJJURXQGSLQDQGRQHELWLVDGGHGWRWKH &RQILJXUDWLRQ6WDWXVUHJLVWHU%XVGULYHUVIRUWKH0+]3&,EXVPHHWWKHVDPH'& FKDUDFWHULVWLFVDQG$&GULYHSRLQWOLPLWVDV0+]3&,EXVGULYHUV KRZHYHU0+] 3&,UHTXLUHVIDVWHUWLPLQJSDUDPHWHUVDQGUHGHILQHGPHDVXUHPHQWFRQGLWLRQV$VD UHVXOW0+]3&,EXVHVPD\VXSSRUWVPDOOHUORDGLQJDQGWUDFHOHQJWKV $0+]3&,GHYLFHRSHUDWHVDVD0+]3&,GHYLFHZKHQLWLVFRQQHFWHGWRD 0+]3&,EXV6LPLODUO\LIDQ\0+]3&,GHYLFHVDUHFRQQHFWHGWRD0+]3&, EXVWKH0+]3&,EXVZLOORSHUDWHDVD0+]3&,EXV 7KHSURJUDPPLQJPRGHOVIRU0+]3&,DQG0+]3&,DUHWKHVDPHLQFOXGLQJ FRQILJXUDWLRQKHDGHUVDQGFODVVW\SHV$JHQWVDQGEULGJHVLQFOXGHD0+]3&,VWDWXV ELW 7.2. 6FRSH 7KLVFKDSWHUGHILQHVDVSHFWVRI0+]3&,WKDWGLIIHUIURPWKRVHGHILQHGHOVHZKHUHLQ WKLVGRFXPHQWLQFOXGLQJLQIRUPDWLRQRQGHYLFHDQGEULGJHVXSSRUW7KLVFKDSWHUZLOOQRW UHSHDWLQIRUPDWLRQGHILQHGHOVHZKHUH 221 Revision 2.2 7.3. Device Implementation Considerations 7.3.1. Configuration Space ,GHQWLILFDWLRQRID0+]3&,FRPSOLDQWGHYLFHLVDFFRPSOLVKHGWKURXJKWKHXVHRIWKH UHDGRQO\0+=B&$3$%/(IODJORFDWHGLQELWRIWKH3&,6WDWXVUHJLVWHU VHH )LJXUH ,IVHWWKLVELWVLJQLILHVWKDWWKHGHYLFHLVFDSDEOHRIRSHUDWLQJLQ0+] PRGH 7.4. Agent Architecture $0+]3&,DJHQWLVGHILQHGDVD3&,DJHQWFDSDEOHRIVXSSRUWLQJ0+]3&, $OO0+]3&,DJHQWVPXVWVXSSRUWDUHDGRQO\0+=B&$3$%/(IODJORFDWHGLQ ELWRIWKH3&,6WDWXVUHJLVWHUIRUWKDWDJHQW,IVHWWKH0+=B&$3$%/(ELWVLJQLILHV WKDWWKHDJHQWFDQRSHUDWHLQ0+]3&,PRGH 7.5. Protocol 7.5.1. 66MHZ_ENABLE (M66EN) Pin Definition 3LQ %RQWKH3&,FRQQHFWRULVGHVLJQDWHGM66EN([SDQVLRQERDUGVDQGEXV VHJPHQWVQRWFDSDEOHRIRSHUDWLRQLQ0+]PRGHPXVWFRQQHFWWKLVSLQWRJURXQG$ M66EN 0+]3&,SODQDUVHJPHQWPXVWSURYLGHDVLQJOHSXOOXSUHVLVWRUWR9FFRQWKH SLQ5HIHUWR6HFWLRQIRUWKHDSSURSULDWHSXOOXSYDOXHM66ENLVEXVHGWRDOO 0+]3&,FRQQHFWRUVDQGSODQDURQO\0+]3&,FRPSRQHQWVWKDWLQFOXGHWKHM66EN SLQ7KH0+]3&,FORFNJHQHUDWLRQFLUFXLWU\PXVWFRQQHFWWRM66ENWRJHQHUDWHWKH DSSURSULDWHFORFNIRUWKHVHJPHQW WR0+]LIM66ENLVDVVHUWHGWR0+]LI M66ENLVGHDVVHUWHG ,ID0+]3&,DJHQWUHTXLUHVFORFNVSHHGLQIRUPDWLRQ IRUH[DPSOHIRUD3//E\SDVV LWLVSHUPLWWHGWRXVHM66ENDVDQLQSXW,ID0+]3&,DJHQWFDQUXQZLWKRXWDQ\ NQRZOHGJHRIWKHVSHHGLWLVSHUPLWWHGWROHDYHM66ENGLVFRQQHFWHG 50 Configuration software identifies agent capabilities by checking the 66MHZ_CAPABLE bit in the Status register. This includes both the primary and secondary Status registers in a PCI-to-PCI bridge. This allows configuration software to detect a 33 MHz PCI agent on a 66 MHz PCI bus or a 66 MHz PCI agent on a 33 MHz PCI bus and issue a warning to the user describing the situation. 222 Revision 2.2 7DEOH %XVDQG$JHQW&RPELQDWLRQV Bus Agent 66MHZ_CAPABLE51 66MHZ_CAPABLE Description 0 0 33 MHz PCI agent located on a 33 MHz PCI bus 0 1 66 MHz PCI agent located on a 33 MHz PCI bus52 1 0 33 MHz PCI agent located on a 66 MHz PCI bus52 1 1 66 MHz PCI agent located on a 66 MHz PCI bus 7.5.2. Latency 7KH0+]3&,EXVLVLQWHQGHGIRUORZODWHQF\GHYLFHV,WLVUHTXLUHGWKDWWKHWDUJHW LQLWLDOODWHQF\QRWH[FHHGFORFNV 7.6. Electrical Specification 7.6.1. Overview 7KLVFKDSWHUGHILQHVWKHHOHFWULFDOFKDUDFWHULVWLFVDQGFRQVWUDLQWVRI0+]3&, FRPSRQHQWVV\VWHPVDQGH[SDQVLRQERDUGVLQFOXGLQJFRQQHFWRUSLQDVVLJQPHQWV $OOHOHFWULFDOVSHFLILFDWLRQVIURP&KDSWHURIWKLVGRFXPHQWDSSO\WR0+]3&, H[FHSWZKHUHH[SOLFLWO\VXSHUVHGHG6SHFLILFDOO\ • 7KH0+]3&,EXVXVHVWKH9VLJQDOLQJHQYLURQPHQW • 7LPLQJSDUDPHWHUVKDYHEHHQVFDOHGWR0+] • $&WHVWORDGLQJFRQGLWLRQVKDYHEHHQFKDQJHG 51 The bus 66MHZ_CAPABLE status bit is located in a bridge’s Status registers. 52 This condition may cause the configuration software to generate a warning to the user stating that the card is installed in an inappropriate socket and should be relocated. 223 Revision 2.2 7.6.2. Transition Roadmap to 66 MHz PCI 7KH0+]3&,EXVXWLOL]HVWKH3&,EXVSURWRFRO 0+]3&,VLPSO\KDVDKLJKHU PD[LPXPEXVFORFNIUHTXHQF\%RWK0+]DQG0+]GHYLFHVFDQFRH[LVWRQWKH VDPHEXVVHJPHQW,QWKLVFDVHWKHEXVVHJPHQWZLOORSHUDWHDVD0+]VHJPHQW 7RHQVXUHFRPSDWLELOLW\0+]3&,GHYLFHVKDYHWKHVDPH'&VSHFLILFDWLRQVDQG$& GULYHSRLQWOLPLWVDV0+]3&,GHYLFHV+RZHYHU0+]3&,UHTXLUHVPRGLILHG WLPLQJSDUDPHWHUVDVGHVFULEHGLQWKHDQDO\VLVRIWKHWLPLQJEXGJHWVKRZQLQ)LJXUH Tcyc ≥ Tval + Tprop + Tskew + Tsu Tcyc = 30 ns 33 MHZ Tval =11 ns Tprop = 10 ns Tskew = 2ns Tsu=7ns Tcyc = 15 ns 66 MHZ Tval Tprop Tskew Tsu 6 ns 5 ns 1 ns 3 ns )LJXUH 0+]3&,YV0+]3&,7LPLQJ 6LQFH$&GULYHUHTXLUHPHQWVDUHWKHVDPHIRU0+]3&,DQG0+]3&,LWLV H[SHFWHGWKDW0+]3&,GHYLFHVZLOOIXQFWLRQRQ0+]3&,EXVHV7KHUHIRUH 0+]3&,GHYLFHVPXVWPHHWERWK0+]3&,DQG0+]3&,UHTXLUHPHQWV 7.6.3. Signaling Environment $0+]3&,SODQDUVHJPHQWPXVWXVHWKH3&,9NH\HGFRQQHFWRU7KHUHIRUH 0+]3&,SODQDUVHJPHQWVDFFHSWHLWKHU9RU8QLYHUVDOH[SDQVLRQERDUGV 9 H[SDQVLRQERDUGVDUHQRWVXSSRUWHG :KLOH0+]3&,EXVGULYHUVDUHGHILQHGE\WKHLU9,FXUYHV0+]3&,RXWSXW EXIIHUVDUHVSHFLILHGLQWHUPVRIWKHLU$&DQG'&GULYHSRLQWVWLPLQJSDUDPHWHUVDQG VOHZUDWH7KHPLQLPXP$&GULYHSRLQWGHILQHVDQDFFHSWDEOHILUVWVWHSYROWDJHDQG PXVWEHUHDFKHGZLWKLQWKHPD[LPXP7YDOWLPH7KHPD[LPXP$&GULYHSRLQWOLPLWV WKHDPRXQWRIRYHUVKRRWDQGXQGHUVKRRWLQWKHV\VWHP7KH'&GULYHSRLQWVSHFLILHV VWHDG\VWDWHFRQGLWLRQV7KHPLQLPXPVOHZUDWHDQGWKHWLPLQJSDUDPHWHUVJXDUDQWHH 0+]RSHUDWLRQ7KHPD[LPXPVOHZUDWHPLQLPL]HVV\VWHPQRLVH7KLVPHWKRGRI VSHFLILFDWLRQSURYLGHVDPRUHFRQFLVHGHILQLWLRQIRUWKHRXWSXWEXIIHU 224 Revision 2.2 7.6.3.1. DC Specifications 5HIHUWR6HFWLRQ 7.6.3.2. AC Specifications 7DEOH $&6SHFLILFDWLRQV Symbol Parameter Condition Min Max Units Notes AC Drive Points Ioh(AC,min) Switching Current Vout = 0.3Vcc -12Vcc -mA1 High, minimum Ioh(AC,max) Switching Current Vout = 0.7Vcc - -32Vcc mA High, maximum Iol(AC,min) Switching Current Vout = 0.6Vcc 16Vcc -mA1 Low, minimum Iol(AC,max) Switching Vout = 0.18Vcc - 38Vcc mA Current Low, maximum DC Drive Points VOH Output high Iout = -0.5 mA 0.9Vcc -V2 voltage VOL Output low Iout = 1.5 mA - 0.1Vcc V2 voltage Slew Rate tr Output rise slew 0.3Vcc to 0.6Vcc 1 4 V/ns 3 rate tf Output fall slew 0.6Vcc to 0.3Vcc 1 4 V/ns 3 rate Clamp Current ≥ Ich High clamp Vcc + 4 > Vin Vcc + 1 25 + (Vin - Vcc - 1) / 0.015 - mA current ≤ Icl Low clamp -3 < Vin -1 -25 + (Vin + 1) / 0.015 - mA current NOTES: 1. Switching current characteristics for REQ# and GNT# are permitted to be one half of that specified here; i.e., half size drivers may be used on these signals. This specification does not apply to CLK and RST# which are system outputs. "Switching Current High" specifications are not relevant to SERR#, PME#, INTA#, INTB#, INTC#, and INTD# which are open drain outputs. 2. These DC values are duplicated from Section 4.2.2.1. and are included here for completeness. 3. This parameter is to be interpreted as the cumulative edge rate across the specified range rather than the instantaneous rate at any point within the transition range. The specified load (see Figure 7-7) is optional. The designer may elect to meet this parameter with an unloaded output per revision 2.0 of the PCI Local Bus Specification. However, adherence to both maximum and minimum parameters is required (the maximum is not simply a guideline). Rise slew rate does not apply to open drain outputs. 225 Revision 2.2 7.6.3.3. Maximum AC Ratings and Device Protection 5HIHUWR6HFWLRQ 7.6.4. Timing Specification 7.6.4.1. Clock Specification 7KHFORFNZDYHIRUPPXVWEHGHOLYHUHGWRHDFK0+]3&,FRPSRQHQWLQWKHV\VWHP,Q WKHFDVHRIH[SDQVLRQERDUGVFRPSOLDQFHZLWKWKHFORFNVSHFLILFDWLRQLVPHDVXUHGDWWKH H[SDQVLRQERDUGFRPSRQHQWQRWDWWKHFRQQHFWRU)LJXUHVKRZVWKHFORFNZDYHIRUP DQGUHTXLUHGPHDVXUHPHQWSRLQWVIRU9VLJQDOLQJHQYLURQPHQWV5HIHUWRLWHPLQ 6HFWLRQIRUVSHFLDOFRQVLGHUDWLRQVZKHQXVLQJ3&,WR3&,EULGJHVRQH[SDQVLRQ ERDUGVRUZKHQH[SDQVLRQERDUGVORWVDUHORFDWHGGRZQVWUHDPRID3&,WR3&,EULGJH 7DEOHVXPPDUL]HVWKHFORFNVSHFLILFDWLRQV T_cyc T_high T_low 3.3 volt Clock 0.6 Vcc 0.5 Vcc 0.4 Vcc 0.4 Vcc, p-to-p (minimum) 0.3 Vcc 0.2 Vcc )LJXUH 9&ORFN:DYHIRUP 6SUHDGVSHFWUXPPRGXODWLRQWHFKQLTXHVDUHSHUPLWWHGZLWKLQWKHOLPLWVVSHFLILHGLQ 7DEOH 226 Revision 2.2 7DEOH &ORFN6SHFLILFDWLRQV 66 MHz 33 MHz4 Symbol Parameter Min Max Min Max Units Notes Tcyc CLK Cycle Time 15 30 30 ∞ ns 1,3 Thigh CLK High Time 6 11 ns Tlow CLK Low Time 6 11 ns - CLK Slew Rate 1.5 4 1 4 V/ns 2 Spread Spectrum Requirements fmod modulation 30 33 - - kHz frequency fspread frequency -1 9 % spread NOTES: 1. In general, all 66 MHz PCI components must work with any clock frequency up to 66 MHz. CLK requirements vary depending upon whether the clock frequency is above 33 MHz. a. Device operational parameters at frequencies at or under 33 MHz will conform to the specifications in Chapter 4. The clock frequency may be changed at any time during the operation of the system so long as the clock edges remain "clean" (monotonic) and the minimum cycle and high and low times are not violated. The clock may only be stopped in a low state. A variance on this specification is allowed for components designed for use on the system planar only. Refer to Section 4.2.3.1. for more information. b. For clock frequencies between 33 MHz and 66 MHz, the clock frequency may not change except while RST# is asserted or when spread spectrum clocking (SSC) is used to reduce EMI emissions. 2. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in Figure 7-2. Clock slew rate is measured by the slew rate circuit shown in Figure 7-7. 3. The minimum clock period must not be violated for any single clock cycle; i.e., accounting for all system jitter. 4. These values are duplicated from Section 4.2.3.1. and included here for comparison. Implementation Note: Spread Spectrum Clocking (SSC) 6SUHDGLQJWKHIUHTXHQF\LVRQO\DOORZHGEHORZWKHPD[LPXPFORFNIUHTXHQF\WKDWLV VSHFLILHG LHWKHPLQLPXPFORFNSHULRGVKRZQLQ7DEOHFDQQRWEHYLRODWHG ,Q RWKHUZRUGVWKHIUHTXHQF\FKDQJHFDQRQO\RFFXUWRUHGXFHWKHIUHTXHQF\RIWKHFORFN DQGQHYHUWRLQFUHDVHLW:KHQ3//VDUHXVHGWRWUDFNCLKWKH\QHHGWRWUDFNWKH66& PRGXODWLRQTXLFNO\LQRUGHUQRWWRDFFXPXODWHH[FHVVLYHSKDVHGLIIHUHQFHEHWZHHQWKH 3//LQSXWDQGRXWSXWFORFNV FRPPRQO\UHIHUUHGWRDV66&WUDFNLQJVNHZ 7KHDPRXQW RIWUDFNLQJVNHZGHSHQGVRQWKH3//EDQGZLGWKSKDVHDQJOHDWN+]DQGWKH DPRXQWRIWKHVSUHDG,WLVGHVLUDEOHWRPD[LPL]HEDQGZLGWKDQGRUUHGXFHWKHSKDVH DQJOHLQRUGHUWRPLQLPL]HWKHWUDFNLQJVNHZ RWKHUZLVHWKH66&IUHTXHQF\VSUHDGRIWKH V\VWHPPXVWEHUHGXFHGWKHUHE\UHGXFLQJWKH66&(0,UHGXFWLRQFDSDELOLW\ 227 Revision 2.2 7.6.4.2. Timing Parameters 7DEOH 0+]DQG0+]7LPLQJ3DUDPHWHUV 66 MHz 33 MHz7 Symbol Parameter Min Max Min Max Units Notes Tval CLK to Signal Valid Delay - 2 6 2 11 ns 1, 2, bused signals 3, 8 Tval(ptp) CLK to Signal Valid Delay - 2 6 2 12 ns 1, 2, point to point signals 3, 8 Ton Float to Active Delay 2 2 ns 1, 8, 9 Toff Active to Float Delay 14 28 ns 1, 9 Tsu Input Setup Time to CLK - 3 7 ns 3, 4, bused signals 10 Tsu(ptp) Input Setup Time to CLK - 5 10,12 ns 3, 4 point to point signals Th Input Hold Time from CLK 0 0 ns 4 Trst Reset Active Time after 1 1 ms 5 power stable µ Trst-clk Reset Active Time after CLK 100 100 s5 stable Trst-off Reset Active to output float 40 40 ns 5, 6 delay trrsu REQ64# to RST# setup time 10Tcyc 10Tcyc ns trrh RST# to REQ64# hold time 0 50 0 50 ns RST# high to first 25 25 Trhfa 2 2 clocks Configuration access RST# high to first FRAME# 5 Trhff 5 clocks assertion NOTES: 1. See the timing measurement conditions in Figure 7-3. It is important that all driven signal transitions drive to their Voh or Vol level within one Tcyc. 2. Minimum times are measured at the package pin with the load circuit shown in Figure 7-7. Maximum times are measured with the load circuit shown in Figures 7-5 and 7-6. 3. REQ# and GNT# are point-to-point signals and have different input setup times than do bused signals. GNT# and REQ# have a setup of 5 ns at 66 MHz. All other signals are bused. 4. See the timing measurement conditions in Figure 7-4. 5. If M66EN is asserted, CLK is stable when it meets the requirements in Section 7.6.4.1. RST# is asserted and deasserted asynchronously with respect to CLK. Refer to Section 4.3.2. for more information. 6. All output drivers must be floated when RST# is active. Refer to Section 4.3.2. for more information. 7. These values are duplicated from Section 4.2.3.2. and are included here for comparison. 8. When M66EN is asserted, the minimum specification for Tval(min), Tval(ptp)(min), and Ton may be reduced to 1 ns if a mechanism is provided to guarantee a minimum value of 2 ns when M66EN is deasserted. 228 Revision 2.2 9. For purposes of Active/Float timing measurements, the Hi-Z or “off” state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 10. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at the same time. Refer to Section 3.10., item 9 for additional details. 7.6.4.3. Measurement and Test Conditions V_th CLK V_test V_tl T_val OUTPUT V_tfall DELAY T_val OUTPUT V_trise DELAY Tri-State OUTPUT T_on T_off )LJXUH 2XWSXW7LPLQJ0HDVXUHPHQW&RQGLWLRQV V_th CLK V_test V_tl T_su T_h V_th inputs V_test V_max INPUT V_test valid V_tl )LJXUH ,QSXW7LPLQJ0HDVXUHPHQW&RQGLWLRQV 229 Revision 2.2 7DEOH 0HDVXUHPHQW&RQGLWLRQ3DUDPHWHUV Symbol 3.3V Signaling Units Notes Vth 0.6Vcc V1 Vtl 0.2Vcc V1 Vtest 0.4Vcc V Vtrise 0.285Vcc V2 Vtfall 0.615Vcc V2 Vmax 0.4Vcc V1 Input Signal 1.5 V/ns 3 Slew Rate NOTES: 1. The test for the 3.3V environment is done with 0.1*Vcc of overdrive. Vmax specifies the maximum peak-to-peak waveform allowed for measuring input timing. Production testing may use different voltage values but must correlate results back to these parameters. 2. Vtrise and Vtfall are reference voltages for timing measurements only. Developers of 66 MHz PCI systems need to design buffers that launch enough energy into a 25 Ω transmission line so that correct input levels are guaranteed after the first reflection. 3. Outputs will be characterized and measured at the package pin with the load shown in Figure 7-7. Input signal slew rate will be measured between 0.3Vcc and 0.6Vcc. pin 1/2 in. max. output buffer 25 Ω 10 pF )LJXUH 7YDO PD[ 5LVLQJ(GJH 1/2 in. max. Vcc 25 Ω 10 pF )LJXUH 7YDO PD[ )DOOLQJ(GJH 230 Revision 2.2 pin 1/2 in. max. output buffer Vcc 10 pF 1K Ω 1K Ω )LJXUH 7YDO PLQ DQG6OHZ5DWH 7.6.5. Vendor Provided Specification 5HIHUWR6HFWLRQ 7.6.6. Recommendations 7.6.6.1. Pinout Recommendations 5HIHUWR6HFWLRQ 7KH0+]3&,HOHFWULFDOVSHFLILFDWLRQDQGSK\VLFDOUHTXLUHPHQWVPXVWEHPHW KRZHYHUWKHGHVLJQHULVSHUPLWWHGWRPRGLI\WKHVXJJHVWHGSLQRXWVKRZQLQ)LJXUH DV UHTXLUHG 7.6.6.2. Clocking Recommendations 7KLVVHFWLRQGHVFULEHVDUHFRPPHQGHGPHWKRGIRUURXWLQJWKH0+]3&,FORFNVLJQDO 5RXWLQJWKH0+]3&,FORFNDVDSRLQWWRSRLQWVLJQDOIURPLQGLYLGXDOORZVNHZFORFN GULYHUVWRERWKSODQDUDQGH[SDQVLRQERDUGFRPSRQHQWVZLOOJUHDWO\UHGXFHVLJQDO UHIOHFWLRQHIIHFWVDQGRSWLPL]HFORFNVLJQDOLQWHJULW\7KLVLQDGGLWLRQWRREVHUYLQJWKH SK\VLFDOUHTXLUHPHQWVRXWOLQHGLQ6HFWLRQZLOOPLQLPL]HFORFNVNHZ 'HYHORSHUVPXVWSD\FDUHIXODWWHQWLRQWRWKHFORFNWUDFHOHQJWKOLPLWVVWDWHGLQ 6HFWLRQDQGWKHYHORFLW\OLPLWVLQ6HFWLRQ)LJXUHLOOXVWUDWHVWKH UHFRPPHQGHGPHWKRGIRUURXWLQJWKH0+]3&,FORFNVLJQDO 231 Revision 2.2 Clock Source Add-in Board 66 MHz Device A PCI Add-in Connector 66 MHz Device B 66 MHz Device C )LJXUH 5HFRPPHQGHG&ORFN5RXWLQJ 7.7. System (Planar) Specification 7.7.1. Clock Uncertainty 7KHPD[LPXPDOORZDEOHFORFNVNHZLQFOXGLQJMLWWHULVQV7KLVVSHFLILFDWLRQDSSOLHV QRWRQO\DWDVLQJOHWKUHVKROGSRLQWEXWDWDOOSRLQWVRQWKHFORFNHGJHWKDWIDOOLQWKH VZLWFKLQJUDQJHGHILQHGLQ7DEOHDQG)LJXUH 7KHPD[LPXPVNHZLVPHDVXUHG EHWZHHQDQ\WZRFRPSRQHQWV QRWEHWZHHQFRQQHFWRUV7RFRUUHFWO\HYDOXDWHFORFN VNHZWKHV\VWHPGHVLJQHUPXVWWDNHLQWRDFFRXQWFORFNGLVWULEXWLRQRQWKHH[SDQVLRQ ERDUGDVVSHFLILHGLQ6HFWLRQ 'HYHORSHUVPXVWSD\FDUHIXODWWHQWLRQWRWKHFORFNWUDFHOHQJWKOLPLWVVWDWHGLQ 6HFWLRQDQGWKHYHORFLW\OLPLWVLQ6HFWLRQ 7DEOH &ORFN6NHZ3DUDPHWHUV Symbol 66 MHz 3.3V Signaling 33 MHz 3.3V Signaling Units Vtest 0.4Vcc 0.4Vcc V Tskew 1 (max) 2 (max) ns 53 The system designer must address an additional source of clock skew. This clock skew occurs between two components that have clock input trip points at opposite ends of the Vil - Vih range. In certain circumstances, this can add to the clock skew measurement as described here. In all cases, total clock skew must be limited to the specified number. 232 Revision 2.2 V_ih V_test CLK V_il (@Device #1) T_skew T_skew T_skew V_ih CLK V_test (@Device #2) V_il )LJXUH &ORFN6NHZ'LDJUDP 7.7.2. Reset 5HIHUWR6HFWLRQ 7.7.3. Pullups 7KH0+]3&,EXVUHTXLUHVDVLQJOHSXOOXSUHVLVWRUVXSSOLHGE\WKHSODQDURQWKH M66ENSLQ5HIHUWR6HFWLRQIRUWKHUHVLVWRUYDOXH 7.7.4. Power 7.7.4.1. Power Requirements 5HIHUWR6HFWLRQ 7.7.4.2. Sequencing 5HIHUWR6HFWLRQ 7.7.4.3. Decoupling 5HIHUWR6HFWLRQ 7.7.5. System Timing Budget :KHQFRPSXWLQJDWRWDO0+]3&,ORDGPRGHOGHVLJQHUVPXVWSD\FDUHIXODWWHQWLRQWR PD[LPXPWUDFHOHQJWKDQGORDGLQJRIH[SDQVLRQERDUGV5HIHUWR6HFWLRQ$OVR WKHPD[LPXPSLQFDSDFLWDQFHRIS)PXVWEHDVVXPHGIRUH[SDQVLRQERDUGVZKHUHDV WKHDFWXDOSLQFDSDFLWDQFHPD\EHXVHGIRUSODQDUGHYLFHV 7KHWRWDOFORFNSHULRGFDQEHGLYLGHGLQWRIRXUVHJPHQWV9DOLGRXWSXWGHOD\ 7YDO DQG LQSXWVHWXSWLPHV 7VX DUHVSHFLILHGE\WKHFRPSRQHQWVSHFLILFDWLRQ7RWDOFORFNVNHZ 7VNHZ DQGEXVSURSDJDWLRQWLPHV 7SURS DUHV\VWHPSDUDPHWHUV7SURSLVDV\VWHP SDUDPHWHUWKDWLVLQGLUHFWO\VSHFLILHGE\VXEWUDFWLQJWKHRWKHUWLPLQJEXGJHWFRPSRQHQWV IURPWKHF\FOHWLPH7DEOHOLVWVWLPLQJEXGJHWVIRUVHYHUDOEXVIUHTXHQFLHV 233 Revision 2.2 7SURSLVPHDVXUHGDVVKRZQLQ)LJXUH,WEHJLQVDWWKHWLPHWKHVLJQDODWWKHRXWSXW EXIIHUZRXOGKDYHFURVVHGWKHWKUHVKROGSRLQW 9WULVHRU9WIDOO KDGWKHRXWSXWEHHQ GULYLQJWKHVSHFLILHG7YDO PD[ ORDG7KHHQGRI7SURSIRUDQ\SDUWLFXODULQSXWLV GHWHUPLQHGE\RQHRIWKHIROORZLQJWZRPHDVXUHPHQWPHWKRGV7KHPHWKRGWKDW SURGXFHVWKHORQJHUYDOXHIRU7SURSPXVWEHXVHG 0HWKRG 7KHHQGRI7SURSLVWKHWLPHZKHQWKHVLJQDODWWKHLQSXWFURVVHV9WHVWIRUWKH ODVWWLPH 6HH)LJXUHDG 0HWKRG &RQVWUXFWDOLQHZLWKDVORSHHTXDOWRWKH,QSXW6LJQDO6OHZ5DWHVKRZQLQ 7DEOHDQGFURVVLQJWKURXJKWKHSRLQWZKHUHWKHVLJQDODWWKHLQSXW FURVVHV9LK KLJKJRLQJ RU9LO ORZJRLQJ IRUWKHODVWWLPH7KHHQGRI 7SURSLVWKHWLPHZKHQWKHFRQVWUXFWHGOLQHFURVVHV9WHVW 6HH)LJXUH EFHI Implementation Note: Determining the End of Tprop 7KHHQGRI7SURSLVDOZD\VGHWHUPLQHGE\WKHFDOFXODWLRQPHWKRGWKDWSURGXFHVWKH ORQJHUYDOXHRI7SURS7KHVKDSHRIWKHZDYHIRUPDWWKHLQSXWEXIIHUZLOOGHWHUPLQH ZKLFKPHDVXUHPHQWPHWKRGZLOOSURGXFHWKHORQJHUYDOXH :KHQWKHVLJQDOULVHVRUIDOOVIURP9WHVWWRWKHODVWFURVVLQJRU9LK KLJKJRLQJ RU9LO ORZJRLQJ IDVWHUWKDQWKH,QSXW6LJQDO6OHZ5DWHVKRZQLQ7DEOH0HWKRGZLOO SURGXFHWKHORQJHUYDOXH 6HH)LJXUHDG :KHQWKHVLJQDOULVHVRUIDOOVIURP9WHVWWRWKHODVWFURVVLQJRU9LK KLJKJRLQJ RU9LO ORZJRLQJ VORZHUWKDQWKH,QSXW6LJQDO6OHZ5DWH0HWKRGZLOOSURGXFHWKHORQJHU YDOXH,QRWKHUZRUGVLIWKHVLJQDOSODWHDXVRUULVHV KLJKJRLQJ RUIDOOV ORZJRLQJ VORZO\DIWHUFURVVLQJ9WHVWRUULQJVEDFNDFURVV9LK KLJKJRLQJ RU9LO ORZJRLQJ VLJQLILFDQWO\DIWHUFURVVLQJ9WHVW0HWKRGZLOOSURGXFHWKHORQJHUYDOXH 6HH)LJXUHEFHI )RUDJLYHQGULYHUORFDWLRQWKHZRUVWFDVHWKDWPXVWEHFRQVLGHUHGZKHQGHWHUPLQLQJWKH YDOXHRI7SURSLVZKHQWKHVLJQDOVHWWOHVDWDOORWKHUGHYLFHVRQWKHEXV7KHYDOXHRI 7SURSLVQRWDIIHFWHGE\WKHWLPHWKHVLJQDOVHWWOHVDWWKHGULYHURXWSXWVLQFHGHYLFHVDUH QRWSHUPLWWHGWRGULYHDQGUHFHLYHDVLJQDODWWKHVDPHWLPH5HIHUWR6HFWLRQ LWHP IRUDGGLWLRQDOGHWDLOV 234 Revision 2.2 0.7Vcc 0.7Vcc Input Signal Driving Bus Slew Rate Vth Vth 0.6V 0.6Vcc cc Driving Vih Vih Bus 0.5Vcc 0.5Vcc Vtest Vtest 0.4Vcc 0.4Vcc V Vtrise 0.3Vcc trise 0.3Vcc Driving Driving 0.2V Test Load 0.2Vcc Test Load cc Tprop Tprop 0.1Vcc 0.1Vcc 0 0 (a) (b) 0.9Vcc 0.9Vcc 0.8Vcc Input Signal 0.8Vcc Slew Rate Tprop 0.7Vcc Driving 0.7Vcc Bus Vth Vtfall 0.6V 0.6Vcc cc Vih Driving 0.5Vcc 0.5Vcc Test Load Vtest Vtest 0.4Vcc 0.4Vcc Vtrise Vil 0.3Vcc 0.3Vcc Driving Vtl Driving Bus 0.2Vcc Test Load 0.2Vcc Tprop 0.1Vcc 0.1Vcc 0 0 (c) (d) 0.9Vcc 0.9Vcc 0.8V 0.8Vcc Tprop cc Tprop 0.7Vcc 0.7Vcc Vtfall Vtfall 0.6V 0.6V cc cc Driving Driving Test Load 0.5Vcc Test Load 0.5Vcc Vtest Vtest 0.4Vcc 0.4Vcc Input Signal Input Signal Vil Slew Rate Vil Slew Rate 0.3Vcc 0.3Vcc Vtl Driving Bus Vtl 0.2Vcc 0.2Vcc 0.1V 0.1Vcc cc Driving Bus 0 0 (e) (f) )LJXUH 0HDVXUHPHQWRI7SURS UHIHUWR7DEOHIRUSDUDPHWHUYDOXHV 235 Revision 2.2 7KHUHOHYDQWWLPLQJEXGJHWFDQEHH[SUHVVHGE\WKHHTXDWLRQ ≥ 7F\F 7YDO7SURS7VX7VNHZ 7KHIROORZLQJWDEOHFRPSDUHV3&,WLPLQJEXGJHWVDWYDULRXVVSHHGV 7DEOH 7LPLQJ%XGJHWV Timing Element 33 MHz 66 MHz 50 MHz1 Units Notes Tcyc 30 15 20 ns Tval 11 6 6 ns Tprop 10 5 10 ns 2 Tsu 733ns Tskew 211ns3 NOTES: 1. The 50 MHz example is shown for example purposes only. 2. These times are computed. The other times are fixed. Thus, slowing down the bus clock enables the system manufacturer to gain additional distance or add additional loads. The component specifications are required to guarantee operation at 66 MHz. 3 Clock skew specified here includes all sources of skew. If spread spectrum clocking (SSC) is used on the system board, the maximum clock skew at the input of the device on an expansion board includes SSC tracking skew. 7.7.6. Physical Requirements 7.7.6.1. Routing and Layout Recommendations for Four-Layer Boards 5HIHUWR6HFWLRQ 7.7.6.2. Planar Impedance 5HIHUWR6HFWLRQ7LPLQJQXPEHUVDUHFKDQJHGDFFRUGLQJWRWKHWDEOHVLQWKLV FKDSWHU 7.7.7. Connector Pin Assignments 7KHM66ENSLQ SLQ % LVWKHRQO\FRQQHFWRUGLIIHUHQFHEHWZHHQEXVVHJPHQWV FDSDEOHRI0+]RSHUDWLRQDQGWKRVHOLPLWHGWR0+]5HIHUWR6HFWLRQIRU SODQDUFRQQHFWRUV7KLVSLQLVDQRUPDOJURXQGSLQLQLPSOHPHQWDWLRQVWKDWDUHQRW FDSDEOHRI0+]RSHUDWLRQ 236 Revision 2.2 ,QLPSOHPHQWDWLRQVWKDWDUH0+]FDSDEOHWKHM66ENSLQLVEXVHGEHWZHHQDOO FRQQHFWRUV ZLWKLQWKHVLQJOHORJLFDOEXVVHJPHQWWKDWLV0+]FDSDEOHDQGWKLVQHW Ω M66EN LVSXOOHGXSZLWKD. UHVLVWRUWR9FF$OVRWKLVQHWLVFRQQHFWHGWRWKH LQSXW SLQRIFRPSRQHQWVORFDWHGRQWKHVDPHORJLFDOEXVVHJPHQWRIWKHV\VWHPSODQDU7KLV VLJQDOLVVWDWLF WKHUHLVQRVWXEOHQJWKUHVWULFWLRQ 7RFRPSOHWHDQ$&UHWXUQSDWKDµ)FDSDFLWRUPXVWEHORFDWHGZLWKLQLQFKHV RIWKHM66ENSLQRIHDFKVXFKH[SDQVLRQERDUGFRQQHFWRUDQGPXVWGHFRXSOHWKH M66ENVLJQDOWRJURXQG$Q\DWWDFKHGFRPSRQHQWRULQVWDOOHGH[SDQVLRQERDUGWKDWLV QRW0+]FDSDEOHPXVWSXOOWKHM66ENQHWWRWKH9LOLQSXWOHYHO7KHUHPDLQLQJ FRPSRQHQWVH[SDQVLRQERDUGVDQGWKHORJLFDOEXVVHJPHQWFORFNUHVRXUFHDUHWKHUHE\ VLJQDOHGWRRSHUDWHLQ0+]PRGH 7.8. Expansion Board Specifications 7KHM66ENSLQ SLQ % LVWKHRQO\FRQQHFWRUGLIIHUHQFHEHWZHHQH[SDQVLRQFDUGV FDSDEOHRI0+]RSHUDWLRQDQGWKRVHOLPLWHGWR0+]5HIHUWR6HFWLRQIRU WKHH[SDQVLRQERDUGHGJHFRQQHFWRU7KHM66ENSLQLVDQRUPDOJURXQGSLQLQ LPSOHPHQWDWLRQVWKDWDUHQRWFDSDEOHRI0+]RSHUDWLRQ ,QLPSOHPHQWDWLRQVWKDWDUH0+]FDSDEOHWKHM66ENSLQPXVWEHGHFRXSOHGWR JURXQGZLWKDµ)FDSDFLWRUZKLFKPXVWEHORFDWHGZLWKLQLQFKHVRIWKHHGJH FRQWDFWWRFRPSOHWHDQ$&UHWXUQSDWK,IWKHM66ENSLQLVSXOOHGWRWKH9LOLQSXWOHYHO LWLQGLFDWHVWKDWWKHH[SDQVLRQERDUGPXVWRSHUDWHLQWKH0+]PRGH 54 As a general rule, there will be only one such connector, but more than one are possible in certain cases. 237 Revision 2.2 238 Revision 2.2 Appendix A Special Cycle Messages 6SHFLDO&\FOHPHVVDJHHQFRGLQJVDUHGHILQHGLQWKLVDSSHQGL[5HVHUYHGHQFRGLQJVVKRXOGQRW EHXVHG3&,6,*PHPEHUFRPSDQLHVWKDWUHTXLUHVSHFLDOHQFRGLQJVRXWVLGHWKHUDQJHRI FXUUHQWO\GHILQHGHQFRGLQJVVKRXOGVHQGDZULWWHQUHTXHVWWRWKH3&,6,*6WHHULQJ&RPPLWWHH 7KH6WHHULQJ&RPPLWWHHZLOODOORFDWHDQGGHILQHVSHFLDOF\FOHHQFRGLQJVEDVHGXSRQ LQIRUPDWLRQSURYLGHGE\WKHUHTXHVWHUVSHFLI\LQJXVDJHQHHGVDQGIXWXUHSURGXFWRUDSSOLFDWLRQ GLUHFWLRQ Message Encodings AD[15::0] 0HVVDJH7\SH K 6+87'2:1 K +$/7 K [DUFKLWHFWXUHVSHFLILF K 5HVHUYHG WKURXJK ))))K 5HVHUYHG 6+87'2:1LVDEURDGFDVWPHVVDJHLQGLFDWLQJWKHSURFHVVRULVHQWHULQJLQWRD VKXWGRZQPRGH +$/7LVDEURDGFDVWPHVVDJHIURPWKHSURFHVVRULQGLFDWLQJLWKDVH[HFXWHGDKDOW LQVWUXFWLRQ 7KH[DUFKLWHFWXUHVSHFLILFHQFRGLQJLVDJHQHULFHQFRGLQJIRUXVHE\[SURFHVVRUV DQGFKLSVHWVAD[31::16]GHWHUPLQHWKHVSHFLILFPHDQLQJRIWKH6SHFLDO&\FOHPHVVDJH 6SHFLILFPHDQLQJVDUHGHILQHGE\,QWHO&RUSRUDWLRQDQGDUHIRXQGLQSURGXFWVSHFLILF GRFXPHQWDWLRQ Use of Specific Encodings 8VHRUJHQHUDWLRQRIDUFKLWHFWXUHVSHFLILFHQFRGLQJVLVQRWOLPLWHGWRWKHUHTXHVWHURIWKH HQFRGLQJ6SHFLILFHQFRGLQJVPD\EHXVHGE\DQ\YHQGRULQDQ\V\VWHP7KHVH HQFRGLQJVDOORZV\VWHPVSHFLILFFRPPXQLFDWLRQOLQNVEHWZHHQFRRSHUDWLQJ3&,GHYLFHV IRUSXUSRVHVZKLFKFDQQRWEHKDQGOHGZLWKWKHVWDQGDUGGDWDWUDQVIHUF\FOHW\SHV 239 Revision 2.2 240 Revision 2.2 Appendix B State Machines This appendix describes master and target state machines. These state machines are for illustrative purposes only and are included to help illustrate PCI protocol. Actual implementations should not directly use these state machines. The machines are believed to be correct; however, if a conflict exists between the specification and the state machines, the specification has precedence. The state machines use three types of variables: states, PCI signals, and internal signals. They can be distinguished from each other by: State in a state machine = STATE PCI signal = SIGNAL Internal signal = Signal The state machines assume no delays from entering a state until signals are generated and available for use in the machine. All PCI signals are latched on the rising edge of CLK. The state machines support some options (but not all) discussed in the PCI specification. A discussion about each state and the options illustrated follows the definition of each state machine. The target state machine assumes medium decode and, therefore, does not describe fast decode. If fast decode is implemented, the state diagrams (and their associated equations) will need to be changed to support fast decode. Caution needs to be taken when supporting fast decode (Refer to Section 3.4.2.). The bus interface consists of two parts. The first is the bus sequencer that performs the actual bus operation. The second part is the backend or hardware application. In a master, the backend generates the transaction and provides the address, data, command, Byte Enables, and the length of the transfer. It is also responsible for the address when a transaction is retried. In a target, the backend determines when a transaction is terminated. The sequencer performs the bus operation as requested and guarantees the PCI protocol is not violated. Note that the target implements a resource lock. The state machine equations assume a logical operation where "*" is an AND function and has precedence over "+" which is an OR function. Parentheses have precedence over both. The "!" character is used to indicate the NOT of the variable. In the state machine equations, the PCI SIGNALs represent the actual state of the signal on the PCI bus. Low true signals will be true or asserted when they appear as !SIGNAL# and will be false or deasserted when they appear as SIGNAL#. High true signals will be true or 241 Revision 2.2 asserted when they appear as SIGNAL and will be false or deasserted when they appear as !SIGNAL. Internal signals will be true when they appear as Signal and false when they appear as !Signal. A few of the output enable equations use the "==" symbol to refer to the previous state. For example: OE[PAR] == [S_DATA * !TRDY# * (cmd=read)] This indicates the output buffer for PAR is enabled when the previous state is S_DATA, TRDY# is asserted, the transaction is a read. The first state machine presented is for the target, the second is the master. Caution needs to be taken when an agent is both a master and a target. Each must have its own state machine that can operate independently of the other to avoid deadlocks. This means that the target state machine cannot be affected by the master state machine. Although they have similar states, they cannot be built into a single machine. Note: LOCK# can only be implemented by a bridge; refer to Appendix F for details about the use of LOCK#. For a non-bridge device, the use of LOCK# is prohibited. IDLE B_BUSY BACKOFF S_DATA Target Sequencer TURN_AR Machine FREE LOCKED Target LOCK Machine IDLE or TURN_AR -- Idle condition or completed transaction on bus. goto IDLE if FRAME# goto B_BUSY if !FRAME# * !Hit 242 Revision 2.2 B_BUSY -- Not involved in current transaction. goto B_BUSY if (!FRAME# + !D_done) * !Hit goto IDLE if FRAME# * D_done + FRAME# * !D_done * !DEVSEL# goto S_DATA if (!FRAME# + !IRDY#) * Hit * (!Term + Term * Ready) * (FREE + LOCKED * L_lock#) goto BACKOFF *if (!FRAME# + !IRDY#) * Hit * (Term * !Ready + LOCKED * !L_lock#) S_DATA -- Agent has accepted request and will respond. goto S_DATA if !FRAME# * !STOP# * !TRDY# * IRDY# + !FRAME# * STOP# + FRAME# * TRDY# * STOP# goto BACKOFF if !FRAME# * !STOP# * (TRDY# + !IRDY#) goto TURN_AR if FRAME# * (!TRDY# + !STOP#) BACKOFF -- Agent busy unable to respond at this time. goto BACKOFF if !FRAME# goto TURN_AR if FRAME# Target LOCK Machine FREE -- Agent is free to respond to all transactions. goto LOCKED if !FRAME# * LOCK# * Hit * (IDLE + TURN_AR) + L_lock# * Hit * B_BUSY) goto FREE if ELSE LOCKED -- Agent will not respond unless LOCK# is deasserted during the address phase. goto FREE if FRAME# * LOCK# goto LOCKED if ELSE Target of a transaction is responsible to drive the following signals: 55 OE[AD[31::00]] = (S_DATA + BACKOFF) * Tar_dly * (cmd = read) OE[TRDY#] = BACKOFF + S_DATA + TURN_AR (See note.) OE[STOP#] = BACKOFF + S_DATA + TURN_AR (See note.) OE[DEVSEL#] = BACKOFF + S_DATA + TURN_AR (See note.) OE[PAR] = OE[AD[31::00]] delayed by one clock OE[PERR#] = R_perr + R_perr (delayed by one clock) Note: If the device does fast decode, OE[PERR#] must be delayed one clock to avoid contention. When the target supports the Special Cycle command, an additional term must be included to ensure these signals are not enabled during a Special Cycle transaction. 243 Revision 2.2 TRDY# = !(Ready * !T_abort * S_DATA * (cmd=write + cmd=read * Tar_dly)) STOP# = ![BACKOFF + S_DATA * (T_abort + Term) * (cmd=write + cmd=read * Tar_dly)] DEVSEL# = ![(BACKOFF + S_DATA) * !T_abort] PAR = even parity across AD[31::00] and C/BE#[3::0] lines. PERR# = R_perr Definitions These signals are between the target bus sequencer and the backend. They indicate how the bus sequencer should respond to the current bus operation. Hit = Hit on address decode. D_done = Decode done. Device has completed the address decode. T_abort = Target is in an error condition and requires the current transaction to stop. Term = Terminate the transaction. (Internal conflict or > n wait states.) Ready = Ready to transfer data. L_lock# = Latched (during address phase) version of LOCK#. Tar_dly = Turn around delay only required for zero wait state decode. R_perr = Report parity error is a pulse of one PCI clock in duration. Last_target = Device was the target of the last (prior) PCI transaction. The following paragraphs discuss each state and describe which equations can be removed if some of the PCI options are not implemented. The IDLE and TURN_AR are two separate states in the state machine, but are combined here because the state transitions are the same from both states. They are implemented as separate states because active signals need to be deasserted before the target tri-states them. If the target cannot do single cycle address decode, the path from IDLE to S_DATA can be removed. The reason the target requires the path from the TURN_AR state to S_DATA and B_BUSY is for back-to-back bus operations. The target must be able to decode back-to-back transactions. B_BUSY is a state where the agent waits for the current transaction to complete and the bus to return to the Idle state. B_BUSY is useful for devices that do slow address decode or perform subtractive decode. If the target does neither of these two options, the path to S_DATA and BACKOFF may be removed. The term "!Hit" may be removed from the B_BUSY equation also. This reduces the state to waiting for the current bus transaction to complete. S_DATA is a state where the target transfers data and there are no optional equations. BACKOFF is where the target goes after it asserts STOP# and waits for the master to deassert FRAME#. FREE and LOCKED refer to the state of the target with respect to a lock operation. If the target does not implement LOCK#, then these states are not required. FREE indicates when the agent may accept any request when it is the target. If LOCKED, the target will retry any request when it is the target unless LOCK# is deasserted during the address phase. The agent marks itself locked whenever it is the target of a transaction and LOCK# is deasserted during the address phase. It is a little confusing for the target to lock itself on a transaction that is not locked. However, from an implementation point of view, it is a simple mechanism that uses combinatorial logic and always works. The device will unlock itself at the end of the transaction when it detects FRAME# and LOCK# both deasserted. 244 Revision 2.2 The second equation in the goto LOCKED in the FREE state can be removed if fast decode is done. The first equation can be removed if medium or slow decode is done. L_lock# is LOCK# latched during the address phase and is used when the agent's decode completes. IDLE ADDR DR_BUS S_TAR M_DATA Master TURN_AR Sequencer Machine FREE BUSY Master LOCK Machine Master Sequencer Machine IDLE -- Idle condition on bus. goto ADDR if (Request * !Step) * !GNT# * FRAME# * IRDY# goto DR_BUS if (Request * Step + !Request) * !GNT# * FRAME# * IRDY# goto IDLE if ELSE ADDR -- Master starts a transaction. JRWR0B'$7$ RQWKHQH[WULVLQJHGJHRICLK 245 Revision 2.2 M_DATA -- Master transfers data. goto M_DATA if !FRAME# + FRAME# * TRDY# * STOP# * !Dev_to goto ADDR if (Request *!Step) * !GNT# * FRAME# * !TRDY# * STOP# * L-cycle * (Sa +FB2B_Ena) goto S_TAR if FRAME# * !STOP# + FRAME# * Dev_to goto TURN_AR if ELSE TURN_AR -- Transaction complete, do housekeeping. goto ADDR if (Request * !Step) * !GNT# goto DR_BUS if (Request * Step + !Request) * !GNT# goto IDLE if GNT# S_TAR -- Stop was asserted, do turn around cycle. goto DR_BUS if !GNT# goto IDLE if GNT# DR_BUS -- Bus parked at this agent or agent is using address stepping. goto DR_BUS if (Request * Step + !Request)* !GNT# goto ADDR if (Request * !Step) * !GNT# goto IDLE if GNT# Master LOCK Machine FREE -- LOCK# is not in use (not owned). goto FREE if LOCK# + !LOCK# * Own_lock goto BUSY if !LOCK# * !Own_lock BUSY -- LOCK# is currently being used (owned). goto FREE if LOCK# * FRAME# goto BUSY if !LOCK# + !FRAME# 246 Revision 2.2 The master of the transaction is responsible to drive the following signals: Enable the output buffers: OE[FRAME#] = ADDR + M_DATA OE[C/BE#[3::0]] = ADDR + M_DATA + DR_BUS if ADDR drive command if M_DATA drive byte enables if DR_BUS if (Step * Request) drive command else drive lines to a valid state OE[AD[31::00] = ADDR + M_DATA * (cmd=write) + DR_BUS if ADDR drive address if M_DATA drive data if DR_BUS if (Step * Request) drive address else drive lines to a valid state OE [LOCK#] = Own_lock * M_DATA + OE [LOCK#] * (!FRAME# + !LOCK#) OE[IRDY#] == [M_DATA + ADDR] OE[PAR] = OE[AD[31::00]] delayed by one clock OE[PERR#] = R_perr + R_perr (delayed by one clock) The following signals are generated from state and sampled (not asynchronous) bus signals. FRAME# = !( ADDR + M_DATA * !Dev_to * {[!Comp * (!To + !GNT#) * STOP#] + !Ready }) IRDY# = ![M_DATA * (Ready + Dev_to)] REQ# = ![(Request * !Lock_a + Request * Lock_a * FREE) *!(S_TAR * Last State was S_TAR)] LOCK# = Own_lock * ADDR + Target_abort + Master_abort + M_DATA * !STOP# * TRDY# * !Ldt + Own_lock * !Lock_a * Comp * M_DATA * FRAME# * !TRDY# PAR = even parity across AD[31::00] and C/BE#[3::0] lines. PERR# = R_perr Master_abort = (M_DATA * Dev_to) Target_abort = (!STOP# * DEVSEL# * M_DATA * FRAME# * !IRDY#) Own_lock = LOCK# * FRAME# * IRDY# * Request * !GNT# * Lock_a + Own_lock * (!FRAME# + !LOCK#) 247 Revision 2.2 Definitions These signals go between the bus sequencer and the backend. They provide information to the sequencer when to perform a transaction and provide information to the backend on how the transaction is proceeding. If a cycle is retried, the backend will make the correct modification to the affected registers and then indicate to the sequencer to perform another transaction. The bus sequencer does not remember that a transaction was retried or aborted but takes requests from the backend and performs the PCI transaction. Master_abort = The transaction was aborted by the master. (No DEVSEL#.) Target_abort = The transaction was aborted by the target. Step = Agent using address stepping (wait in the state until !Step). Request = Request pending. Comp = Current transaction in last data phase. L-cycle = Last cycle was a write. To = Master timeout has expired. Dev_to = Devsel timer has expired without DEVSEL# being asserted. Sa = Next transaction to same agent as previous transaction. Lock_a = Request is a locked operation. Ready = Ready to transfer data. Sp_cyc = Special Cycle command. Own_lock = This agent currently owns LOCK#. Ldt = Data was transferred during a LOCK operation. R_perr = Report parity error is a pulse one PCI clock in duration. FB2B_Ena = Fast Back-to-Back Enable (Configuration register bit). The master state machine has many options built in that may not be of interest to some implementations. Each state will be discussed indicating what affect certain options have on the equations. IDLE is where the master waits for a request to do a bus operation. The only option in this state is the term "Step". It may be removed from the equations if address stepping is not supported. All paths must be implemented. The path to DR_BUS is required to insure that the bus is not left floating for long periods. The master whose GNT# is asserted must go to the drive bus if its Request is not asserted. ADDR has no options and is used to drive the address and command on the bus. M_DATA is where data is transferred. If the master does not support fast back-to-back transactions, the path to the ADDR state is not required. The equations are correct from the protocol point of view. However, compilers may give errors when they check all possible combinations. For example, because of protocol, Comp cannot be asserted when FRAME# is deasserted. Comp indicates the master is in the last data phase, and FRAME# must be deasserted for this to be true. TURN_AR is where the master deasserts signals in preparation for tri-stating them. The path to ADDR may be removed if the master does not do back-to-back transactions. S_TAR could be implemented a number of ways. The state was chosen to clarify that "state" needs to be remembered when the target asserts STOP#. 248 Revision 2.2 DR_BUS is used when GNT# has been asserted, and the master either is not prepared to start a transaction (for address stepping) or has none pending. If address stepping is not implemented, then the equation in goto DR_BUS that has "Step" may be removed and the goto ADDR equation may also remove "Step". If LOCK# is not supported by the master, the FREE and BUSY states may be removed. These states are for the master to know the state of LOCK# when it desires to do a locked transaction. The state machine simply checks for LOCK# being asserted. Once asserted, it stays BUSY until FRAME# and LOCK# are both deasserted signifying that LOCK# is now free. 249 Revision 2.2 250 Revision 2.2 Appendix C Operating Rules 7KLVDSSHQGL[LVQRWDFRPSOHWHOLVWRIUXOHVRIWKHVSHFLILFDWLRQDQGVKRXOGQRWEHXVHG DVDUHSODFHPHQWIRUWKHVSHFLILFDWLRQ7KLVDSSHQGL[RQO\FRYHUVWKHEDVLFSURWRFRODQG UHTXLUHPHQWVFRQWDLQHGLQ&KDSWHU,WLVPHDQWWREHXVHGDVDQDLGRUTXLFNUHIHUHQFH WRWKHEDVLFUXOHVDQGUHODWLRQVKLSVRIWKHSURWRFRO When Signals are Stable 7KHIROORZLQJVLJQDOVDUHJXDUDQWHHGWREHVWDEOHRQDOOULVLQJHGJHVRICLK RQFH UHVHWKDVFRPSOHWHG LOCK# IRDY#TRDY#FRAME#DEVSEL#STOP# REQ#GNT#REQ64#ACK64#SERR# RQIDOOLQJHGJHRQO\ DQGPERR# $GGUHVV'DWDOLQHVDUHJXDUDQWHHGWREHVWDEOHDWWKHVSHFLILHGFORFNHGJHDVIROORZV D $GGUHVVAD[31::00]DUHVWDEOHUHJDUGOHVVRIZKHWKHUVRPHDUHORJLFDOGRQ W FDUHVRQWKHILUVWFORFNWKDWVDPSOHVFRAME#DVVHUWHG E $GGUHVVAD[63::32]DUHVWDEOHDQGYDOLGGXULQJWKHILUVWFORFNDIWHU REQ64# DVVHUWLRQZKHQELWDGGUHVVLQJLVEHLQJXVHG 6$& RUWKHILUVWWZRFORFNV DIWHUREQ64#DVVHUWLRQZKHQELWDGGUHVVLQJLVXVHG '$& :KHQREQ64# LVGHDVVHUWHGAD[63::32]DUHSXOOHGXSE\WKHFHQWUDOUHVRXUFH F 'DWDAD[31::00]DUHVWDEOHDQGYDOLGUHJDUGOHVVZKLFKE\WHODQHVDUHLQYROYHG LQWKHWUDQVDFWLRQRQUHDGVZKHQTRDY#LVDVVHUWHGDQGRQZULWHVZKHQIRDY# LVDVVHUWHG$WDQ\RWKHUWLPHWKH\PD\EHLQGHWHUPLQDWH7KHADOLQHVFDQQRW FKDQJHXQWLOWKHFXUUHQWGDWDSKDVHFRPSOHWHVRQFHIRDY#LVDVVHUWHGRQDZULWH WUDQVDFWLRQRUTRDY#LVDVVHUWHGRQDUHDGWUDQVDFWLRQ G 'DWDAD[63::32] DUHVWDEOHDQGYDOLGUHJDUGOHVVZKLFKE\WHODQHVDUHLQYROYHG LQWKHWUDQVDFWLRQZKHQACK64#LVDVVHUWHGDQGHLWKHUTRDY#LVDVVHUWHGRQ UHDGVRUIRDY#LVDVVHUWHGRQZULWHV$WDQ\RWKHUWLPHWKH\PD\EH LQGHWHUPLQDWH H 'DWD6SHFLDOF\FOHFRPPDQGAD[31::00]DUHVWDEOHDQGYDOLGUHJDUGOHVV ZKLFKE\WHODQHVDUHLQYROYHGLQWKHWUDQVDFWLRQZKHQIRDY#LVDVVHUWHG I 'RQRWJDWHDV\QFKURQRXVGDWDGLUHFWO\RQWR3&,ZKLOHIRDY#LVDVVHUWHGRQD ZULWHWUDQVDFWLRQDQGZKLOHTRDY#LVDVVHUWHGRQDUHDGWUDQVDFWLRQ 251 Revision 2.2 &RPPDQG%\WHHQDEOHVDUHJXDUDQWHHGWREHVWDEOHDWWKHVSHFLILHGFORFNHGJHDV IROORZV D &RPPDQGC/BE[3::0]# DUHVWDEOHDQGYDOLGWKHILUVWWLPHFRAME# LV VDPSOHGDVVHUWHGDQGFRQWDLQWKHFRPPDQGFRGHVC/BE[7::4]# DUHVWDEOHDQG YDOLGGXULQJWKHILUVWFORFNDIWHU REQ64#DVVHUWLRQZKHQELWDGGUHVVLQJLV EHLQJXVHG 6$& DQGDUHUHVHUYHGC/BE[7::4]# DUHVWDEOHDQGYDOLGGXULQJWKH ILUVWWZRFORFNVDIWHUREQ64#DVVHUWLRQZKHQELWDGGUHVVLQJLVXVHG '$& DQGFRQWDLQWKHDFWXDOEXVFRPPDQG:KHQREQ64#LVGHDVVHUWHGWKH C/BE[7::4]# DUHSXOOHGXSE\WKHFHQWUDOUHVRXUFH E %\WH(QDEOHVC/BE[3::0]# DUHVWDEOHDQGYDOLGWKHFORFNIROORZLQJWKH DGGUHVVSKDVHDQGHDFKFRPSOHWHGGDWDSKDVHDQGUHPDLQYDOLGHYHU\FORFN GXULQJWKHHQWLUHGDWDSKDVHUHJDUGOHVVLIZDLWVWDWHVDUHLQVHUWHGDQGLQGLFDWH ZKLFKE\WHODQHVFRQWDLQYDOLGGDWDC/BE[7::4]# KDYHWKHVDPHPHDQLQJDV C/BE[3::0]# H[FHSWWKH\FRYHUWKHXSSHUE\WHVZKHQREQ64#LVDVVHUWHG PARLVVWDEOHDQGYDOLGRQHFORFNIROORZLQJWKHYDOLGWLPHRIAD[31::00]PAR64 LVVWDEOHDQGYDOLGRQHFORFNIROORZLQJWKHYDOLGWLPHRIAD[63::32] IDSELLVRQO\VWDEOHDQGYDOLGWKHILUVWFORFNFRAME#LVDVVHUWHGZKHQWKHDFFHVV LVDFRQILJXUDWLRQFRPPDQGIDSELLVLQGHWHUPLQDWHDWDQ\RWKHUWLPH RST# INTA#INTB#INTC#DQGINTD#DUHQRWTXDOLILHGRUV\QFKURQRXV Master Signals $WUDQVDFWLRQVWDUWVZKHQFRAME#LVDVVHUWHGIRUWKHILUVWWLPH 7KHIROORZLQJJRYHUQFRAME#DQGIRDY#LQDOO3&,WUDQVDFWLRQV D FRAME#DQGLWVFRUUHVSRQGLQJIRDY#GHILQHWKH%XV\,GOHVWDWHRIWKHEXV ZKHQHLWKHULVDVVHUWHGWKHEXVLVEXV\ ZKHQERWKDUHGHDVVHUWHGWKHEXVLVLQ WKH,GOHVWDWH E 2QFHFRAME#KDVEHHQGHDVVHUWHGLWFDQQRWEHUHDVVHUWHGGXULQJWKHVDPH WUDQVDFWLRQ F FRAME#FDQQRWEHGHDVVHUWHGXQOHVVIRDY#LVDVVHUWHG IRDY#PXVWDOZD\V EHDVVHUWHGRQWKHILUVWFORFNHGJHWKDWFRAME#LVGHDVVHUWHG G 2QFHDPDVWHUKDVDVVHUWHGIRDY#LWFDQQRWFKDQJHIRDY#RUFRAME#XQWLO WKHFXUUHQWGDWDSKDVHFRPSOHWHV e. The master must deassert IRDY# the clock after the completion of the last data phase. :KHQFRAME#DQGIRDY# DUHGHDVVHUWHGWKHWUDQVDFWLRQKDVHQGHG :KHQWKHFXUUHQWWUDQVDFWLRQLVWHUPLQDWHGE\WKHWDUJHW STOP#DVVHUWHG WKH PDVWHUPXVWGHDVVHUWLWVREQ#VLJQDOEHIRUHUHSHDWLQJWKHWUDQVDFWLRQ$GHYLFH FRQWDLQLQJDVLQJOHVRXUFHRIPDVWHUDFWLYLW\PXVWGHDVVHUWREQ#IRUDPLQLPXPRI WZRFORFNV RQHEHLQJZKHQWKHEXVJRHVWRWKH,GOHVWDWH DWWKHHQGRIWKH WUDQVDFWLRQZKHUHSTOP#ZDVDVVHUWHG DQGHLWKHUWKHFORFNEHIRUHRUWKHFORFN DIWHUWKH,GOHVWDWH$GHYLFHFRQWDLQLQJPXOWLSOHVRXUFHVRIPDVWHUDFWLYLW\LV SHUPLWWHGWRDOORZHDFKVRXUFHWRXVHWKHEXVZLWKRXWGHDVVHUWLQJREQ#HYHQLIRQH RUPRUHVRXUFHVDUHWDUJHWWHUPLQDWHG+RZHYHUWKHGHYLFHPXVWGHDVVHUWREQ#IRU 252 Revision 2.2 WZRFORFNVRQHRIZKLFKZKLOHWKHEXVLV,GOHEHIRUHDQ\WUDQVDFWLRQWKDWZDVWDUJHW WHUPLQDWHGFDQEHUHSHDWHG $PDVWHUWKDWLVWDUJHWWHUPLQDWHGZLWK5HWU\PXVWXQFRQGLWLRQDOO\UHSHDWWKHVDPH UHTXHVWXQWLOLWFRPSOHWHV KRZHYHULWLVQRWUHTXLUHGWRUHSHDWWKHWUDQVDFWLRQZKHQ WHUPLQDWHGZLWK'LVFRQQHFW Target Signals 7KHIROORZLQJJHQHUDOUXOHVJRYHUQFRAME#IRDY#TRDY#DQGSTOP#ZKLOH WHUPLQDWLQJWUDQVDFWLRQV D $GDWDSKDVHFRPSOHWHVRQDQ\ULVLQJFORFNHGJHRQZKLFKIRDY#LVDVVHUWHG DQGHLWKHUSTOP#RUTRDY#LVDVVHUWHG E ,QGHSHQGHQWRIWKHVWDWHRISTOP#DGDWDWUDQVIHUWDNHVSODFHRQHYHU\ULVLQJ HGJHRIFORFNZKHUHERWKIRDY#DQGTRDY#DUHDVVHUWHG F 2QFHWKHWDUJHWDVVHUWVSTOP#LWPXVWNHHSSTOP#DVVHUWHGXQWLOFRAME#LV GHDVVHUWHGZKHUHXSRQLWPXVWGHDVVHUWSTOP# G 2QFHDWDUJHWKDVDVVHUWHGTRDY#RUSTOP#LWFDQQRWFKDQJHDEVSEL# TRDY#RUSTOP#XQWLOWKHFXUUHQWGDWDSKDVHFRPSOHWHV H :KHQHYHUSTOP#LVDVVHUWHGWKHPDVWHUPXVWGHDVVHUWFRAME#DVVRRQDV IRDY#FDQEHDVVHUWHG I ,IQRWDOUHDG\GHDVVHUWHGTRDY#STOP#DQGDEVSEL#PXVWEHGHDVVHUWHG WKHFORFNIROORZLQJWKHFRPSOHWLRQRIWKHODVWGDWDSKDVHDQGPXVWEHWULVWDWHG WKHQH[WFORFN $QDJHQWFODLPVWREHWKHWDUJHWRIWKHDFFHVVE\DVVHUWLQJDEVSEL# DEVSEL#PXVWEHDVVHUWHGZLWKRUSULRUWRWKHHGJHDWZKLFKWKHWDUJHWHQDEOHVLWV RXWSXWV TRDY#STOP#RU RQDUHDG ADOLQHV 2QFHDEVSEL#KDVEHHQDVVHUWHGLWFDQQRWEHGHDVVHUWHGXQWLOWKHODVWGDWDSKDVH KDVFRPSOHWHGH[FHSWWRVLJQDO7DUJHW$ERUW Data Phases 7KHVRXUFHRIWKHGDWDLVUHTXLUHGWRDVVHUWLWV[RDY#VLJQDOXQFRQGLWLRQDOO\ZKHQ GDWDLVYDOLG IRDY#RQDZULWHWUDQVDFWLRQTRDY#RQDUHDGWUDQVDFWLRQ 'DWDLVWUDQVIHUUHGEHWZHHQPDVWHUDQGWDUJHWRQHDFKFORFNHGJHIRUZKLFKERWK IRDY#DQGTRDY#DUHDVVHUWHG /DVWGDWDSKDVHFRPSOHWHVZKHQ D FRAME#LVGHDVVHUWHGDQGTRDY#LVDVVHUWHG QRUPDOWHUPLQDWLRQ RU E FRAME#LVGHDVVHUWHGDQGSTOP#LVDVVHUWHG WDUJHWWHUPLQDWLRQ RU F FRAME#LVGHDVVHUWHGDQGWKHGHYLFHVHOHFWWLPHUKDVH[SLUHG 0DVWHU$ERUW RU G DEVSEL#LVGHDVVHUWHGDQGSTOP#LVDVVHUWHG 7DUJHW$ERUW 253 Revision 2.2 &RPPLWWLQJWRFRPSOHWHDGDWDSKDVHRFFXUVZKHQWKHWDUJHWDVVHUWVHLWKHUTRDY# RUSTOP#7KHWDUJHWFRPPLWVWR D 7UDQVIHUGDWDLQWKHFXUUHQWGDWDSKDVHDQGFRQWLQXHWKHWUDQVDFWLRQ LIDEXUVW E\DVVHUWLQJTRDY#DQGQRWDVVHUWLQJSTOP# E 7UDQVIHUGDWDLQWKHFXUUHQWGDWDSKDVHDQGWHUPLQDWHWKHWUDQVDFWLRQE\DVVHUWLQJ ERWKTRDY#DQGSTOP# F 1RWWUDQVIHUGDWDLQWKHFXUUHQWGDWDSKDVHDQGWHUPLQDWHWKHWUDQVDFWLRQE\ DVVHUWLQJSTOP#DQGGHDVVHUWLQJTRDY# G 1RWWUDQVIHUGDWDLQWKHFXUUHQWGDWDSKDVHDQGWHUPLQDWHWKHWUDQVDFWLRQZLWKDQ HUURUFRQGLWLRQ 7DUJHW$ERUW E\DVVHUWLQJSTOP#DQGGHDVVHUWLQJTRDY#DQG DEVSEL# 7KHWDUJHWKDVQRWFRPPLWWHGWRFRPSOHWHWKHFXUUHQWGDWDSKDVHZKLOHTRDY#DQG STOP#DUHERWKGHDVVHUWHG7KHWDUJHWLVVLPSO\LQVHUWLQJZDLWVWDWHV Arbitration 7KHDJHQWLVSHUPLWWHGWRVWDUWDWUDQVDFWLRQRQO\LQWKHIROORZLQJWZRFDVHV D GNT#LVDVVHUWHGDQGWKHEXVLVLGOH FRAME#DQGIRDY#DUHGHDVVHUWHG E GNT#LVDVVHUWHGLQWKHODVWGDWDSKDVHRIDWUDQVDFWLRQDQGWKHDJHQWLVVWDUWLQJD QHZWUDQVDFWLRQXVLQJIDVWEDFNWREDFNWLPLQJ FRAME#LVGHDVVHUWHGDQG TRDY#RUSTOP#LVDVVHUWHGRUWKHWUDQVDFWLRQWHUPLQDWHVZLWK0DVWHU$ERUW 7KHDUELWHUPD\GHDVVHUWDQDJHQW VGNT#RQDQ\FORFN 2QFHDVVHUWHGGNT#PD\EHGHDVVHUWHGDFFRUGLQJWRWKHIROORZLQJUXOHV D ,IGNT#LVGHDVVHUWHGDQGFRAME#LVDVVHUWHGRQWKHVDPHFORFNWKHEXV WUDQVDFWLRQLVYDOLGDQGZLOOFRQWLQXH E 2QHGNT#FDQEHGHDVVHUWHGFRLQFLGHQWZLWKDQRWKHUGNT# EHLQJDVVHUWHGLI WKHEXVLVQRWLQWKH,GOHVWDWH2WKHUZLVHDRQHFORFNGHOD\LVUHTXLUHGEHWZHHQ WKHGHDVVHUWLRQRIDGNT#DQGWKHDVVHUWLRQRIWKHQH[WGNT#RUHOVHWKHUHPD\ EHFRQWHQWLRQRQWKHADOLQHVDQGPAR F :KLOHFRAME#LVGHDVVHUWHGGNT#PD\EHGHDVVHUWHGDWDQ\WLPHLQRUGHUWR VHUYLFHDKLJKHUSULRULW\ PDVWHURULQUHVSRQVHWRWKHDVVRFLDWHGREQ#EHLQJ GHDVVHUWHG :KHQWKHDUELWHUDVVHUWVDQDJHQW VGNT#DQGWKHEXVLVLQWKH,GOHVWDWHWKDWDJHQW PXVWHQDEOHLWVAD[31::00]C/BE[3::0]#DQG RQHFORFNODWHU PARRXWSXWEXIIHUV ZLWKLQHLJKW3&,FORFNV UHTXLUHG ZKLOHWZRWKUHHFORFNVLVUHFRPPHQGHG Latency 25. All targets are required to complete the initial data phase of a transaction (read or write) within 16 clocks from the assertion of FRAME#. Host bus bridges have an exception (refer to Section 3.5.1.1.). 56 Higher priority here does not imply a fixed priority arbitration, but refers to the agent that would win arbitration at a given instant in time. 254 Revision 2.2 26. The target is required to complete a subsequent data phase within eight clocks from the completion of the previous data phase. 27. A master is required to assert its IRDY# within eight clocks for any given data phase (initial and subsequent). Device Selection 28. A target must do a full decode before driving/asserting DEVSEL# or any other target response signal. 29. A target must assert DEVSEL# (claim the transaction) before it is allowed to issue any other target response. 30. In all cases except Target-Abort, once a target asserts DEVSEL# it must not deassert DEVSEL# until FRAME# is deasserted (IRDY# is asserted) and the last data phase has completed. 31. A PCI device is a target of a Type 0 configuration transaction (read or write) only if its IDSEL is asserted, and AD[1::0] are “00” during the address phase of the command. Parity 3DULW\LVJHQHUDWHGDFFRUGLQJWRWKHIROORZLQJUXOHV D 3DULW\LVFDOFXODWHGWKHVDPHRQDOO3&,WUDQVDFWLRQVUHJDUGOHVVRIWKHW\SHRU IRUP E 7KHQXPEHURI³´VRQAD[31::00]C/BE[3::0]#DQGPARHTXDOVDQHYHQ QXPEHU F 7KHQXPEHURI³´VRQAD[63::32]C/BE[7::4]#DQGPAR64HTXDOVDQHYHQ QXPEHU G *HQHUDWLQJSDULW\LVQRWRSWLRQDO LWPXVWEHGRQHE\DOO3&,FRPSOLDQWGHYLFHV 33. Only the master of a corrupted data transfer is allowed to report parity errors to software using mechanisms other than PERR# (i.e., requesting an interrupt or asserting SERR#). In some cases, the master delegates this responsibility to a PCI- to-PCI bridge handling posted memory write data. See the PCI-to-PCI Bridge Architecture Specification for details. 255 Revision 2.2 256 Revision 2.2 Appendix D Class Codes 7KLVDSSHQGL[GHVFULEHVWKHFXUUHQW&ODVV&RGHHQFRGLQJV7KLVOLVWPD\EHHQKDQFHGDW DQ\WLPH7KH3&,6,*ZHESDJHVFRQWDLQWKHODWHVWYHUVLRQ&RPSDQLHVZLVKLQJWR GHILQHDQHZHQFRGLQJVKRXOGFRQWDFWWKH3&,6,*$OOXQVSHFLILHGYDOXHVDUHUHVHUYHG IRU6,*DVVLJQPHQW Base Class Meaning 00h Device was built before Class Code definitions were finalized 01h Mass storage controller 02h Network controller 03h Display controller 04h Multimedia device 05h Memory controller 06h Bridge device 07h Simple communication controllers 08h Base system peripherals 09h Input devices 0Ah Docking stations 0Bh Processors 0Ch Serial bus controllers 0Dh Wireless controller 0Eh Intelligent I/O controllers 0Fh Satellite communication controllers 10h Encryption/Decryption controllers 11h Data acquisition and signal processing controllers 12h - FEh Reserved FFh Device does not fit in any defined classes 257 Revision 2.2 %DVH&ODVVK 7KLVEDVHFODVVLVGHILQHGWRSURYLGHEDFNZDUGFRPSDWLELOLW\IRUGHYLFHVWKDWZHUHEXLOW EHIRUHWKH&ODVV&RGHILHOGZDVGHILQHG1RQHZGHYLFHVVKRXOGXVHWKLVYDOXHDQG H[LVWLQJGHYLFHVVKRXOGVZLWFKWRDPRUHDSSURSULDWHYDOXHLISRVVLEOH )RUFODVVFRGHVZLWKWKLVEDVHFODVVYDOXHWKHUHDUHWZRGHILQHGYDOXHVIRUWKHUHPDLQLQJ ILHOGVDVVKRZQLQWKHWDEOHEHORZ$OORWKHUYDOXHVDUHUHVHUYHG Base Class Sub-Class Interface Meaning 00h 00h All currently implemented devices 00h except VGA-compatible devices 01h 00h VGA-compatible device %DVH&ODVVK 7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRIPDVVVWRUDJHFRQWUROOHUV6HYHUDOVXEFODVV YDOXHVDUHGHILQHG7KH,'(FRQWUROOHUFODVVLVWKHRQO\RQHWKDWKDVDVSHFLILFUHJLVWHU OHYHOSURJUDPPLQJLQWHUIDFHGHILQHG Base Class Sub-Class Interface Meaning 00h 00h SCSI bus controller 01h xxh IDE controller (see below) 01h 02h 00h Floppy disk controller 03h 00h IPI bus controller 04h 00h RAID controller 80h 00h Other mass storage controller )LJXUH' 3URJUDPPLQJ,QWHUIDFH%\WH/D\RXWIRU,'(&RQWUROOHU&ODVV&RGH 7KH3&,6,*GRFXPHQW3&,,'(&RQWUROOHU6SHFLILFDWLRQFRPSOHWHO\GHVFULEHVWKH OD\RXWDQGPHDQLQJRIELWVWKURXJKLQWKH3URJUDPPLQJ,QWHUIDFHE\WH7KH GRFXPHQW%XV0DVWHU3URJUDPPLQJ,QWHUIDFHIRU,'($7$&RQWUROOHUVGHVFULEHVWKH PHDQLQJRIELWLQWKH3URJUDPPLQJ,QWHUIDFHE\WH7KLVGRFXPHQWFDQEHREWDLQHGYLD )$;E\FDOOLQJ DQGUHTXHVWLQJGRFXPHQW 258 Revision 2.2 %DVH&ODVVK 7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRIQHWZRUNFRQWUROOHUV6HYHUDOVXEFODVVYDOXHV DUHGHILQHG7KHUHDUHQRUHJLVWHUOHYHOSURJUDPPLQJLQWHUIDFHVGHILQHG Base Class Sub-Class Interface Meaning 00h 00h Ethernet controller 02h 01h 00h Token Ring controller 02h 00h FDDI controller 03h 00h ATM controller 04h 00h ISDN controller 80h 00h Other network controller %DVH&ODVVK 7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRIGLVSOD\FRQWUROOHUV)RU9*$GHYLFHV 6XE &ODVVK WKHSURJUDPPLQJLQWHUIDFHE\WHLVGLYLGHGLQWRDELWILHOGWKDWLGHQWLILHV DGGLWLRQDOYLGHRFRQWUROOHUFRPSDWLELOLWLHV$GHYLFHFDQVXSSRUWPXOWLSOHLQWHUIDFHVE\ XVLQJWKHELWPDSWRLQGLFDWHZKLFKLQWHUIDFHVDUHVXSSRUWHG)RUWKH;*$GHYLFHV 6XE &ODVVK RQO\WKHVWDQGDUG;*$LQWHUIDFHLVGHILQHG6XE&ODVVKLVIRUFRQWUROOHUV WKDWKDYHKDUGZDUHVXSSRUWIRU'RSHUDWLRQVDQGDUHQRW9*$FRPSDWLEOH Base Class Sub-Class Interface Meaning 00000000b VGA-compatible controller. Memory addresses 0A0000h through 0BFFFFh. I/O addresses 3B0h to 3BBh and 3C0h to 3DFh and all aliases of these addresses. 03h 00h 00000001b 8514-compatible controller -- 2E8h and its aliases, 2EAh-2EFh 01h 00h XGA controller 02h 00h 3D controller 80h 00h Other display controller %DVH&ODVVK 7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRIPXOWLPHGLDGHYLFHV6HYHUDOVXEFODVVYDOXHV DUHGHILQHG7KHUHDUHQRUHJLVWHUOHYHOSURJUDPPLQJLQWHUIDFHVGHILQHG Base Class Sub-Class Interface Meaning 00h 00h Video device 01h 00h Audio device 04h 02h 00h Computer telephony device 80h 00h Other multimedia device 259 Revision 2.2 %DVH&ODVVK 7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRIPHPRU\FRQWUROOHUV UHIHUWR6HFWLRQ 6HYHUDOVXEFODVVYDOXHVDUHGHILQHG7KHUHDUHQRUHJLVWHUOHYHOSURJUDPPLQJLQWHUIDFHV GHILQHG Base Class Sub-Class Interface Meaning 00h 00h RAM 05h 01h 00h Flash 80h 00h Other memory controller %DVH&ODVVK 7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRIEULGJHGHYLFHV$3&,EULGJHLVDQ\3&,GHYLFH WKDWPDSV3&,UHVRXUFHV PHPRU\RU,2 IURPRQHVLGHRIWKHGHYLFHWRWKHRWKHU 6HYHUDOVXEFODVVYDOXHVDUHGHILQHG Base Class Sub-Class Interface Meaning 00h 00h Host bridge 01h 00h ISA bridge 02h 00h EISA bridge 06h 03h 00h MCA bridge 00h PCI-to-PCI bridge 04h 01h Subtractive Decode PCI-to-PCI bridge. This interface code identifies the PCI-to-PCI bridge as a device that supports subtractive decoding in addition to all the currently defined functions of a PCI-to-PCI bridge. 05h 00h PCMCIA bridge 06h 00h NuBus bridge 07h 00h CardBus bridge 08h xxh RACEway bridge (see below) 80h 00h Other bridge device 5$&(ZD\LVDQ$16,VWDQGDUG $16,9,7$ VZLWFKLQJIDEULF)RUWKH 3URJUDPPLQJ,QWHUIDFHELWV> @DUHUHVHUYHGUHDGRQO\DQGUHWXUQ]HURV%LWGHILQHV WKHRSHUDWLRQPRGHDQGLVUHDGRQO\ 7UDQVSDUHQWPRGH (QGSRLQWPRGH 260 Revision 2.2 Base Class 07h 7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRIVLPSOHFRPPXQLFDWLRQVFRQWUROOHUV6HYHUDO VXEFODVVYDOXHVDUHGHILQHGVRPHRIWKHVHKDYLQJVSHFLILFZHOONQRZQUHJLVWHUOHYHO SURJUDPPLQJLQWHUIDFHV Base Class Sub-Class Interface Meaning 00h Generic XT-compatible serial controller 00h 01h 16450-compatible serial controller 02h 16550-compatible serial controller 03h 16650-compatible serial controller 04h 16750-compatible serial controller 05h 16850-compatible serial controller 06h 16950-compatible serial controller 00h Parallel port 01h Bi-directional parallel port 01h 02h ECP 1.X compliant parallel port 03h IEEE1284 controller FEh IEEE1284 target device (not a controller) 07h 02h 00h Multiport serial controller 00h Generic modem 01h Hayes compatible modem, 16450- compatible interface (see below) 03h 02h Hayes compatible modem, 16550- compatible interface (see below) 03h Hayes compatible modem, 16650- compatible interface (see below) 04h Hayes compatible modem, 16750- compatible interface (see below) 80h 00h Other communications device )RU+D\HVFRPSDWLEOHPRGHPVWKHILUVWEDVHDGGUHVVUHJLVWHU DWRIIVHWK PDSVWKH DSSURSULDWHFRPSDWLEOH LHHWF UHJLVWHUVHWIRUWKHVHULDOFRQWUROOHUDW WKHEHJLQQLQJRIWKHPDSSHGVSDFH1RWHWKDWWKHVHUHJLVWHUVFDQEHHLWKHUPHPRU\RU ,2PDSSHGGHSHQGLQJZKDWNLQGRI%$5LVXVHG 261 Revision 2.2 %DVH&ODVVK 7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRIJHQHULFV\VWHPSHULSKHUDOV6HYHUDOVXEFODVV YDOXHVDUHGHILQHGPRVWRIWKHVHKDYLQJDVSHFLILFZHOONQRZQUHJLVWHUOHYHO SURJUDPPLQJLQWHUIDFH Base Class Sub-Class Interface Meaning 00h Generic 8259 PIC 01h ISA PIC 02h EISA PIC 00h 10h I/O APIC interrupt controller (see below) 20h I/O(x) APIC interrupt controller 00h Generic 8237 DMA controller 01h 01h ISA DMA controller 08h 02h EISA DMA controller 00h Generic 8254 system timer 02h 01h ISA system timer. 02h EISA system timers (two timers) 03h 00h Generic RTC controller 01h ISA RTC controller 04h 00h Generic PCI Hot-Plug controller 80h 00h Other system peripheral )RU,2$3,&,QWHUUXSW&RQWUROOHUWKH%DVH$GGUHVV5HJLVWHUDWRIIVHW[LVXVHGWR UHTXHVWDPLQLPXPRIE\WHVRIQRQSUHIHWFKDEOHPHPRU\7ZRUHJLVWHUVZLWKLQWKDW VSDFHDUHORFDWHGDW%DVH[ ,26HOHFW5HJLVWHU DQG%DVH[ ,2:LQGRZ 5HJLVWHU )RUDIXOOGHVFULSWLRQRIWKHXVHRIWKHVHUHJLVWHUVUHIHUWRWKHGDWDVKHHWIRU WKH,QWHO(%LQWKH3&,VHW(,6$%ULGJH'DWDERRN 262 Revision 2.2 %DVH&ODVV K 7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRILQSXWGHYLFHV6HYHUDOVXEFODVVYDOXHVDUH GHILQHG$UHJLVWHUOHYHOSURJUDPPLQJLQWHUIDFHLVGHILQHGIRUJDPHSRUWFRQWUROOHUV Base Class Sub-Class Interface Meaning 00h 00h Keyboard controller 01h 00h Digitizer (pen) 02h 00h Mouse controller 09h 03h 00h Scanner controller 04h 00h Gameport controller (generic) 10h Gameport controller (see below) 80h 00h Other input controller $JDPHSRUWFRQWUROOHUZLWKD3URJUDPPLQJ,QWHUIDFH KLQGLFDWHVWKDWDQ\%DVH $GGUHVVUHJLVWHUVLQWKLVIXQFWLRQWKDWUHTXHVWDVVLJQ,2DGGUHVVVSDFHWKHUHJLVWHUVLQ WKDW,2VSDFHFRQIRUPWRWKHVWDQGDUGµOHJDF\¶JDPHSRUWV7KHE\WHDWRIIVHWKLQDQ ,2UHJLRQEHKDYHVDVDOHJDF\JDPHSRUWLQWHUIDFHZKHUHUHDGVWRWKHE\WHUHWXUQ MR\VWLFNJDPHSDGLQIRUPDWLRQDQGZULWHVWRWKHE\WHVWDUWWKH5&WLPHU7KHE\WHDW RIIVHWKLVDQDOLDVRIWKHE\WHDWRIIVHWK$OORWKHUE\WHVLQDQ,2UHJLRQDUH XQVSHFLILHGDQGFDQEHXVHGLQYHQGRUXQLTXHZD\V %DVH&ODVV$K 7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRIGRFNLQJVWDWLRQV1RVSHFLILFUHJLVWHUOHYHO SURJUDPPLQJLQWHUIDFHVDUHGHILQHG Base Class Sub-Class Interface Meaning 0Ah 00h 00h Generic docking station 80h 00h Other type of docking station %DVH&ODVV%K 7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRISURFHVVRUV6HYHUDOVXEFODVVYDOXHVDUH GHILQHGFRUUHVSRQGLQJWRGLIIHUHQWSURFHVVRUW\SHVRULQVWUXFWLRQVHWV7KHUHDUHQR VSHFLILFUHJLVWHUOHYHOSURJUDPPLQJLQWHUIDFHVGHILQHG Base Class Sub-Class Interface Meaning 00h 00h 386 01h 00h 486 0Bh 02h 00h Pentium 10h 00h Alpha 20h 00h PowerPC 30h 00h MIPS 40h 00h Co-processor 263 Revision 2.2 %DVH&ODVV&K 7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRIVHULDOEXVFRQWUROOHUV6HYHUDOVXEFODVVYDOXHV DUHGHILQHG7KHUHDUHVSHFLILFUHJLVWHUOHYHOSURJUDPPLQJLQWHUIDFHVGHILQHGIRU 8QLYHUVDO6HULDO%XVFRQWUROOHUVDQG,((( FRQWUROOHUV Base Class Sub-Class Interface Meaning 00 00h IEEE 1394 (FireWire) 10h IEEE 1394 following the 1394 OpenHCI specification 01h 00h ACCESS.bus 02h 00h SSA 00h Universal Serial Bus (USB) following the Universal Host Controller Specification 0Ch 03h 10h Universal Serial Bus (USB) following the Open Host Controller Specification 80h Universal Serial Bus with no specific programming interface FEh USB device (not host controller) 04h 00h Fibre Channel 05h 00h SMBus (System Management Bus) %DVH&ODVV'K 7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRIZLUHOHVVFRQWUROOHUV6HYHUDOVXEFODVVYDOXHV DUHGHILQHG7KHUHDUHQRVSHFLILFUHJLVWHUOHYHOSURJUDPPLQJLQWHUIDFHVGHILQHG Base Class Sub-Class Interface Meaning 00 00h iRDA compatible controller 0Dh 01h 00h Consumer IR controller 10h 00h RF controller 80h 00h Other type of wireless controller %DVH&ODVV(K 7KLVEDVHFODVVLVGHILQHGIRULQWHOOLJHQW,2FRQWUROOHUV7KHSULPDU\FKDUDFWHULVWLFRI WKLVEDVHFODVVLVWKDWWKH,2IXQFWLRQSURYLGHGIROORZVVRPHVRUWRIJHQHULFGHILQLWLRQ IRUDQ,2FRQWUROOHU Base Class Sub-Class Interface Meaning 0Eh 00 xxh Intelligent I/O (I2O) Architecture Specification 1.0 00h Message FIFO at offset 040h 7KHVSHFLILFDWLRQIRU,QWHOOLJHQW,2$UFKLWHFWXUH,2FDQEHGRZQORDGHGIURP IWSLQWHOFRPSXE,$/LR 264 Revision 2.2 %DVH&ODVV)K 7KLVEDVHFODVVLVGHILQHGIRUVDWHOOLWHFRPPXQLFDWLRQFRQWUROOHUV&RQWUROOHUVRIWKLV W\SHDUHXVHGWRFRPPXQLFDWHZLWKVDWHOOLWHV Base Class Sub-Class Interface Meaning 01h 00h TV 0Fh 02h 00h Audio 03h 00h Voice 04h 00h Data %DVH&ODVVK 7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRIHQFU\SWLRQDQGGHFU\SWLRQFRQWUROOHUV6HYHUDO VXEFODVVYDOXHVDUHGHILQHG7KHUHDUHQRUHJLVWHUOHYHOLQWHUIDFHVGHILQHG Base Class Sub-Class Interface Meaning 00h 00h 1HWZRUNDQGFRPSXWLQJHQGHFU\SWLRQ 10h 10h 00h (QWHUWDLQPHQWHQGHFU\SWLRQ 80h 00h Other en/decryption %DVH&ODVVK 7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRIGDWDDFTXLVLWLRQDQGVLJQDOSURFHVVLQJ FRQWUROOHUV6HYHUDOVXEFODVVYDOXHVDUHGHILQHG7KHUHDUHQRUHJLVWHUOHYHOLQWHUIDFHV GHILQHG Base Class Sub-Class Interface Meaning 00h 00h '3,2PRGXOHV 11h 80h 00h 2WKHUGDWDDFTXLVLWLRQVLJQDO SURFHVVLQJFRQWUROOHUV 265 Revision 2.2 266 Revision 2.2 Appendix E System Transaction Ordering Many programming tasks, especially those controlling intelligent peripheral devices common in PCI systems, require specific events to occur in a specific order. If the events generated by the program do not occur in the hardware in the order intended by the software, a peripheral device may behave in a totally unexpected way. PCI transaction ordering rules are written to give hardware the flexibility to optimize performance by rearranging certain events that do not affect device operation, yet strictly enforce the order of events that do affect device operation. One performance optimization that PCI systems are allowed to do is the posting of memory write transactions. Posting means the transaction is captured by an intermediate agent; e.g., a bridge from one bus to another, so that the transaction completes at the source before it actually completes at the intended destination. This allows the source to proceed with the next operation while the transaction is still making its way through the system to its ultimate destination. While posting improves system performance, it complicates event ordering. Since the source of a write transaction proceeds before the write actually reaches its destination, other events that the programmer intended to happen after the write may happen before the write. Many of the PCI ordering rules focus on posting buffers requiring them to be flushed to keep this situation from causing problems. If the buffer flushing rules are not written carefully, however, deadlock can occur. The rest of the PCI transaction ordering rules prevent the system buses from deadlocking when posting buffers must be flushed. Simple devices do not post outbound transactions. Therefore, their requirements are much simpler than those presented here for bridges. Refer to Section 3.2.5.1. for the requirements for simple devices. The focus of the remainder of this appendix is on a PCI-to-PCI bridge. This allows the same terminology to be used to describe a transaction initiated on either interface and is easier to understand. To apply these rules to other bridges, replace a PCI transaction type with its equivalent transaction type of the host bus (or other specific bus). While the discussion focuses on a PCI-to-PCI bridge, the concepts can be applied to all bridges. 267 Revision 2.2 The ordering rules for a specific implementation may vary. This appendix covers the rules for all accesses traversing a bridge assuming that the bridge can handle multiple transactions at the same time in each direction. Simpler implementations are possible but are not discussed here. E.1 Producer - Consumer Ordering Model The Producer - Consumer model for data movement between two masters is an example of a system that would require this kind of ordering. In this model, one agent, the Producer, produces or creates the data and another agent, the Consumer, consumes or uses the data. The Producer and Consumer communicate between each other via a flag and a status element. The Producer sets the flag when all the data has been written and then waits for a completion status code. The Consumer waits until it finds the flag set, then it resets the flag, consumes the data, and writes the completion status code. When the Producer finds the completion status code, it clears it and the sequence repeats. Obviously, the order in which the flag and data are written is important. If some of the Producer’s data writes were posted, then without buffer-flushing rules it might be possible for the Consumer to see the flag set before the data writes had completed. The PCI ordering rules are written such that no matter which writes are posted, the Consumer can never see the flag set and read the data until the data writes are finished. This specification refers to this condition as “having a consistent view of data.” Notice that if the Consumer were to pass information back to the Producer in addition to the status code, the order of writing this additional information and the status code becomes important, just as it was for the data and flag. In practice, the flag might be a doorbell register in a device or it might be a main- memory pointer to data located somewhere else in memory. And the Consumer might signal the Producer using an interrupt or another doorbell register, rather than having the Producer poll the status element. But in all cases, the basic need remains the same; the Producer’s writes to the data area must complete before the Consumer observes that the flag has been set and reads the data. This model allows the data, the flag, the status element, the Producer, and the Consumer to reside anywhere in the system. Each of these can reside on different buses and the ordering rules maintain a consistent view of the data. For example, in Figure E-1, the agent producing the data, the flag, and the status element reside on Bus 1, while the actual data and the Consumer of the data both reside on Bus 0. The Producer writes the last data and the PCI-to-PCI bridge between Bus 0 and 1 completes the access by posting the data. The Producer of the data then writes the flag changing its status to indicate that the data is now valid for the Consumer to use. In this case, the flag has been set before the final datum has actually been written (to the final destination). PCI ordering rules require that when the Consumer of the data reads the flag (to determine if the data is valid), the read will cause the PCI-to-PCI bridge to flush the posted write data to the final destination before completing the read. When the Consumer determines the data is valid by checking the flag, the data is actually at the final destination. 268 Revision 2.2 Consumer Data PCI Bus 0 PCI-PCI Bridge PCI Bus 1 Producer Flag Status )LJXUH( ([DPSOH3URGXFHU&RQVXPHU0RGHO The ordering rules lead to the same results regardless of where the Producer, the Consumer, the data, the flag, and the status element actually reside. The data is always at the final destination before the Consumer can read the flag. This is true even when all five reside on different bus segments of the system. In one configuration, the data will be forced to the final destination when the Consumer reads the flag. In another configuration, the read of the flag occurs without forcing the data to its final destination; however, the read request of the actual data pushes the final datum to the final destination before completing the read. A system may have multiple Producer-Consumer pairs operating simultaneously, with different data - flag-status sets located all around the system. But since only one Producer can write to a single data-flag set, there are no ordering requirements between different masters. Writes from one master on one bus may occur in one order on one bus, with respect to another master’s writes, and occur in another order on another bus. In this case, the rules allow for some writes to be rearranged; for example, an agent on Bus 1 may see Transaction A from a master on Bus 1 complete first, followed by Transaction B from another master on Bus 0. An agent on Bus 0 may see Transaction B complete first followed by Transaction A. Even though the actual transactions complete in a different order, this causes no problem since the different masters must be addressing different data-flag sets. E.2. Summary of PCI Ordering Requirements Following is a summary of the general PCI ordering requirements presented in Section 3.2.5. These requirements apply to all PCI transactions, whether they are using Delayed Transactions or not. General Requirements 1. The order of a transaction is determined when it completes. Transactions terminated with Retry are only requests and can be handled by the system in any order. 269 Revision 2.2 2. Memory writes can be posted in both directions in a bridge. I/O and Configuration writes are not posted. (I/O writes can be posted in the Host Bridge, but some restrictions apply.) Read transactions (Memory, I/O, or Configuration) are not posted. 3. Posted memory writes moving in the same direction through a bridge will complete on the destination bus in the same order they complete on the originating bus. 4. Write transactions crossing a bridge in opposite directions have no ordering relationship. 5. A read transaction must push ahead of it through the bridge any posted writes originating on the same side of the bridge and posted before the read. Before the read transaction can complete on its originating bus, it must pull out of the bridge any posted writes that originated on the opposite side and were posted before the read command completes on the read-destination bus. 6. A bridge can never make the acceptance (posting) of a memory write transaction as a target contingent on the prior completion of a non-locked transaction as a master on the same bus. Otherwise, a deadlock may occur. Bridges are allowed to refuse to accept a memory write for temporary conditions which are guaranteed to be resolved with time. A bridge can make the acceptance of a memory write transaction as a target contingent on the prior completion of locked transaction as a master only if the bridge has already established a locked operation with its intended target. The following is a summary of the PCI ordering requirements specific to Delayed Transactions, presented in Section 3.3.3.3. Delayed Transaction Requirements 1. A target that uses Delayed Transactions may be designed to have any number of Delayed Transactions outstanding at one time. 2. Only non-posted transactions can be handled as Delayed Transactions. 3. A master must repeat any transaction terminated with Retry since the target may be using a Delayed Transaction. 4. Once a Delayed Request has been attempted on the destination bus, it must continue to be repeated until it completes on the destination bus. Before it is attempted on the destination bus, it is only a request and may be discarded at any time. 5. A Delayed Completion can only be discarded when it is a read from a prefetchable region, or if the master has not repeated the transaction in 2 15 clocks. 6. A target must accept all memory writes addressed to it, even while completing a request using Delayed Transaction termination. 7. Delayed Requests and Delayed Completions are not required to be kept in their original order with respect to themselves or each other. 8. Only a Delayed Write Completion can pass a Posted Memory Write. A Posted Memory Write must be given an opportunity to pass everything except another Posted Memory Write. 270 Revision 2.2 9. A single master may have any number of outstanding requests terminated with Retry. However, if a master requires one transaction to be completed before another, it cannot attempt the second one on PCI until the first one has completed. E.3. Ordering of Requests A transaction is considered to be a request when it is presented on the bus. When the transaction is terminated with Retry, it is still considered a request. A transaction becomes complete or a completion when data actually transfers (or is terminated with Master-Abort or Target-Abort). The following discussion will refer to transactions as being a request or completion depending on the success of the transaction. A transaction that is terminated with Retry has no ordering relationship with any other access. Ordering of accesses is only determined when an access completes (transfers data). For example, four masters A, B, C, and D reside on the same bus segment and all desire to generate an access on the bus. For this example, each agent can only request a single transaction at a time and will not request another until the current access completes. The order in which transactions complete are based on the algorithm of the arbiter and the response of the target, not the order in which each agent’s REQ# signal was asserted. Assuming that some requests are terminated with Retry, the order in which they complete is independent of the order they were first requested. By changing the arbiter’s algorithm, the completion of the transactions can be any sequence (i.e., A, B, C, and then D or B, D, C, and then A, and so on). Because the arbiter can change the order in which transactions are requested on the bus, and, therefore, the completion of such transactions, the system is allowed to complete them in any order it desires. This means that a request from any agent has no relationship with a request from any other agent. The only exception to this rule is when LOCK# is used, which is described later. Take the same four masters (A, B, C, and D) used in the previous paragraph and integrate them onto a single piece of silicon (a multi-function device). For a multi- function device, the four masters operate independent of each other, and each function only presents a single request on the bus for this discussion. The order their requests complete is the same as if they where separate agents and not a multi-function device, which is based on the arbitration algorithm. Therefore, multiple requests from a single agent may complete in any order, since they have no relationship to each other. Another device, not a multi-function device, has multiple internal resources that can generate transactions on the bus. If these different sources have some ordering relationship, then the device must ensure that only a single request is presented on the bus at any one time. The agent must not attempt a subsequent transaction until the previous transaction completes. For example, a device has two transactions to complete on the bus, Transaction A and Transaction B and A must complete before B to preserve internal ordering requirements. In this case, the master cannot attempt B until A has completed. The following example would produce inconsistent results if it were allowed to occur. Transaction A is to a flag that covers data, and Transaction B accesses the actual data covered by the flag. Transaction A is terminated with Retry, because the addressed target is currently busy or resides behind a bridge. Transaction B is to a target that is ready and will complete the request immediately. Consider what happens when these 271 Revision 2.2 two transactions are allowed to complete in the wrong order. If the master allows Transaction B to be presented on the bus after Transaction A was terminated with Retry, Transaction B can complete before Transaction A. In this case, the data may be accessed before it is actually valid. The responsibility to prevent this from occurring rests with the master, which must block Transaction B from being attempted on the bus until Transaction A completes. A master presenting multiple transactions on the bus must ensure that subsequent requests (that have some relationship to a previous request) are not presented on the bus until the previous request has completed. The system is allowed to complete multiple requests from the same agent in any order. When a master allows multiple requests to be presented on the bus without completing, it must repeat each request independent of how any of the other requests complete. E.4. Ordering of Delayed Transactions A Delayed Transaction progresses to completion in three phases: 1. Request by the master 2. Completion of the request by the target 3. Completion of the transaction by the master During the first phase, the master generates a transaction on the bus, the target decodes the access, latches the information required to complete the access, and terminates the request with Retry. The latched request information is referred to as a Delayed Request. During the second phase, the target independently completes the request on the destination bus using the latched information from the Delayed Request. The result of completing the Delayed Request on the destination bus produces a Delayed Completion, which consists of the latched information of the Delayed Request and the completion status (and data if a read request). During the third phase, the master successfully re- arbitrates for the bus and reissues the original request. The target decodes the request and gives the master the completion status (and data if a read request). At this point, the Delayed Completion is retired and the transaction has completed. The number of simultaneous Delayed Transactions a bridge is capable of handling is limited by the implementation and not by the architecture. Table E-1 represents the ordering rules when a bridge in the system is capable of allowing multiple transactions to proceed in each direction at the same time. Each column of the table represents an access that was accepted by the bridge earlier, while each row represents a transaction just accepted. The contents of the box indicate what ordering relationship the second transaction must have to the first. PMW - Posted Memory Write is a transaction that has completed on the originating bus before completing on the destination bus and can only occur for Memory Write and Memory Write and Invalidate commands. DRR - Delayed Read Request is a transaction that must complete on the destination bus before completing on the originating bus and can be an I/O Read, Configuration Read, Memory Read, Memory Read Line, or Memory Read Multiple commands. As mentioned earlier, once a request has been attempted on the destination bus, it must continue to be repeated until it completes on the destination bus. Before it is attempted 272 Revision 2.2 on the destination bus the DRR is only a request and may be discarded at any time to prevent deadlock or improve performance, since the master must repeat the request later. DWR - Delayed Write Request is a transaction that must complete on the destination bus before completing on the originating bus and can be an I/O Write or Configuration Write command. Note: Memory Write and Memory Write and Invalidate commands must be posted (PMW) and not be completed as DWR. As mentioned earlier, once a request has been attempted on the destination bus, it must continue to be repeated until it completes. Before it is attempted on the destination bus, the DWR is only a request and may be discarded at any time to prevent deadlock or improve performance, since the master must repeat the request later. DRC - Delayed Read Completion is a transaction that has completed on the destination bus and is now moving toward the originating bus to complete. The DRC contains the data requested by the master and the status of the target (normal, Master-Abort, Target- Abort, parity error, etc.). DWC - Delayed Write Completion is a transaction that has completed on the destination bus and is now moving toward the originating bus. The DWC does not contain the data of the access, but only status of how it completed (Normal, Master-Abort, Target-Abort, parity error, etc.). The write data has been written to the specified target. No - indicates that the subsequent transaction is not allowed to complete before the previous transaction to preserve ordering in the system. The four No boxes found in column 2 prevent PMW data from being passed by other accesses and thereby maintain a consistent view of data in the system. Yes - indicates that the subsequent transaction must be allowed to complete before the previous one or a deadlock can occur. When blocking occurs, the PMW is required to pass the Delayed Transaction. If the master continues attempting to complete Delayed Requests, it must be fair in attempting to complete the PMW. There is no ordering violation when these subsequent transactions complete before a prior transaction. Yes/No - indicates that the bridge designer may choose to allow the subsequent transaction to complete before the previous transaction or not. This is allowed since there are no ordering requirements to meet or deadlocks to avoid. How a bridge designer chooses to implement these boxes may have a cost impact on the bridge implementation or performance impact on the system. 273 Revision 2.2 Table E-1: Ordering Rules for a Bridge PMW DRR DWR DRC DWC Row pass Col.? (Col 2) (Col 3) (Col 4) (Col 5) (Col 6) PMW (Row 1) No1 Yes5 Yes5 Yes7 Yes7 DRR (Row 2) No2 Yes/No Yes/No Yes/No Yes/No DWR (Row 3) No3 Yes/No Yes/No Yes/No Yes/No DRC (Row 4) No4 Yes6 Yes6 Yes/No Yes/No DWC (Row 5) Yes/No Yes6 Yes6 Yes/No Yes/No Rule 1 - A subsequent PMW cannot pass a previously accepted PMW. (Col 2, Row 1) Posted Memory write transactions must complete in the order they are received. If the subsequent write is to the flag that covers the data, the Consumer may use stale data if write transactions are allowed to pass each other. Rule 2 - A read transaction must push posted write data to maintain ordering. (Col 2, Row 2) For example, a memory write to a location followed by an immediate memory read of the same location returns the new value (refer to Section 3.10, item 6, for possible exceptions). Therefore, a memory read cannot pass posted write data. An I/O read cannot pass a PMW, because the read may be ensuring the write data arrives at the final destination. Rule 3 - A non-postable write transaction must push posted write data to maintain ordering. (Col 2, Row 3) A Delayed Write Request may be the flag that covers the data previously written (PMW), and, therefore, the write flag cannot pass the data that it potentially covers. Rule 4 - A read transaction must pull write data back to the originating bus of the read transaction. (Col 2, Row 4) For example, the read of a status register of the device writing data to memory must not complete before the data is pulled back to the originating bus; otherwise, stale data may be used. Rule 5 - A Posted Memory Write must be allowed to pass a Delayed Request (read or write) to avoid deadlocks. (Col 3 and Col 4, Row 1) A deadlock can occur when bridges that support Delayed Transactions are used with bridges that do not support Delayed Transactions. Referring to Figure E-2, a deadlock can occur when Bridge Y (using Delayed Transactions) is between Bridges X and Z (designed to a previous version of this specification and not using Delayed Transactions). Master 1 initiates a read to Target 1 that is forwarded through Bridge X and is queued as a Delayed Request in Bridge Y. Master 3 initiates a read to Target 3 that is forwarded through Bridge Z and is queued as a Delayed Request in Bridge 274 Revision 2.2 Y. After Masters 1 and 3 are terminated with Retry, Masters 2 and 4 begin memory write transactions of a long duration addressing Targets 2 and 4 respectively, which are posted in the write buffers of Bridges X and Z respectively. When Bridge Y attempts to complete the read in either direction, Bridges X and Z must flush their posted write buffers before allowing the Read Request to pass through it. If the posted write buffers of Bridges X and Z are larger than those of Bridge Y, Bridge Y’s buffers will fill. If posted write data is not allowed to pass the DRR, the system will deadlock. Bridge Y cannot discard the read request since it has been attempted, and it cannot accept any more write data until the read in the opposite direction is completed. Since this condition exists in both directions, neither DRR can complete because the other is blocking the path. Therefore, the PMW data is required to pass the DRR when the DRR blocks forward progress of PMW data. The same condition exists when a DWR sits at the head of both queues, since some old bridges also require the posting buffers to be flushed on a non-posted write cycle. Rule 6 – A Delayed Completion (read or write) must be allowed to pass a Delayed Request (read or write) to avoid deadlocks. (Cols 3 and 4, Rows 4 and 5) A deadlock can occur when two bridges that support Delayed Transactions are requesting accesses to each other. The common PCI bus segment is on the secondary bus of Bridge A and the primary bus for Bridge B. If neither bridge allows Delayed Completions to pass the Delayed Requests, neither can make progress. For example, suppose Bridge A’s request to Bridge B completes on Bridge B’s secondary bus, and Bridge B’s request completes on Bridge A’s primary bus. Bridge A’s completion is now behind Bridge B’s request and Bridge B’s completion is behind Bridge A’s request. If neither bridge allows completions to pass the requests, then a deadlock occurs because neither master can make progress. Rule 7 - A Posted Memory Write must be allowed to pass a Delayed Completion (read or write) to avoid deadlocks. (Col 5 and Col 6, Row 1) As in the example for Rule 5, another deadlock can occur in the system configuration in Figure E-2. In this case, however, a DRC sits at the head of the queues in both directions of Bridge Y at the same time. Again the old bridges (X and Z) contain posted write data from another master. The problem in this case, however, is that the read transaction cannot be repeated until all the posted write data is flushed out of the old bridge and the master is allowed to repeat its original request. Eventually, the new bridge cannot accept any more posted data because its internal buffers are full and it cannot drain them until the DRC at the other end completes. When this condition exists in both directions, neither DRC can complete because the other is blocking the path. Therefore, the PMW data is required to pass the DRC when the DRC blocks forward progress of PMW data. The same condition exists when a DWC sits at the head of both queues. 275 Revision 2.2 Transactions that have no ordering constraints Some transactions enqueued as Delayed Requests or Delayed Completions have no ordering relationship with any other Delayed Requests or Delayed Completions. The designer can (for performance or cost reasons) allow or disallow Delayed Requests to pass other Delayed Requests and Delayed Completions that were previously enqueued. Delayed Requests can pass other Delayed Requests (Cols 3 and 4, Rows 2 and 3). Since Delayed Requests have no ordering relationship with other Delayed Requests, these four boxes are don’t cares. Delayed Requests can pass Delayed Completions (Col 5 and 6, Rows 2 and 3). Since Delayed Requests have no ordering relationship with Delayed Completions, these four boxes are don’t cares. Delayed Completions can pass other Delayed Completions (Col 5 and 6, Rows 4 and 5). Since Delayed Completions have no ordering relationship with other Delayed Completions, these four boxes are don’t cares. Delayed Write Completions can pass posted memory writes or be blocked by them (Col 2, Row 5). If the DWC is allowed to pass a PMW or if it remains in the same order, there is no deadlock or data inconsistencies in either case. The DWC data and the PMW data are moving in opposite directions, initiated by masters residing on different buses accessing targets on different buses. Target 1 Target 2 Master 3 Master 4 PCI Bus P PCI-PCI PCI-PCI PCI-PCI Bridge X Bridge Y Bridge Z (pre 2.1) (Rev. 2.1) (pre 2.1) PCI Bus N Master 1 Master 2 Target 3 Target 4 Figure E-2: Example System with PCI-to-PCI Bridges E.5. Delayed Transactions and LOCK# The bridge is required to support LOCK# when a transaction is initiated on its primary bus (and is using the lock protocol), but is not required to support LOCK# on transactions that are initiated on its secondary bus. If a locked transaction is initiated on the primary bus and the bridge is the target, the bridge must adhere to the lock semantics 276 Revision 2.2 defined by this specification. The bridge is required to complete (push) all PMWs (accepted from the primary bus) onto the secondary bus before attempting the lock on the secondary bus. The bridge may discard any requests enqueued, allow the locked transaction to pass the enqueued requests, or simply complete all enqueued transactions before attempting the locked transaction on the secondary interface. Once a locked transaction has been enqueued by the bridge, the bridge cannot accept any other transaction from the primary interface until the lock has completed except for a continuation of the lock itself by the lock master. Until the lock is established on the secondary interface, the bridge is allowed to continue enqueuing transactions from the secondary interface, but not the primary interface. Once lock has been established on the secondary interface, the bridge cannot accept any posted write data moving toward the primary interface until LOCK# has been released (FRAME# and LOCK# deasserted on the same rising clock edge). (In the simplest implementation, the bridge does not accept any other transactions in either direction once lock is established on the secondary bus, except for locked transactions from the lock master.) The bridge must complete PMW, DRC, and DWC transactions moving toward the primary bus before allowing the locked access to complete on the originating bus. The preceding rules are sufficient for deadlock free operation. However, an implementation may be more or less restrictive, but, in all cases must ensure deadlock-free operation. E.6. Error Conditions A bridge is free to discard data or status of a transaction that was completed using Delayed Transaction termination when the master has not repeated the request within 2 10 PCI clocks (about 30 µs at 33 MHz). However, it is recommended that the bridge not discard the transaction until 215 PCI clocks (about 983 µs at 33 MHz) after it acquired the data or status. The shorter number is useful in a system where a master designed to a previous version of this specification frequently fails to repeat a transaction exactly as first requested. In this case, the bridge may be programmed to discard the abandoned Delayed Completion early and allow other transactions to proceed. Normally, however, the bridge would wait the longer time, in case the repeat of the transaction is being delayed by another bridge or bridges designed to a previous version of this specification that did not support Delayed Transactions. When this timer (referred to as the Discard Timer) expires, the device is required to discard the data; otherwise, a deadlock may occur. Note: When the transaction is discarded, data may be destroyed. This occurs when the discarded Delayed Completion is a read to a non- prefetchable region. When the Discard Timer expires, the device may choose to report or ignore the error. When the data is prefetchable, it is recommended that the device ignore the error since system integrity is not affected. However, when the data is not prefetchable, it is recommended that the device report the error to its device driver since system integrity is affected. A bridge may assert SERR# since it typically does not have a device driver. 277 Revision 2.2 278 Revision 2.2 Appendix F Exclusive Accesses 7KHXVHRILOCK#LVRQO\DOORZHGWREHVXSSRUWHGE\DKRVWEXVEULGJHD3&,WR3&, EULGJHRUDQH[SDQVLRQEXVEULGJH,QHDUOLHUYHUVLRQVRIWKLVVSHFLILFDWLRQRWKHUGHYLFHV ZHUHDOORZHGWRLQLWLDWHDQGUHVSRQGWRH[FOXVLYHDFFHVVHVXVLQJLOCK#+RZHYHUWKH XVHIXOQHVVRIDKDUGZDUHEDVHGORFNPHFKDQLVPKDVGLPLQLVKHGDQGLVRQO\XVHIXOWR SUHYHQWDGHDGORFNRUWRSURYLGHEDFNZDUGFRPSDWLELOLW\7KHUHIRUHDOORWKHUGHYLFHV DUHUHTXLUHGWRLJQRUHLOCK# $KRVWEXVEULGJHFDQRQO\LQLWLDWHDQH[FOXVLYHDFFHVVWRSUHYHQWDGHDGORFNDVGHVFULEHG LQ6HFWLRQLWHPRUWRSURYLGHEDFNZDUGFRPSDWLELOLW\WRDQH[SDQVLRQEXVEULGJH WKDWVXSSRUWVH[FOXVLYHDFFHVV$KRVWEXVEULGJHFDQRQO\KRQRUDQH[FOXVLYHDFFHVVDV DWDUJHWZKHQSURYLGLQJFRPSDWLELOLW\WRDQDFFHVVLQLWLDWHGE\DQH[SDQVLRQEXVEULGJH WKDWVXSSRUWVH[FOXVLYHDFFHVVHV 1RRWKHUDJHQWFDQLQLWLDWHDORFNHGDFFHVVWRWKH+RVW %XVEULGJH $3&,WR3&,EULGJHLVRQO\DOORZHGWRSURSDJDWHDQH[FOXVLYHDFFHVVIURPLWVSULPDU\ EXVWRLWVVHFRQGDU\EXVDQGLVQHYHUDOORZHGWRLQLWLDWHDQH[FOXVLYHDFFHVVRILWVRZQ LQLWLDWLYH$3&,WR3&,EULGJHLVUHTXLUHGWRLJQRUHLOCK#ZKHQDFWLQJDVDWDUJHWRQ LWVVHFRQGDU\LQWHUIDFH $QH[SDQVLRQEXVEULGJHLVRQO\DOORZHGWRLQLWLDWHDQH[FOXVLYHDFFHVVWRSURYLGH EDFNZDUGFRPSDWLELOLW\7KLVPHDQVWKDWWKHH[SDQVLRQEXVVXSSRUWVDKDUGZDUHEDVHG H[FOXVLYHDFFHVVPHFKDQLVP LH(,6$DQGQRW,6$ 7KHH[SDQVLRQEXVEULGJHFDQ KRQRUDQH[FOXVLYHDFFHVVDVDWDUJHWZKHQVXSSRUWHGE\WKHH[SDQVLRQEXV RWKHUZLVH LOCK#KDVQRPHDQLQJWRWKHEULGJH 7KHUHPDLQGHURIWKLVFKDSWHULVRQO\DSSOLFDEOHWRDGHYLFHWKDWLVDOORZHGWRVXSSRUW LOCK#1RWH H[LVWLQJVRIWZDUHWKDWGRHVQRWVXSSRUWWKH3&,ORFNXVDJHUXOHVKDVWKH SRWHQWLDORIQRWZRUNLQJFRUUHFWO\6RIWZDUHLVQRWDOORZHGWRXVHDQH[FOXVLYHDFFHVVWR GHWHUPLQHLIDGHYLFHLVSUHVHQW F.1. Exclusive Accesses on PCI 3&,SURYLGHVDQH[FOXVLYHDFFHVVPHFKDQLVPZKLFKDOORZVQRQH[FOXVLYHDFFHVVHVWR SURFHHGLQWKHIDFHRIH[FOXVLYHDFFHVVHV7KLVDOORZVDPDVWHUWRKROGDKDUGZDUHORFN DFURVVVHYHUDODFFHVVHVZLWKRXWLQWHUIHULQJZLWKQRQH[FOXVLYHGDWDWUDQVIHUVXFKDVUHDO WLPHYLGHREHWZHHQWZRGHYLFHVRQWKHVDPHEXVVHJPHQW7KHPHFKDQLVPLVEDVHGRQ 279 Revision 2.2 ORFNLQJRQO\WKH3&,UHVRXUFHWRZKLFKWKHRULJLQDOORFNHGDFFHVVZDVWDUJHWHGDQGLV FDOOHGDUHVRXUFHORFN LOCK#LQGLFDWHVZKHWKHUWKHPDVWHUGHVLUHVWKHFXUUHQWWUDQVDFWLRQWRFRPSOHWHDVDQ H[FOXVLYHDFFHVVRUQRW&RQWURORILOCK#LVREWDLQHGXQGHULWVRZQSURWRFROLQ FRQMXQFWLRQZLWKGNT#5HIHUWR6HFWLRQ)IRUGHWDLOV0DVWHUVDQGWDUJHWVQRW LQYROYHGLQWKHH[FOXVLYHDFFHVVDUHDOORZHGWRSURFHHGZLWKQRQH[FOXVLYHDFFHVVHV ZKLOHDQRWKHUPDVWHUUHWDLQVRZQHUVKLSRILOCK#+RZHYHUZKHQFRPSDWLELOLW\ GLFWDWHVWKHDUELWHUFDQRSWLRQDOO\JUDQWWKHDJHQWWKDWRZQVLOCK#H[FOXVLYHDFFHVVWR WKHEXVXQWLOLOCK#LVUHOHDVHG7KLVLVUHIHUUHGWRDVFRPSOHWHEXVORFNDQGLV GHVFULEHGLQ6HFWLRQ))RUDUHVRXUFHORFNWKHWDUJHWRIWKHDFFHVVJXDUDQWHHV H[FOXVLYLW\ 7KHIROORZLQJSDUDJUDSKVGHVFULEHWKHEHKDYLRURIDPDVWHUDQGDWDUJHWIRUDORFNHG RSHUDWLRQ7KHUXOHVRILOCK#ZLOOEHVWDWHGIRUERWKWKHPDVWHUDQGWDUJHW$GHWDLOHG GLVFXVVLRQRIKRZWRVWDUWFRQWLQXHDQGFRPSOHWHDQH[FOXVLYHDFFHVVRSHUDWLRQIROORZV WKHGLVFXVVLRQRIWKHUXOHV$GLVFXVVLRQRIKRZDWDUJHWEHKDYHVZKHQLWVXSSRUWVD UHVRXUFHORFNZLOOIROORZWKHGHVFULSWLRQRIWKHEDVLFORFNPHFKDQLVP7KHFRQFOXGLQJ VHFWLRQZLOOGLVFXVVKRZWRLPSOHPHQWDFRPSOHWHEXVORFN 0DVWHUUXOHVIRUVXSSRUWLQJLOCK# $PDVWHUFDQDFFHVVRQO\DVLQJOHUHVRXUFH GXULQJDORFNRSHUDWLRQ 7KHILUVWWUDQVDFWLRQRIDORFNRSHUDWLRQPXVWEHDPHPRU\UHDGWUDQVDFWLRQ LOCK#PXVWEHDVVHUWHGWKHFORFN IROORZLQJWKHDGGUHVVSKDVHDQGNHSWDVVHUWHG WRPDLQWDLQFRQWURO LOCK#PXVWEHUHOHDVHGLIWKHLQLWLDOWUDQVDFWLRQRIWKHORFNUHTXHVWLVWHUPLQDWHG ZLWK5HWU\ /RFNZDVQRWHVWDEOLVKHG LOCK#PXVWEHUHOHDVHGZKHQHYHUDQDFFHVVLVWHUPLQDWHGE\7DUJHW$ERUWRU 0DVWHU$ERUW LOCK#PXVWEHGHDVVHUWHGEHWZHHQFRQVHFXWLYH ORFNRSHUDWLRQVIRUDPLQLPXPRI RQHFORFNZKLOHWKHEXVLVLQWKH,GOHVWDWH 57 In previous versions of this specification, a minimum of 16 bytes (naturally aligned) was considered the lock resource. A device was permitted to lock its entire memory address space. This definition still applies for an upstream locked access to main memory. For downstream locked access, a resource is the PCI-to- PCI bridge or the Expansion Bus bridge that is addressed by the locked operation. 58 For a SAC, this is the clock after the address phase. For a DAC, this occurs the clock after the first address phase. 59 Once lock has been established, the master retains ownership of LOCK# when terminated with Retry or Disconnect. 60 Consecutive refers to back-to-back locked operations and not a continuation of the current locked operation. 280 Revision 2.2 7DUJHW5XOHVIRUVXSSRUWLQJLOCK# $EULGJHDFWLQJDVDWDUJHWRIDQDFFHVVORFNVLWVHOIZKHQLOCK#LVGHDVVHUWHG GXULQJWKHDGGUHVVSKDVHDQGLVDVVHUWHGRQWKHIROORZLQJFORFN 2QFHORFNLVHVWDEOLVKHG DEULGJHUHPDLQVORFNHGXQWLOERWKFRAME#DQG LOCK#DUHVDPSOHGGHDVVHUWHGUHJDUGOHVVRIKRZWKHWUDQVDFWLRQLVWHUPLQDWHG 7KHEULGJHLVQRWDOORZHGWRDFFHSWDQ\QHZUHTXHVWV IURPHLWKHULQWHUIDFH ZKLOHLW LVLQDORFNHGFRQGLWLRQH[FHSWIURPWKHRZQHURILOCK# F.2. Starting an Exclusive Access :KHQDQDJHQWQHHGVWRGRDQH[FOXVLYHRSHUDWLRQLWFKHFNVWKHLQWHUQDOO\WUDFNHGVWDWH RILOCK#EHIRUHDVVHUWLQJREQ#7KHPDVWHUPDUNVLOCK#EXV\DQ\WLPHLOCK#LV DVVHUWHG XQOHVVLWLVWKHPDVWHUWKDWRZQVLOCK# DQGQRWEXV\ZKHQERWKFRAME# DQGLOCK#DUHGHDVVHUWHG,ILOCK#LVEXV\ DQGWKHPDVWHUGRHVQRWRZQLOCK# WKHDJHQWPXVWGHOD\WKHDVVHUWLRQRIREQ#XQWLOLOCK#LVDYDLODEOH :KLOHZDLWLQJIRUGNT#WKHPDVWHUFRQWLQXHVWRPRQLWRULOCK#,ILOCK#LVHYHU EXV\WKHPDVWHUGHDVVHUWVREQ#EHFDXVHDQRWKHUDJHQWKDVJDLQHGFRQWURORILOCK# :KHQWKHPDVWHULVJUDQWHGDFFHVVWRWKHEXVDQGLOCK#LVQRWEXV\RZQHUVKLSRI LOCK#KDVEHHQREWDLQHG7KHPDVWHULVIUHHWRSHUIRUPDQH[FOXVLYHRSHUDWLRQZKHQ WKHFXUUHQWWUDQVDFWLRQFRPSOHWHVDQGLVWKHRQO\DJHQWRQWKHEXVWKDWFDQGULYHLOCK# $OORWKHUDJHQWVPXVWQRWGULYHLOCK#HYHQZKHQWKH\DUHWKHFXUUHQWPDVWHU )LJXUH)LOOXVWUDWHVVWDUWLQJDQH[FOXVLYHDFFHVVLOCK#LVGHDVVHUWHGGXULQJWKH DGGUHVVSKDVH RQHFORFNIRU6$&RU'$& WRUHTXHVWDORFNRSHUDWLRQZKLFKPXVWEH LQLWLDWHGZLWKDPHPRU\UHDGFRPPDQGLOCK#PXVWEHDVVHUWHGWKHFORFNIROORZLQJ WKHILUVWDGGUHVVSKDVHZKLFKRFFXUVRQFORFNWRNHHSWKHWDUJHWLQWKHORFNHGVWDWH 7KLVDOORZVWKHFXUUHQWPDVWHUWRUHWDLQRZQHUVKLSRILOCK#EH\RQGWKHHQGRIWKH FXUUHQWWUDQVDFWLRQ 61 A locked operation is established when LOCK# is deasserted during the address phase, asserted the following clock, and data is transferred during the current transaction. 281 Revision 2.2 &/. )5$0( /2&. $' $'' '$7$ ,5'< 75'< '(96(/ Figure F-1: Starting an Exclusive Access $ORFNHGRSHUDWLRQLVQRWHVWDEOLVKHGRQWKHEXVXQWLOFRPSOHWLRQRIWKHILUVWGDWDSKDVH RIWKHILUVWWUDQVDFWLRQ IRDY#DQGTRDY#DVVHUWHG ,IWKHWDUJHWWHUPLQDWHVWKHILUVW WUDQVDFWLRQZLWK5HWU\WKHPDVWHUWHUPLQDWHVWKHWUDQVDFWLRQDQGUHOHDVHVLOCK#2QFH WKHILUVWGDWDSKDVHFRPSOHWHVZLWKERWKTRDY#DQGIRDY#DVVHUWHGWKHH[FOXVLYH RSHUDWLRQLVHVWDEOLVKHGDQGWKHPDVWHUNHHSVLOCK#DVVHUWHGXQWLOHLWKHUWKHORFN RSHUDWLRQFRPSOHWHVRUDQHUURU 0DVWHU$ERUWRU7DUJHW$ERUW FDXVHVDQHDUO\ WHUPLQDWLRQ7DUJHWWHUPLQDWLRQRI5HWU\DQG'LVFRQQHFWLVQRUPDOWHUPLQDWLRQHYHQ ZKHQDORFNRSHUDWLRQLVHVWDEOLVKHG:KHQDPDVWHULVWHUPLQDWHGE\WKHWDUJHWZLWK 'LVFRQQHFWRU5HWU\DIWHUWKHORFNKDVEHHQHVWDEOLVKHGWKHWDUJHWLVLQGLFDWLQJLWLV FXUUHQWO\EXV\DQGXQDEOHWRFRPSOHWHWKHUHTXHVWHGGDWDSKDVH7KHWDUJHWZLOODFFHSW WKHDFFHVVZKHQLWLVQRWEXV\DQGFRQWLQXHVWRKRQRUWKHORFNE\H[FOXGLQJDOORWKHU DFFHVVHV7KHPDVWHUFRQWLQXHVWRFRQWUROLOCK#LIWKLVFRQGLWLRQRFFXUV1RQ H[FOXVLYHDFFHVVHVWRXQORFNHGWDUJHWVRQWKHVDPH3&,EXVVHJPHQWDUHDOORZHGWRRFFXU ZKLOHLOCK#LVDVVHUWHG+RZHYHUWUDQVDFWLRQVWRRWKHUEXVVHJPHQWVDUHQRWDOORZHG WRFURVVDORFNHGEULGJH :KHQDEULGJHLVORFNHGLWPD\RQO\DFFHSWUHTXHVWVZKHQLOCK#LVGHDVVHUWHGGXULQJ WKHDGGUHVVSKDVH ZKLFKLQGLFDWHVWKDWWKHWUDQVDFWLRQLVDFRQWLQXDWLRQRIWKHH[FOXVLYH DFFHVVVHTXHQFHE\WKHPDVWHUWKDWHVWDEOLVKHGWKHORFN ,ILOCK#LVDVVHUWHGGXULQJ WKHDGGUHVVSKDVHDORFNHGEULGJHZLOOWHUPLQDWHDOODFFHVVHVE\DVVHUWLQJSTOP#ZLWK TRDY#GHDVVHUWHG 5HWU\ $ORFNHGWDUJHWUHPDLQVLQWKHORFNHGVWDWHXQWLOERWK FRAME#DQGLOCK#DUHGHDVVHUWHG 'HOD\HG7UDQVDFWLRQVDQG/RFN $ORFNHGWUDQVDFWLRQFDQEHFRPSOHWHGXVLQJ'HOD\HG7UDQVDFWLRQWHUPLQDWLRQ$OOWKH UXOHVRILOCK#VWLOODSSO\H[FHSWWKHEULGJHPXVWFRQVLGHULWVHOIORFNHGZKHQLW HQTXHXHVWKHUHTXHVWHYHQWKRXJKQRGDWDKDVWUDQVIHUUHG7KLVFRQGLWLRQLVUHIHUUHGWR DVDWDUJHWORFN:KLOHLQWDUJHWORFNWKHEULGJHHQTXHXHVQRQHZUHTXHVWVRQWKH SULPDU\LQWHUIDFHDQGWHUPLQDWHVDOOUHTXHVWVZLWK5HWU\7KHEULGJHORFNVLWVVHFRQGDU\ LQWHUIDFHZKHQORFNLVHVWDEOLVKHGRQWKHVHFRQGDU\EXVDQGVWDUWVFKHFNLQJIRUWKHUHSHDW RIWKHRULJLQDOORFNUHTXHVWRQWKHSULPDU\LQWHUIDFH$WDUJHWORFNEHFRPHVDIXOOORFN ZKHQWKHPDVWHUUHSHDWVWKHORFNHGUHTXHVWDQGWKHEULGJHWUDQVIHUVGDWD$WWKLVSRLQW WKHPDVWHUKDVHVWDEOLVKHGWKHORFN 282 Revision 2.2 $EULGJHDFWLQJDVDWDUJHWWKDWVXSSRUWVH[FOXVLYHDFFHVVHVPXVWVDPSOHLOCK#ZLWK WKHDGGUHVVDQGRQDVXEVHTXHQWFORFN,IWKHEULGJHSHUIRUPVPHGLXPRUVORZGHFRGHLW PXVWODWFKLOCK#GXULQJWKHILUVWDGGUHVVSKDVH2WKHUZLVHWKHEULGJHFDQQRW GHWHUPLQHLIWKHDFFHVVLVDORFNRSHUDWLRQZKHQGHFRGHFRPSOHWHV$EULGJHPDUNVLWVHOI DVWDUJHWORFNHGLILOCK#LVGHDVVHUWHGGXULQJWKHILUVWDGGUHVVSKDVHDQGLVDVVHUWHGRQ WKHQH[WFORFN$EULGJHGRHVQRWPDUNLWVHOIWDUJHWORFNHGLILOCK#LVGHDVVHUWHGWKH FORFNIROORZLQJWKHILUVWDGGUHVVSKDVHDQGLVIUHHWRUHVSRQGWRRWKHUUHTXHVWV F.3. Continuing an Exclusive Access )LJXUH)VKRZVDPDVWHUFRQWLQXLQJDQH[FOXVLYHDFFHVV+RZHYHUWKLVDFFHVVPD\RU PD\QRWFRPSOHWHWKHH[FOXVLYHRSHUDWLRQ:KHQWKHPDVWHULVJUDQWHGDFFHVVWRWKHEXV LWVWDUWVDQRWKHUH[FOXVLYHDFFHVVWRWKHWDUJHWLWSUHYLRXVO\ORFNHGLOCK#LVGHDVVHUWHG GXULQJWKHDGGUHVVSKDVHWRFRQWLQXHWKHORFN7KHORFNHGGHYLFHDFFHSWVDQGUHVSRQGV WRWKHUHTXHVWLOCK#LVDVVHUWHGRQFORFNWRNHHSWKHWDUJHWLQWKHORFNHGVWDWHDQG DOORZWKHFXUUHQWPDVWHUWRUHWDLQRZQHUVKLSRILOCK#EH\RQGWKHHQGRIWKHFXUUHQW WUDQVDFWLRQ :KHQWKHPDVWHULVFRQWLQXLQJWKHORFNRSHUDWLRQLWFRQWLQXHVWRDVVHUWLOCK#:KHQ WKHPDVWHUFRPSOHWHVWKHORFNRSHUDWLRQLWGHDVVHUWVLOCK#DIWHUWKHFRPSOHWLRQRIWKH ODVWGDWDSKDVHZKLFKRFFXUVRQFORFN5HIHUWR6HFWLRQ)IRUPRUHLQIRUPDWLRQRQ FRPSOHWLQJDQH[FOXVLYHDFFHVV CLK 1 2 3 4 5 FRAME# Release LOCK# Continue AD ADDRESS DATA IRDY# TRDY# DEVSEL# )LJXUH) &RQWLQXLQJDQ([FOXVLYH$FFHVV F.4. Accessing a Locked Agent )LJXUH)VKRZVDPDVWHUWU\LQJDQRQH[FOXVLYHDFFHVVWRDORFNHGDJHQW:KHQ LOCK#LVDVVHUWHGGXULQJWKHDGGUHVVSKDVHDQGLIWKHWDUJHWLVORFNHG IXOOORFNRU WDUJHWORFN LWWHUPLQDWHVWKHWUDQVDFWLRQZLWK5HWU\DQGQRGDWDLVWUDQVIHUUHG 283 Revision 2.2 CLK 1 2 3 4 5 FRAME# LOCK# (driven low by master holding lock) AD ADDRESS DATA IRDY# TRDY# STOP# DEVSEL# )LJXUH) $FFHVVLQJD/RFNHG$JHQW F.5. Completing an Exclusive Access 'XULQJWKHILQDOWUDQVDFWLRQRIDQH[FOXVLYHRSHUDWLRQLOCK#LVGHDVVHUWHGVRWKHWDUJHW ZLOODFFHSWWKHUHTXHVWDQGWKHQUHDVVHUWHGXQWLOWKHH[FOXVLYHDFFHVVWHUPLQDWHV VXFFHVVIXOO\7KHPDVWHUPD\GHDVVHUWLOCK#DWDQ\WLPHZKHQWKHH[FOXVLYHRSHUDWLRQ KDVFRPSOHWHG+RZHYHULWLVUHFRPPHQGHG EXWQRWUHTXLUHG WKDWLOCK#EH GHDVVHUWHGZLWKWKHGHDVVHUWLRQRIIRDY#IROORZLQJWKHFRPSOHWLRQRIWKHODVWGDWDSKDVH RIWKHORFNHGRSHUDWLRQ5HOHDVLQJLOCK# DWDQ\RWKHUWLPHPD\UHVXOWLQDVXEVHTXHQW WUDQVDFWLRQEHLQJWHUPLQDWHGZLWK5HWU\XQQHFHVVDULO\$ORFNHGDJHQWXQORFNVLWVHOI ZKHQHYHULOCK#DQGFRAME#DUHGHDVVHUWHG ,IDPDVWHUZDQWVWRH[HFXWHWZRLQGHSHQGHQWH[FOXVLYHRSHUDWLRQVRQWKHEXVLWPXVW HQVXUHDPLQLPXPRIRQHFORFNEHWZHHQRSHUDWLRQVZKHUHERWKFRAME#DQGLOCK# DUHGHDVVHUWHG )RUH[DPSOHWKHIDVWEDFNWREDFNFDVHGHSLFWHGLQ)LJXUH FORFN FDQQRWORFNERWKWUDQVDFWLRQV 7KLVHQVXUHVDQ\WDUJHWORFNHGE\WKHILUVWRSHUDWLRQLV UHOHDVHGSULRUWRVWDUWLQJWKHVHFRQGRSHUDWLRQ $QDJHQWPXVWXQORFNLWVHOIZKHQ FRAME#DQGLOCK#DUHERWKGHDVVHUWHGRQWKHVDPHFORFN F.7. Complete Bus Lock 7KH3&,UHVRXUFHORFNFDQEHFRQYHUWHGLQWRDFRPSOHWHEXVORFNE\KDYLQJWKHDUELWHU QRWJUDQWWKHEXVWRDQ\RWKHUDJHQWZKLOHLOCK#LVDVVHUWHG,IWKHILUVWDFFHVVRIWKH ORFNHGVHTXHQFHLVWHUPLQDWHGZLWK5HWU\WKHPDVWHUPXVWGHDVVHUWERWKREQ#DQG LOCK#,IWKHILUVWDFFHVVFRPSOHWHVQRUPDOO\WKHFRPSOHWHEXVORFNKDVEHHQ HVWDEOLVKHGDQGWKHDUELWHUZLOOQRWJUDQWWKHEXVWRDQ\RWKHUDJHQW,IWKHDUELWHUJUDQWHG WKHEXVWRDQRWKHUDJHQWZKHQWKHFRPSOHWHEXVORFNZDVEHLQJHVWDEOLVKHGWKHDUELWHU PXVWUHPRYHWKHRWKHUJUDQWWRHQVXUHWKDWFRPSOHWHEXVORFNVHPDQWLFVDUHREVHUYHG$ FRPSOHWHEXVORFNPD\KDYHDVLJQLILFDQWLPSDFWRQWKHSHUIRUPDQFHRIWKHV\VWHP SDUWLFXODUO\WKHYLGHRVXEV\VWHP$OOQRQH[FOXVLYHDFFHVVHVZLOOQRWSURFHHGZKLOHD FRPSOHWHEXVORFNRSHUDWLRQLVLQSURJUHVV 284 Revision 2.2 Appendix G I/O Space Address Decoding for Legacy Devices $IXQFWLRQWKDWVXSSRUWVD3&OHJDF\IXQFWLRQ ,'(9*$HWF LVDOORZHGWRFODLPWKRVH DGGUHVVHVDVVRFLDWHGZLWKWKHVSHFLILFIXQFWLRQZKHQWKH,26SDFH VHH)LJXUH HQDEOHELWLVVHW 7KHVHDGGUHVVHVDUHQRWUHTXHVWHGXVLQJD%DVH$GGUHVVUHJLVWHUEXWDUHDVVLJQHGE\ LQLWLDOL]DWLRQVRIWZDUH,IDGHYLFHLGHQWLILHVLWVHOIDVDOHJDF\IXQFWLRQ FODVVFRGH WKH LQLWLDOL]DWLRQVRIWZDUHJUDQWVWKHGHYLFHSHUPLVVLRQWRFODLPWKH,2OHJDF\DGGUHVVHVE\ VHWWLQJWKHGHYLFH¶V,26SDFHHQDEOHELW ,IWKHGHYLFHGRHVQRWRZQDOOE\WHVZLWKLQD':25'RIDOHJDF\,2UDQJHLWLV UHTXLUHGWRXVHAD[1::0]WRFRPSOHWHWKHGHFRGHEHIRUHFODLPLQJWKHDFFHVVE\DVVHUWLQJ DEVSEL#,IDOHJDF\IXQFWLRQLVDGGUHVVHGE\DQ,2WUDQVDFWLRQEXWGRHVQRWRZQDOO E\WHVEHLQJDFFHVVHGLQWKH':25'LWLVUHTXLUHGWRWHUPLQDWHWKHWUDQVDFWLRQZLWK 7DUJHW$ERUW$QH[SDQVLRQEXVEULGJHLVJUDQWHGDQH[FHSWLRQWRWKLVUHTXLUHPHQWZKHQ SHUIRUPLQJVXEWUDFWLYHGHFRGH7KHEULGJHLVSHUPLWWHGWRDVVXPHWKDWDOOE\WHVZLWKLQ WKH':25'EHLQJDGGUHVVHGUHVLGHRQWKHH[SDQVLRQEXV7KLVPHDQVWKDWWKHEULGJHLV QRWUHTXLUHGWRFKHFNWKHHQFRGLQJRIAD[1::0]DQGWKHE\WHHQDEOHVEHIRUHSDVVLQJWKH UHTXHVWWRWKHH[SDQVLRQEXVWRFRPSOHWH 285 Revision 2.2 286 Revision 2.2 Appendix H Capability IDs 7KLVDSSHQGL[GHVFULEHVWKHFXUUHQW&DSDELOLW\,'V(DFKGHILQHGFDSDELOLW\PXVWKDYHD 3&,6,*DVVLJQHG,'FRGH7KHVHFRGHVDUHDVVLJQHGDQGKDQGOHGPXFKOLNHWKH&ODVV &RGHV 6HFWLRQRIWKLVVSHFLILFDWLRQSURYLGHVDIXOOGHVFULSWLRQRIWKH([WHQGHG&DSDELOLWLHV /LVWIRU3&,GHYLFHV 7DEOH+ &DSDELOLW\,'V ID Capability 0 Reserved 1 PCI Power Management Interface – This capability structure provides a standard interface to control power management features in a PCI device. It is fully documented in the PCI Power Management Interface Specification. This document is available from the PCI SIG as described in Chapter 1 of this specification. 2 AGP – This capability structure identifies a controller that is capable of using Accelerated Graphics Port features. Full documentation can be found in the Accelerated Graphics Port Interface Specification. This is available at http://www.agpforum.org. 3 VPD – This capability structure identifies a device that supports Vital Product Data. Full documentation of this feature can be found in Section 6.4. and Appendix I of this specification. 287 Revision 2.2 7DEOH+ &DSDELOLW\,'V FRQWLQXHG ID Capability 4 6ORW,GHQWLILFDWLRQ–7KLVFDSDELOLW\VWUXFWXUHLGHQWLILHVDEULGJHWKDW SURYLGHVH[WHUQDOH[SDQVLRQFDSDELOLWLHV)XOOGRFXPHQWDWLRQRIWKLV IHDWXUHFDQEHIRXQGLQWKH3&,WR3&,%ULGJH$UFKLWHFWXUH 6SHFLILFDWLRQ7KLVGRFXPHQWLVDYDLODEOHIURPWKH3&,6,*DV GHVFULEHGLQ&KDSWHURIWKLVVSHFLILFDWLRQ 5 Message Signaled Interrupts – This capability VWUXFWXUHidentifies a PCI function that can do message signaled interrupt delivery as defined in Section 6.8. of this specification. 6 CompactPCI Hot Swap – This capability VWUXFWXUHprovides a standard interface to control and sense status within a device that supports Hot Swap insertion and extraction in a CompactPCI system. This capability is documented in the CompactPCI Hot Swap Specification PICMG 2.1, R1.0 available at http://www.picmg.org. 7-255 Reserved 288 Revision 2.2 Appendix I Vital Product Data 9LWDO3URGXFW'DWD 93' LVLQIRUPDWLRQWKDWXQLTXHO\LGHQWLILHVKDUGZDUHDQG SRWHQWLDOO\VRIWZDUHHOHPHQWVRIDV\VWHP7KH93'FDQSURYLGHWKHV\VWHPZLWK LQIRUPDWLRQRQYDULRXV)LHOG5HSODFHDEOH8QLWVVXFKDVSDUWQXPEHUVHULDOQXPEHUDQG RWKHUGHWDLOHGLQIRUPDWLRQ7KHREMHFWLYHIURPDV\VWHPSRLQWRIYLHZLVWRPDNHWKLV LQIRUPDWLRQDYDLODEOHWRWKHV\VWHPRZQHUDQGVHUYLFHSHUVRQQHO6XSSRUWRI93'LV RSWLRQDO 93'UHVLGHVLQDVWRUDJHGHYLFH IRUH[DPSOHDVHULDO((3520 LQD3&,GHYLFH $FFHVVWRWKH93'LVSURYLGHGXVLQJWKH&DSDELOLWLHV/LVWLQ&RQILJXUDWLRQ6SDFH7KH 93'FDSDELOLW\VWUXFWXUHKDVWKHIROORZLQJIRUPDW 31 30 16 15 8 7 0 F VPD Address Pointer to Next ID ID = 03h VPD Data )LJXUH, 93'&DSDELOLW\6WUXFWXUH 5HJLVWHU)LHOG'HVFULSWLRQV ,'²&DSDELOLW\VWUXFWXUH,'KZKLFKLVDUHDGRQO\ILHOG 3RLQWHUWR1H[W,'²3RLQWHUWRWKHQH[WFDSDELOLW\VWUXFWXUHRUKLIWKLVLVWKHODVW VWUXFWXUHLQWKH&DSDELOLW\/LVW7KLVLVDUHDGRQO\ILHOG 93'$GGUHVV²':25'DOLJQHGE\WHDGGUHVVRIWKH93'WREHDFFHVVHG7KHUHJLVWHU LVUHDGZULWHDQGWKHLQLWLDOYDOXHDWSRZHUXSLVLQGHWHUPLQDWH )²$IODJXVHGWRLQGLFDWHZKHQWKHWUDQVIHURIGDWDEHWZHHQWKH93''DWDUHJLVWHUDQG WKHVWRUDJHFRPSRQHQWLVFRPSOHWHG7KHIODJUHJLVWHULVZULWWHQZKHQWKH93'$GGUHVV UHJLVWHULVZULWWHQ7RUHDG93'LQIRUPDWLRQD]HURLVZULWWHQWRWKHIODJUHJLVWHUZKHQ WKHDGGUHVVLVZULWWHQWRWKH93'$GGUHVVUHJLVWHU7KHKDUGZDUHGHYLFHZLOOVHWWKHIODJ WRDRQHZKHQE\WHVRIGDWDIURPWKHVWRUDJHFRPSRQHQWKDYHEHHQWUDQVIHUUHGWRWKH 93''DWDUHJLVWHU6RIWZDUHFDQPRQLWRUWKHIODJDQGDIWHULWLVVHWWRDRQHUHDGWKH 93'LQIRUPDWLRQIURPWKH93''DWDUHJLVWHU,IHLWKHUWKH93'$GGUHVVRU93''DWD UHJLVWHULVZULWWHQSULRUWRWKHIODJELWEHLQJVHWWRDRQHWKHUHVXOWVRIWKHRULJLQDOUHDG RSHUDWLRQDUHXQSUHGLFWDEOH7RZULWH93'LQIRUPDWLRQWRWKHUHDGZULWHSRUWLRQRIWKH 93'VSDFHZULWHWKHGDWDWRWKH93''DWDUHJLVWHU7KHQZULWHWKHDGGUHVVRIZKHUHWKH 93'GDWDLVWREHVWRUHGLQWRWKH93'$GGUHVVUHJLVWHUDQGZULWHWKHIODJELWWRDRQH DW 289 Revision 2.2 WKHWLPHWKHDGGUHVVLVZULWWHQ 7KHVRIWZDUHWKHQPRQLWRUVWKHIODJELWDQGZKHQLWLV VHWWR]HUR E\GHYLFHKDUGZDUH WKH93'GDWD DOOE\WHV KDVEHHQWUDQVIHUUHGIURPWKH 93''DWDUHJLVWHUWRWKHVWRUDJHFRPSRQHQW,IHLWKHUWKH93'$GGUHVVRU93''DWD UHJLVWHULVZULWWHQSULRUWRWKHIODJELWEHLQJVHWWRD]HURWKHUHVXOWVRIWKHZULWH RSHUDWLRQWRWKHVWRUDJHFRPSRQHQWDUHXQSUHGLFWDEOH 93''DWD²93'GDWDFDQEHUHDGWKURXJKWKLVUHJLVWHU7KHOHDVWVLJQLILFDQWE\WHRI WKLVUHJLVWHU DWRIIVHWLQWKLVFDSDELOLW\VWUXFWXUH FRUUHVSRQGVWRWKHE\WHRI93'DWWKH DGGUHVVVSHFLILHGE\WKH93'$GGUHVVUHJLVWHU7KHGDWDUHDGIURPRUZULWWHQWRWKLV UHJLVWHUXVHVWKHQRUPDO3&,E\WHWUDQVIHUFDSDELOLWLHV)RXUE\WHVDUHDOZD\VWUDQVIHUUHG EHWZHHQWKLVUHJLVWHUDQGWKH93'VWRUDJHFRPSRQHQW5HDGLQJRUZULWLQJGDWDRXWVLGH RIWKH93'VSDFHLQWKHVWRUDJHFRPSRQHQWLVQRWDOORZHG7KH93' ERWKWKHUHDGRQO\ LWHPVDQGWKHUHDGZULWHILHOGV LVVWRUHGLQIRUPDWLRQDQGZLOOKDYHQRGLUHFWFRQWURORI DQ\GHYLFHRSHUDWLRQV7KHLQLWLDOYDOXHRIWKLVUHJLVWHUDWSRZHUXSLVLQGHWHUPLQDWH 7KH93'$GGUHVVILHOGLVDE\WHDGGUHVVEXWPXVWVSHFLI\D':25'DOLJQHGORFDWLRQ LHWKHERWWRPWZRELWVPXVWEH]HUR (YHU\ERDUGPD\FRQWDLQ93':KHQD3&,H[SDQVLRQERDUGFRQWDLQVPXOWLSOHGHYLFHV 93'LISURYLGHGLVUHTXLUHGRQRQO\RQHRIWKHPEXWPD\EHLQFOXGHGLQHDFK3&, GHYLFHVGHVLJQHGH[FOXVLYHO\IRUXVHRQWKHV\VWHPERDUGPD\DOVRVXSSRUWWKHRSWLRQDO 93'UHJLVWHUV 93'LQD3&,H[SDQVLRQERDUGXVHVWZRRIWKHSUHGHILQHGWDJLWHPQDPHVSUHYLRXVO\ GHILQHGLQWKH3OXJDQG3OD\,6$6SHFLILFDWLRQDQGWZRQHZRQHVGHILQHGVSHFLILFDOO\IRU 3&,93'7KH3Q3,6$WDJLWHPQDPHVWKDWDUHXVHGDUH ,GHQWLILHU6WULQJ [ IRUD /DUJH5HVRXUFH'DWD7\SHDQG(QG7DJ [) IRUD6PDOO5HVRXUFH'DWD7\SH7KH QHZODUJHUHVRXUFHLWHPQDPHVIRU93'DUH93'5ZLWKDYDOXHRI[IRUUHDGRQO\ GDWDDQG93':ZLWKDYDOXHRI[IRUUHDGZULWHGDWD 9LWDO3URGXFW'DWDLVPDGHXSRI6PDOODQG/DUJH5HVRXUFH'DWD7\SHVDVGHVFULEHGLQ WKH3OXJDQG3OD\,6$6SHFLILFDWLRQ9HUVLRQD8VHRIWKHVHGDWDVWUXFWXUHVDOORZV OHYHUDJLQJRIGDWDW\SHVDOUHDG\IDPLOLDUWRWKHLQGXVWU\DQGPLQLPL]HVWKHDPRXQWRI DGGLWLRQDOUHVRXUFHVQHHGHGIRUVXSSRUW7KLVGDWDIRUPDWFRQVLVWVRIDVHULHVRI³WDJJHG´ GDWDVWUXFWXUHV7KHGDWDW\SHVIURPWKH3OXJDQG3OD\,6$6SHFLILFDWLRQ9HUVLRQD DUHUHSURGXFHGLQWKHIROORZLQJILJXUHV Offset Field Name Byte 0 Value = 0xxxxyyyb (Type = Small(0), Small Item Name = xxxx, length = yy bytes Bytes 1 to n Actual information )LJXUH, 6PDOO5HVRXUFH'DWD7\SH7DJ%LW'HILQLWLRQV 290 Revision 2.2 Offset Field Name Byte 0 Value = 1xxxxxxxB (Type = Large(1), Large item name = xxxxxxx) Byte 1 Length of data items bits[7:0] (lsb) Byte 2 Length of data items bits[15:8] (msb) Byte 3 to n Actual data items )LJXUH, /DUJH5HVRXUFH'DWD7\SH7DJ%LW'HILQLWLRQV 7KH,GHQWLILHU6WULQJ [ WDJLVWKHILUVW93'WDJDQGSURYLGHVWKHSURGXFWQDPHRIWKH GHYLFH2QH93'5 [ WDJLVXVHGDVDKHDGHUIRUWKHUHDGRQO\NH\ZRUGVDQGRQH 93': [ WDJLVXVHGDVDKHDGHUIRUWKHUHDGZULWHNH\ZRUGV7KH93'5OLVW LQFOXGLQJWDJDQGOHQJWK PXVWFKHFNVXPWR]HUR7KHVWRUDJHFRPSRQHQWFRQWDLQLQJ WKHUHDGZULWHGDWDLVDQRQYRODWLOHGHYLFHWKDWZLOOUHWDLQWKHGDWDZKHQSRZHUHGRII $WWHPSWVWRZULWHWKHUHDGRQO\GDWDZLOOEHH[HFXWHGDVDQRRS7KHODVWWDJPXVWEH WKH(QG7DJ [) $VPDOOH[DPSOHRIWKHUHVRXUFHGDWDW\SHWDJVXVHGLQDW\SLFDO 93'LVVKRZQLQ)LJXUH, TAG Identifier String TAG VPD-R list containing one or more VPD keywords TAG VPD-W list containing one or more VPD keywords TAG End Tag )LJXUH, 5HVRXUFH'DWD7\SH)ODJVIRUD7\SLFDO93' 291 Revision 2.2 I.1. VPD Format ,QIRUPDWLRQILHOGVZLWKLQD93'UHVRXUFHW\SHFRQVLVWRIDWKUHHE\WHKHDGHUIROORZHGE\ VRPHDPRXQWRIGDWD VHH)LJXUH, 7KHWKUHHE\WHKHDGHUFRQWDLQVDWZRE\WH NH\ZRUGDQGDRQHE\WHOHQJWK $NH\ZRUGLVDWZRFKDUDFWHU $6&,, PQHPRQLFWKDWXQLTXHO\LGHQWLILHVWKHLQIRUPDWLRQ LQWKHILHOG7KHODVWE\WHRIWKHKHDGHULVELQDU\DQGUHSUHVHQWVWKHOHQJWKYDOXH LQ E\WHV RIWKHGDWDWKDWIROORZV Keyword Length Data Byte 0 Byte 1 Byte 2 Bytes 3 through n )LJXUH, 93')RUPDW 93'NH\ZRUGVDUHOLVWHGLQWZRFDWHJRULHV UHDGRQO\ILHOGVDQGUHDGZULWHILHOGV 8QOHVVRWKHUZLVHQRWHGNH\ZRUGGDWDILHOGVDUHSURYLGHGDV$6&,,FKDUDFWHUV8VHRI $6&,,DOORZVNH\ZRUGGDWDWREHPRYHGDFURVVGLIIHUHQWHQWHUSULVHFRPSXWHUV\VWHPV ZLWKRXWWUDQVODWLRQGLIILFXOW\$QH[DPSOHRIWKH³H[SDQVLRQERDUGVHULDOQXPEHU´93' LWHPLVDVIROORZV .H\ZRUG 61 /HQJWK K 'DWD ³ ´ I.2. VPD Compatibility 2SWLRQDO93'ZDVVXSSRUWHGLQSULRUYHUVLRQVRIWKLVVSHFLILFDWLRQ)RULQIRUPDWLRQRQ WKHSUHYLRXVGHILQLWLRQRI93'VHH3&,/RFDO%XV6SHFLILFDWLRQ5HYLVLRQ I.3. VPD Definitions 7KLVVHFWLRQGHVFULEHVWKHFXUUHQW93'ODUJHDQGVPDOOUHVRXUFHGDWDWDJVSOXVWKH93' NH\ZRUGV7KLVOLVWPD\EHHQKDQFHGDWDQ\WLPH&RPSDQLHVZLVKLQJWRGHILQHDQHZ NH\ZRUGVKRXOGFRQWDFWWKH3&,6,*$OOXQVSHFLILHGYDOXHVDUHUHVHUYHGIRU6,* DVVLJQPHQW 292 Revision 2.2 I.3.1. VPD Large and Small Resource Data Tags 93'LVFRQWDLQHGLQIRXUW\SHVRI/DUJHDQG6PDOO5HVRXUFH'DWD7DJV7KHIROORZLQJ WDJVDQG93'NH\ZRUGILHOGVPD\EHSURYLGHGLQ3&,GHYLFHV Large resource type Identifier This tag is the first item in the VPD storage String Tag component. It contains the name of the board in (0x2) alphanumeric characters. Large resource type VPD-R This tag contains the read only VPD keywords for a Tag board. (0x10) Large resource type VPD-W This tag contains the read/write VPD keywords for Tag the board. (0x11) Small resource type End Tag This tag identifies the end of VPD in the storage (0xF) component. I.3.1.1. Read-Only Fields PN Board Part Number This keyword is provided as an extension to the Device ID (or Subsystem ID) in the Configuration Space header in Figure 6-1. EC EC Level of the Board The characters are alphanumeric and represent the engineering change level for this board. MN Manufacture ID This keyword is provided as an extension to the Vendor ID (or Subsystem Vendor ID) in the Configuration Space header in Figure 6-1. This allows vendors the flexibility to identify an additional level of detail pertaining to the sourcing of this device. SN Serial Number The characters are alphanumeric and represent the unique board Serial Number. Vx Vendor Specific This is a vendor specific item and the characters are alphanumeric. The second character (x) of the keyword can be 0 through Z. 293 Revision 2.2 CP Extended Capability This field allows a new capability to be identified in the VPD area. Since dynamic control/status cannot be placed in VPD, the data for this field identifies where, in the device’s memory or I/O address space, the control/status registers for the capability can be found. Location of the control/status registers is identified by providing the index (a value between 0 and 5) of the Base Address register that defines the address range that contains the registers, and the offset within that Base Address register range where the control/status registers reside. The data area for this field is four bytes long. The first byte contains the ID of the extended capability. The second byte contains the index (zero based) of the Base Address register used. The next two bytes contain the offset (in little endian order) within that address range where the control/status registers defined for that capability reside. RV Checksum and The first byte of this item is a checksum byte. The Reserved checksum is correct if the sum of all bytes in VPD (from VPD address 0 up to and including this byte) is zero. The remainder of this item is reserved space (as needed) to identify the last byte of read-only space. The read-write area does not have a checksum. This field is required. I.3.1.2 Read/Write Fields Vx Vendor Specific This is a vendor specific item and the characters are alphanumeric. The second character (x) of the keyword can be 0 through Z. Yx System Specific This is a system specific item and the characters are alphanumeric. The second character (x) of the keyword can be 0 through 9 and B through Z. YA Asset Tag Identifier This is a system specific item and the characters are alphanumeric. This keyword contains the system asset identifier provided by the system owner. RW Remaining Read/Write This descriptor is used to identify the unused Area portion of the read/write space. The product vendor initializes this parameter based on the size of the read/write space or the space remaining following the Vx VPD items. One or more of the Vx, Yx, and RW items are required. 294 Revision 2.2 I.3.2. VPD Example The following is an example of a typical VPD. Offset Item Value 0 Large Resource Type ID String Tag 0x82 “Product Name” (0x02) 1 Length 0x0021 3 Data “ABCD Super-Fast Widget Controller” 36 Large Resource Type VPD-R Tag (0x10) 0x90 37 Length 0x0059 39 VPD Keyword “PN” 41 Length 0x08 42 Data “6181682A” 50 VPD Keyword “EC” 52 Length 0x0A 53 Data “4950262536” 63 VPD Keyword “SN” 65 Length 0x08 66 Data “00000194” 74 VPD Keyword “MN” 76 Length 0x04 77 Data “1037” 81 VPD Keyword “RV” 83 Length 0x2C 84 Data Checksum 85 Data Reserved (0x00) 295 Revision 2.2 Offset Item Value 128 Large Resource Type VPD-W Tag (0x11) 0x91 129 Length 0x007E 131 VPD Keyword “V1” 133 Length 0x05 134 Data “65A01” 139 VPD Keyword “Y1” 141 Length 0x0D 142 Data “Error Code 26” 155 VPD Keyword “RW” 157 Length 0x61 158 Data Reserved (0x00) 255 Small Resource Type End Tag (0xF) 0x78 296 Revision 2.2 Glossary 64-bit extension A group of PCI signals that support a 64-bit data path. Address Spaces A reference to the three separate physical address regions of PCI: Memory, I/O, and Configuration. agent An entity that operates on a computer bus. arbitration latency The time that the master waits after having asserted REQ# until it receives GNT#, and the bus returns to the idle state after the previous master’s transaction. backplate The metal plate used to fasten an expansion board to the system chassis. BIST register An optional register in the header region used for control and status of built-in self tests. bridge The logic that connects one computer bus to another, allowing an agent on one bus to access an agent on the other. burst transfer The basic bus transfer mechanism of PCI. A burst is comprised of an address phase and one or more data phases. bus commands Signals used to indicate to a target the type of transaction the master is requesting. bus device A bus device can be either a bus master or target: • master -- drives the address phase and transaction boundary (FRAME#). The master initiates a transaction and drives data handshaking (IRDY#) with the target. • target -- claims the transaction by asserting DEVSEL# and handshakes the transaction (TRDY#) with the initiator. catastrophic error An error that affects the integrity of system operation such as a detected address parity error or an invalid PWR_GOOD signal. 297 Revision 2.2 central resources Bus support functions supplied by the host system, typically in a PCI compliant bridge or standard chipset. command See bus command. Configuration Address Space A set of 64 registers (DWORDs) used for configuration, initialization, and catastrophic error handling. This address space consists of two regions: a header region and a device-dependent region. configuration transaction Bus transaction used for system initialization and configuration via the configuration address space. DAC Dual address cycle. A PCI transaction where a 64-bit address is transferred across a 32-bit data path in two clock cycles. See also SAC. deadlock When two devices (one a master, the other a target) require the other device to respond first during a single bus transaction. For example, a master requires the addressed target to assert TRDY# on a write transaction before the master will assert IRDY#. (This behavior is a violation of this specification.) Delayed Transaction The process of a target latching a request and completing it after the master was terminated with Retry. device See PCI device. device dependent region The last 48 DWORDS of the PCI configuration space. The contents of this region are not described in this document. Discard Timer When this timer expires, a device is permitted to discard unclaimed Delayed Completions (refer to Section 3.3.3.3.3. and Appendix E). DWORD A 32-bit block of data. EISA Extended Industry Standard Architecture expansion bus, based on the IBM PC AT bus, but extended to 32 bits of address and data. expansion board A circuit board that plugs into a motherboard and provides added functionality. expansion bus bridge A bridge that has PCI as its primary interface and ISA, EISA, or Micro Channel as its secondary interface. This specification does not preclude the use of bridges to other buses, although deadlock and other system issues for those buses have not been considered. Function A set of logic that is represented by a single Configuration Space. 298 Revision 2.2 header region The first 16 DWORDS of a device’s Configuration Space. The header region consists of fields that uniquely identify a PCI device and allow the device to be generically controlled. See also device dependent region. hidden arbitration Arbitration that occurs during a previous access so that no PCI bus cycles are consumed by arbitration, except when the bus is idle. host bus bridge A low latency path through which the processor may directly access PCI devices mapped anywhere in the memory, I/O, or configuration address spaces. Idle state Any clock period that the bus is idle (FRAME# and IRDY# deasserted). Initialization Time The period of time that begins when RST# is deasserted and completes 225 PCI clocks later. ISA Industry Standard Architecture expansion bus built into the IBM PC AT computer. keepers Pullup resistors or active components that are only used to sustain a signal state. latency See arbitration latency, master data latency, target initial latency, and target subsequent latency. Latency Timer A mechanism for ensuring that a bus master does not extend the access latency of other masters beyond a specified value. master An agent that initiates a bus transaction. Master-Abort A termination mechanism that allows a master to terminate a transaction when no target responds. master data latency The number of PCI clocks until IRDY# is asserted from FRAME# being asserted for the first data phase or from the end of the previous data phase. MC The Micro Channel architecture expansion bus as defined by IBM for its PS/2 line of personal computers. motherboard A circuit board containing the basic functions (e.g., CPU, memory, I/O, and expansion connectors) of a computer. multi-function device A device that implements from two to eight functions. Each function has its own Configuration Space that is addressed by a different encoding of AD[10::08] during the address phase of a configuration transaction. 299 Revision 2.2 multi-master device A single-function device that contains more than one source of bus master activity. For example, a device that has a receiver and transmitter that operate independently. NMI Non-maskable interrupt. operation A logical sequence of transactions, e.g., Lock. output driver An electrical drive element (transistor) for a single signal on a PCI device. PCI connector An expansion connector that conforms to the electrical and mechanical requirements of the PCI local bus standard. PCI device A device that (electrical component) conforms to the PCI specification for operation in a PCI local bus environment. PGA Pin grid array component package. phase One or more clocks in which a single unit of information is transferred, consisting of: • an address phase (a single address transfer in one clock for a single address cycle and two clocks for a dual address cycle) • a data phase (one transfer state plus zero or more wait states) positive decoding A method of address decoding in which a device responds to accesses only within an assigned address range. See also subtractive decoding. POST Power-on self test. A series of diagnostic routines performed when a system is powered up. pullups Resistors used to insure that signals maintain stable values when no agent is actively driving the bus. run time The time that follows Initialization Time. SAC Single address cycle. A PCI transaction where a 32-bit address is transferred across a 32-bit data path in a single clock cycle. See also DAC. shared slot An arrangement on a PCI motherboard that allows a PCI connector to share the system bus slot nearest the PCI bus layout with an ISA, EISA, or MC bus connector. In an MC system, for example, the shared slot can accommodate either an MC expansion board or a PCI expansion board. single-function device A device that contains only one function. sideband signals Any signal not part of the PCI specification that connects two or more PCI-compliant agents and has meaning only to those agents. 300 Revision 2.2 Special Cycle A message broadcast mechanism used for communicating processor status and/or (optionally) logical sideband signaling between PCI agents. stale data Data in a cache-based system that is no longer valid and, therefore, must be discarded. stepping The ability of an agent to spread assertion of qualified signals over several clocks. subtractive decoding A method of address decoding in which a device accepts all accesses not positively decoded by another agent. See also positive decoding. target An agent that responds (with a positive acknowledgment by asserting DEVSEL#) to a bus transaction initiated by a master. Target-Abort A termination mechanism that allows a target to terminate a transaction in which a fatal error has occurred, or to which the target will never be able to respond. target initial latency The number of PCI clocks that the target takes to assert TRDY# for the first data transfer. target subsequent latency The number of PCI clocks that the target takes to assert TRDY# from the end of the previous data phase of a burst. termination A transaction termination brings bus transactions to an orderly and systematic conclusion. All transactions are concluded when FRAME# and IRDY# are deasserted (an idle cycle). Termination may be initiated by the master or the target. transaction An address phase plus one or more data phases. turnaround cycle A bus cycle used to prevent contention when one agent stops driving a signal and another agent begins driving it. A turnaround cycle must last one clock and is required on all signals that may be driven by more than one agent. wait state A bus clock in which no transfer occurs. 301 Revision 2.2 302