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PCI Local Bus Specification Revision 3.0 June 2002Junedecember 5February 3, 20043 28, 2002

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PCI Local Bus Specification Revision 3.0 June 2002Junedecember 5February 3, 20043 28, 2002 PCI Local Bus Specification Revision 3.0 June 2002JuneDecember 5February 3, 20043 28, 2002 PCI LOCAL BUS SPECIFICATION, REV. 3.0 PCI SPECIFICATIONS REVISION REVISION HISTORY DATE 1.0 Original issue. 6/22/92 2.0 Incorporated connector and add-in card specification. 4/30/93 2.1 Incorporated clarifications and added 66 MHz chapter. 6/1/95 2.2 Incorporated ECNs and improved readability. 12/18/98 2.3 Incorporated ECNs, errata, and deleted 5 volt only keyed 3/29/02 add-in cards. 3.0 Incorporated ECNs, errata, and Rremoved support for the 212/305/ 5.0 volt keyed system board connector. Moved the 043 Expansion ROM description to the PCI Firmware Specification. The PCI Special Interest Group-SIG disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does the PCI-SIG Special Interest Group make a commitment to update the information contained herein. Contact the PCI-SIG Special Interest Group office to obtain the latest revision of the specification. Questions regarding the PCI specification or membership in the PCI-SIG Special Interest Grou may be forwarded to: PCI-SIG Special Interest Group 5440 SW Westgate Drive Suite 217 Portland, Oregon 97221 Phone: 800-433-5177 (Inside the U.S.) 503-291-2569 (Outside the U.S.) Fax: 503-297-1090 e-mail [email protected] http://www.pcisig.com DISCLAIMER This PCI Local Bus Specification is provided "“as is" ” with no warranties whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample. The PCI-SIG SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. All product names are trademarks, registered trademarks, or servicemarks of their respective owners. 2 VOLUME 1 PCI -SIG PCI LOCAL BUS SPECIFICATION, REV. 1.13.0 PCI LOCAL BUS SPECIFICATION, REV. 3.0 PCI SPECIFICATIONS FireWire is a trademark of Apple Computer, Inc. Token Ring and VGA are trademarks and PS/2, IBM, Micro Channel, OS/2, and PC AT are registered trademarks of IBM Corporation. Windows, MS-DOS, and Microsoft are registered trademarks of Microsoft Corporation. Tristate is a registered trademark of National Semiconductor. NuBus is a trademark of Texas Instruments. Ethernet is a registered trademark of Xerox Corporation. All other product names are trademarks, registered trademarks, or service marks of their respective owners. Copyright © 1992, 1993, 1995, 1998, 200432 PCI-SIG Special Interest Group PCI-SIG 3 III PCI LOCAL BUS SPECIFICATION, REV. 1.13.0 PCI LOCAL BUS SPECIFICATION, REV. 3.0 PCI SPECIFICATIONS 4 VOLUME 1 PCI -SIG PCI LOCAL BUS SPECIFICATION, REV. 1.13.0 PCI LOCAL BUS SPECIFICATION, REV. 3.0 REVISION 2.3 Preface Specification Supersedes Earlier Documents This document contains the formal specifications of the protocol, electrical, and mechanical features of the PCI Local Bus Specification, Revision 2.33.0, as the production version effective March 29December 19February 3, 200432. The PCI Local Bus Specification, Revision 2.23, issued December 18March 29, 19982002, is not superseded by this specification. For compliance information and schedules, refer to the PCI-SIG home page at http://www.pcisig.com. Following publication of the PCI Local Bus Specification, Revision 3.02.3, there may be future approved errata and/or approved changes to the specification prior to the issuance of another formal revision. To assure designs meet the latest level requirements, designers of PCI devices must refer to the PCI-SIG home page at http://www.pcisig.com for any approved changes. Incorporation of Engineering Change Notices (ECNs) The following ECNs has have been incorporated into this production version of the specification: ECN Description System Board Connector Removed support for the 5 volt keyed system board PCI connector MSI-X Enhanced MSI interrupt support 13 PCI LOCAL BUS SPECIFICATION, REV. 3.0 PCI SPECIFICATIONS Document Conventions The following name and usage conventions are used in this document: asserted, deasserted The terms asserted and deasserted refer to the globally visible state of the signal on the clock edge, not to signal transitions. edge, clock edge The terms edge and clock edge refer to the rising edge of the clock. On the rising edge of the clock is the only time signals have any significance on the PCI bus. # A # symbol at the end of a signal name indicates that the signal's asserted state occurs when it is at a low voltage. The absence of a # symbol indicates that the signal is asserted at a high voltage. reserved The contents or undefined states or information are not defined at this time. Using any reserved area in the PCI specification is not permitted. All areas of the PCI specification can only be changed according to the by-laws of the PCI Special Interest Group-SIG. Any use of the reserved areas of the PCI specification will result in a product that is not PCI-compliant. The functionality of any such product cannot be guaranteed in this or any future revision of the PCI specification. signal names Signal names are indicated with this font. signal range A signal name followed by a range enclosed in brackets, for example AD[31::00], represents a range of logically related signals. The first number in the range indicates the most significant bit (msb) and the last number indicates the least significant bit (lsb). implementation notes Implementation notes are enclosed in a box. They are not part of the PCIis specification and are included for clarification and illustration only. 14VOLUME 1 14 PCI -SIG PCI LOCAL BUS SPECIFICATION, REV. 1.13.0 PCI LOCAL BUS SPECIFICATION, REV. 3.0 PCI SPECIFICATIONS 1 1. Introduction 1.1. Specification Contents The PCI Local Bus is a high performance 32-bit or 64-bit bus with multiplexed address and data lines. The bus is intended for use as an interconnect mechanism between highly integrated peripheral controller components, peripheral add-in cards, and processor/memory systems. The PCI Local Bus Specification, Rev. 2.33.0, includes the protocol, electrical, mechanical, and configuration specification for PCI Local Bus components and add-in cards. The electrical definition provides for the 3.3V and 5V signaling environments. The PCI Local Bus Specification defines the PCI hardware environment. Contact the PCI SIG for information on the other PCI Specifications. For information on how to join the PCI SIG or to obtain these documents, refer to Section 1.6. 1.2. Motivation When the PCI Local Bus Specification was originally developed in 1992, graphics-oriented operating systems such as Windows and OS/2 had created a data bottleneck between the processor and its display peripherals in standard PC I/O architectures. Moving peripheral functions with high bandwidth requirements closer to the system's processor bus can eliminate this bottleneck. Substantial performance gains are seen with graphical user interfaces (GUIs) and other high bandwidth functions (i.e., full motion video, SCSI, LANs, etc.) when a "local bus" design is used. PCI successfully met these demands of the industry and is now the most widely accepted and implemented expansion standard in the world. PCI-SIG VOLUME15 1 PCI LOCAL BUS SPECIFICATION, REV. 1.13.0 PCI LOCAL BUS SPECIFICATION, REV. 3.0 PCI SPECIFICATIONS 1.3. PCI Local Bus Applications The PCI Local Bus has been defined with the primary goal of establishing an industry standard, high performance local bus architecture that offers low cost and allows differentiation. While the primary focus is on enabling new price-performance points in today's systems, it is important that a new standard also accommodates future system requirements and be applicable across multiple platforms and architectures. Figure 1-1 shows the multiple dimensions of the PCI Local Bus. Servers High End Auto 64-bit Upgrade Desktops Configuration Path PCI 33 PCI-X 66 PCI-X 266 PCI Express Low, Mid- PCI 66 PCI-X 133 PCI-X 533 Range Desktop Mobile A-0151 Figure 1-1: PCI Local Bus Applications While the initial focus of local bus applications has beenwas on low to high end desktop systems, the PCI Local Bus also comprehends the requirements from mobile applications up through servers. The PCI Local Bus specifies both the 3.3 volt and 5 volt signaling requirements and this revision no longer supports 5 volt only keyed add-in cards, which represents a significant step in the migration path to the 3.3 volt signaling environment. The PCI component and add-in card interface is processor independent, enabling an efficient transition to future processor generations and use with multiple processor architectures. Processor independence allows the PCI Local Bus to be optimized for I/O functions, enables concurrent operation of the local bus with the processor/memory subsystem, and accommodates multiple high performance peripherals in addition to graphics (motion video, LAN, SCSI, FDDI, hard disk drives, etc.). Movement to enhanced video and multimedia displays (i.e., HDTV and 3D graphics) and other high bandwidth I/O will continue to increase local bus bandwidth requirements. A transparent 64-bit extension of the 32-bit data and address buses is defined, doubling the bus bandwidth and offering forward and backward compatibility of 32-bit and 64-bit PCI Local Bus peripherals. A forward and backward compatible PCI-X specification (see the PCI-X Addendum to the PCI Local Bus Specification) is also defined, increasing the bandwidth capabilities of the 33 MHz definition by a factor of four.
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