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PCI Local Bus Specification Revision 3.0 February 3, 2004

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PCI Local Bus Specification Revision 3.0 February 3, 2004 PCI Local Bus Specification Revision 3.0 February 3, 2004 PCI LOCAL BUS SPECIFICATION, REV. 3.0 REVISION REVISION HISTORY DATE 1.0 Original issue. 6/22/92 2.0 Incorporated connector and add-in card specification. 4/30/93 2.1 Incorporated clarifications and added 66 MHz chapter. 6/1/95 2.2 Incorporated ECNs and improved readability. 12/18/98 2.3 Incorporated ECNs, errata, and deleted 5 volt only keyed 3/29/02 add-in cards. 3.0 Incorporated ECNs, errata, and removed support for the 2/3/04 5.0 volt keyed system board connector. Moved the Expansion ROM description to the PCI Firmware Specification. PCI-SIG disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does PCI-SIG make a commitment to update the information contained herein. Contact the PCI-SIG office to obtain the latest revision of the specification. Questions regarding this PCI specification or membership in PCI-SIG may be forwarded to: PCI-SIG 5440 SW Westgate Drive Suite 217 Portland, Oregon 97221 Phone: 503-291-2569 Fax: 503-297-1090 e-mail [email protected] http://www.pcisig.com DISCLAIMER This PCI Local Bus Specification is provided "as is" with no warranties whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample. PCI-SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. PCI Express is a trademark of PCI-SIG. All other product names are trademarks, registered trademarks, or servicemarks of their respective owners. Copyright © 1992, 1993, 1995, 1998, and 2004 PCI-SIG 2 PCI LOCAL BUS SPECIFICATION, REV. 3.0 Contents PREFACE........................................................................................................................13 SPECIFICATION ............................................................................................................... 13 INCORPORATION OF ENGINEERING CHANGE NOTICES (ECNS)....................................... 13 DOCUMENT CONVENTIONS ............................................................................................ 14 1. INTRODUCTION................................................................................................... 15 1.1. SPECIFICATION CONTENTS ................................................................................. 15 1.2. MOTIVATION...................................................................................................... 15 1.3. PCI LOCAL BUS APPLICATIONS ......................................................................... 16 1.4. PCI LOCAL BUS OVERVIEW............................................................................... 17 1.5. PCI LOCAL BUS FEATURES AND BENEFITS ........................................................ 18 1.6. ADMINISTRATION...............................................................................................20 2. SIGNAL DEFINITION ..........................................................................................21 2.1. SIGNAL TYPE DEFINITION .................................................................................. 22 2.2. PIN FUNCTIONAL GROUPS.................................................................................. 22 2.2.1. System Pins................................................................................................ 23 2.2.2. Address and Data Pins.............................................................................. 24 2.2.3. Interface Control Pins............................................................................... 25 2.2.4. Arbitration Pins (Bus Masters Only) ........................................................27 2.2.5. Error Reporting Pins................................................................................. 27 2.2.6. Interrupt Pins (Optional) .......................................................................... 28 2.2.7. Additional Signals ..................................................................................... 31 2.2.8. 64-Bit Bus Extension Pins (Optional) ....................................................... 33 2.2.9. JTAG/Boundary Scan Pins (Optional)...................................................... 34 2.2.10. System Management Bus Interface Pins (Optional) ................................. 35 2.3. SIDEBAND SIGNALS............................................................................................ 36 2.4. CENTRAL RESOURCE FUNCTIONS....................................................................... 36 3. BUS OPERATION.................................................................................................. 37 3.1. BUS COMMANDS ................................................................................................37 3.1.1. Command Definition ................................................................................. 37 3.1.2. Command Usage Rules ............................................................................. 39 3.2. PCI PROTOCOL FUNDAMENTALS ....................................................................... 42 3.2.1. Basic Transfer Control.............................................................................. 43 3.2.2. Addressing................................................................................................. 44 3.2.3. Byte Lane and Byte Enable Usage ............................................................ 56 3.2.4. Bus Driving and Turnaround.................................................................... 57 3.2.5. Transaction Ordering and Posting ...........................................................58 3.2.6. Combining, Merging, and Collapsing....................................................... 62 3 PCI LOCAL BUS SPECIFICATION, REV. 3.0 3.3. BUS TRANSACTIONS...........................................................................................64 3.3.1. Read Transaction ......................................................................................65 3.3.2. Write Transaction......................................................................................66 3.3.3. Transaction Termination...........................................................................67 3.4. ARBITRATION.....................................................................................................87 3.4.1. Arbitration Signaling Protocol..................................................................89 3.4.2. Fast Back-to-Back Transactions ...............................................................91 3.4.3. Arbitration Parking...................................................................................94 3.5. LATENCY............................................................................................................95 3.5.1. Target Latency...........................................................................................95 3.5.2. Master Data Latency.................................................................................98 3.5.3. Memory Write Maximum Completion Time Limit..................................... 99 3.5.4. Arbitration Latency .................................................................................100 3.6. OTHER BUS OPERATIONS .................................................................................110 3.6.1. Device Selection ......................................................................................110 3.6.2. Special Cycle...........................................................................................111 3.6.3. IDSEL Stepping.......................................................................................113 3.6.4. Interrupt Acknowledge ............................................................................114 3.7. ERROR FUNCTIONS...........................................................................................115 3.7.1. Parity Generation....................................................................................115 3.7.2. Parity Checking.......................................................................................116 3.7.3. Address Parity Errors .............................................................................116 3.7.4. Error Reporting.......................................................................................117 3.7.5. Delayed Transactions and Data Parity Errors....................................... 120 3.7.6. Error Recovery........................................................................................121 3.8. 64-BIT BUS EXTENSION ...................................................................................123 3.8.1. Determining Bus Width During System Initialization.............................126 3.9. 64-BIT ADDRESSING .........................................................................................127 3.10. SPECIAL DESIGN CONSIDERATIONS..............................................................130 4. ELECTRICAL SPECIFICATION......................................................................137 4.1. OVERVIEW .......................................................................................................137 4.1.1. Transition Road Map ..............................................................................137
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