IBM Z13 Server Technology

Introducing the IBM® z13™ Server Platform Structure and Performance Monte Bauman Enterprise Server Technical Support IBM Columbus [email protected] January 2015 IBM z Systems Agenda § Design Imperatives § The IBM z Systems z13 Server § The z13 Big Data Server 2 © 2015 IBM Corporation IBM z Systems Design Imperatives IBM z Systems Business Imperatives The Mobile Moment The Odds are High … Business Management is interested in... Enterprise § Promoting High Retention Rates and Capturing Class Competitive share through mobile interactions Cloud § Driving integrated/smart transactions that improve the Client Experience (e.g. Next Best Action) Business- Critical § Growing and Improving the IT services consumer Analytics experience within Existing Environmental Envelope Smart Transactions 4 © 2015 IBM Corporation IBM z Systems IBM z13 Design Primitives The IBM z13 Server was developed with the intent to: § Capture transaction growth through mobile enablement of existing systems § Drive integrated analytics at the time of the transaction § Deliver higher levels of Capacity and Performance within the Existing Environmental Envelope Enclave-Encapsulated Systems of Engagement Systems of Record Systems of Insight 5 © 2015 IBM Corporation IBM z Systems The IBM z13 Server 6 © 2015 IBM Corporation IBMIBM z Systems z13 platform positioning Platform Core Capabilities: Transaction Processing • The world’s premier transaction and data engine now enabled for Data Serving the mobile generation Mixed Workloads Operational Efficiency • The integrated transaction and analytics system for right-time Trusted and Secure Computing insights at the point of impact Reliable, Available, Resilient Virtually Limitless Scale • The world’s most efficient and trusted cloud system that transforms the economics of IT © 2015 IBM Corporation 7 7 © 2015 IBM Corporation IBM z Systems z13 Overview § Machine Type – 2964 § 5 Models – N30, N63, N96, NC9 and NE1 § Processor Units (PUs) – 39 (42 for NE1) PU cores per CPC drawer – Up to 24 SAPs per system, standard – 2 spares designated per system Customer Max – Dependant on the H/W model - up to 30, 63, 96, 129,141 PU cores Model PUs Memory available for characterization • Central Processors (CPs), Internal Coupling Facility (ICFs), Integrated Facility for Linux (IFLs), IBM z Integrated Information Processor (zIIP), optional - additional System Assist Processors (SAPs) and Integrated NE1 141 10 TB Firmware Processor (IFP) • 85 LPARs, increased from 60 – Sub-capacity available for up to 30 CPs NC9 129 10 TB • 3 sub-capacity points § Memory – RAIM Memory design N96 96 7.5 TB – System Minimum of 64 GB – Up to 2.5 TB GB per drawer – Up to 10 TB for System and up to 10 TB per LPAR (OS dependant) N63 63 5 TB • LPAR support of the full memory enabled • 96 GB Fixed HSA, standard • 32/64/96/128/256/512 GB increments N30 30 2.5 TB ─ Flash Express § I/O – 6 GBps I/O Interconnects – carry forward only – Up to 40 PCIe Gen3 Fanouts @ 16 GBps each and Integrated Coupling Adapters @ 2 x 8 GBps per System – 6 Logical Channel Subsystems (LCSSs) • 4 Sub-channel sets per LCSS § Server Time Protocol (STP) 8 © 2015 IBM Corporation IBM z Systems z13 Continues the CMOS Mainframe Heritage Begun in 1994 5.5 GHz 5.2 GHz 60006000 5.0 GHz 4.4 GHz 50005000 40004000 1695* +12% 1514* +26% GHz 30003000 -9% 1.7 GHz 1202* GHz +33% +6% GHz 1.2 GHz 20002000 902* +18% 3.99B MHz/GHz 770 MHz +50% GHz 2.75B 41.6MB +159% 1.4B 10001000 20.8MB 1B 15.7MB 0 0 5.6MB 2000 2003 2005 2008 2010 2012 2015 z900z900 z990z990 z9ecz9 EC z10ecz10 EC z196z196 zEC12zEC12 zNextz13 189 nm SOI 130 nm SOI 90 nm SOI 65 nm SOI 45 nm SOI 32 nm SOI 22 nm SOI 16 Cores** 32 Cores** 54 Cores** 64 Cores** 80 Cores** 101 Cores** EC141 Cores** Full 64-bit z/ Superscalar System level High-freq core OOO core OOO and eDRAM SMT &SIMD Architecture Modular SMP scaling 3-level cache eDRAM cache cache RAIM memory improvements Up to 10TB of zBX integration PCIe Flash Memory Arch extensions for scaling * MIPS Tables are NOT adequate for making comparisons of z Systems processors. Additional capacity planning required ** Number of PU cores for customer use 9 © 2015 IBM Corporation IBM z Systems [email protected] vs. [email protected] Instruction-Set Instructions SIMD(z13) vs. no SIMD(zEC12) Memory Fetch Instructions 42MB/core(z13) vs 21MB/core(zEC12) Instructions Cycles Seconds Seconds ---------------- X ---------------- X ---------------- = ---------------- Workload Instruction Cycle Workload OoOX and RISC-like CISC 6 instructions/cycle(z13) vs. 3 instructions/cycle(zEC12) 10 © 2015 IBM Corporation IBM z Systems Pipeline zEC12 Decode Order Load/Store Unit Order Stage Load/Store Unit De-Stage 1500 Core to Fixed Point Unit Retry L1 Instruction Fixed Point Unit 1650 Cache 64KB CP MIPS Floating Point Unit L1 Data Decimal FP Unit Cache 96KB Branch Unit SAP 5.5GHz L2 Instruction Branch Unit Cache 1MB ICF Out Compression Crypto Assist L2 Data Unit Unit of Cache 1MB Order IFL Translation GeneralGeneral Purpose Purpose Registers Registers 23 New Lookaside Floating Point Registers zIIP Instr. Buffer Control Registers zAAP Branch 3 Instr. Processor Status Word History Per Instruction Pointer Table Cycle zEC12 Core 11 © 2015 IBM Corporation IBM z Systems Pipeline Pipeline Pipeline Decode Order Load/Store Unit Order Decode Order Load/Store Unit Order Decode Order Load/Store Unit Order Stage Load/Store Unit De-Stage Stage Load/Store Unit De-Stage Stage Load/Store Unit De-Stage zEC12 Fixed Point Unit Retry Fixed Point Unit Retry Fixed Point Unit Retry L1 Instruction L1 Instruction L1 Instruction Cache Fixed Point Unit Cache Fixed Point Unit Cache Fixed Point Unit Floating Point Unit Floating Point Unit Floating Point Unit L1 Data L1 Data L1 Data Cache Decimal FP Unit Cache Decimal FP Unit Cache Decimal FP Unit Branch Unit Branch Unit Branch Unit L2 Core L2 Core L2 Core Chip Cache General Purpose Registers Cache General Purpose Registers Cache General Purpose Registers Translation Floating Point Registers Translation Floating Point Registers Translation Floating Point Registers Lookaside Lookaside Lookaside Buffer Control Registers Buffer Control Registers Buffer Control Registers Processor Status Word Processor Status Word Processor Status Word Branch Branch Branch History Instruction Pointer History Instruction Pointer History Instruction Pointer Table Table Table Compression Crypto Assist Compression Crypto Assist Compression Crypto Assist Unit Unit Unit Unit Unit Unit zEC12 Core zEC12 Core zEC12 Core 2.75B Transistors L3 L3 zEC12 Chip Chip Hex-Core L1/L2/L3 Cache Cache Total Chip 61MB 24MB 24MB cache Pipeline Pipeline Pipeline Decode Order Load/Store Unit Order Decode Order Load/Store Unit Order Decode Order Load/Store Unit Order Stage Load/Store Unit De-Stage Stage Load/Store Unit De-Stage Stage Load/Store Unit De-Stage Fixed Point Unit Retry Fixed Point Unit Retry Fixed Point Unit Retry L1 Instruction L1 Instruction L1 Instruction Cache Fixed Point Unit Cache Fixed Point Unit Cache Fixed Point Unit Floating Point Unit Floating Point Unit Floating Point Unit L1 Data L1 Data L1 Data Cache Decimal FP Unit Cache Decimal FP Unit Cache Decimal FP Unit Branch Unit Branch Unit Branch Unit L2 Core L2 Core L2 Core Cache General Purpose Registers Cache General Purpose Registers Cache General Purpose Registers Translation Floating Point Registers Translation Floating Point Registers Translation Floating Point Registers Lookaside Lookaside Lookaside Buffer Control Registers Buffer Control Registers Buffer Control Registers Processor Status Word Processor Status Word Processor Status Word Branch Branch Branch History Instruction Pointer History Instruction Pointer History Instruction Pointer Table Table Table Compression Crypto Assist Compression Crypto Assist Compression Crypto Assist Unit Unit Unit Unit Unit Unit zEC12 Core zEC12 Core zEC12 Core 12 © 2015 IBM Corporation IBM z Systems zEC12 Core Core Core Core Core Core Core Core Core L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 Multi-Chip L2 L2 L2 L2 L2 L2 L2 L2 L2 Module L3 Chip L3 L3 Chip L3 L3 Chip L3 Core Core Core Core Core Core Core Core Core L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L2 L2 L2 L2 L2 L2 L2 L2 L2 L4 Shared Storage Control Storage Control 384MB & Clock Chip zEC12 & Clock Chip L4 MCM Cache MCM L4 MCM Cache 1800 Watts Core Core Core Core Core Core Core Core Core L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L2 L2 L2 L2 L2 L2 L2 L2 L2 L3 Chip L3 L3 Chip L3 L3 Chip L3 Core Core Core Core Core Core Core Core Core L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L2 L2 L2 L2 L2 L2 L2 L2 L2 13 © 2015 IBM Corporation IBM z Systems zEC12 Book Core Core Core Core Core Core Core Core Core L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L2 L2 L2 L2 L2 L2 L2 L2 L2 L3 Chip L3 L3 Chip L3 L3 Chip L3 Core Core Core Core Core Core Core Core Core L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L2 L2 L2 L2 L2 L2 L2 L2 L2 Connectors Storage Control Storage Control & Clock Chip & Clock Chip RAM zEC12 (RAIM) L4 MCM Cache MCM L4 MCM Cache Core Core Core Core Core Core Core Core Core RAIM SC to L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 RAM (DIMs) L2 L2 L2 L2 L2 L2 L2 L2 L2 Interconnect L3 Chip L3 L3 Chip L3 L3 Chip L3 Core Core Core Core Core Core Core Core Core L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L2 L2 L2 L2 L2 L2 L2 L2 L2 Book 14 © 2015 IBM Corporation Up to IBM z Systems 101 Up to zEC12 Processor Cage config’d 120 cores active cores Core Core Core Core Core Core Core Core Core L1 L1 L1 L1 L1 L1 L1 L1 L1 L1 L1

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