Linux on IBM Z13:Performance Aspects of New Technology And
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IBM Z Systems Introduction May 2017
IBM z Systems Introduction May 2017 IBM z13s and IBM z13 Frequently Asked Questions Worldwide ZSQ03076-USEN-15 Table of Contents z13s Hardware .......................................................................................................................................................................... 3 z13 Hardware ........................................................................................................................................................................... 11 Performance ............................................................................................................................................................................ 19 z13 Warranty ............................................................................................................................................................................ 23 Hardware Management Console (HMC) ..................................................................................................................... 24 Power requirements (including High Voltage DC Power option) ..................................................................... 28 Overhead Cabling and Power ..........................................................................................................................................30 z13 Water cooling option .................................................................................................................................................... 31 Secure Service Container ................................................................................................................................................. -
Energy Efficient Spin-Locking in Multi-Core Machines
Energy efficient spin-locking in multi-core machines Facoltà di INGEGNERIA DELL'INFORMAZIONE, INFORMATICA E STATISTICA Corso di laurea in INGEGNERIA INFORMATICA - ENGINEERING IN COMPUTER SCIENCE - LM Cattedra di Advanced Operating Systems and Virtualization Candidato Salvatore Rivieccio 1405255 Relatore Correlatore Francesco Quaglia Pierangelo Di Sanzo A/A 2015/2016 !1 0 - Abstract In this thesis I will show an implementation of spin-locks that works in an energy efficient fashion, exploiting the capability of last generation hardware and new software components in order to rise or reduce the CPU frequency when running spinlock operation. In particular this work consists in a linux kernel module and a user-space program that make possible to run with the lowest frequency admissible when a thread is spin-locking, waiting to enter a critical section. These changes are thread-grain, which means that only interested threads are affected whereas the system keeps running as usual. Standard libraries’ spinlocks do not provide energy efficiency support, those kind of optimizations are related to the application behaviors or to kernel-level solutions, like governors. !2 Table of Contents List of Figures pag List of Tables pag 0 - Abstract pag 3 1 - Energy-efficient Computing pag 4 1.1 - TDP and Turbo Mode pag 4 1.2 - RAPL pag 6 1.3 - Combined Components 2 - The Linux Architectures pag 7 2.1 - The Kernel 2.3 - System Libraries pag 8 2.3 - System Tools pag 9 3 - Into the Core 3.1 - The Ring Model 3.2 - Devices 4 - Low Frequency Spin-lock 4.1 - Spin-lock vs. -
On the Performance of MPI-Openmp on a 12 Nodes Multi-Core Cluster
On the Performance of MPI-OpenMP on a 12 nodes Multi-core Cluster Abdelgadir Tageldin Abdelgadir1, Al-Sakib Khan Pathan1∗ , Mohiuddin Ahmed2 1 Department of Computer Science, International Islamic University Malaysia, Gombak 53100, Kuala Lumpur, Malaysia 2 Department of Computer Network, Jazan University, Saudi Arabia [email protected] , [email protected] , [email protected] Abstract. With the increasing number of Quad-Core-based clusters and the introduction of compute nodes designed with large memory capacity shared by multiple cores, new problems related to scalability arise. In this paper, we analyze the overall performance of a cluster built with nodes having a dual Quad-Core Processor on each node. Some benchmark results are presented and some observations are mentioned when handling such processors on a benchmark test. A Quad-Core-based cluster's complexity arises from the fact that both local communication and network communications between the running processes need to be addressed. The potentials of an MPI-OpenMP approach are pinpointed because of its reduced communication overhead. At the end, we come to a conclusion that an MPI-OpenMP solution should be considered in such clusters since optimizing network communications between nodes is as important as optimizing local communications between processors in a multi-core cluster. Keywords: MPI-OpenMP, hybrid, Multi-Core, Cluster. 1 Introduction The integration of two or more processors within a single chip is an advanced technology for tackling the disadvantages exposed by a single core when it comes to increasing the speed, as more heat is generated and more power is consumed by those single cores. -
Benchmarking-HOWTO.Pdf
Linux Benchmarking HOWTO Linux Benchmarking HOWTO Table of Contents Linux Benchmarking HOWTO.........................................................................................................................1 by André D. Balsa, [email protected] ..............................................................................................1 1.Introduction ..........................................................................................................................................1 2.Benchmarking procedures and interpretation of results.......................................................................1 3.The Linux Benchmarking Toolkit (LBT).............................................................................................1 4.Example run and results........................................................................................................................2 5.Pitfalls and caveats of benchmarking ..................................................................................................2 6.FAQ .....................................................................................................................................................2 7.Copyright, acknowledgments and miscellaneous.................................................................................2 1.Introduction ..........................................................................................................................................2 1.1 Why is benchmarking so important ? ...............................................................................................3 -
IBM Z13 Server Technology
Introducing the IBM® z13™ Server Platform Structure and Performance Monte Bauman Enterprise Server Technical Support IBM Columbus [email protected] January 2015 IBM z Systems Agenda § Design Imperatives § The IBM z Systems z13 Server § The z13 Big Data Server 2 © 2015 IBM Corporation IBM z Systems Design Imperatives IBM z Systems Business Imperatives The Mobile Moment The Odds are High … Business Management is interested in... Enterprise § Promoting High Retention Rates and Capturing Class Competitive share through mobile interactions Cloud § Driving integrated/smart transactions that improve the Client Experience (e.g. Next Best Action) Business- Critical § Growing and Improving the IT services consumer Analytics experience within Existing Environmental Envelope Smart Transactions 4 © 2015 IBM Corporation IBM z Systems IBM z13 Design Primitives The IBM z13 Server was developed with the intent to: § Capture transaction growth through mobile enablement of existing systems § Drive integrated analytics at the time of the transaction § Deliver higher levels of Capacity and Performance within the Existing Environmental Envelope Enclave-Encapsulated Systems of Engagement Systems of Record Systems of Insight 5 © 2015 IBM Corporation IBM z Systems The IBM z13 Server 6 © 2015 IBM Corporation IBMIBM z Systems z13 platform positioning Platform Core Capabilities: Transaction Processing • The world’s premier transaction and data engine now enabled for Data Serving the mobile generation Mixed Workloads Operational Efficiency • The integrated transaction -
Exploring Coremark™ – a Benchmark Maximizing Simplicity and Efficacy by Shay Gal-On and Markus Levy
Exploring CoreMark™ – A Benchmark Maximizing Simplicity and Efficacy By Shay Gal-On and Markus Levy There have been many attempts to provide a single number that can totally quantify the ability of a CPU. Be it MHz, MOPS, MFLOPS - all are simple to derive but misleading when looking at actual performance potential. Dhrystone was the first attempt to tie a performance indicator, namely DMIPS, to execution of real code - a good attempt, which has long served the industry, but is no longer meaningful. BogoMIPS attempts to measure how fast a CPU can “do nothing”, for what that is worth. The need still exists for a simple and standardized benchmark that provides meaningful information about the CPU core - introducing CoreMark, available for free download from www.coremark.org. CoreMark ties a performance indicator to execution of simple code, but rather than being entirely arbitrary and synthetic, the code for the benchmark uses basic data structures and algorithms that are common in practically any application. Furthermore, EEMBC carefully chose the CoreMark implementation such that all computations are driven by run-time provided values to prevent code elimination during compile time optimization. CoreMark also sets specific rules about how to run the code and report results, thereby eliminating inconsistencies. CoreMark Composition To appreciate the value of CoreMark, it’s worthwhile to dissect its composition, which in general is comprised of lists, strings, and arrays (matrixes to be exact). Lists commonly exercise pointers and are also characterized by non-serial memory access patterns. In terms of testing the core of a CPU, list processing predominantly tests how fast data can be used to scan through the list. -
SIMD Processing on IBM Z14, Z13 and Z13s
with current compilers. String and character array processing, traditional loop and array SIMD Processing on IBM z14, z13 and z13s Background Companies want to quickly and efficiently processing with integer and floating point data process huge amounts of information for can all be accelerated using SIMD. Complex analytics, mobile applications, data serving and mathematical processing, algorithmic-intensive more. To cost-effectively achieve these programs, image processing applications, and efficiencies new innovative technologies are other applications can be efficiently processed needed. Vector processing and SIMD optimize with SIMD. SIMD also enables processing of a performance by processing data in parallel on new class of applications on IBM Z using ® IBM Z . analytics, mathematical optimization without requiring an offload to specialized processors. What is SIMD? Standard SIMD math and linear algebra libraries SIMD stands for Single Instruction Multiple Data. enable easier porting from X86 platforms. Unlike instructions which performs a single operation on a single data point, SIMD instructions Compilers can perform the same operation on multiple data SIMD helps you achieve efficiencies using IBM points at once. z/OS® XL C/C++ V2.1.1, IBM Enterprise COBOL 5.2 and IBM Enterprise PL/I for z/OS V4.5, for SIMD is an innovation that was delivered with applications with character or integer IBM z13® (z13) and IBM z13s™ (z13s). With SIMD manipulation. IBM z/OS XL C/C++ V2.1.1 entire arrays of data can be processed by a compilers offer new capabilities, such as single instruction enabling more efficient architecture sections, inline assembly, and high processing of data. -
A Multicore Computing Platform for Benchmarking
A MULTICORE COMPUTING PLATFORM FOR BENCHMARKING DYNAMIC PARTIAL RECONFIGURATION BASED DESIGNS by DAVID A. THORNDIKE Submitted in partial fulfillment of the requirements For the degree of Master of Science Thesis Advisor: Dr. Christos A. Papachristou Department of Electrical Engineering and Computer Science CASE WESTERN RESERVE UNIVERSITY August, 2012 CASE WESTERN RESERVE UNIVERSITY SCHOOL OF GRADUATE STUDIES We hereby approve the thesis/dissertation of David A. Thorndike candidate for the Master of Science degree *. (signed) Christos A.Papachristou (chair of the committee) Francis L. Merat Francis G. Wolff (date) June 1, 2012 *We also certify that written approval has been obtained for any proprietary material contained therein. Table of Contents List of Figures ................................................................................................................... iii List of Tables .................................................................................................................... iv Abstract .............................................................................................................................. v 1. Introduction .................................................................................................................. 1 1.1 Motivation .......................................................................................................... 1 1.2 Contributions ...................................................................................................... 2 1.3 Thesis Outline -
IBM Z13s Frequently Asked Questions
IBM z Systems Introduction April 2016 IBM z13s Frequently Asked Questions Worldwide ZSQ03076-USEN-09 1 Table of Contents z Systems Naming ........................................................................................................................................ 3 z13s Hardware .............................................................................................................................................. 4 z13 Hardware .............................................................................................................................................. 15 Performance ................................................................................................................................................ 24 z13 Warranty ............................................................................................................................................... 28 Hardware Management Console (HMC) ..................................................................................................... 30 Power requirements (including High Voltage DC Power option) ............................................................... 36 Overhead Cabling and Power ..................................................................................................................... 38 z13 Water cooling option ............................................................................................................................. 39 z Appliance Container Infrastructure - zACI ............................................................................................... -
IBM Z Systems Hardware - 2016 Technical Overview
IBM z Systems Hardware - 2016 Technical Overview Session B01 / C15 Walter Kläy, IMS SWAT Team [email protected] with support from Kevin Hite (SVL) and Silvia Mueller (BOB) © 2016 IBM Corporation Innovation never stops. …2016… Internet of things GA2 Cloud SMT MobileIMS Rockhopper z13s Mainframe Mainframe IBM SIMD Internet of things IBM IBMEmperor LinuxOne Cloud CloudInternet of things z13 Mobile Mobile 2 Digital Revolution Transform interactions World becoming smarter Personalized everything In the moment right now What is happening? 16 billion connected devices Infrastructure of the company 75 billion devices by 2020 Infrastructure of the city 7 billion smart phones Infrastructure of the world Respect and protect security and privacy 3 The market is moving, forcing businesses to transform Explosion in Analytics is Hybrid cloud is the transaction growth moving to real time new standard driven by mobility to capture new for delivering service, and the Internet of opportunities at the agility, trust and Things point of impact efficiency 4 z13 Overview © 2016 IBM Corporation IBM z Systems Evolution New Brand: LinuxOne 6 z13(s) Functions and Features (DGA Driver Level 22) System, Processor, Memory I/O Subsystem, Parallel Sysplex, STP, Security Five hardware models New PCIe Gen3 I/O fanouts with 16 GBps Buses Eight core 22nm PU SCM LCSS increased from 4 to 6 Up to 141 processors configurable as CPs, zIIPs, IFLs, ICFs, or optional SAPs 4th Subchannel Set per LCSS Increased Uni processor capacity z13 Maximum number of I/O Devices (subchannels) -
IBM Db2 12 for Z/OS Performance Topics
Front cover IBM Db2 12 for z/OS Performance Topics Akiko Hoshikawa Mai Nguyen Bart Steegmans Neena Cherian Bharat Verma Nguyen Dao Brian Baggett Ou Jin Chang Kim Peng Huang Chongchen Xu Ping Liang Chung Wu Robert Boon Cristian Molaro Todd Munk Jasmi Thekveli Xue Lian Zhang Kaitlin E. Murray Liang Zhang Lingyun Wang Redbooks International Technical Support Organization IBM Db2 12 for z/OS Performance Topics September 2017 SG24-8404-00 Note: Before using this information and the product it supports, read the information in “Notices” on page ix. First Edition (September 2017) © Copyright International Business Machines Corporation 2017. All rights reserved. Note to U.S. Government Users Restricted Rights -- Use, duplication or disclosure restricted by GSA ADP Schedule Contract with IBM Corp. Contents Notices . ix Trademarks . .x Preface . xi Authors. xi Now you can become a published author, too! . xiii Comments welcome. xiii Stay connected to IBM Redbooks . xiv Chapter 1. Introduction . 1 1.1 Overview . 2 1.1.1 Performance . 2 1.1.2 High-level expectations . 4 1.2 Db2 12 for z/OS performance features . 6 1.2.1 System-level performance . 6 1.2.2 Query performance improvement . 16 1.2.3 Access path stability for dynamic SQL statements . 17 1.3 Other key features in Db2 12 for z/OS . 18 1.3.1 Mobile application enablement . 18 1.3.2 Resiliency and continuous availability. 19 1.3.3 Simplified migration and continuous delivery support . 20 1.4 How to use this book . 21 1.4.1 Measurement environments . 22 Chapter 2. Scalability enhancements and subsystem performance . -
NOEL-XCKU-EX Quick Start Guide
NOEL-XCKU-EX Quick Start Guide. 2020 User's Manual The most important thing we build is trust NOEL-XCKU-EX Quick Start Guide NOEL-XCKU-EX-QSG 1 www.cobhamaes.com/gaisler June 2020, Version 1.1 Table of Contents 1. Introduction .......................................................................................................................... 4 1.1. Overview ................................................................................................................... 4 1.2. Availability ................................................................................................................ 4 1.3. Prerequisites ............................................................................................................... 4 1.4. References .................................................................................................................. 4 2. Overview .............................................................................................................................. 5 2.1. Boards ....................................................................................................................... 5 2.2. Design summary ......................................................................................................... 5 2.3. Processor features ........................................................................................................ 5 2.4. Software Development Environment ............................................................................... 5 2.4.1. RTEMS ..........................................................................................................