Scheduling on Clouds Considering Energy Consumption and Performance Trade-Offs : from Modelization to Industrial Applications Daniel Balouek-Thomert
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Energy Efficient Spin-Locking in Multi-Core Machines
Energy efficient spin-locking in multi-core machines Facoltà di INGEGNERIA DELL'INFORMAZIONE, INFORMATICA E STATISTICA Corso di laurea in INGEGNERIA INFORMATICA - ENGINEERING IN COMPUTER SCIENCE - LM Cattedra di Advanced Operating Systems and Virtualization Candidato Salvatore Rivieccio 1405255 Relatore Correlatore Francesco Quaglia Pierangelo Di Sanzo A/A 2015/2016 !1 0 - Abstract In this thesis I will show an implementation of spin-locks that works in an energy efficient fashion, exploiting the capability of last generation hardware and new software components in order to rise or reduce the CPU frequency when running spinlock operation. In particular this work consists in a linux kernel module and a user-space program that make possible to run with the lowest frequency admissible when a thread is spin-locking, waiting to enter a critical section. These changes are thread-grain, which means that only interested threads are affected whereas the system keeps running as usual. Standard libraries’ spinlocks do not provide energy efficiency support, those kind of optimizations are related to the application behaviors or to kernel-level solutions, like governors. !2 Table of Contents List of Figures pag List of Tables pag 0 - Abstract pag 3 1 - Energy-efficient Computing pag 4 1.1 - TDP and Turbo Mode pag 4 1.2 - RAPL pag 6 1.3 - Combined Components 2 - The Linux Architectures pag 7 2.1 - The Kernel 2.3 - System Libraries pag 8 2.3 - System Tools pag 9 3 - Into the Core 3.1 - The Ring Model 3.2 - Devices 4 - Low Frequency Spin-lock 4.1 - Spin-lock vs. -
On the Performance of MPI-Openmp on a 12 Nodes Multi-Core Cluster
On the Performance of MPI-OpenMP on a 12 nodes Multi-core Cluster Abdelgadir Tageldin Abdelgadir1, Al-Sakib Khan Pathan1∗ , Mohiuddin Ahmed2 1 Department of Computer Science, International Islamic University Malaysia, Gombak 53100, Kuala Lumpur, Malaysia 2 Department of Computer Network, Jazan University, Saudi Arabia [email protected] , [email protected] , [email protected] Abstract. With the increasing number of Quad-Core-based clusters and the introduction of compute nodes designed with large memory capacity shared by multiple cores, new problems related to scalability arise. In this paper, we analyze the overall performance of a cluster built with nodes having a dual Quad-Core Processor on each node. Some benchmark results are presented and some observations are mentioned when handling such processors on a benchmark test. A Quad-Core-based cluster's complexity arises from the fact that both local communication and network communications between the running processes need to be addressed. The potentials of an MPI-OpenMP approach are pinpointed because of its reduced communication overhead. At the end, we come to a conclusion that an MPI-OpenMP solution should be considered in such clusters since optimizing network communications between nodes is as important as optimizing local communications between processors in a multi-core cluster. Keywords: MPI-OpenMP, hybrid, Multi-Core, Cluster. 1 Introduction The integration of two or more processors within a single chip is an advanced technology for tackling the disadvantages exposed by a single core when it comes to increasing the speed, as more heat is generated and more power is consumed by those single cores. -
Benchmarking-HOWTO.Pdf
Linux Benchmarking HOWTO Linux Benchmarking HOWTO Table of Contents Linux Benchmarking HOWTO.........................................................................................................................1 by André D. Balsa, [email protected] ..............................................................................................1 1.Introduction ..........................................................................................................................................1 2.Benchmarking procedures and interpretation of results.......................................................................1 3.The Linux Benchmarking Toolkit (LBT).............................................................................................1 4.Example run and results........................................................................................................................2 5.Pitfalls and caveats of benchmarking ..................................................................................................2 6.FAQ .....................................................................................................................................................2 7.Copyright, acknowledgments and miscellaneous.................................................................................2 1.Introduction ..........................................................................................................................................2 1.1 Why is benchmarking so important ? ...............................................................................................3 -
Exploring Coremark™ – a Benchmark Maximizing Simplicity and Efficacy by Shay Gal-On and Markus Levy
Exploring CoreMark™ – A Benchmark Maximizing Simplicity and Efficacy By Shay Gal-On and Markus Levy There have been many attempts to provide a single number that can totally quantify the ability of a CPU. Be it MHz, MOPS, MFLOPS - all are simple to derive but misleading when looking at actual performance potential. Dhrystone was the first attempt to tie a performance indicator, namely DMIPS, to execution of real code - a good attempt, which has long served the industry, but is no longer meaningful. BogoMIPS attempts to measure how fast a CPU can “do nothing”, for what that is worth. The need still exists for a simple and standardized benchmark that provides meaningful information about the CPU core - introducing CoreMark, available for free download from www.coremark.org. CoreMark ties a performance indicator to execution of simple code, but rather than being entirely arbitrary and synthetic, the code for the benchmark uses basic data structures and algorithms that are common in practically any application. Furthermore, EEMBC carefully chose the CoreMark implementation such that all computations are driven by run-time provided values to prevent code elimination during compile time optimization. CoreMark also sets specific rules about how to run the code and report results, thereby eliminating inconsistencies. CoreMark Composition To appreciate the value of CoreMark, it’s worthwhile to dissect its composition, which in general is comprised of lists, strings, and arrays (matrixes to be exact). Lists commonly exercise pointers and are also characterized by non-serial memory access patterns. In terms of testing the core of a CPU, list processing predominantly tests how fast data can be used to scan through the list. -
Linux on IBM Z13:Performance Aspects of New Technology And
Linux on IBM z13: Performance Aspects of New Technology and Features Mario Held ([email protected]) Linux on z Systems Performance Analyst IBM Corporation Session 17772 August 13, 2015 Trademarks The following are trademarks of the International Business Machines Corporation in the United States and/or other countries. BlueMix ECKD IBM* Maximo* Smarter Cities* WebSphere* z Systems BigInsights FICON* Ibm.com MQSeries* Smarter Analytics XIV* z/VSE* Cognos* FileNet* IBM (logo)* Performance Toolkit for VM SPSS* z13 z/VM* DB2* FlashSystem IMS POWER* Storwize* zEnterprise* DB2 Connect GDPS* Informix* Quickr* System Storage* z/OS* Domino* GPFS InfoSphere Rational* Tivoli* DS8000* Sametime* * Registered trademarks of IBM Corporation The following are trademarks or registered trademarks of other companies. Adobe, the Adobe logo, PostScript, and the PostScript logo are either registered trademarks or trademarks of Adobe Systems Incorporated in the United States, and/or other countries. IT Infrastructure Library is a registered trademark of the Central Computer and Telecommunications Agency which is now part of the Office of Government Commerce. Intel, Intel logo, Intel Inside, Intel Inside logo, Intel Centrino, Intel Centrino logo, Celeron, Intel Xeon, Intel SpeedStep, Itanium, and Pentium are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. Linux is a registered trademark of Linus Torvalds in the United States, other countries, or both. Microsoft, Windows, Windows NT, and the Windows logo are trademarks of Microsoft Corporation in the United States, other countries, or both. Windows Server and the Windows logo are trademarks of the Microsoft group of countries. ITIL is a registered trademark, and a registered community trademark of the Office of Government Commerce, and is registered in the U.S. -
A Multicore Computing Platform for Benchmarking
A MULTICORE COMPUTING PLATFORM FOR BENCHMARKING DYNAMIC PARTIAL RECONFIGURATION BASED DESIGNS by DAVID A. THORNDIKE Submitted in partial fulfillment of the requirements For the degree of Master of Science Thesis Advisor: Dr. Christos A. Papachristou Department of Electrical Engineering and Computer Science CASE WESTERN RESERVE UNIVERSITY August, 2012 CASE WESTERN RESERVE UNIVERSITY SCHOOL OF GRADUATE STUDIES We hereby approve the thesis/dissertation of David A. Thorndike candidate for the Master of Science degree *. (signed) Christos A.Papachristou (chair of the committee) Francis L. Merat Francis G. Wolff (date) June 1, 2012 *We also certify that written approval has been obtained for any proprietary material contained therein. Table of Contents List of Figures ................................................................................................................... iii List of Tables .................................................................................................................... iv Abstract .............................................................................................................................. v 1. Introduction .................................................................................................................. 1 1.1 Motivation .......................................................................................................... 1 1.2 Contributions ...................................................................................................... 2 1.3 Thesis Outline -
NOEL-XCKU-EX Quick Start Guide
NOEL-XCKU-EX Quick Start Guide. 2020 User's Manual The most important thing we build is trust NOEL-XCKU-EX Quick Start Guide NOEL-XCKU-EX-QSG 1 www.cobhamaes.com/gaisler June 2020, Version 1.1 Table of Contents 1. Introduction .......................................................................................................................... 4 1.1. Overview ................................................................................................................... 4 1.2. Availability ................................................................................................................ 4 1.3. Prerequisites ............................................................................................................... 4 1.4. References .................................................................................................................. 4 2. Overview .............................................................................................................................. 5 2.1. Boards ....................................................................................................................... 5 2.2. Design summary ......................................................................................................... 5 2.3. Processor features ........................................................................................................ 5 2.4. Software Development Environment ............................................................................... 5 2.4.1. RTEMS .......................................................................................................... -
A Comparison of Complete Global Optimization Solvers
A comparison of complete global optimization solvers Arnold Neumaier Oleg Shcherbina Waltraud Huyer Institut furÄ Mathematik, UniversitÄat Wien Nordbergstr. 15, A-1090 Wien, Austria Tam¶as Vink¶o Research Group on Arti¯cial Intelligence of the Hungarian Academy of Sciences and University of Szeged, H-6720 Szeged, Aradi v¶ertanuk¶ tere 1., Hungary Please send correspondence to: [email protected] Abstract. Results are reported of testing a number of existing state of the art solvers for global constrained optimization and constraint satisfaction on a set of over 1000 test problems in up to 1000 variables. 1 Overview As the recent survey Neumaier [24] of complete solution techniques in global optimization documents, there are now about a dozen solvers for constrained global optimization that claim to solve global optimization and/or constraint satisfaction problems to global optimality by performing a complete search. Within the COCONUT project [30, 31], we evaluated many of the existing software packages for global optimization and constraint satisfaction prob- lems. This is the ¯rst time that di®erent constrained global optimization and constraint satisfaction algorithms are compared on a systematic basis and with a test set that allows to derive statistically signi¯cant conclusions. We tested the global solvers BARON, GlobSol, ICOS, LGO, LINGO, OQNLP, Premium Solver, the local solver MINOS, and a basic combination strategy COCOS implemented in the COCONUT platform. 1 The testing process turned out to be extremely time-consuming, due to var- ious reasons not initially anticipated. A lot of e®ort went into creating ap- propriate interfaces, making the comparison fair and reliable, and making it possible to process a large number of test examples in a semiautomatic fashion. -
Measuring Performance
Computer Architecture 10 Measuring Performance Made wi th OpenOffi ce.org 1 Performance Measurement FactorsFactors influencinginfluencing thethe performanceperformance ofof modernmodern computerscomputers pure microelectronic & CPU architecture issues I/O performance interprocessor communication cache coherence memory hierarchy Amdahl's law FieldField ofof computercomputer applicationapplication dedicated/specific tasks general-purpose Made wi th OpenOffi ce.org 2 MIPS MeasureMeasure ofof aa computer'scomputer's processorprocessor speedspeed inin (Millions)(Millions) InstructionsInstructions PerPer SecondSecond historically the oldest, straightforward and naïve rated to 1MIPS VAX 11/780 in the 70's (0.5MIPS) direct correlation with clock speed strong influence of instruction set CISC/RISC & Cache misunderstandings Meaningless Indication of Processor Speed Meaningless Information on Performance for Salespeople Made wi th OpenOffi ce.org 3 MIPS poor,poor, but...but... gives some elementary performance overview very good to compare the CPU's with: ● the same instruction set ● the same reference code ● built with the same compiler important for microcontrollers to estimate the resource-management abilities BogoMips ("bogus" MIPS) is a measurement of CPU speed made by the Linux kernel when it boots, to calibrate an internal busy-loop and cache effect Made wi th OpenOffi ce.org 4 MIPS – Examples ١٩٧٤ 640 kIPS at 2 MHz ٨٠٨٠ Intel ١٩٧٧ 500 kIPS ٧٨٠/١١ VAX ١٩٧٩ MHz ٨ MIPS at ١ ٦٨٠٠٠ Motorola ١٩٨٨ MHz ٢٥ MIPS at ٨.٥ ٣٨٦DX Intel ١٩٩٢ MHz ٦٦ MIPS -
Linux All-In-One for Dummies CHAPTER 3: Commanding the Shell
Linux ® ALL-IN-ONE Linux ® ALL-IN-ONE 6th Edition by Emmett Dulaney Linux® All-in-One For Dummies®, 6th Edition Published by: John Wiley & Sons, Inc., 111 River Street, Hoboken, NJ 07030-5774, www.wiley.com Copyright © 2018 by John Wiley & Sons, Inc., Hoboken, New Jersey Published simultaneously in Canada No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning or otherwise, except as permitted under Sections 107 or 108 of the 1976 United States Copyright Act, without the prior written permission of the Publisher. Requests to the Publisher for permission should be addressed to the Permissions Department, John Wiley & Sons, Inc., 111 River Street, Hoboken, NJ 07030, (201) 748-6011, fax (201) 748-6008, or online at http://www.wiley.com/go/ permissions. Trademarks: Wiley, For Dummies, the Dummies Man logo, Dummies.com, Making Everything Easier, and related trade dress are trademarks or registered trademarks of John Wiley & Sons, Inc. and may not be used without written permission. Linux is a registered trademark of Linus Torvalds. All other trademarks are the property of their respective owners. John Wiley & Sons, Inc. is not associated with any product or vendor mentioned in this book. LIMIT OF LIABILITY/DISCLAIMER OF WARRANTY: THE PUBLISHER AND THE AUTHOR MAKE NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS WORK AND SPECIFICALLY DISCLAIM ALL WARRANTIES, INCLUDING WITHOUT LIMITATION WARRANTIES OF FITNESS FOR A PARTICULAR PURPOSE. NO WARRANTY MAY BE CREATED OR EXTENDED BY SALES OR PROMOTIONAL MATERIALS. -
Mini-HOWTO Bogomips
Mini-HOWTO BogoMips Wim van Dorst, [email protected] v0, 8 f´evrier 1999 Ce texte donne des renseignements sur les BogoMips, tir´es de diverses sources comme les News ou de courriers ´electroniques personnels. Vous pouvez trouver l’original de ce mini-HOWTO dans les diff´erentesarchives Linux sous le r´epertoire .../HOWTO/mini/BogoMips . La traductions de ce document est a priori disponible sur les archives appropri´ees en japonais, italien, allemand, polonais et portugais. Un article explicatif complet intitul´e ’the Quintessential Linux Benchmark,’ a ´et´epubli´edans le num´erode janvier 1996 du Linux Journal(tm). De nouvelles entr´ees pour les processeurs non r´ef´erenc´esseraient grandement appr´eci´ees. Elles peuvent ˆetre envoy´ees par e-mail `al’auteur. Traduction du 04 mars 1999 par Antoine Levavasseur <[email protected]> Contents 1 Les scores Bogomips records des syst`emes mono-processeur 2 1.1 Le plus faible score BogoMips au boot de Linux .......................... 2 1.2 Le meilleur score BogoMips au boot d’un Linux mono-processeur ................ 2 1.3 Le meilleur score BogoMips au boot d’un Linux multi-processeur ................ 2 1.4 Le meilleur score BogoMips non-Linux ............................... 2 2 Que sont les BogoMips ? 3 3 Comment calculer quelle devrait ˆetreune vitesse en BogoMips ? 3 4 Comment savoir quelle est la vitesse en BogoMips ? 4 5 Fluctuation dans la mesure des BogoMips 5 6 BogoMips ... failed 5 7 A` propos des processeurs clones (Cyrix, NexGen, AMD, etc.) 6 8 Pourquoi se pr´eoccuper des BogoMips ? 6 9 Compilation de mesures 6 9.1 386, bizarrement ou mal configur´es ................................ -
A Framework for Investigating Workload Interactions on Multicore Systems
A Framework for Investigating Workload Interactions on Multicore Systems by Eric Charles Matthews B.A.Sc., Simon Fraser University, 2009 Thesis submitted in partial fulfillment of the requirements for the degree of Master of Applied Science In the School of Engineering Science © Eric Charles Matthews 2012 SIMON FRASER UNIVERSITY Spring 2012 All rights reserved. However, in accordance with the Copyright Act of Canada, this work may be reproduced, without authorization, under the conditions for “Fair Dealing.” Therefore, limited reproduction of this work for the purposes of private study, research, criticism, review, and news reporting is likely to be in accordance with the law, particularly if cited appropriately. APPROVAL Name: Eric Charles Matthews Degree: Master of Applied Science Title of Thesis: A Framework for Investigating Workload Interactions on Multicore Systems Examining Committee: Dr. Bonnie Gray, P.Eng. Associate Professor of Engineering Science Chair Dr. Lesley Shannon, P.Eng. Assistant Professor of Engineering Science Senior Supervisor Dr. Alexandra Fedorova Assistant Professor of Computing Science Supervisor Dr. Arrvindh Shriraman Assistant Professor of Computing Science Examiner Date Defended: ii. Partial Copyright Licence Abstract Multicore processor systems are everywhere today, targeting markets from the high-end server space to the embedded systems domain. Despite their prevalence, predicting the performance of workloads on these systems is difficult due to a lack of visibility into the various runtime interactions for shared resources. At the same time, existing support in processors for performance monitoring is primarily limited to capturing single events and thus cannot provide the depth of information required to predict dynamic workload interactions. This thesis presents a configurable and scalable multicore system framework for enabling new avenues for systems and architectural research.