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Intel®Server Boards S2400LP Intel® Server Boards S2400LP Technical Product Specification Intel order number G52803-002 Revision 2.0 December 2013 Platform Collaboration and Systems Division - Marketing Revision History Intel® Server Boards S2400LP TPS Revision History Date Revision Modifications Number May 2012 1.0 Initial release. December 2013 2.0 Added support for Intel® Xeon® processor E5-2400 v2 product family ii Intel order number G52803-002 Revision 2.0 Intel® Server Boards S2400LP TPS Disclaimers Disclaimers INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. A "Mission Critical Application" is any application in which failure of the Intel Product could result, directly or indirectly, in personal injury or death. SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND EMPLOYEES OF EACH, HARMLESS AGAINST ALL CLAIMS COSTS, DAMAGES, AND EXPENSES AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM OF PRODUCT LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined". Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information. The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725, or go to: http://www.intel.com/design/literature. Revision 2.0 Intel order number G52803-002 iii Table of Contents Intel® Server Boards S2400LP TPS Table of Contents 1. Introduction ........................................................................................................................ 1 1.1 Section Outline ....................................................................................................... 1 1.2 Server Board Use Disclaimer ................................................................................. 2 2. Server Board Overview ...................................................................................................... 3 2.1 Server Board Connector and Component Layout ................................................... 5 2.1.1 Board Rear Connector Placement .......................................................................... 5 2.2 Server Board Mechanical Drawings ....................................................................... 6 3. Product Architecture Overview ......................................................................................... 8 3.1 High Level Product Features .................................................................................. 8 3.2 Processor Support ................................................................................................. 9 3.2.1 Processor Socket Assembly ................................................................................... 9 3.2.2 Processor Population Rules ................................................................................. 10 3.3 Processor Functions Overview ............................................................................. 13 3.3.1 Intel® QuickPath Interconnect ............................................................................... 13 3.3.2 Integrated Memory Controller (IMC) and Memory Subsystem .............................. 14 3.3.2.1 Supported Memory ............................................................................................ 15 3.3.2.2 Memory Population Rules .................................................................................. 17 3.3.2.3 Publishing System Memory ............................................................................... 18 3.3.2.4 RAS Features .................................................................................................... 18 3.3.3 Processor Integrated I/O Module (IIO) .................................................................. 19 3.3.3.1 Riser Card Support ............................................................................................ 20 3.3.3.2 Riser Types ....................................................................................................... 21 3.3.3.3 Network Interface .............................................................................................. 22 3.3.3.4 I/O Module Support ........................................................................................... 23 3.4 Intel® C600-A/B PCH Functional Overview ........................................................... 23 3.4.1 PCI Express* ........................................................................................................ 24 3.4.2 Universal Serial Bus (USB) .................................................................................. 24 3.4.3 Serial Attached SCSI(SAS) and Serial ATA(SATA) Controller .............................. 25 3.4.4 PCI Interface ........................................................................................................ 26 3.4.5 Low Pin Count (LPC) Interface ............................................................................. 26 3.4.6 Digital Media Interface (DMI) ................................................................................ 26 3.4.7 Serials Peripheral Interface (SPI) ......................................................................... 26 3.4.8 Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller) ..... 26 3.4.9 Advanced Programmable Interrupt Controller (APIC) ........................................... 27 3.4.10 Real Time Clock (RTC) ........................................................................................ 27 3.4.11 GPIO .................................................................................................................... 27 3.4.12 Enhanced Power Management ............................................................................ 27 3.4.13 Fan Speed Control ............................................................................................... 27 3.4.14 Intel® Virtualization Technology for Direct I/O (Intel® VT-d) ................................... 28 3.4.15 KVM/Serial Over LAN (SOL) Function .................................................................. 28 3.4.16 IDE-R Function ..................................................................................................... 28 iv Intel order number G52803-002 Revision 2.0 Intel® Server Boards S2400LP TPS Table of Contents 3.4.17 Manageability ....................................................................................................... 28 3.4.18 System Management Bus (SMBus* 2.0) .............................................................. 29 3.4.19 Network Interface Controller (NIC) ....................................................................... 29 3.4.19.1 MAC Address Definition (TBD) ........................................................................ 30 3.4.19.2 LAN Manageability .......................................................................................... 30 3.4.19.3 Wake-On-LAN ................................................................................................. 31 3.4.19.4 LAN Connector Ordering ................................................................................. 31 3.4.19.5 Intel® I350 Thermal Sensor .............................................................................. 31 3.5 InfiniBand* Controller ........................................................................................... 31 3.5.1 Device Interfaces ................................................................................................. 32 3.5.2 Quad Small Form-factor Pluggable (QSFP) connector ......................................... 32 3.6 Baseboard Management Controller Overview ...................................................... 33 3.6.1 Super I/O Controller ............................................................................................. 35 3.6.1.1 Keyboard and Mouse Support ........................................................................... 35 3.6.1.2 Wake-up Control ...............................................................................................
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