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Intel's Core Family – the TICK Lines Penryn to Broadwell

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Intel’s Core family – the TICK lines Penryn to Broadwell Dezső Sima Vers. 1.0 September 2015 Contents • 1. Introduction • 2. The Penryn line • 3. The Westmere line • 4. The Ivy Bridge line • 5. The Broadwell line • 6. The Kannon Lake line 1. Introduction 1. Introduction (1) 1. Introduction The evolution of Intel’s basic Core family 1. gen. 2. gen. 3. gen. 4. gen. 5. gen. 6. gen. Core 2 Penryn Nehalem West- Sandy Ivy Haswell Broad- Skylake mere Bridge Bridge well New New New New New New New New New Microarch. Process Microarch. Microarchi. Microarchi. Process Microarch. Process Process 65 nm 45 nm 45 nm 32 nm 32 nm 22 nm 22 nm 14 nm 14 nm TOCK TICK TOCK TICK TOCK TICK TOCK TICK TOCK Figure 1.1: Intel’s Tick-Tock development model (Based on [1]) 1. Introduction (2) Intel’s Tick-Tock model Key new features of the ISP and the microarchitecture TICK 180nm 11/2000 TOCK Pentium 4 /Willamette New microarch. 2 YEARS TICK New microarch., Pentium 4 /Northwood 130nm 01/2002 TOCK hyperthreading (HT) 2 YEARS TICK New microarch., Pentium 4 /Prescott 90nm 02/2004 TOCK 64-bit 2 YEARS TICK Pentium 4 / Cedar Mill 01/2006 65nm New microarch.: 4-wide core, TOCK Core 2 07/2006 2 YEARS 128-bit SIMD/FP, shared L2 , no HT TICK Penryn Family 11/2007 45nm New microarch.: integrated MC, QPI, TOCK Nehalem 2 YEARS 11/2008 (inclusive) L3, HT TICK Westmere 01/2010 In package integr. GPU 32nm New microarch.: 256-bit AVX, TOCK Sandy Bridge 01/2011 2 YEARS ring bus, integr. GPU TICK Ivy Bridge 04/2012 22nm AVX2, TOCK Haswell 2 YEARS 06/2013 L4 cache (discrete eDRAM), FIVR TICK Broadwell 09/2014 Shared Virtual Memory 14nm ISP, TOCK Skylake 08/2015 2 YEARS Memory Side $ (eDRAM), No FIVR Figure : Overview of Intel’s Tick-Tock model (Based on [3]) 2. The Penryn line • 2.1 Introduction • 2.2 Key enhancement of the Penryn line vs. the Core 2 • 2.2.1 More advanced digital media support • 2.2.2 More advanced power management • 2.3 Overview of Penryn based processor lines 2.1 IntroductionPenryn () (1) 2.1 Introduction Penryn Basically a shrink (tick) from the 65 nm Core to 45 nm with a few microarchitectural and ISA enhancements, discussed subsequently. Introduced in 11/2007. Figure 4.1.1: Intel’s Tick-Tock development model (Based on [1]) 1. gen. 2. gen. 3. gen. 4. gen. 5. gen. 6. gen. Core 2 Penryn Nehalem West- Sandy Ivy Haswell Broad- Skylake mere Bridge Bridge well New New New New New New New New New Microarch. Process Microarch. Microarchi. Microarchi. Process Microarch. Process Process 65 nm 45 nm 45 nm 32 nm 32 nm 22 nm 22 nm 14 nm 14 nm TOCK TICK TOCK TICK TOCK TICK TOCK TICK TOCK Figure : Intel’s Tick-Tock development model (Based on [1]) 2.1 Introduction (2) Dynamic and static power dissipation trends in chips [21] Sub-threshold = Source-Drain 2.1 Introduction (3) Structure of a high-k + metal gate transistor [23] 2.1 Introduction (4) Benefits of high-k + metal gate transistors [23], [24] 2.1 Introduction (5) The 45 nm Penryn as a shrink of the 65 nm Core 2 with a few enhancements [25] Core 2 Quad: 2 x Core 2 2 x Penryn 2.2 Key enhancements of Penryn line (1) 2.2 Key enhancements of the Penryn line vs the Core 2 (based on [25]) Fast Radix-16 Divider Large shared L2 cache Intel SSE4 ISA Extension Super Shuffle Engine 2.2.1 More advanced digital media support (1) 2.2.1 More advanced digital media support Introduction of the SSE4.1 ISA extension, as indicated in the next Figure. 2.2.1 More advanced digital media support (2) Intel’s x86 ISA extensions - the operations introduced (based on [17]) 64-bit FX SIMD with 32/16/8-bit operands (ops) Support of MM 128-bit FX, FP SIMD with 32/16/8-bit FX, 32-bit FP ops. Support of MM/3D 128-bit FX, FP SIMD with 64/32/16/8-bit FX, 64/32-bit FP, Support for MPEG-2, video, MP3 NorthwoodNorhwood (Pentium4) DSP-oriented FP enhancements, enhanced thread manipulation Diverse arithmetic enhancements Media acceleration (video encoding, MM, gaming) Accelerated string/text manip., appl. targeted acceleration Accelerated encription operations 256-bit FX, FP SIMD with 64/32/16/8-bit FX, 64/32-bit FP????, Ivy Bridge 2.2.2 More advanced power management (1) 2.2.2 More advanced power management • Deep Power Down (DPD) technology • Enhanced Dynamic Acceleration (EDAT) available only on mobile platforms. (Both techniques became introduced in Nehalem for general use)! 2.2.2 More advanced power management (2) The Deep Power Down technology (DPD) [26] (First Introduced in the Core Duo (3. core of the Pentium M line) • Intelligent heuristics decides when enter into. 2.2.2 More advanced power management (3) Operation of Intel’s Deep Power Down technology [27] (OS API WAIT) 2.2.2 More advanced power management (4) Power reduction achieved by the Deep Power Down Technology [27] 2.2.2 More advanced power management (5) Enhanced Dynamic Acceleration Technology (EDAT) (for mobiles) Principle of EDAT in the dual core Penryn processors [27] 2.2.2 More advanced power management (6) Remark Intel’s next basic core, the Nehalem includes a more advanced technology than the Enhanced Dynamic Acceleration Technology, called the Turbo Boost Technology for increasing clock frequency in case of inactive cores or light workloads. 2.2.2 More advanced power management (7) Overall performance achievements of Penryn vs. Core 2 at the same clock rate [26 2.3 Overview of Penryn based processor lines (1) 2.3 Overview of Penryn based processor lines Mobiles Core 2 Extreme Mobile X9000, Penryn-3C, 2C, 1/2008 Core 2 Duo T8xxx/T9xxx, Penryn-3M, 2C, 1/2008 Core 2 Duo T6xxx, Penryn-3M, 2C, 1/2009 Core 2 Quad Q9xxx, Penryn QC, 2x2C, (2xPenryn-3M), 8/2008 Desktops Core 2 Duo E8xxx, Wolfdale, 2C, 1/2008 Core 2 Duo E7xxx, Wolfdale-3M, 2C, 4/2008 Core 2 Quad Q9xxx, Yorkfield-6M, 2x2C, (2x Wolfdale-3M), 3/2008 Core 2 Quad Q8xxx, Yorkfield-6M, 2x2C, (2x Wolfdale-3M), 8/2008 Core 2 Extreme QX9xxx, Yorkfield XE, 2x2C (2x Wolfdale), 11/2007 Servers UP-Servers E31xx Wolfdale, 2C, 1/2008 X33xx, Yorkfield-6M, 2x2C, (2xWolfdale), 1/2008 X33xx, Yorkfield, (2xWolfdale), 2x2C, 1/2008 DP-Servers E52xx, Wolfdale, 2C, 11/2007 E54xx/X54xx, Harpertown 2x2C, (2xWolfdale), 11/2007 MP-Servers E74xx, 4C/6C, Dunnington, 9/2008 Based on [43] https://techreport.com/review/14882/intel-p45-express-chipset 3. The Westmere lines • 3.1 Introduction 3.2 Key enhancements of the Westmere lines vs. • the Nehalem lines • 3.3 Dual-core Westmere-based mobile/desktop lines • 3.3.1 Overview 3.3.2 Innovations and enhancements of the • dual-core mobile/desktop lines • 3.4 The six core Westmere-based desktop line 3.1 Introduction (1) 3.1 Introduction • Westmere (formerly Nehalem-C) is the 32 nm die shrink of Nehalem • First Westmere-based processors were launched in 1/2010 • In-package integrated CPU/GPU 3.1 Introduction (2) Westmere family Westmere lines Westmere-EX lines (only servers) This Section Mobiles Core i3-3xxM Arrandale 2C+G 1/2010 Core i5-4xxM Arrandale 2C+G 1/2010 Core i5-5xxM Arrandale 2C+G 1/2010 Core i7-6xxM Arrandale 2C+G 1/2010 Desktops Core i3-5xx Clarkdale 2C+G 1/2010 Core i5-6xx Clarkdale 2C+G 1/2010 Core i7-970/980/980X/990X Gulftown 6C 3/2010 Servers UP-Servers UP-Servers 36xx Gulftown (Westmere-EP) 6C 3/2010 E7-28xx Westmere-EX 10C 4/2011 DP-Servers DP-Servers 56xx Gulftown (Westmere-EP) 6C 3/2010 E7-28xx Westmere-EX 10C 4/2011 MP-Servers E7-48xx Westmere-EX 10C 4/2011 E7-88xx Westmere-EX 10C 4/2011 Data based on [44] 3.1 Introduction (3) Westmere 2-core and 6-core die plots [57] 2-core die plot 6-core die plot 248 mm2, 1.17 billion transistors) Arrandale (mobile) Gulftown (desktop, Westmere-EP UP/DP server) Clarkdale (desktop) 3.2 Key enhancements of the Westmere lines vs. the Nehalem lines (1) 3.2 Key enhancements of the Westmere lines vs. the Nehalem lines [44] • Over 100 incremental improvements in the microarchitecture [58] (not discussed here). • Enhanced support for AES (Advanced Encryption Standard) by providing a set of instructions to perform hardware accelerated encryption/decryption (not discussed here). • Enhanced support for virtualization (not discussed here). 3.2 Key enhancements of the Westmere lines vs. the Nehalem lines (2) Overview of the Westmere lines Westmere lines Dual-core Six-core Six core mobile/desktop lines desktop line Westmere-EP server lines Section 3.3 Section 3.4 Section 3.5 3.3.1 Overview (1) 3.3 Dual-core Westmere-based mobile/desktop lines 3.3.1 Overview Dual-core Westmere-based mobile/desktop lines Mobile lines Desktop lines Arrandale lines Clarkdale lines i3 3xxM 2C i3 5xx 2C i5 4xx/5xx 2C i5 6xx 2C i7 6xx 2C 3.3.2 Innovations and enhancements of the dual-core mobile/desktop lines (1) 3.3.2 Innovations and enhancements of the dual-core mobile/desktop lines 3.3.2.1 Overview • In-package integrated CPU/GPU for the 2 core mobile and desktop segments (Section 3.3.2.2). • Enhanced Turbo Boost technology in the dual-core mobile Arrandale line (Section 3.3.2.3).
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    Case 3:20-cv-00863-SI Document 1 Filed 05/29/20 Page 1 of 279 Steve D. Larson, OSB No. 863540 Email: [email protected] Jennifer S. Wagner, OSB No. 024470 Email: [email protected] STOLL STOLL BERNE LOKTING & SHLACHTER P.C. 209 SW Oak Street, Suite 500 Portland, Oregon 97204 Telephone: (503) 227-1600 Attorneys for Plaintiffs [Additional Counsel Listed on Signature Page.] UNITED STATES DISTRICT COURT DISTRICT OF OREGON PORTLAND DIVISION BLUE PEAK HOSTING, LLC, PAMELA Case No. GREEN, TITI RICAFORT, MARGARITE SIMPSON, and MICHAEL NELSON, on behalf of CLASS ACTION ALLEGATION themselves and all others similarly situated, COMPLAINT Plaintiffs, DEMAND FOR JURY TRIAL v. INTEL CORPORATION, a Delaware corporation, Defendant. CLASS ACTION ALLEGATION COMPLAINT Case 3:20-cv-00863-SI Document 1 Filed 05/29/20 Page 2 of 279 Plaintiffs Blue Peak Hosting, LLC, Pamela Green, Titi Ricafort, Margarite Sampson, and Michael Nelson, individually and on behalf of the members of the Class defined below, allege the following against Defendant Intel Corporation (“Intel” or “the Company”), based upon personal knowledge with respect to themselves and on information and belief derived from, among other things, the investigation of counsel and review of public documents as to all other matters. INTRODUCTION 1. Despite Intel’s intentional concealment of specific design choices that it long knew rendered its central processing units (“CPUs” or “processors”) unsecure, it was only in January 2018 that it was first revealed to the public that Intel’s CPUs have significant security vulnerabilities that gave unauthorized program instructions access to protected data. 2. A CPU is the “brain” in every computer and mobile device and processes all of the essential applications, including the handling of confidential information such as passwords and encryption keys.