Programmable Implementation Technologies

Introduction to Digital Logic Course Outline

1. Digital Computers, Number Systems, Arithmetic Operations, Decimal, Alphanumeric, and Gray Codes 2. Binary Logic, Gates, Boolean Algebra, Standard Forms 3. Circuit Optimization, Two-Level Optimization, Map Manipulation, Multi-Level Prof. Nizamettin AYDIN Circuit Optimization 4. Additional Gates and Circuits, Other Gate Types, Exclusive-OR Operator and Gates, High-Impedance Outputs 5. Implementation Technology and Logic Design, Design Concepts and Automation, The Design Space, Design Procedure, The major design steps [email protected] 6. Programmable Implementation Technologies: Read-Only Memories, Programmable Logic Arrays, Programmable Array Logic,Technology mapping to programmable http://www.yildiz.edu.tr/~naydin logic devices 7. Combinational Functions and Circuits 8. Arithmetic Functions and Circuits 9. Sequential Circuits Storage Elements and Sequential Circuit Analysis 10. Sequential Circuits, Sequential Circuit Design State Diagrams, State Tables 11. Counters, register cells, buses, & serial operations 12. Sequencing and Control, Datapath and Control, Algorithmic State Machines (ASM) 13. Memory Basics

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Introduction to Digital Logic Programmable Logic devices

Lecture 6

Programmable Implementation Technologies Read-Only Memories, Programmable Logic Arrays, Programmable Array Logic Technology mapping to programmable logic devices

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Why Programmable Logic? Programmable Logic - Additional Advantages

• Facts: • Many programmable logic devices are field- – It is most economical to produce an IC in large volumes programmable , i. e., can be programmed outside of the – Many designs required only small volumes of ICs manufacturing environment • Need an IC that can be: • Most programmable logic devices are erasable and reprogrammable . – Produced in large volumes – Allows “updating” a device or correction of errors – Handle many designs required in small volumes – Allows reuse the device for a different design - the ultimate in re- • A programmable logic part can be: usability! – Ideal for course laboratories – made in large volumes • Programmable logic devices can be used to prototype – programmed to implement large numbers of different low- design that will be implemented for sale in regular ICs. volume designs – Complete Intel Pentium designs were actually prototype with specialized systems based on large numbers of VLSI programmable devices!

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• Programming technologies are used to: • The technologies (continued) – Control connections – Build lookup tables – Build lookup tables • Storage elements (as in a memory) – Control transistor switching – Transistor Switching Control • The technologies • Stored charge on a floating transistor gate – Erasable – Control connections – Electrically erasable • Mask programming – Flash (as in Flash Memory) • Fuse • Storage elements (as in a memory) • Antifuse • Single-bit storage element

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Technology Characteristics Programmable Configurations

• Permanent - Cannot be erased and reprogrammed • Read Only Memory (ROM ) - a fixed array of AND gates and a programmable array of OR gates • Mask programming • Programmable Array Logic (PAL ) - a programmable • Fuse array of AND gates feeding a fixed array of OR • Antifuse gates. • Reprogrammable • Programmable Logic Array (PLA ) - a programmable – Volatile - Programming lost if chip power lost array of AND gates feeding a programmable array of • Single-bit storage element OR gates. • Complex Programmable Logic Device (CPLD ) – Non-Volatile /Field- Programmable Gate Array (FPGA ) - • Erasable complex enough to be called “architectures” - See • Electrically erasable VLSI Programmable Logic Devices reading supplement • Flash (as in Flash Memory)

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ROM, PAL and PLA Configurations Read Only Memory

• Read Only Memories (ROM) or Programmable Read Only Memories Fixed Programmable Programmable Inputs AND array Outputs (PROM) have: Connections OR array (decoder) – N input lines,

(a) Programmable read-only memory (PROM) – M output lines, and – 2N decoded minterms. • Fixed AND array with 2 N outputs implementing all N-literal minterms. Programmable Inputs Programmable Fixed Outputs • Programmable OR Array with M outputs lines to form up to M sum of Connections AND array OR array minterm expressions.

(b) Programmable array logic (PAL) device • A program for a ROM or PROM is simply a multiple-output truth table – If a 1 entry, a connection is made to the corresponding minterm for the corresponding output Programmable Programmable – If a 0, no connection is made Inputs Programmable Programmable Outputs Connections AND array Connections OR array • Can be viewed as a memory with the inputs as addresses of data (output values), hence ROM or PROM names! (c) Programmable logic array (PLA) device

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• Example: A 8 X 4 ROM (N = 3 input lines, M= 4 output lines) • The PAL is the opposite of the ROM, having a • The fixed "AND" array is a programmable set of ANDs combined with fixed ORs. “decoder” with 3 inputs and 8 D7 XXX • Disadvantage outputs implementing minterms. D6 D5 X X – ROM guaranteed to implement any M functions of N • The programmable "OR“ D4 X inputs. PAL may have too few inputs to the OR gates. A A2 D3 array uses a single line to D2 X • Advantages B A1 D1 X X represent all inputs to an X – For given internal complexity, a PAL can have larger N and M C A0 D0 OR gate. An “X” in the – Some PALs have outputs that can be complemented, adding POS array corresponds to attaching the functions minterm to the OR – No multilevel circuit implementations in ROM (without external • Read Example: For input (A 2,A 1,A 0) F3 F2 F1 F0 connections from output to input). PAL has = 010, output is (F 3,F 2,F 1,F 0 ) = 0011. outputs from OR terms as internal inputs to all AND terms, making implementation of multi-level circuits easier. • What are functions F 3, F 2 , F 1 and F 0 in terms of (A 2, A 1, A 0)?

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Programmable Array Logic Example Programmable Logic Array (PLA) AND gates inputs 01 2 3 4 5 6 7 8 9

Product 1 X

term X

• 4-input, 3-output PAL 2 X F1 • Compared to a ROM and a PAL, a PLA is the most flexible with fixed, 3-input OR 3 having a programmable set of ANDs combined with a

I1 A programmable set of ORs.

X X terms X

4 • Advantages

X • What are the equations X

5 F2 – A PLA can have large N and M permitting implementation of X

for F1 through F4? 6 X equations that are impractical for a ROM (because of the number of

F1 = A B + C I2 B inputs, N, required X

F2 = A B C + AC + AB 7 X – A PLA has all of its product terms connectable to all outputs,

8 X X F3 overcoming the problem of the limited inputs to the PAL Ors F3 =

X – Some PLAs have outputs that can be complemented, adding POS

F4 = 9

I3 C functions X

10 X • Disadvantage X X 11 F4 – Often, the product term count limits the application of a PLA.

12 X Two-level multiple-output optimization reduces the number of I4 product terms in an implementation, helping to fit it into a PLA. 01 2 3 4 5 6 7 8 9

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Programmable Logic Array Example Complex Programmable Logic Device (CPLD) • also known as: – EPLD (Erasable Programmable Logic Device) A What are the equations for F 1 and F 2? – PEEL (Programmable Electrically Erasable Logic) Could the PLA implement the – EEPLD (Electrically-Erasable Programmable B Logic Device) functions without the XOR gates? – MAX (Multiple Array matriX, Altera) C • CPLDs consist of multiple PAL-like X logic blocks interconnected with a X 1 X X A B programmable switch matrix . • Typically, each logic block contains 4 to X X 2 X B C X Fuse intact 16 macrocells depending on the vendor Fuse blown and the architecture. X X 3 X A C • A macrocell on most modern CPLDs contains a sum-of-products X X 4 X A B combinatorial logic function and an CC BB AA X 0 optional flip-flop. The combinatorial X 1 logic function typically supports four to 16 product terms with wide fan-in. In • 3-input, 3-output PLA F1 other words, a macrocell function can with 4 product terms have many inputs, but the complexity of F2 the logic function is limited. 17 18

• MPGA was developed to handle larger logic circuits. • Like MPGA, an FPGA consists • A common MPGA consists of of an array of uncommitted rows of transistors that can be elements that can be interconnected to implement interconnected in general way . desired logic circuits. – User specified connects are • Like a PAL, the interconnections available both within the rows between elements are user- and between the rows. – This enabled implementation of programmable . basic logic gates and the ability • FPGAs are approximately 10 to interconnect the gates. • As the metal layers are defined times less dense \ and 3 times at the manufacturer, significant slower than MPGAs . time and cost are incurred in producing the run. • Consist of an array of logic – In 1985, Xilinx Inc. introduced blocks, surrounded by the FPGA (Field Programmable programmable I/O blocks, and Gate Array). The interconnects between all the elements were connected with programmable designed to be user interconnect . programmable 19 20

Programmable logic design process Programmable logic design process

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some relevant links

• http://www.latticesemi.com • http://www.xilinx.com • http://www.ti.com/sc/docs/products/proglgc • http://www.altera.com • http://www.actel.com • http://www.atmel.com • http://ece.ut.ac.ir/Classpages/F86/ECE045/FP GA%20Tutorial.pdf • http://www.klabs.org/richcontent/Tutorial/tutor ial.htm#ProgrammableLogic