(19) TZZ_Z_T

(11) EP 1 485 940 B1

(12) EUROPEAN PATENT SPECIFICATION

(45) Date of publication and mention (51) Int Cl.: of the grant of the patent: H01L 29/732 (2006.01) H01L 21/04 (2006.01) 08.01.2014 Bulletin 2014/02 H01L 29/10 (2006.01) H01L 29/16 (2006.01) H01L 29/06 (2006.01) (21) Application number: 03709157.6 (86) International application number: (22) Date of filing: 21.02.2003 PCT/US2003/004873

(87) International publication number: WO 2003/073468 (04.09.2003 Gazette 2003/36)

(54) SILICON CARBIDE BIPOLAR JUNCTION TRANSISTOR WITH OVERGROWN BASE REGION SILIZIUMCARBID-BIPOLAR-SPERRSCHICHTTRANSISTOR MIT ÜBERWACHSENER BASISREGION TRANSISTOR A JONCTION BIPOLAIRE DE CARBURE DE SILICIUM AVEC ZONE DE BASE DE RECOUVREMENT

(84) Designated Contracting States: (72) Inventors: AT BE BG CH CY CZ DE DK EE ES FI FR GB GR • SANKIN, Igor HU IE IT LI LU MC NL PT SE SI SK TR Starkville, MS 39759 (US) • CASADY, Janna, B. (30) Priority: 22.02.2002 US 79893 c/o SemiSouth Lab. Inc. Starkville, MS 39759 (US) (43) Date of publication of application: 15.12.2004 Bulletin 2004/51 (74) Representative: Clark, Jane Anne et al Mathys & Squire LLP (60) Divisional application: 120 Holborn 10189603.3 London EC1N 2SQ (GB)

(73) Proprietor: Power Integrations, Inc. (56) References cited: San Jose, California 94538 (US) FR-A- 2 335 054 US-A- 4 916 083 US-B1- 6 218 254

Note: Within nine months of the publication of the mention of the grant of the European patent in the European Patent Bulletin, any person may give notice to the European Patent Office of opposition to that patent, in accordance with the Implementing Regulations. Notice of opposition shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention). EP 1 485 940 B1

Printed by Jouve, 75001 PARIS (FR) 1 EP 1 485 940 B1 2

Description ther n-p-n or p-n-p transistors. [0005] In operation, when current is injected into or ex- BACKGROUND OF THE INVENTION tracted from the base (depending upon whether the tran- sistor is n-p-n or p-n-p), the flow of charge carriers (i.e. Field of the Invention 5 electrons or holes) which can move from the collector to the emitter will be effected. Typically, small currents ap- [0001] The present invention relates, in general, to a plied to the base can control proportionally large currents method of making a bipolar junction transistor (BJT) passing through the transistor, making the bipolar junc- formed on silicon carbide and, in particular, to a fully epi- tion transistor useful as a component of electronic cir- taxial vertical SiC bipolar junction transistor with an over- 10 cuits. grown base region suitable for use in power microwave [0006] Silicon carbide has known advantageous char- applications. acteristics as a semiconductor material. These charac- teristics include a wide bandgap, a high thermal conduc- Background of the Technology tivity, a high melting point, a high electric field breakdown 15 strength, a low dielectric constant, and a high saturated [0002] High power microwave transistors are of great electron drift velocity. As a result, electronic devices demand in such applications as cellular phone stations, formed from silicon carbide should have the capability of radar systems, etc. Along with silicon lateral MOSFETS, operating at higher temperatures, at higher device den- silicon bipolar transistors are now the primary technology sities, at higher speeds, at higher power levels and even used in solid-state radar transmitters. In recent years the 20 under higher levels of radiation than other semiconductor advantages of bipolar junction transistors as a power materials. Silicon carbide bipolar transistors, which have stage in the 0.4 to 4 GHz range have been widely rec- excellent blocking capability, small specific on-resist- ognized. The newest radar systems are calling for per- ance, and high thermal conductivity, are therefore prom- formance requirements that far surpass the capabilities ising candidates to replace silicon devices, particularly of klystron or tube-type transmitters, but appear ideally 25 in power transistors for high frequency applications. suited to solid-state devices. [0007] Silicon carbide bipolar junction transistors are [0003] Today, as the building block power stage unit, known. See, for example, v. Münch et al., "Silicon Car- a silicon bipolar transistor is the best candidate device bide Bipolar Transistor", Solid State Electronics, Vol. 21, for the frequency ranges from UHF through S- band, not- pp. 479 - 480 (1978); Luo et al., "Demonstration of 4H- withstanding the advantages in power GaAs and more 30 SiC Power Bipolar Junction Transistors", Electronic Let- recent GaN FET technology. Bipolar devices cost- effec- ters, Vol. 36, No. 17 (2000); Tang et al., "An Implanted- tively provide for system requirements reliability; rug- Emitter 4H-SiC Bipolar Transistor with High Current gedness, electrical performance, packaging, biasing, Gain", IEEE Electron Device Letters, Volume 22, Issue cooling, availability, and ease of maintenance. Largely 3, pp. 119 -120 (2001) and U.S. Patent Nos. 4,762,806, dueto newdevelopments in processingtechnology, such 35 4,945,394 and 6,218,254. A 4H- SiC bipolar junction tran- as using more shallow emitter diffusions, reduced collec- sistor, for example, has been reported to demonstrate a tor-base time constants, submicron geometries, and blocking voltage of 1.8 kV, on resistance of 10.8 m Ω•cm2, more exotic photolithographic processes and etching and a temperature stable current gain with a peak value techniques, creative device packaging, and internal of 20. See Agarwal et al., "Development of Silicon Car- matching techniques, silicon devices are competing ef- 40 bide High Temperature Bipolar Devices", HITEC, Albu- fectively up to S-band requirements. querque, NM (2000). This SiC transistor also showed a [0004] The bipolar junction transistor (BJT) is a well positive temperature coefficient in the resistance on- known semiconductor device. A bipolar junction transis- characteristics, which may facilitate paralleling the de- tor is generally defined as a device formed of a semicon- vice. These properties could confer advantages over sil- ductor material having two p- n junctions in close proxim- 45 icon bipolar junction transistors, where thermal runaway ity to one another. In operation, current enters a region can be a problem. (i.e., the emitter) of the device adjacent one of the p-n [0008] At high frequencies, the operating characteris- junctions and exits the device from a region (i.e., the col- tics of silicon carbide bipolar junction transistors are high- lector) of the adjacent the other p-n junction. The collector ly dependent on the thickness of the p-base layer. Gen- and emitter have the same conductivity type (i.e., either 50 erally, thinner p- base layers confer better high frequency p or n). A portion of semiconductor material having the performance. However, it can be difficult to form base oppositeconductivity type from thecollector and theemit- layers having desirable thicknesses for high frequency ter is positioned between the collector and the emitter. (e.g., microwave) applications. Further, achieving ade- This material is known as the base. The two p- n junctions quate ohmic contact to a very thin base region while min- of the transistor are formed where the collector meets 55 imizing peripheral base resistance can be difficult. As a the base and where the base meets the emitter. Because solution to this problem, v. Münch et al ., supra, proposed of their respective structures and conductivity types, bi- thinning an epitaxially grown.SiC base layer and forming polar junction transistors are generally referred to as ei- an overgrown emitter layer thereon.

2 3 EP 1 485 940 B1 4

[0009] The lateral dimensions of a bipolar junction tran- and the upper surface of each emitter region; forming an sistor can also affect the high frequency performance of emitter contact opening through the second base layer the device. It is generally desirable to shrink or scale on an upper surface of each raised emitter region to ex- down the dimensions of the device. Features are typically pose emitter material, each emitter contact opening hav- formed in semiconductor devices using photolithography 5 ing bottom and sidewall surfaces; forming base contacts techniques. Such techniques, however, require numer- on surfaces of the second base material in the etched ous process steps and can be costly to implement. Fur- regions; and forming an emitter contact on a surface of ther, the resolutions obtainable using conventional pho- the emitter material in each emitter contact opening. tolithography techniques are limited. Self alignment tech- [0013] By use of the method of the invention a silicon niques have also been proposed as an alternative to pho- 10 carbide bipolar junction transistor is produced. The tran- tolithographic techniques. See, for example, U.S. Patent sistor include, a collector having first and second major No. 6,218,254 (hereinafter the ’254 patent). Self align- surfaces. The collector comprises silicon carbide doped ment techniques are manufacturing techniques wherein with a donor material. A drift layer can be formed on the device features automatically and inherently align as a first major surface of the collector. The drift layer com- result of the manufacturing process. The use of self- align- 15 prises silicon carbide doped with a donor material. A plu- ment techniques can allow for the formation of fine fea- rality of raised emitter regions are formed on either the tures while simplifying the manufacture of the device. The drift layer or on the first major surface of the collector. ’254 patent discloses a method of fabrication of SiC bi- The raised emitter regions are non-coextensive with the polar junction transistorS having self- aligned ion implant- drift layer or the collector and are formed on a central ed n-plus emitter regions or ion implanted p- plus regions 20 portion of the drift layer or collector. The raised emitter for base ohmic contacts. The high energies required for regions include an upper emitter layer formed on a lower ion implantation, however, can result in damage to the base layer. The lower base layer is in contact with either device. Further, ion implantation typically requires a high the collector or drift layer and the upper emitter layer is temperature annealing step to activate the implanted im- substantially coextensive with the lower base layer. The purities. These additional process steps add to both the 25 upper emitter layer comprises SiC doped with a donor cost and complexity of the manufacturing process. material and the lower base layer comprises SiC doped [0010] There still remains a need, therefore, for im- with an acceptor material. The transistor also includes a proved methods of making SiC bipolar junction transis- second base layer doped with an acceptor material at a tors having sufficiently thin p-base regions for improved higherdoping level than thelower base layer. The second high frequency performance. Such methods would ide- 30 base layer is formed on exposed surfaces of the collector ally allow for adequate ohmic contact to the base and or drift layer and on exposed surfaces of the raised emit- would provide devices having minimal peripheral base ter regions.Emitter openings can be formedin the second resistance. base layer on upper surfaces of the emitter regions and emitter contacts can be disposed in the emitter openings. SUMMARY OF THE INVENTION 35 Base contacts can be formed on the second base layer. According to a preferred embodiment of the invention, [0011] According to the invention there is provided a the first base layer of the transistor has a thickness of method as defined in the independent claims 1 and 13. 0.2mm or less. [0012] According to a first aspect of the invention, a [0014] The silicon carbide bipolar junction transistor method of making a SiC bipolar junction transistor is pro- 40 may e.g. further include a base contact layer formed on vided. The method includes steps of: providing a collector and coextensive with the second base layer. Emitter con- comprising SiC doped with a donor material, the collector tact openings can e.g. be formed in the base contact having first and second major surfaces; optionally form- layer and the underlying second base layer on upper sur- ing a drift layer on the first major surface of the collector, faces of the emitter regions such that the emitter contact thedrift layer comprisingSiC doped with adonor material; 45 openings in the second base layer are substantially forming a first base layer on the first major surface of the aligned with the emitter contact openings in the base con- collector or on the drift layer, the first base layer compris- tact layer. Emitter contacts can e.g. be disposed on ex- ing SiC doped with an acceptor material; forming an emit- posed emitter material in the emitter contact openings. ter layer on the first base layer, the emitter layer com- [0015] According to another embodiment of the inven- prising SiC doped with a donor material; etching through 50 tion there is provided a method of making a SiC bipolar the emitter layer and the first base layer to expose the junction transistor comprising: collector or drift layer and to form one or more raised emitter regions each having an upper surface defined by providing a collector comprising SiC doped with a regions of etched emitter and first base layer, the etched donor material, the collector having first and second regions comprising bottom and sidewall surfaces; form- 55 major surfaces; ing a second base layer comprising SiC doped with an optionally forming a drift layer on the first major sur- acceptor material, wherein the second base layer covers face of the collector, the drift layer comprising SiC the bottom and sidewall surfaces of the etched regions doped with a donor material;

3 5 EP 1 485 940 B1 6

forming a first base layer on the first major surface having an overgrown p+ layer as set forth in FIG. 1; of the collector or on the drift layer, the first base FIG. 5B shows the simulated breakdown character- layer comprising SiC doped with an acceptor mate- istics of the 4H-SiC bipolar junction transistor simu- rial; lated in the depiction of FIG 5A; forming an emitter layer on the first base layer, the 5 FIGS. 6A - 6G show steps involved in the manufac- emitter layer comprising SiC doped with a donor ma- ture of a bipolar junction transistor according to a terial; first embodiment of the invention; and etching through the emitter layer and the first base FIGS. 7A - 7F show steps involved in manufacture layer to expose the collector or drift layer and to form of a bipolar junction transistor according to a second at least one raised emitter region defined by regions 10 embodiment of the invention. of etched emitter and first base layer, each raised emitter region having an upper surface and the DETAILED DESCRIPTION OF THE INVENTION etched regions comprising bottom and sidewall sur- faces; [0017] According to the invention, an epitaxially grown forming a second base layer comprising SiC doped 15 high-frequency bipolar junction transistor (BJT) in SiC with an acceptor dopant, wherein the second base can be produced. The device according to the invention layer covers the bottom and sidewall surfaces of the comprises a relatively thin (e.g., 3 mm or less) first base etched regions and the upper surface of each raised region and an overgrown second base region. The over- emitter region; grown base region provides electrical contact to the first forming a base contact layer on the second base 20 base region of the bipolar junction transistor. According layer; to the invention, emitter contact openings can be formed forming an emitter contact opening through the base (e.g., etched) in the overgrown base layer with a self- contact layer on a surface of each raised emitter re- alignmenttechnique wherein a basecontact layerformed gion to expose the second base layer; on the overgrown base layer is used as a mask to etch etching an emitter contact opening through the sec- 25 the underlying overgrown base layer. Emitter contacts ond base layer on the upper surface of each raised can then be formed in the resulting self-aligned emitter emitter region using the base contact layer as a mask contact openings. A silicon carbide bipolar junction tran- to expose emitter material; sistor producible witha methodaccording to the invention forming an emitter contact on the emitter material in can have a thin base region, the thickness of which can each emitter contact opening. 30 depend on the doping level and the target base punch- through voltage of the device. BRIEF DESCRIPTION OF THE FIGURES [0018] The cutoff frequency of a transistor may be ex- pressed through the emitter-to collector delay time as [0016] The present invention may be better under- follows: stood by reference to the accompanying drawings in35 which:

FIG. 1 is a cross- sectional view of a portion of a SiC bipolar junction transistor with an overgrown p+ base region producible with a method according to a first 40 embodiment of the invention; FIG. 2 is a cross-sectional view of a multi-fingered

SiC bipolar junction transistor having p+ overgrown wherein fT is the transition frequency and τee is the emit- base regions and guard rings; ter-to-collector delay time. The emitter-to-collector time 45 FIG. 3 is a cross sectional view of a portion of a SiC τEC is made up of a number of delay components as set bipolar junction transistor with an overgrown p+ base forth in the following equation: region wherein the base contact layer is used as a mask for etching emitter contact openings in the un- derlying p+ overgrown base layer according to a sec- ond embodiment of the invention; 50 FIG. 4 is a cross-sectional view of a multi-fingered SiC bipolar junction transistor having overgrown p+ wherein τe is the emitter-base junction capacitance base regions and an overgrown base contact layer charging time, τt is the base transit time, τd is the transit wherein emitter contact openings and guard rings time through the collector depletion region, and τe is the have been formed by etching the overgrown base 55 collector capacitance charging time. At the mode of high layer using the base contact layer as a mask; level injection, the base layer charging time τt becomes FIG. 5A is a depiction of the simulation of the blocking the determining factor of the transistor high frequency capabilities of a 4H-SiC bipolar junction transistor performance. This term is proportional to the square of

4 7 EP 1 485 940 B1 8 the base width Wb and inversely proportional to the mi- be suppressed since the potential barrier between the nority carrier diffusion length in the neutral base Db as emitter and the overgrown p- plus layer is higher than that set forth in the following equation: between the emitter and the p-type base region. [0022] FIG. 1 shows a cross sectional view of a portion 5 of a SiC bipolar junction transistor producible with a meth- od according to a first embodiment of the invention. Tran- sistor 10 comprises a collector 12, a drift layer 13, a first base layer 14, and emitter regions 16. Emitter regions 16 are shown spaced from one another by a trench 20. 10 [0023] The structure shown in FIG. 1 can be made by Such dependence of frequency response on base pa- forming on a first major surface of collector 12, in suc- rameters shows the importance of making the base re- cession, drift layer 13, first base layer 14 and a layer of gion of SiC bipolar junction transistors as thin as possible, emitter material. The collector can be a doped SiC single especially when operating at high (e.g., microwave) fre- crystal. Doped SiC single crystals can be obtained from quencies. 15 commercial sources such as Cree, Inc. of Durham, North [0019] Because of the limited diffusion of dopants in Carolina. SiC, the base and emitter regions of a SiC bipolar junction [0024] The drift, first base and emitter layers can be transistor may be either implanted or grown. Ion implan- formed by epitaxial growth wherein the dopant material tation, however, can result in surface and bulk damage. is incorporated into the SiC layer during growth. An Ion implantation also requires a special treatment after 20 etched region (e.g. a trench) can then be formed by etch- implantation (e.g., a post implant anneal) to activate the ing through the emitter layer. Since the first base layer implanted impurity. Further, even after a high tempera- is very thin (e.g., as thin as 0.1m m or less), first base ture post-implant anneal, a large percentage of certain layer 14 will also be etched through during etching of the implanted impurities (e.g. boron and aluminum which are emitter layer to expose underlying drift layer 13. An over- typically used for doping SiC) can remain electrically in- 25 grown base layer 18 can then be formed on bottom and active occupying interstitial sites. This phenomenon can sidewall surfaces of trench 20 as well as on upper sur- result in a reduction in the electron lifetime of the implant- faces of emitter regions. Emitter contact openings 22 can ed base. Bulk damage in the emitter region resulting from then be provided in overgrown base region 18 on upper ion implantation can also increase the recombination rate surfaces of emitter regions 16. Emitter contacts 24 and in the emitter, which can lead to an increase of the base 30 base contact 26 can then be disposed in emitter contact current. openings and trenches respectively. A collector contact [0020] Doping in-situ during epitaxial growth of the 28 is also shown disposed on the remaining exposed base and emitter regions can be used to avoid certain of major surface of collector 12. The method of making the the aforementioned problems associated with ion im- SiC bipolar junction transistor is described in detail with plantation. For example, very thin (i.e., 0.1 mm) base lay- 35 reference to FIGS. 6 and 7 below. ers can be formed using in-situ doping during epitaxial [0025] Although a trench 20 is shown in FIG. 1 sepa- growth. However, making the epitaxial base as thin as rating two raised emitter regions 16, a device having a possible, which is very desirable in high frequency appli- single raised emitter region can also be made according cations, can give rise to other problems including making to the invention. In the manufacture of such a device, ohmic contact to such a base and minimizing the periph- 40 there would be no need to form trenches. Rather, emitter eral resistance of the base. Thinning the base layer after material could be removed from regions surrounding the formation (e.g., by etching) is one means that has been raised emitter region to form the single emitter. employed toachieve adesired base layer thickness. See, [0026] According to a preferred embodiment of the in- for example, v. Münch et al., supra. However, it is very vention, the collector is heavily doped with a donor ma- difficult to avoid over-etching a thin (e.g., 0.1 mm thick) 45 terial. The preferred thickness of the collector is between base layer. Further, the sheet resistance of a thin base 300 and 400 mm. Collectors of other thicknesses, how- region may be too high to achieve acceptable high fre- ever, can be used depending on the desired character- quency performance. istics of the transistor. Although a drift layer is shown in [0021] The present inventors have discovered that im- FIG. 1, it is not necessary for a bipolar junction transistor proved bipolar junction transistor device performance 50 producible with a method according to the invention to can be achieved by using a heavily doped overgrown include a drift layer. A drift layer is typically used to im- base region. The overgrown base region can.be used to prove operating characteristics of the device in certain providea larger electrical contact surface for the thinbase applications (e.g., in power applications). If a drift layer layer. The overgrown base region according to the in- is used, the drift layer will have a doping level less than vention can also reduce the peripheral base resistance 55 that of the collector layer. The drift layer thickness can of the bipolar junction transistor. By using a high doping also be varied according to the invention to achieve de- level in the overgrown base layer, minority carrier injec- sirableoperating characteristics.Drift layer thickness can tion from the emitter into the overgrown base layer can be chosen, for example, based on the operating voltage

5 9 EP 1 485 940 B1 10 and operating frequency of the device. For high voltage 1018 atoms•cm-3 or greater, lightly doped corresponds applications, the drift layer preferably has a thickness of to dopant concentrations of 5x1016 atoms•cm-3 or less 4 mm or greater. For high frequency applications (e.g., 2 and moderately doped corresponds to dopant concen- Ghz or greater), the drift layer preferably has a thickness trations of between 5x1016 atoms•cm-3 and 1018 at- of 4 mm or less. 5 oms•cm-3. [0027] According to a preferred embodiment of the in- [0033] The bipolar junction transistors producible with vention, the collector layer is heavily doped with a donor a method according to the invention can be made without material and the drift layer is lightly or moderately doped expensive ion implantation and post-implant anneal with a donor material. Suitable donor materials include steps. Moreover, the use of a heavily doped epitaxial nitrogen and phosphorous. Nitrogen is a preferred donor 10 layer to form the overgrown base region allows fabrica- material according to the invention. The above materials tion at the same time of an edge termination structure in are merely exemplary, however, and any other donor ma- theovergrown base layer. The edge terminationstructure terial suitable for silicon carbide can also be used. can be used to increase the blocking capabilities of the [0028] The emitter layer is also preferably heavily device. One example of an edge termination structure doped with a donor material. The thickness of the emitter 15 are the epitaxial guard rings shown depicted in FIG. 2. layer can also be varied to provide desirable device op- [0034] FIG. 2 shows a cross-section of a multi-finger erating characteristics. According to a preferred embod- SiC bipolar junction transistor according to the invention. iment of the invention, the emitter layer has a thickness The designation "multi-finger" refers to the configuration of 0.5 to 1 mm. of the base and emitter contacts of the device. A multi- [0029] The first base layer according to the invention 20 fingered device comprises a plurality of elongate emitter is preferably moderately or lightly doped with an acceptor contacts interdigitated with a plurality of elongate base material. The doping level of the first base layer can be contacts. Multifingered arrangements are used to in- varied depending upon the operating conditions (e.g., crease the peripheral length of the emitter region and to voltage and frequency) of the device. Generally, the dop- thereby improve the current carrying capability of the de- ing level of the first base layer will be sufficiently high to 25 vice. See, for example, Baliga, Power Semiconductor prevent voltage punch-through during operation of the Devices, pp. 231 - 232 (1996). Typically, in multi- fingered device. The punch through voltage of the device, how- arrangements, base regions are located outside the out- ever, is also dependent upon the thickness as well as ermost emitter regions to maximize the peripheral length the doping level of the base layer. Generally, higher dop- of the emitter. ing levels are required for thinner base layers to prevent 30 [0035] As shown in FIG. 2, bipolar junction transistor voltage punch through. For example, for a 0.1 mm thick 30 comprises three raised emitter regions 16 (e.g., fin- base layer and a 4m m thick drift region with a donor gers) separated and defined by trenches 20. Trenches concentration of 5 x 1016 atoms•cm-3, the base p-type 20 can be used as openings for base contacts as de- doping level can be in the range of 2 x 10 18 atoms•cm-3 scribed below. Emitter contact openings 22 are shown to 3 x 10 18 atoms•cm -3. The doping level of the base layer 35 formed in overgrown base layer 18 on the upper surface will preferably be in the range of 1 x1018 atoms•cm-3 to of raised emitter regions 16. Emitter contacts 24 and base 2 x1018 atoms•cm-3. According to a preferred embodi- contacts 26 are also shown formed in emitter contact ment of the invention, the first base layer will have a thick- openings 22 and trenches 20, respectively. ness of 0.1 to 0.3 mm. [0036] Guard rings 32 are also shown formed in the [0030] Suitable acceptor materials for doping silicon 40 overgrown base layer in a peripheral region of the device. carbide include boron and aluminum. Aluminum is a pre- Guardrings 32,which areetched in overgrownbase layer ferred acceptor material. The above materials are merely 18, can be formed simultaneously with emitter contact exemplary, however, and any acceptor material which openings 22. As described below, guard rings 32 can be can be doped into silicon carbide can be used according used to improve the blocking capabilities of the bipolar to the invention. 45 junction transistor. Although guard rings are shown, other [0031] The overgrown base layer according to the in- known edge termination structures can also be used. vention will have a higher doping level than the first base [0037] The use of guard rings or other.edge termina- layer. The overgrown base layer is preferably heavily tion structures is optional. For example, in some appli- doped with an acceptor material. The doping level and cations (e.g., at high frequencies) a BJT may have a rel- thickness of the overgrown base layer can be varied de- 50 atively low blocking voltage (e.g., = 200 V). Under these pending upon the requirements and operating character- conditions, edge terminations are not necessary be- istics of the device. cause the blocking voltage will be limited not by ava- [0032] The doping levels and thicknesses of the vari- lanche breakdown near the edge of the device but by the ous layers of the bipolar junction transistor according to base punch-through voltage of the device. the invention can be varied to produce a device having 55 [0038] As set forth above, the lateral dimensions (i.e., desired characteristics for a particular application. Un- scale) ofthe transistor can also affect high- frequencyper- less otherwise indicated, heavily doped in the context of formance. According to the invention, a self- aligned fab- the invention corresponds to dopant concentrations of rication process can be used to form emitter contact

6 11 EP 1 485 940 B1 12 openings and guard rings in the overgrown base layer. [0043] FIG. 4 shows a cross-section of a multi-finger Self aligrunent techniques are manufacturing techniques SiC bipolar junction transistor producible with a method through which device features automatically and inher- according to the invention. As shown in FIG. 4, bipolar ently align as a result of the manufacturing process. Self junction transistor 40 comprises three raised emitter re- alignment manufacturing techniques have been used to 5 gions 16 separated and defined by trenches 20. Emitter produce silicon carbide MOSFETs and bipolar junction contact openings 22 are shown formed on the upper sur- transistors. See, for example, U.S. Patent Nos.face ofemitter regions 16 in overgrown base contactlayer 5,726,463 and 6,218,254. 36 and in underlying overgrown base layer 18. Emitter [0039] A self-aligned process according to the inven- contacts 24 are also shown formed in emitter contact tion comprises using the base ohmic contact material 10 openings 22. Guard rings 42 are shown formed at the (e.g., metal) as an etch mask for fabrication of the emitter edge of transistor 40. contact openings in the underlying overgrown base layer. [0044] According to an embodiment of the invention, In this manner, the openings etched in the overgrown guard rings 42, which are formed in overgrown base con- base layer will be aligned with the openings formed in tact layer 36 and in underlying overgrown base layer 18, the base ohmic contact layer. A device made using this 15 can be formed simultaneously with emitter contact open- technique is illustrated in FIG. 3. ings 22. In particular, both emitter contact openings 22 [0040] FIG. 3 shows the cross section of a portion of and guard rings 42 can be etched or otherwise formed a silicon carbide bipolar junction transistor producible in overgrown base contact layer 36 in a first step and the with a method according to a second embodiment of the base contact layer can then be used as a mask to form invention wherein a base contact layer 36 is formed on 20 openings in the underlying overgrown base layer 18. overgrown base layer 18. As can be seen from FIG. 3, [0045] After formation of the emitter contact openings, base contact layer 36 is formed on bottom and sidewall emitter and/or base contacts can be deposited in contact surfaces of trench 20 as well as on upper surfaces of openings (e.g., emitter contact openings or trenches). emitter regions. The base contact layer 36 is typically a The emitter contacts can be deposited in the openings metal (e.g., titanium) layer. The base contact layer 36 25 using a conventional lithography process to space the can be applied by any metallization technique known in edges of the contacts from the sidewalls of the openings. the art. According to a preferred embodiment of the in- [0046] Using the self-alignment method according to vention, base contact layer is applied by sputtering. the invention allows for the manufacture of bipolar junc- [0041] After forming base contact layer 36, emitter con- tion transistors wherein the distance between each emit- tact openings 22 are provided in both base contact layer 30 ter contact and adjacent base contacts can be made very 36 and overgrown base layer 18 on the upper surfaces small. For example, when the contacts are formed in the of emitter regions 16. Emitter contact openings 22 can contact openings by a photolithography technique, spac- be formed by first forming openings in base contact layer ings of the emitter contacts from the sidewalls of the emit- 36 on the upper surfaces of base contact regions 16 to ter contact openings (and thus from the edges of the base expose the underlying overgrown base layer 18. The35 contacts) can be obtained down to the limits of conven- base contact layer 36 having emitter contact openings tional photolithography (e.g., 0.18 mm or less). When the formed therein can then be used as a mask to form open- base contact layer is overgrown and used as an etch ings in overgrown base layer 18. This process is de- mask (as depicted in FIGS. 3 and 4), the horizontal spac- scribed in detail below with reference to FIG. 7. Emitter ing between the edges of the base and emitter contacts contact openings 22 can be formed in base contact layer 40 will also be equal to this spacing since the openings in 36 by any conventional technique including an etching the base contact layer and the underlying overgrown process (e.g., dry or wet etch) or by a lift-off technique. base layer are self- aligned. By reducing spacing between The portion of the overgrown base contact layer 36 re- the base and emitter contacts, it is possible to reduce the maining after formation of emitter contact openings 22 transistor dimensions and to thereby improve the high- can then be used as a base contact for the bipolar junction 45 frequency performance of the device. transistor. After formation of emitter contact openings [0047] When the base contact layer is not overgrown 22, emitter contacts 24 can be disposed in emitter contact on the emitter regions and used as an etch mask for the openings 22 in contact with emitter material from raised emitter contact openings, base contacts can be applied emitter regions 16. to the bottom surfaces of the trenches. The base contacts [0042] As set forth above, the base contact layer can 50 can also be spaced from the trench sidewalls using a be deposited on the overgrown base layer and etched to conventional photolithography process. Base contacts form openings for the emitter contacts. The etched base formed in trenches are shown, for example, in FIGS. 1 contact layer can then be used as an etch mask for mak- and 2. As can be seen in FIGS. 1 and 2, the base contacts ing openings in the overgrown base layer. As can be are spaced from the side walls of the trenches. seen in FIG. 3, by using this technique the openings for 55 [0048] Formation of base and emitter contacts can be the emitter contacts in the overgrown base layer are self- achieved, for example, by forming an insulating layer aligned with emitter contact openings formed in the over- (e.g., SiO2) on the surface of the device and forming lying base contact layer. openings (e.g., by etching) in the insulating layer at de-

7 13 EP 1 485 940 B1 14 sired locations. The openings can be located using a pho- cording to the invention to achieve the desired current tolithography technique. carrying capacity for the device. [0049] A number of metals and metal composites are [0054] A 4H-SiC bipolar junction transistor having the appropriate for use as base, collector and emitter con- structure shown in FIG. 1 was simulated using "ATLAS" tacts according to the invention. For example, nickel or 5 device simulation software from Silvaco, International of nickel-titanium combinations are appropriate ohmic con- Santa Clara, California to determine the base punch- tacts to silicon carbide doped with donor materials while through voltage. The designation "4H" refers to the crys- aluminum or aluminum-titanium combinations are useful tal structure or polytype of the silicon carbide. Silicon car- ohmic contacts to silicon carbide doped with acceptor bide crystallizes in over 150 different polytypes, or crystal materials. According to a preferred embodiment of the 10 structures, of which the most common are designated invention, nickel is used as both an emitter and collector 3C, 4H and 6H. The designation "C" stands for "cubic" contact material and titanium is used as a base contact and the designation "H" stands for "hexagonal." Current- material. Suitable ohmic contact materials and structures ly, the 6H polytype is the most thoroughly characterized. are also disclosed in U.S. Patent Nos. 5,323,022 and The 4H polytype is more attractive for power devices, 5,409,859. 15 however, because of its higher electron mobility. [0050] The improved spacing achieved using the self- [0055] The results of the simulation for the 4H- SiC bi- alignment method of the present invention can reduce polar junction transistor are shown in FIG. 5A. The bipolar base resistance and base collector capacitance of the junction transistor simulated in FIG. 5A had a first base device, and can thereby enable the production of devices layer 14 having a thickness of 0.2 mm and a doping level which operate at higher frequencies. By reducing the 20 of 5x10 17 atoms•cm -3. The bipolar junction transistor also spacing between base and emitter contacts, the specific had a drift layer 13 having a thickness of 4m m and a on-resistance of the device may also be reduced. doping level of 3x1016 cm-3. An emitter contact 24 is [0051] Another self-aligned process according to the shown in contact with raised emitter region 16 and a base invention comprises using the base ohmic contact ma- contact 26 is shown in contact with overgrown base layer terial can as an etch mask for fabrication of edge termi- 25 18. Distance (in mm) from a centerline through the raised nation structures (e.g., guard rings) surrounding the bi- emitter region is shown on the x-axis and distance (in polar junction transistor. These guard rings can be mm) from the top of the overgrown base regions is shown formed simultaneously with the formation of the emitter on the y- axis. The shading in FIG. 5A indicates the impact contact openings. The epitaxial guard rings formed using generation rate in the device. Impact generation rate is the bulk deposited base contact layer as an etch mask 30 given in units of s-1•cm-3. therefore comprise a conductive (e.g., metal) top layer [0056] For the simulation shown in FIG. 5A, edge ef- overlying an overgrown base material layer. This con- fects were ignored. In actual use, however, edge field ductive layer can help to keep the entire ring at the same crowding may degrade blocking capabilities significantly. potential and thereby improve the overall blocking capa- As discussed in more detail below, an edge termination bility of the edge termination structure. 35 structure (e.g., guard rings) can be used to increase the [0052] As set forth above, FIG. 4 shows a multifinger blocking capability of the transistor. As described above, SiC bipolar junction transistor with guard rings wherein examples of SiC bipolar junction transistor devices with the base metal layer was used as the etch mask to form edge termination structures comprising guard rings are both the emitter contact openings and the guard rings. shown in FIGS. 2 and 4. As can be seen from FIG. 4, each of the three guard rings 40 [0057] FIG. 5B is a graph showing the simulated break- shown has a conductive top layer formed by forming down characteristics of the 4H- SiC bipolar junction tran- openings in the base contact layer and the underlying sistor which was simulated in FIG 5A. In FIG. 5B, both overgrown base layer. Although three guard rings are the base current (x) and the collector current◊ ) ( are shown, any number of guard rings may be employed ac- shown as a function of voltage applied to the collector. cording to the invention to achieve desired blocking ca- 45 As can be seen from FIG. 5B, both the base and collector pabilities for the device. Further, the spacing, width and current spike at a collector voltage of approximately 220 thickness of the guard rings can also be varied according volts indicating that the breakdown of the device occurs to the invention to achieve the desired edge termination at this voltage. effects. [0058] FIGS. 6A - 6G illustrate steps involved accord- [0053] The number of base and emitter contact "fin- 50 ing to a first embodiment of the invention in making a SiC gers" or elongate regions can also be varied according bipolar junction transistor. In FIG. 6A, a drift layer 102 is to the invention. Generally, the current carrying capability shown disposed on a first major surface of collector layer of a transistor is proportional to the peripheral length of 100. A collector contact layer 108 is shown disposed on the emitter regions. Therefore, use of a finger geometry the remaining exposed major surface of collector 100. wherein emitter contacts are interdigitated with base con- 55 [0059] According to a preferred embodiment of the in- tacts allows the emitter periphery and, as a result, the vention, the drift layer is an SiC layer lightly doped with current carrying capacity of the transistor to be maxi- a donor material (e.g., n minus doped) and the collector mized. Any number of emitter fingers can be used ac- is SiC heavily doped with a donor material (e.g. n plus

8 15 EP 1 485 940 B1 16 doped).The doping of theSiC with thedopant (e.g., donor ess. After the etching step, insulating layer 111 remains or acceptor) is preferably performed in-situ during epi- on the side walls of emitter contact openings 107 and taxial growth of the SiC layers. The SiC layers can be trench 109. formed by any epitaxial growth method known in the art, [0066] FIG. 6G shows a second step in a method of including CVD, molecualr beam and sublimation epitaxy. 5 forming self- aligned base and emitter contacts. As shown According to preferred embodiment of the invention, the in FIG. 6G, base contact 118 and emitter contacts 116 doped SiC layers according to the invention are formed have been deposited on exposed surfaces of overgrown by doping in-situ during epitaxial growth wherein dopant base 110 in trench 109 and on exposed surfaces of emit- atoms are incorporated into the silicon carbide during ter layer 106 in emitter contact openings 107 respective- growth. 10 ly. As can be seen in FIG. 6G, the base and emitter con- [0060] In FIG. 6A, a first base layer 104 is shown dis- tacts are spaced from the sidewalls of trench 109 and posed on drift layer 102 and an emitter layer 106 is shown emitter contact openings 107 by insulating material 112 disposed on first base layer 104. According to a preferred from insulating layer 111. embodiment of the invention, first base layer 104 is mod- [0067] FIGS. 7A - 7F illustrate a method of forming a erately doped with an acceptor material and emitter layer 15 SiC bipolar junction transistor according to a second em- 106 is heavily doped with a donor material. bodiment of the invention. FIG. 7A shows a base contact [0061] FIG. 6B shows the cross section of FIG. 6A after layer 120 disposed on the overgrown base layer of the a first etching step according to the invention. As can be substrate of FIG. 6C. Base contact layer 120 can be de- seen from FIG. 6B, a trench 109 is shown etched through posited on overgrown base layer 110 by any method emitter layer 106 and first base layer 104. Material from 20 (e.g., chemical vapor deposition, sputtering, etc.) known drift layer 102 is shown exposed on the bottom of trench in the art. Base contact layer is preferably a metal layer. 109. According to a preferred embodiment of the inven- [0068] FIG. 7B shows emitter contact openings 121 tion, a series of spaced apart trenches are etched parallel formed in base contact layer 120 on the upper surfaces to one another in the substrate forming an interdigitated of raised emitter regions 106. The emitter contact open- structure of raised emitter areas and trenches (e.g., multi- 25 ings can be formed in base contact layer by any known fingered device). As can be seen in FIG. 6A, the raised metal patterning technique including metal etching and emitter regions comprise material from emitter layer 106 metal lift-off techniques. and first base layer 104. [0069] FIG. 7C shows emitter contact openings 121 [0062] FIG. 6C shows a second base layer 110 formed etched in overgrown base layer 110 on the upper surfac- on the exposed surfaces of the structure depicted in FIG. 30 es of raised emitter regions 106. The etching step can 6B. Second base layer 110 is preferably a heavily p- be performed using base contact layer 120 with emitter doped SiC layer. As can be seen from FIG. 6C, second contact openings 121 formed therein as a mask in the base layer 110 forms a layer on both the bottom (i.e., etching of overgrown base layer 110. In this manner, horizontal) and sidewall (i.e., vertical) surfaces of the emitter contact openings in overgrown base layer 110 trenches and on the upper (i.e., horizontal) surface of the 35 are self- alignedwith emitter contactopenings 121 in base raised emitter regions. contact layer 120. [0063] FIG.6D shows a second etch stepin which emit- [0070] FIG. 7Dshows afirst step ina methodof forming ter contact openings 107 are formed in the overgrown self-aligned emitter contacts on the substrate of FIG. 7C. base layer on the upper surfaces of emitter mesas ex- In FIG. 7D, an insulating layer 122 is formed on the ex- posing material from underlying emitter layer 106. 40 posed surfaces of the substrate. Insulating layer 122 is [0064] FIG. 6E shows a first step in a method of forming preferably a silicon dioxide layer. The insulating layer can base and emitter contacts according to the invention. In be formed by any known deposition process (e.g., CVD FIG. 6E, an insulating layer 111 is formed on the exposed or PECVD). As shown in FIG. 7C, insulating layer 122 surfaces of the etched substrate of FIG. 6D. Insulating comprises horizontal portions 128 and vertical portions layer 111 is preferably a silicon dioxide layer. The insu- 45 124. lating layer can be formed by any known deposition proc- [0071] FIG. 7E shows a second step in a method of ess (e.g., CVD or PECVD). As shown in FIG. 6E, insu- forming self-aligned emitter contacts. As shown in FIG. latinglayer 111 comprises horizontal portions114 formed 7E, an etching process has been used to selectively re- on bottom surfaces of trench 109 and emitter openings move portions of insulating layer 122 from surfaces 125 107 and vertical portions 112 formed on the sidewalls of 50 of emitter contact regions 106. Selective removal can be trench 109 and emitter openings 107. accomplished using photolithography techniques. As a [0065] FIG. 6F shows a second step in a method of result, portions of insulating layer 122 remain on the side forming base and emitter contacts. As shown in FIG. 6F, walls of emitter contact openings 107. an etching process has been used to remove the insu- [0072] FIG. 7F shows a third step in a method of form- lating layer 111 from emitter regions 106 and overgrown 55 ing self-aligned emitter contacts. As shown in FIG. 7F, base layer 110 to form openings for base and emitter emitter contacts 126 have been deposited on exposed contacts. The insulating layer 111 can be selectively re- surfaces of emitter layer 106 in the emitter contact open- moved from these regions using a photolithography proc- ings. As can be seen from FIG. 7F, emitter contacts 126

9 17 EP 1 485 940 B1 18 are spaced from sidewalls of the emitter contact open- forming the drift layer (13) comprises epitaxially ings by insulating material from insulating layer 122. The growing the drift layer (13) on an exposed surface methods illustrated in FIGS. 6 and 7 are merely exem- of the collector (12) and wherein the step of forming plary of methods that can be used according to the in- the firstbase layer (14) comprises epitaxially growing vention to manufacture SiC BJTs. Other known semicon- 5 the first base layer (14) on an exposed surface of ductor manufacturing techniques can also be used ac- the drift layer (13). cording to the invention. [0073] From the foregoing, it will be appreciated that, 3. A method as claimed in claim 1, wherein the collector although specific embodiments of the invention have is doped with a donor material at a first doping level been described herein for purposes of illustration, various 10 and the drift layer (13) is doped with a donor material modifications may be made without deviating from the at a second doping level and wherein the first doping scope of the invention as defined by the claims. level is higher than the second doping level.

4. A method as claimed in claim 3, wherein the first Claims 15 doping level is 1018 atoms • cm-3 or greater and the second doping level is 1015 atoms • cm-3 or less. 1. A method of making a SiC bipolar junction transistor comprising: 5. A method as claimed in claim 2, wherein the step of forming the emitter layer (16) comprises epitaxially providing a collector (12) comprising SiC- doped 20 growing the emitter layer (16) on the first base layer with a donor material, the collector (12) having (14). first and second major surfaces; optionally forming a drift layer (13) on the first 6. A method as claimed in claim 5, wherein the emitter major surface of the collector, the drift layer (13) layer (16) is doped with a donor material during the comprising SiC doped with a donor material; 25 epitaxial growth. forming a first base layer (14) on the first major surface of the collector (12) or on the drift layer 7. A method as claimed in claim 6, wherein the emitter (13), the first base layer (14) comprising SiC layer (16) is doped at a doping level of 10 18 atoms • doped with an acceptor material; cm-3 or greater during epitaxial growth. forming an emitter layer (16) on the first base 30 layer (14), the emitter layer (16) comprising SiC 8. A method as claimed in claim 5, wherein the step of doped with a donor material; forming the second base layer (18) comprises epi- etching through the emitter layer (16) and the taxially growing the second base layer (18) on an first base layer (14) to expose the collector (12) exposed surface of the emitter layer (16). or drift layer (13) and to form at least one raised 35 emitter region (16) defined by regions of etched 9. A method as claimed in claim 8, wherein the second emitter and first base layer (14), each raised base layer (18) is doped with an acceptor material emitter region having an upper surface and the during epitaxial growth. etched regions comprising bottom and sidewall surfaces; 40 10. A method as claimed in claim 9, wherein the second forminga second base layer (18) comprising SiC base layer (18) is doped at a doping level of 1018 doped with an acceptor material, wherein the atoms • cm-3 or greater during expitaxial growth. second base layer (18) covers the bottom and sidewall surfaces of the etched regions and the 11. A method as claimed in claim 1, further comprising: upper surface of each raised emitter region; 45 forming an emitter contact opening (22) through forming a plurality of raised guard rings (32) in the second base layer (IS) on the upper surface the second base layer (18), the raised guard of each raised emitter region (16) to expose rings (32) circumscribing the at least one raised emitter material, each emitter contact opening emitter region (16). (22) having bottom and sidewall surfaces; 50 forming a base contact (26) on surfaces of the 12. A method as claimed in claim 11, wherein the guard second base material (18) in the etched regions; rings (32) are formed simultaneously with the forma- and tion of the at least one emitter contact opening (22). forming an emitter contact (24) on a surface of the emitter material in each emitter contact55 13. A method of making a SiC bipolar junction transistor opening (22). comprising:

2. A method as claimed in claim 1, wherein the step of providing a collector (12) comprising SiC doped

10 19 EP 1 485 940 B1 20

with a donor material, the collector having first wherein the dopant materials are incorporated and second major surfaces; into each of the layers during growth. optionally forming a drift layer (13) on the first major surface of the collector (12), the drift layer 15. A method as claimed in claim 13, wherein the col- (13) comprising SiC doped with a donor mate- 5 lector (12) is doped with a donor material at a first rial; doping level and the drift layer (13) is doped with a forming a first base layer (14) on the first major donor material at a second doping level. surface of the collector (12) or on the drift layer (13), the first base layer (14) comprising SiC 16. A method as claimed in claim 15, wherein the first doped with an acceptor material; 10 doping level is 1018 atoms • cm-3 or greater and the forming an emitter layer (16) on the first base second doping level is 1015 atoms • cm-3 or less. layer (14), the emitter layer (16) comprising SiC doped with a donor material; 17. A method as claimed in claim 14, wherein the emitter etching through the emitter layer (16) and the layer (J 6) is doped at a doping level of 1018 atoms first base layer (14) to expose the collector (12) 15 • cm-3 or greater during epitaxial growth. or drift layer (13) and to form at least one raised emitter region (16) defmed by regions of etched 18. A method as claimed in claim 14, wherein the second emitter (16) and first base layer (14), each raised base layer (18) is doped at a doping level of 1018 emitter region having an upper surface and the atoms • cm-3 or greater during epitaxial growth. etched regions comprising bottom and sidewall 20 surfaces; 19. A method as claimed in claim 14, further comprising: forminga second base layer (18) comprising SiC doped with an acceptor dopant, wherein the sec- forming a plurality of raised guard rings (42), the ond base layer (18) covers the bottom and side- raised guard rings (42) circumscribing the one wall surfaces of the etched regions and the up- 25 or more raised emitter regions (16) and etched per surface of each raised emitter region; regions, wherein forming the plurality of raised forming a base contact layer (36) on the second guard rings (42) comprises: base layer (18); forming an emitter contact opening (22) through a first forming step of etching or otherwise the base contact layer (36) on the upper surface 30 forming openings in the base contact layer of each raised emitter region (16) to expose the (36); and second base layer (18); a second forming step wherein the base etching an emitter contact opening (22) through contact layer (36) is used as a mask to form the second base layer (18) on the upper surface openings in the second base layer (18). of each raised emitter region using the base con- 35 tact layer (36) as a mask to expose emitter ma- 20. A method as claimed in claim 19, wherein the first terial; forming step is carried out simultaneously with form- forming an emitter contact (24) on the emitter ing each emitter contact opening (22) through the material (16) in each emitter contact opening base contact layer (36) on the upper surface of each (22). 40 raised emitter region (16) to expose the second base layer (18). 14. A method as claimed in claim 13, wherein: 21. A method as claimed in claim 19, wherein the second the step of forming the drift layer (13) comprises forming step is carried out simultaneously with etch- epitaxially growing the drift layer (13) on the first 45 ing each emitter contact opening (22) through the major surface of the collector (12); second base layer (18) on the upper surface of each the step of forming the first base layer (14) com- raised emitter region using the base contact layer prisesepitaxially growingthe first base layer (14) (36) as a mask to expose emitter material. on the drift layer (13) or on the first major surface of the collector (12); 50 22. A method as claimed in any one of claims 19, 20 or the step of forming the emitter layer (16) com- 21 wherein the guard rings (42) and each emitter prises epitaxially growing the emitter layer (16) contact opening (22) are formed simultaneously. on an exposed surface of the first base layer (14); and the step of forming the second base layer (18) 55 Patentansprüche comprises epitaxially growing the second base layer (18) on an exposed surface of the emitter 1. Verfahren zur Herstellung eines SiC bipolaren layer (16); Sperrschichttransistors, das Folgendes beinhaltet:

11 21 EP 1 485 940 B1 22

Bereitstellen eines Kollektors (12), der mit ei- rungsniveau dotiert ist, und wobei das erste Dotie- nem Spendermaterial dotiertes SiC umfasst, rungsniveau höher ist als das zweite Dotierungsni- wobei der Kollektor (12) eine erste und eine veau. zweite Hauptfläche aufweist; optional Ausbilden einer Driftschicht (13) auf der 5 4. Verfahren nach Anspruch 3, wobei das erste Dotie- ersten Hauptfläche des Kollektors, wobei die rungsniveau 1018 Atome • cm -3 oder höher und das Driftschicht (13) mit einem Spendermaterial do- zweiteDotierungsniveau 10 15Atome • cm -3 oder we- tiertes SiC beinhaltet; niger ist. Ausbilden einer ersten Basisschicht (14) auf der ersten Hauptfläche des Kollektors (12) oder auf 10 5. Verfahren nach Anspruch 2, wobei der Schritt des der Driftschicht (13), wobei die erste Basis- Bildens der Emitterschicht (16) epitaxiales Aufwach- schicht (14) mit einem Akzeptormaterial dotier- senlassen der Emitterschicht (16) auf der ersten Ba- tes SiC beinhaltet; sisschicht (14) beinhaltet. Ausbilden einer Emitterschicht (16) auf der er- sten Basisschicht (14), wobei die Emitterschicht 15 6. Verfahren nach Anspruch 5, wobei die Emitter- (16) mit einem Spendermaterial dotiertes SiC schicht (16) während des epitaxialen Aufwachsen- beinhaltet; lassens mit einem Spendermaterial dotiert wird. Ätzendurch dieEmitterschicht (16) und die erste Basisschicht (14), um den Kollektor (12) oder 7. Verfahren nach Anspruch 6, wobei die Emitter- die Driftschicht (13) zu exponieren und um we- 20 schicht (16) während des epitaxialen Aufwachsen- nigstens eine erhabene Emitterregion (16) zu lassens mit einem Dotierungsniveau von 1018 Ato- bilden, die durch Regionen der geätzten Emit- men • cm-3 oder mehr dotiert wird. ter- und ersten Basisschicht (14) definiert wird, wobei jede erhabene Emitterregion eine Ober- 8. Verfahren nach Anspruch 5, wobei der Schritt des seite hat und die geätzten Regionen Boden- und 25 Bildens der zweiten Basisschicht (18) epitaxiales Seitenwandflächen aufweisen; Aufwachsenlassen der zweiten Basisschicht (18) Ausbilden einer zweiten Basisschicht (18), die auf einer exponierten Oberfläche der Emitterschicht mit einem Akzeptormaterial dotiertes SiC be- (16) beinhaltet. inhaltet, wobei die zweite Basisschicht (18) die Boden- und Seitenwandflächen der geätzten 30 9. Verfahren nach Anspruch 8, wobei die zweite Basis- Regionen und die Oberseite jeder erhabenen schicht (18) während des epitaxialen Aufwachsen- Emitterregion bedeckt; lassens mit einem Akzeptormaterial dotiert ist. Ausbilden einer Emitterkontaktöffnung (22) durch die zweite Basisschicht (18) auf der Ober- 10. Verfahren nach Anspruch 9, wobei die zweite Basis- seite jeder erhabenen Emitterregion (16), um 35 schicht (18) während des epitaxialen Aufwachsen- Emittermaterial zu exponieren, wobei jede lassens mit einem Dotierungsniveau von 1018 Ato- Emitterkontaktöffnung (22) Boden- und Seiten- men • cm-3 oder höher dotiert wird. wandflächen aufweist; Ausbilden eines Basiskontakts (26) auf Oberflä- 11. Verfahren nach Anspruch 1, das ferner Folgendes chen des zweiten Basismaterials (18) in den ge- 40 beinhaltet: ätzten Regionen; und Ausbilden eines Emitterkontakts (24) auf einer Ausbilden mehrerer erhabener Schutzringe (32) Oberfläche des Emittermaterials in jeder Emit- in der zweiten Basisschicht (18), wobei die er- terkontaktöffnung (22). habenen Schutzringe (32) die wenigstens eine 45 erhabene Emitterregion (16) umschreiben. 2. Verfahren nach Anspruch 1, wobei der Schritt des Bildens der Driftschicht (13) epitaxiales Aufwach- 12. Verfahren nach Anspruch 11, wobei die Schutzringe senlassen der Driftschicht (13) auf einer exponierten (32) gleichzeitig mit der Bildung von wenigstens ei- Oberfläche des Kollektors (12) beinhaltet, und wobei ner Emitterkontaktöffnung (22) ausgebildet werden. der Schritt des Ausbildens der ersten Basisschicht 50 (14) epitaxiales Aufwachsenlassen der ersten Ba- 13. Verfahren zur Herstellung eines SiC bipolaren sisschicht (14) auf einer exponierten Oberfläche der Sperrschichttransistors, das Folgendes beinhaltet: Driftschicht (13) beinhaltet. Bereitstellen eines Kollektors (12), der mit ei- 3. Verfahren nach Anspruch 1, wobei der Kollektor mit 55 nem Spendermaterial dotiertes SiC umfasst, einem Spendermaterial mit einem ersten Dotie- wobei der Kollektor eine erste und eine zweite rungsniveau dotiert ist und die Driftschicht (13) mit Hauptfläche aufweist; einem Spendermaterial mit einem zweiten Dotie- optionales Bilden einer Driftschicht (13) auf der

12 23 EP 1 485 940 B1 24

ersten Hauptfläche des Kollektors (12), wobei schicht (18) epitaxiales Aufwachsenlassen der die Driftschicht (13) mit einem Spendermaterial zweiten Basisschicht (18) auf einer exponierten dotiertes SiC beinhaltet; Oberfläche der Emitterschicht (16) beinhaltet; Ausbilden einer ersten Basisschicht (14) auf der wobei die Dotierungsmittelmaterialien während ersten Hauptfläche des Kollektors (12) oder auf 5 des Aufwachsenlassens in jede der Schichten der Driftschicht (13), wobei die erste Basis- integriert werden. schicht (14) mit einem Akzeptormaterial dotier- tes SiC beinhaltet; 15. Verfahren nach Anspruch 13, wobei der Kollektor Ausbilden einer Emitterschicht (16) auf der er- (12) mit einem Spendermaterial mit einem ersten sten Basisschicht (14), wobei die Emitterschicht 10 Dotierungsniveau dotiert wird und die Driftschicht (16) mit einem Spendermaterial dotiertes SiC (13) mit einem Spendermaterial mit einem zweiten beinhaltet; Dotierungsniveau dotiert wird. Ätzendurch dieEmitterschicht (16) und die erste Basisschicht (14), um den Kollektor (12) oder 16. Verfahren nach Anspruch 15, wobei das erste Do- die Driftschicht (13) zu exponieren und um we- 15 tierungsniveau 1018 Atome • cm -3 oder mehr beträgt nigstens eine erhabene Emitterregion (16) zu und das zweite Dotierungsniveau 10 15 Atome • cm -3 bilden, die durch Regionen von geätzter Emitter- oder weniger beträgt. (16) und erster Basisschicht (14) definiert wird, wobei jede erhabene Emitterregion eine Ober- 17. Verfahren nach Anspruch 14, wobei die Emitter- seite hat und die geätzten Regionen Boden- und 20 schicht (16) während des epitaxialen Aufwachsen- Seitenwandflächen beinhalten; lassens mit einem Dotierungsniveau von 1018 Ato- Ausbilden einer zweiten Basisschicht (18), die men • cm-3 oder mehr dotiert wird. mit einem Akzeptor-Dotierungsmittel dotiertes SiC beinhaltet, wobei die zweite Basisschicht 18. Verfahren nach Anspruch 14, wobei die zweite Ba- (18) die Boden- und Seitenwandflächen der ge- 25 sisschicht (18) während des epitaxialen Aufwach- ätzten Regionen und die Oberseite jeder erha- senlassens mit einem Dotierungsniveau von 1018 benen Emitterregion bedeckt; Atomen • cm-3 oder mehr dotiert wird. Ausbilden einer Basiskontaktschicht (36) auf der zweiten Basisschicht (18); 19. Verfahren nach Anspruch 14, das ferner Folgendes Ausbilden einer Emitterkontaktöffnung (22)30 beinhaltet: durch die Basiskontaktschicht (36) auf der Ober- seite jeder erhabenen Emitterregion (16), um Ausbilden mehrerer erhabener Schutzringe die zweite Basisschicht (18) zu exponieren; (42), wobei die erhabenen Schutzringe (42) die Ätzen einer Emitterkontaktöffnung (22) durch ein oder mehreren erhabenen Emitterregionen die zweite Basisschicht (18) auf der Oberseite 35 (16) und geätzten Regionen umschreiben, wo- jeder erhabenen Emitterregion unter Verwen- bei das Ausbilden der mehreren erhabenen dung der Basiskontaktschicht (36) als Maske Schutzringe (42) Folgendes beinhaltet: zum Exponieren von Emittermaterial; Ausbilden eines Emitterkontakts (24) auf dem einenersten Bildungsschritt des Ätzensund Emittermaterial (16) in jeder Emitterkontaktöff- 40 anderweitigen Bildens von Öffnungen in der nung (22). Basiskontaktschicht (36); und einen zweiten Bildungsschritt, bei dem die 14. Verfahren nach Anspruch 13, wobei: Basiskontaktschicht (36) als Maske zum Bilden von Öffnungen in der zweiten Basis- der Schritt des Bildens der Driftschicht (13)45 schicht (18) benutzt wird. epitaxiales Aufwachsenlassen der Driftschicht (13) auf der ersten Hauptfläche des Kollektors 20. Verfahren nach Anspruch 19, wobei der erste Bil- (12) beinhaltet; dungsschritt gleichzeitig mit dem Ausbilden jeder der Schritt des Ausbildens der ersten Basis- Emitterkontaktöffnung (22) durch die Basiskontakt- schicht (14) epitaxiales Aufwachsenlassen der 50 schicht (36) auf der Oberseite jeder erhabenen Emit- ersten Basisschicht (14) auf der Driftschicht (13) terregion (16) ausgeführt wird, um die zweite Basis- oder auf der ersten Hauptfläche des Kollektors schicht (18) zu exponieren. (12) beinhaltet; der Schritt des Ausbildens der Emitterschicht 21. Verfahren nach Anspruch 19, wobei der zweite Bil- (16) epitaxiales Aufwachsenlassen der Emitter- 55 dungsschritt gleichzeitig mit dem Ätzen jeder Emit- schicht (16) auf einer exponierten Oberfläche terkontaktöffnung (22) durch die zweite Basisschicht der ersten Basisschicht (14) beinhaltet; und (18) auf der Oberseite jeder erhabenen Emitterregi- der Schritt des Ausbildens der zweiten Basis- on unter Verwendung der Basiskontaktschicht (36)

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als Maske zum Exponieren von Emittermaterial régions soumises à l’attaque chimique ; et durchgeführt wird. former un contact émetteur (24) sur une surface du matériau émetteur dans chaque ouverture 22. Verfahren nach Anspruch 19, 20 oder 21, bei dem de contact émetteur (22). die Schutzringe (42) und jede Emitterkontaktöffnung 5 (22) gleichzeitig ausgebildet werden. 2. Procédé selon la revendication 1, dans lequel l’étape de formation de la couche de dérive (13) comprend la croissance épitaxiale de la couche de dérive (13) Revendications sur une surface exposée du collecteur (12), et dans 10 lequel l’étape de formation de la première couche 1. Procédé de fabrication d’un transistor à jonction bi- de base (14) comprend la croissance épitaxiale de polaire en carbure de silicium, consistant à : la première couche de base (14) sur une surface exposée de la couche de dérive (13). fournirun collecteur (12) comprenant du carbure de silicium dopé avec un matériau donneur, le 15 3. Procédé selon la revendication 1, dans lequel le col- collecteur(12) comportant une première surface lecteur est dopé avec un matériau donneur à un pre- principale et une deuxième surface principale ; mier niveau de dopage et la couche de dérive (13) éventuellement, former une couche de dérive est dopée avec un matériau donneur à un deuxième (13) sur la première surface principale du col- niveau de dopage, le premier niveau de dopage lecteur, la couche de dérive (13) comprenant du 20 étant supérieur au deuxième niveau de dopage. carbure de silicium dopé avec un matériau donneur ; 4. Procédé selon la revendication 3, dans lequel le pre- former une première couche de base (14) sur la mier niveau de dopage est de 1018 atomes • cm-3 première surface principale du collecteur (12) ou plus et le deuxième niveau de dopage est de 10 15 ou sur la couche de dérive (13), la première cou- 25 atomes • cm-3 ou moins. che de base (14) comprenant du carbure de si- licium dopé avec un matériau accepteur ; 5. Procédé selon la revendication 2, dans lequel l’étape former une couche émettrice (16) sur la premiè- de formation de la couche émettrice (16) comprend re couche de base (14), la couche émettrice (16) la croissance épitaxiale de la couche émettrice (16) comprenant du carbure de silicium dopé avec 30 sur la première couche de base (14). un matériau donneur ; produire une attaque chimique traversant la 6. Procédé selon la revendication 5, dans lequel la cou- couche émettrice (16) et la première couche de che émettrice (16) est dopée avec un matériau don- base (14) pour exposer le collecteur (12) ou la neur durant la croissance épitaxiale. couche de dérive (13) et pour former au moins 35 une région émettrice surélevée (16) délimitée 7. Procédé selon la revendication 6, dans lequel la cou- par des régions de la couche émettrice et de la che émettrice (16) est dopée à un niveau de dopage première couche de base (14) soumises à l’at- de 1018 atomes • cm-3 ou plus durant la croissance taque chimique, chaque région émettrice suré- épitaxiale. levée comportant une surface supérieure et les 40 régions soumises à l’attaque chimique compre- 8. Procédé selon la revendication 5, dans lequel l’étape nant un fond et des surfaces de parois latérales ; de formation de la deuxième couche de base (18) former une deuxième couche de base (18) com- comprend la croissance épitaxiale de la deuxième prenant du carbure de silicium dopé avec un ma- couche de base (18) sur une surface exposée de la tériau accepteur, la deuxième couche de base 45 couche émettrice (16). (18) recouvrant le fond et les surfaces de parois latérales des régions soumises à l’attaque chi- 9. Procédé selon la revendication 8, dans lequel la mique et la surface supérieure de chaque région deuxième couche de base (18) est dopée avec un émettrice surélevée ; matériau accepteur durant la croissance épitaxiale. former une ouverture de contact émetteur (22) 50 à travers la deuxième couche de base (18) sur 10. Procédé selon la revendication 9, dans lequel la la surface supérieure de chaque région émettri- deuxième couche de base (18) est dopée à un ni- ce surélevée (16) pour exposer le matériau veaude dopage de 10 18 atomes • cm -3ou plus durant émetteur, chaque ouverture de contact émet- la croissance épitaxiale. teur (22) comportant un fond et des surfaces de 55 parois latérales ; 11. Procédéselon la revendication 1, consistant en outre former un contact de base (26) sur des surfaces à: du deuxième matériau de base (18) dans les

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former une pluralité d’anneaux de garde suré- former par attaque chimique une ouverture de levés (32) dans la deuxième couche de base contact émetteur (22)à travers la deuxième cou- (18), les anneaux de garde surélevés (32) déli- che de base (18) sur la surface supérieure de mitant ladite au moins une région émettrice su- chaque région émettrice surélevée en utilisant rélevée (16). 5 la couche de contact de base (36) comme mas- que pour exposer le matériau émetteur ; 12. Procédé selon la revendication 11, dans lequel les former un contact émetteur (24) sur le matériau anneaux de garde (32) sont formés simultanément émetteur (16) dans chaque ouverture de contact à la formation de ladite au moins une ouverture de émetteur (22). contact émetteur (22). 10 14. Procédé selon la revendication 13, dans lequel : 13. Procédé de fabrication d’un transistor à jonction bi- polaire en carbure de silicium, consistant à : l’étape de formation de la couche de dérive (13) comprend la croissance épitaxiale de la couche fournirun collecteur (12) comprenant du carbure 15 de dérive (13) sur la première surface principale de silicium dopé avec un matériau donneur, le du collecteur (12) ; collecteur comportant une première surface l’étape de formation de la première couche de principale et une deuxième surface principale ; base (14) comprend la croissance épitaxiale de éventuellement, former une couche de dérive la première couche de base (14) sur la couche (13) sur la première surface principale du col- 20 de dérive (13) ou sur la première surface prin- lecteur (12), la couche de dérive (13) compre- cipale du collecteur (12) ; nant du carbure de silicium dopé avec un maté- l’étape de formation de la couche émettrice (16) riau donneur ; comprend la croissance épitaxiale de la couche former une première couche de base (14) sur la émettrice (16) sur une surface exposée de la première surface principale du collecteur (12) 25 première couche de base (14) ; et ou sur la couche de dérive (13), la première cou- l’étape de formation de la deuxième couche de che de base (14) comprenant du carbure de si- base (18) comprend la croissance épitaxiale de licium dopé avec un matériau accepteur ; la deuxième couche de base (18) sur une sur- former une couche émettrice (16) sur la premiè- face exposée de la couche émettrice (16) ; re couche de base (14), la couche émettrice (16) 30 les matériaux dopants étant incorporés dans comprenant du carbure de silicium dopé avec chacune des couches durant la croissance. un matériau donneur ; produire une attaque chimique traversant la 15. Procédé selon la revendication 13, dans lequel le couche émettrice (16) et la première couche de collecteur (12) est dopé avec un matériau donneur base (14) pour exposer le collecteur (12) ou la 35 à un premier niveau de dopage et la couche de dérive couche de dérive (13) et pour former au moins (13) est dopée avec un matériau donneur à un une région émettrice surélevée (16) délimitée deuxième niveau de dopage. par des régions de la couche émettrice (16) et de la première couche de base (14) soumises 16. Procédé selon la revendication 15, dans lequel le à l’attaque chimique, chaque région émettrice 40 premier niveau de dopage est de 10 18 atomes • cm -3 surélevée comportant une surface supérieure, ou plus et le deuxième niveau de dopage est de 10 15 et les régions soumises à l’attaque chimique atomes • cm-3 ou moins. comprenant un fond et des surfaces de parois latérales ; 17. Procédé selon la revendication 14, dans lequel la former une deuxième couche de base (18) com- 45 couche émettrice (16) est dopée à un niveau de do- prenant du carbure de silicium dopé avec un page de 1018 atomes • cm-3 ou plus durant la crois- dopant accepteur, la deuxième couche de base sance épitaxiale. (18) recouvrant le fond et les surfaces de parois latérales des régions soumises à l’attaque chi- 18. Procédé selon la revendication 14, dans lequel la mique et la surface supérieure de chaque région 50 deuxième couche de base (18) est dopée à un ni- émettrice surélevée ; veaude dopage de 10 18 atomes • cm -3ou plus durant former une couche de contact de base (36) sur la croissance épitaxiale. la deuxième couche de base (18) ; former une ouverture de contact émetteur (22) 19. Procédé selon la revendication 14, consistant en à travers la couche de contact de base (36) sur 55 outre à : la surface supérieure de chaque région émettri- ce surélevée (16) pour exposer la deuxième former une pluralité d’anneaux de garde suré- couche de base (18) ; levés (42), les anneaux de garde surélevés (42)

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délimitant lesdites une ou plusieurs régions émettrices surélevées (16) et les régions sou- mises à l’attaque chimique, la formation de la pluralité d’anneaux de garde surélevés (42) comprenant : 5

une première étape de formation par atta- que chimique ou de formation par un autre moyen d’ouvertures dans la couche de con- tact de base (36) ; et 10 une deuxième étape de formation, dans la- quelle la couche de contact de base (36) est utilisée comme masque pour former des ouvertures dans la deuxième couche de ba- se (18). 15

20. Procédé selon la revendication 19, dans lequel la première étape de formation est exécutée simulta- nément à la formation de chaque ouverture de con- tact émetteur (22) à travers la couche de contact de 20 base (36) sur la surface supérieure de chaque région émettrice surélevée (16) pour exposer la deuxième couche de base (18).

21. Procédé selon la revendication 19, dans lequel la 25 deuxième étape de formation est exécutée simulta- nément à la formation par attaque chimique de cha- que ouverture de contact émetteur (22) à travers la deuxième couche de base (18) sur la surface supé- rieure de chaque région émettrice surélevée en uti- 30 lisant la couche de contact de base (36) comme mas- que pour exposer le matériau émetteur.

22. Procédé selon l’une quelconque des revendications 19, 20 ou 21, dans lequel les anneaux de garde (42) 35 et chaque ouverture de contact émetteur (22) sont formés simultanément.

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REFERENCES CITED IN THE DESCRIPTION

This list of references cited by the applicant is for the reader’s convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

Patent documents cited in the description

• US 4762806 A [0007] • US 6218254 A [0038] • US 4945394 A [0007] • US 5323022 A [0049] • US 6218254 B [0007] [0009] • US 5409859 A [0049] • US 5726463 A [0038]

Non-patent literature cited in the description

• V. MÜNCH et al. Silicon Carbide Bipolar Transistor. • AGARWAL et al. Development of Silicon Carbide Solid State Electronics, 1978, vol. 21, 479-480 [0007] High Temperature Bipolar Devices.HITEC, Albu- • LUO et al. Demonstration of 4H-SiC Power Bipolar querque, NM, 2000 [0007] Junction Transistors. Electronic Letters, 2000, vol. 36 • BALIGA. Power Semiconductor Devices, 1996, (17 [0007] 231-232 [0034] • TANG et al. An Implanted-Emitter 4H-SiC Bipolar Transistor with High Current Gain. IEEE Electron De- vice Letters, 2001, vol. 22 (3), 119-120 [0007]

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