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System Design Choices System Design Choices Programmable System Design Choices Programmable Logic Programmable Logic • – PLD e.g. Lattice ispGAL22V10, Atmel ATF1502 CPLD – Field Programmable Gate Array (FPGA) e.g. Altera Cyclone III, Xilinx Artix-7/Zync-7000 Semi-Custom Design • – Mask Programmable Gate Array e.g. ECS CMOS Gate Array Altera HardCopy II structured ASICs – Standard Cell Design ICT PEEL22CV10 Source: ICT e.g. Alcatel Mietec MTC45000 0.35µm cell library One time use - Fuse programmable. • Full Custom Design Reprogrammable - UV/Electrically Erasable. • • 8001 8003 System Design Choices Field Programmable Gate Array – Xilinx XC4000 Programmable I/O Buffers Programmable Logic START HERE Interconnection • Point – Best possible design turnaround time CLB CLB – Cheapest for prototyping CLB CLB – Best time to market Switching Matrix – Minimum skill required CLB Semi-Custom Design I/O Buffers I/O Buffers • Vertical Routing Channel Full Custom Design Horizontal Routing Channel • – Cheapest for mass production – Fastest I/O Buffers – Lowest Power 2 1 Configurable Logic Blocks (CLBs) & I/O Blocks – Highest Density • – Most skill required Programmable Interconnect • 1optimization limited by speed/power/area trade off 2Xilinx XC4013 has 576 (24 24) CLBs and up to 192 (4 48) user I/O pins. × × 8002 8004 Slice Description X-Ref Target - Figure 2-3 SRHI D SRLO Reset Type INIT1 Q CE Sync/Async COUT INIT0 CK SR FF/LAT DX DMUX DI2 D6:1 A6:A1 W6:W1 D D O6 FF/LAT O5 DX INIT1 Q DQ D INIT0 CK DI1 SRHI CE SRLO WEN MC31 SRHI D SRLO CK Q SR DI INIT1 CE INIT0 CK SR CX CMUX DI2 C6:1 A6:A1 W6:W1 C C O6 O5 FF/LAT CX INIT1 Q CQ D INIT0 CK DI1 CE SRHI SRLO WEN MC31 SRHI CK D SRLO SR CI INIT1 Q CE INIT0 CK SR BX 3 BMUX Product Obsolete or Under Obsolescence R DI2 Field Programmable Gate Array – Xilinx XC4000 CLB Xilinx Artix-7B6:1 –A6:A1 SLICEM CLB W6:W1 B XC4000E and XC4000X Series Field Programmable Gate Arrays B O6 O5 FF/LAT BX INIT1 Q BQ D DI1 INIT0 CK CE SRHI SRLO WEN MC31 SRHI CK 4 D SRLO SR C • • • C BI 1 4 INIT1 Q CE INIT0 CK SR AX H1 DIN/H2 SR/H0 EC AMUX DI2 A6:1 A6:A1 W6:W1 A A G S/R Bypass O6 4 O5 FF/LAT CONTROL AX INIT1 Q AQ D INIT0 DI1 DIN YQ CK CE SRHI G LOGIC SRLO 3 F' SD WEN MC31 CK FUNCTION D Q G' G' SR OF AI 0/1 H' G2 G1-G4 SR CE CLK CK G1 WEN LOGIC WE CIN EC UG474_c2_02_110510 FUNCTION G' RD OF H' H' Figure 2-3: Diagram of SLICEM F', G', 1 AND Y H1 Source: Xilinx F 4 S/R Bypass 7Series FPGAs CLB User Guide www.xilinx.com 19 CONTROL DIN XQ 4x 6-input Look-UpUG474 (v1.7) November Tables 17, 2014 (LUTs) for combinational logic F LOGIC 3 F' SD FUNCTION D Q • F' G' OF H' F2 F1-F4 Carry chain supporting fast carry lookahead • F1 8x storage elements EC RD • K (CLOCK) 1 LUTs can be alternatively configured as H' X F' Multiplexer Controlled 256 bits RAM by Configuration Program X6692 • 32-bit shift register Figure 1: Simplified Block Diagram of XC4000 Series CLB (RAM and Carry Logic functions not shown) • Source: Xilinx 3Xilinx XC7A200T has 16,825 CLBs (each containing 2 slices) and up to 500 user I/O pins. Flip-Flops Clock Enable The CLB can pass the combinatorial output(s) to the inter-8005The clock enable signal (EC) is active High. The EC pin is 8007 connect network, but can also store the combinatorial shared by both storage elements. If left unconnected for results or other incoming data in one or two flip-flops, and either, the clock enable for that storage element defaults to connect their outputs to the interconnect network as well. the active state. EC is not invertible within the CLB. The two edge-triggered D-type flip-flops have common clock (K) and clock enable (EC) inputs. Either or both clock Table 2: CLB Storage Element Functionality inputs can also be permanently enabled. Storage element (active rising edge isSlice shown) Description functionality is described in Table 2. Mode K EC SR D Q X-Ref Target - Figure 2-3 Power-UpSRHI or Latches (XC4000X only) D SRLO Reset Type INIT1 Q X X X X SR FPGA - System On Chip CE Sync/Async COUT INIT0GSR CK The CLB storage elements can also be configured as SR FF/LAT latches. The two latches have common clock (K) and clock X X 1 X SR DX Flip-Flop __/ 1*DMUX 0* D D enable (EC) inputs. StorageDI2 element functionality is D6:1 A6:A1 described in Table 2. W6:W1 0 XD 0* X Q D O6 FF/LAT O5 DX 1INIT1 Q 1*DQ 0* X Q INIT0 Modern FPGAs are big enough for: D Clock Input CK DI1 Latch SRHI CE SRLO WEN MC31 SRHI 0 1* 0* D D D SRLO CK INIT1 Q SR Each flip-flop can be triggeredDI on either the rising or falling CE INIT0 Both X 0 0* X Q clock edge. The clock pin is shared by both storage ele- CK SR Legend: CX One or more soft-core processors ments. However, the clock is individually invertible for each CMUX DI2 X Don’t care • C6:1 A6:A1 storage element. Any inverter placedW6:W1 on the clock input is __/ Rising edge C C O6 SR Set or ResetFF/LAT value. Reset is default. automatically absorbed into the CLB.O5 Program memory CX INIT1 Q CQ 0* Input Dis LowINIT0 or unconnected (default value) CK DI1 SRHI • CE SRLO WEN MC31 SRHI 1* Input CKis High or unconnected (default value) D SRLO SR CI INIT1 Q CE INIT0 Data memory CK SR • BX BMUX DI2 + specialist hardware B6:1 A6:A1 W6:W1 B B O6 6-10 O5 FF/LAT May 14, 1999 (Version 1.6) BX INIT1 Q BQ D DI1 INIT0 CK CE SRHI SRLO WEN MC31 SRHI CK The new trend is for FPGAs with hard processors built in: D SRLO SR BI INIT1 Q CE INIT0 CK SR AX AMUX Xilinx Zync-7000 includes dual-core ARM A9 DI2 A6:1 A6:A1 • W6:W1 A A O6 O5 FF/LAT AX INIT1 Q AQ D INIT0 Altera Arria V includes dual-core ARM A9 DI1 CK CE SRHI SRLO • WEN MC31 CK SR AI 0/1 4 SR Cypress PSoC 4 includes ARM Cortex-M0 and programmable digital and ana- CE CLK • CK log blocks WEN WE CIN UG474_c2_02_110510 Figure 2-3: Diagram of SLICEM Artix-7 – SLICEM CLB Source: Xilinx 4here the digital block is PLD rather than FPGA 7Series FPGAs CLB User Guide www.xilinx.com 19 UG474 (v1.7) November 17, 2014 8006 8008 Mask Programmable Gate Array Standard Cell Design Logic Functions 9 Output Pads • VDD Pad 8 Input Pads 68 Gate Sites arranged as 4 columns of 17 sites each. Auto Generated Macro Blocks • – PLA – ROM – RAM 8 Input Pads System Level Blocks • GND Pad – Microprocessor core5 9 Output Pads 5Will support System On Chip applications. 8009 8011 Mask Programmable Gate Array Full Custom GND Vdd GND Vdd X X X X All design styles need full custom designers O O O O C C C C to design the base programmable logic chips B B B B • to design building blocks for semi-custom A A A A • Where large ASICs use full custom techniques they are likely to be used alongside semi-custom techniques. Vdd ACB e.g. Hand-held computer game chip O C Full custom bitslice datapath • B hand crafted for optimum area efficiency and low power consumption A GND Standard cell controller • Macro block RAM, ROM Customize Metal and Contact Window masks only. • • 8010 8012.
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