Lecture Topics

ECE 486/586 • Instruction Set Principles – Classifying Instruction Set Architectures Computer Architecture – Memory Addressing • Alignment • Byte Order Lecture # 6 – Addressing Modes – Operations in the Instruction Set

Spring 2015 Reference: Portland State University • Appendix A: Sections A.2, A.3, A.4, A.5

Register and Memory Operands ISA Comparison Memory Addressing Memory Addressing

• Byte Addressing • Two issues – Each byte has a unique address – Alignment – Byte order (Big Endian vs. Little Endian) • Word Addressing – Half-word: 16-bit (or 2 bytes) • Alignment specifies whether there are any boundaries – Word: 32-bit (or 4 bytes) for word addressing – Double word : 64-bit (or 8 bytes) – Quad word: 128-bit (or 16 bytes) • Byte order specifies how multiple bytes within a word are mapped to memory addresses

Memory Addressing Memory Addressing

• Alignment • Alignment – Must half word, words, double words begin mod 2, mod 4, – Or are there no alignment restrictions? mod 8 boundaries? 160 161 162 163 164 165 166 167 160 161 162 163 164 165 166 167 Alignment: Why Care? Memory Alignment

• Non-aligned memory references may cause multiple memory accesses

160 161 162 163 164 165 166 167

First Access Second Access • Consider a system in which memory reads return 4 bytes and a reference to a word spans a 4-byte boundary: two memory accesses are required • Complicates memory and cache controller design • Assemblers typically force alignment for efficiency

Byte Order Byte Order

• Little Endian: • Little Endian: – The least significant byte within a word (or half word or double – The least significant byte within a word (or half word or double word) is stored in the smallest address word) is stored in the smallest address

• Example: A word (5827A6FD) is stored at address 180 in little- 160 161 162 163 164 165 166 167 16 endian format. Show the contents of bytes 180 through 183.

MSB LSB

byte 1 byte 0

161 160 Byte Order Byte Order

• Little Endian: • Big Endian: – The least significant byte within a word (or half word or double – The most significant byte within a word (or half word or double word) is stored in the smallest address word) is stored in the smallest address

• Example: A word (5827A6FD) is stored at address 180 in little- 16 160 161 162 163 164 165 166 167 endian format. Show the contents of bytes 180 through 183.

Address Value 180 FD MSB LSB 181 A6 byte 1 byte 0 182 27 183 58 160 161

Byte Order Byte Order

• Big Endian: • Big Endian: – The most significant byte within a word (or half word or double – The most significant byte within a word (or half word or double word) is stored in the smallest address word) is stored in the smallest address

• Example: A word (5827A6FD) 16 is stored at address 180 in big- • Example: A word (5827A6FD) 16 is stored at address 180 in big- endian format. Show the contents of bytes 180 through 183. endian format. Show the contents of bytes 180 through 183.

Address Value 180 58 181 27 182 A6 183 FD Byte Order in Real Systems Addressing Modes

• Pros/Cons – Often exaggerated – Little Endian • Character strings appear “backwards” in registers • Intuitive when incrementing from LSB to MSB

• Big Endian: Motorola 68000, Sun Sparc, PDP-11 • Little Endian: VAX, Intel IA32 • Configurable: MIPS, ARM

Addressing Modes Addressing Modes

• Addressing modes can reduce instruction counts but at a cost • Addressing modes can reduce instruction counts but at a cost of added CPU design complexity and/or increase average CPI of added CPU design complexity and/or increase average CPI

• Example (usage of auto-increment mode): • Example (usage of displacement mode): – With auto-increment mode: – With displacement mode: Add R1, (R2)+ Add R4, 100(R1) – Without auto-increment mode – Without displacement mode Add R1, (R2) Add R1, #100 Add R2, #1 Add R4, (R1) Sub R1, #100 Addressing Modes Frequency of Addressing Modes

• Addressing modes can reduce instruction counts but at a cost of added CPU design complexity and/or increase average CPI

• Example (usage of displacement mode): – With displacement mode: Add R4, 100(R1) – Without displacement mode Add R1, #100 Add R4, (R1) Sub R1, #100

Support most frequently used addressing modes (make the common case fast)

Displacement Values are Widely Immediate Operand Frequency Distributed Distribution of Immediate Values Type and Size of Operands

Operations in the Instruction Set Most Frequent 80x86 Instructions

Most widely executed instructions are the simple operations of an instruction set Optimize the common case => make the common instructions run as fast as possible