Datapath Components and The

ΗΜΥ 312 -- ΑΡΧΙΤΕΚΤΟΝΙΚΗ ΗΛΕΚΤΡΟΝΙΚΩΝ ΥΠΟΛΟΓΙΣΤΩΝ

ΔΙΑΛΕΞΕΙΣ 12-13: CPU Datapath Design – Intro to ALU

Διδάσκων: Χάρης Θεοχαρίδης, ΗΜΜΥ ([email protected]) [Προσαρμογή από Computer Architecture, Computer Organization and Design, Patterson & Hennessy, © 2005 και Superscalar Microprocessor Design, Johnson, © 1992 ] The Stored Program Computer

• 1943: ENIAC – Presper Eckert and John Mauchly -- first general electronic computer (or was it John V. Atananasoff in 1939?) – Hard-wired program -- settings of dials and switches • 1944: Beginnings of EDVAC – among other improvements, includes program stored in memory • 1945: John von Neumann – wrote a report on the stored program concept, known as the First Draft of a Report on EDVAC • The basic structure proposed in the draft became known as the “von Neumann machine” (or model). – a memory, containing instructions and data – a processing unit, for performing arithmetic and logical operations – a control unit, for interpreting instructions

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.2 Von Neumann Model

MEMORY

MAR MDR

INPUT OUTPUT Keyboard Monitor PROCESSING UNIT Mouse Printer Scanner LED Disk, etc. ALU REG FILE Disk, etc.

CONTROL UNIT

PC IR

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.3 Data Path Components • Global bus – Set of wires that carry n-bit signals to many components – Inputs to bus are controlled by triangle structure called tri-state devices » Place signal on bus when enabled » Only one (n-bit) signal should be enabled at a time » Control unit decides which signal “drives” the bus – Any number of components can read bus » Register only captures bus data if write-enabled by the control unit

• Memory and I/O – Control signals and data registers for memory and I/O devices – Memory: LW, SW – Input (keyboard): Interrupt, DMA – Output (text display): Interrupt, DMA

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.4 Data Path Components (cont.) • ALU/FPU – Input: register file or sign-extended bits from IR (immediate field) – Output: bus; used by… » Condition code registers » Register file » Memory and I/O registers

• Register File – Two read addresses, one write address – Input: n-bits from bus » Result of ALU operation or memory (or I/O) read – Outputs: two n-bit » Used by ALU, PC, memory address » Data for store instructions passes through ALU

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.5 Instructions (ISA)

• Fundamental unit of work • Constituents – Opcode: operation to be performed – Operands: data/locations to be used for operation

• Encoded as a sequence of bits (just like data!) – Sometimes have a fixed length (e.g., 16 or 32 bits) – Atomic: operation is either executed completely, or not at all

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.6 Instruction Processing

FETCH instruction from mem.

DECODE instruction

EVALUATE ADDRESS

FETCH OPERANDS

EXECUTE operation

STORE result

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.7 Instruction Processing: FETCH • Idea – Put next instruction in IR & increment PC F

• Steps D – Load contents of PC into MAR – Increment PC – Send “read” signal to memory EA – Read contents of MDR, store in IR

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.8 Instruction Processing: DECODE

• Identify opcode F – In LC-3, always first four bits of instruction – 4-to-16 decoder asserts control line corresponding D to desired opcode

EA • Identify operands from the remaining bits – Depends on opcode e.g., for LDR, last six bits give offset OP e.g., for ADD, last three bits name source operand #2

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.9 Instruction Processing: EVALUATE ADDRESS

• Compute address F – For loads and stores – For control-flow instructions D

• Examples EA – Add offset to base register (as in LDR) – Add offset to PC (as in LD and BR) OP

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.10 Instruction Processing: FETCH OPERANDS

• Get source operands for operation F

D • Examples – Read data from register file (ADD) – Load data from memory (LDR) EA

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.11 Instruction Processing: EXECUTE

• Actually performs operation F

D • Examples – Send operands to ALU and assert ADD signal – Do nothing (e.g., for loads and stores) EA

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.12 Instruction Processing: STORE

• Write results to destination F – Register or memory D • Examples – Result of ADD is placed in destination reg. EA – Result of load instruction placed in destination reg. – For store instruction, place data in memory OP » Set MDR » Assert WRITE signal to memory EX

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.13 Datapath and Control Unit

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.14 Tracking Control Signals - Cycle 1

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.15 Tracking Control Signals - Cycle 2

SW LW

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.16 Tracking Control Signals - Cycle 3

0 01 ADD SW LW

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.17 Tracking Control Signals - Cycle 4

SUB ADD SW LW

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.18 Tracking Control Signals - Cycle 5

SUB ADD SW LW

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.19 Changing the Sequence of Instructions • In the FETCH phase, we incremented the Program Counter by 1 (address)

• What if we don’t want to always execute the instruction that follows this one? – examples: loop, if-then, function call

• Need special instructions that change the contents of the PC. • These are called jumps and branches. – jumps are unconditional -- they always change the PC – branches are conditional -- they change the PC only if some condition is true (e.g., the contents of a register is zero)

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.20 Instruction Processing Summary

• Instructions look just like data -- it’s all interpretation.

• Three basic kinds of instructions: – computational instructions (ADD, AND, …) – data movement instructions (LD, ST, …) – control instructions (JMP, BRnz, …)

• Six basic phases of instruction processing: F ® D ® EA ® OP ® EX ® S – not all phases are needed by every instruction – phases may take variable number of machine cycles

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.21 Driving Force: The Clock

• The clock is a signal that keeps the control unit moving – At each clock “tick,” control unit moves to the next machine cycle -- may be next instruction or next phase of current instruction. • Clock generator circuit: – Based on crystal oscillator – Generates regular sequence of “0” and “1” logic levels – Clock cycle (or machine cycle) -- rising edge to rising edge

“1” “0” Machine time® Cycle

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.22 Instructions vs. Clock Cycles

• MIPS vs. MHz – MIPS = millions of instructions per second – MHz = millions of clock cycles per second

• These are not the same -- why?

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.23 The Control Unit

• Program is stored in memory – as machine language instructions, in binary • The task of the control unit is to execute programs by repeatedly: – Fetch from memory the next instruction to be executed. – Decode it, that is, determine what is to be done. – Execute it by issuing the appropriate signals to the ALU, memory, and I/O subsystems. – Continues until the HALT instruction

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.24 von Neumann Architecture

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.25 (c) Yngvi Bjornsson The Von Neumann Architecture

Bus

Processor (CPU)

Memory Input-Output Control Unit

ALU Communicate with Store data and program "outside world", e.g. • Screen Execute program • Keyboard • Storage devices • ... Do arithmetic/logic operations requested by program

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.26 The ALU Subsystem

• The ALU (Arithmetic/Logic Unit) performs – mathematical operations (+, -, x, /, …) – logic operations (=, <, >, and, or, not, ...) • In today's computers integrated into the CPU • Consists of: – Circuits to do the arithmetic/logic operations. – Registers (fast storage units) to store intermediate computational results. – Bus that connects the two.

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.27 Structure of the ALU

• Registers: – Very fast local memory cells, that store R0 operands of operations and R1 intermediate results. – CCR (condition code register), a special R2 purpose register that stores the result of <, = , > operations • ALU circuitry: – Contains an array of circuits to do Rn mathematical/logic operations. • Bus: – Data path interconnecting the registers ALU circuitry to the ALU circuitry.

GT EQ LT

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.28 28 ALU and its importance qArithmetic and Logic Unit (ALU) ● It is a functional box designed to perform basic arithmetic, logic, and shift operations on the data. ● Implementation of the basic operations such as logic, program control, and data transfer operations are easier than arithmetic and I/O operations. Therefore, in this section we concentrate on arithmetic operations.

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.29 Why do we need to improve the ALU? qArithmetic and Logic Unit (ALU) ● In an attempt to improve the performance, this section will talk about the Arithmetic Logic Unit. ● In regard to our previous mentions about CPU time (T), we are looking at techniques to reduce p.

T = Ic * CPI * t = Ic * (p+m*k)* t

Instruction Count Clock

Processor Memory Latency (+ Cache)

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.30 Review: MIPS Arithmetic Instructions 31 25 20 15 5 0 zeroovf 1 R-type: op Rs Rt Rd funct 1 A 32 ALU result I-Type: op Rs Rt Immed 16 32 B 32 4 ● expand immediates to 32 bits before ALU m (operation) ● 10 operations so can encode in 4 bits 0 add Type op funct 1 addu ADD 00 100000 2 sub ADDU 00 100001 3 subu

SUB 00 100010 Type op funct 4 and SUBU 00 100011 00 101000 5 or AND 00 100100 00 101001 6 xor OR 00 100101 SLT 00 101010 7 nor XOR 00 100110 SLTU 00 101011 a slt NOR 00 100111 00 101100 b sltu

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.31 Logic Operations Logic Operation Symbol MIPS instruction

shift left << sll $10, $16, 8

shift right >> srl $10, $16, 8

AND & and $3, $7, $8

OR | or $3, $7, $8 R-type (add, sub) instruction format: op rs rt rd shamt funct

6 bits 5 5 5 5 6 = 32 opcode 1st src 2nd src dest shift amount func --> fields

For shift instructions (shift left and shift right), the 1st source register is unused.

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.32 ALU q Some ALU operations: ● arithmetic:

● logic:

● “comparison”:

q Big Picture:

What’s in there?? How do we build it??

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.33 Principles qArithmetic and Logic Unit (ALU) ● For a simple machine, the ALU should at least be able to perform operations such as: - add - increment - subtract - decrement • • • qArithmetic and Logic Unit (ALU) ● A simple ALU is basically an adder and some control circuits augmented by special circuits to carry out the logic and shift operations.

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.34 Serial/Parallel/Modular ALUs qArithmetic and Logic Unit (ALU) ● An ALU can be of three types: - Serial - Parallel - Functional (Modular)

● Similar to the definition of serial and parallel adders, one can define serial and parallel ALUs. ● In a serial ALU, one bit of the operand(s) participates in the operation during each clock pulse. ● In a parallel ALU, operation on all the bits of the operand(s) is initiated simultaneously. - In simple terms a parallel ALU can be looked at as a cascade of identical units forming a one dimensional array of cells.

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.35 Parallel ALU qArithmetic and Logic Unit (ALU) ● Parallel ALU

Control Signals

B A B B n n 2 A2 1 A1

C C C C n+1 n 3 C2 1 F F n 2 F1

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.36 Parallel ALU qArithmetic and Logic Unit (ALU) ● Parallel ALU - ALU operation is determined by the control signals. - In a very simple form, the bit-pattern of the control signal is determined by the operation code. - In a parallel ALU, one needs to determine the design of a unit and then replicate it.

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.37 Simple ALU Design Example qArithmetic and Logic Unit (ALU) ● A Simple Arithmetic Logic Unit

A i X i C S i+1 2

S1 Yi Fi

C Z i i M

-S2, S1, S0, and M are the control signals.

-Ai, Bi, and Ci are the operand bits and carry-in, respectively.

-Fi and Ci+1 are the result bit and carry-out, respectively. ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.38 Simple ALU Design Example qArithmetic and Logic Unit (ALU) ● A Simple Arithmetic Logic Unit Full Adder A i X i C S i+1 2

S1 Yi Fi

C Z i i M

-S2, S1, S0, and M are the control signals.

-Ai, Bi, and Ci are the operand bits and carry-in, respectively.

-Fi and Ci+1 are the result bit and carry-out, respectively. ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.39 Simple ALU Design Example qArithmetic and Logic Unit (ALU) ● A Simple Arithmetic Logic Unit - The function of each stage can be defined as:

Fi º Xi Å Yi Å Zi

Ci+1 º XiYi +(XiÅYi)Zi = XiYi+XiZi+YiZi - By appropriate setting of the control signals one can initiate a variety of the operations.

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.40 Simple ALU Design Example qArithmetic and Logic Unit (ALU) ● A Simple Arithmetic Logic Unit — Example

M=0 S2 =1 S1 =0 Þ F ¬ A Å B S0 =1 C1 =x

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.41 Simple ALU Design Example qArithmetic and Logic Unit (ALU) ● A Simple Arithmetic Logic Unit — Example

M=1 S2 =1 S1 =1 Þ F ¬ A - 1 S0 =1 C1 =0

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.42 Improvements? qArithmetic and Logic Unit (ALU) ● As discussed before a parallel ALU offers a higher speed relative to a serial ALU. ● How can one improve the performance (speed) of ALU further? ● Is it possible to build (design) an ALU faster than a parallel ALU?

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.43 Functional (Modular) ALU qArithmetic and Logic Unit (ALU) ● Functional (modular) ALU - ALU is a collection of independent units each tailored for a specific operation. As a result, independent operations can be overlapped. - This approach allows an additional degree of concurrency relative to a parallel ALU, since it allows several operations to be performed on data simultaneously. - This speed improvement comes at the expense of extra overhead needed to detect data independent operations.

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.44 Functional (Modular) ALU qArithmetic and Logic Unit (ALU) ● Functional (modular) ALU

Adder1 Adder2 Subtractor

Multiplier • • •

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.45 How do we design an ALU? qArithmetic and Logic Unit (ALU) ● Is it possible to improve the performance of an ALU further? ● Naturally, we can improve the performance (physical speed) by taking advantage of the advances in technology. ● How can we improve the logical speed of the ALU further? qArithmetic and Logic Unit (ALU) ● In a functional ALU, is it possible to devise algorithms which allow one to improve the performance of the basic operations? ● If this is a valid direction, then the question of how to design a fast ALU will change to how to design a fast adder, a fast multiplier, ...?"

As a computer architect, how do you design an ALU?

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.46 Review: A 32-bit Adder/Subtractor add/subt q Built out of 32 full c0=carry_in adders (FAs) A0 1-bit FA S0 B0 carry_in c1

A1 1-bit FA S1 A 1 bit B1 FA S c2 B A2 1-bit FA S2 carry_out B2 c3

S = A xor B xor carry_in . c31 carry_out = AÙB v AÙcarry_in v BÙcarry_in A 1-bit (majority function) 31 FA S31 B 31 c =carry_out q Small but slow! 32

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.47 Lets start with the addition… qFast Adder ● How to design an adder faster than a parallel adder? ● What is the major bottle-neck in a parallel adder? ● Is the carry generation and propagation the major bottleneck? ● Is it possible to eliminate, moderate, or reduce the delay of carry generation and propagation?

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.48 How do we speed up Adders? qFast Adder ● Carry Lookahead: Generate and propagate carries ahead of time relative to a parallel adder. - Scheme 1 - Scheme 2 ● Carry Select

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.49 Recall from ECE 210/211/212/213

● Basic Building Block — A 4-Bit Ripple-Carry Adder ● Timing: Let Dt propagation delay of 1 gate

F1 = 2Dt C2 = 2Dt

F2 = 4Dt C3 = 4Dt

F3 = 6Dt C4 = 6Dt

F4 = 8Dt C5 = 8Dt or, give n –bits, it requires 2n logic levels (gate delays) A B B A B A B4 4 3 A3 2 2 1 1

C5 C C4 C3 C2 1 Carry-out FA FA FA FA Carry-in

F F3 F 4 2 F1

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.50 Carry Lookahead Adder (CLA) qFast Adder ● Carry Lookahead (Scheme 1)

Ci+1=AiBi+(AiÅBi)Ci=AiBi+(Ai+Bi)Ci

Carry Propagate Term (P ) Carry Generate term (Gi) i

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.51 Σχεδιασμός CLA

q Από ένα FA, διαχωρίζουμε μεταξύ της παραγωγής (generation) του κρατουμένου (όταν ένα νέο κρατούμενο παράγεται, Cout=1) και της μετάδοσης (propagation) του κρατουμένου (όταν ένα υπάρχον Cin μεταδίδεται στο Cout)

q Παραγωγή: Gi = AiBi: if 1, Ci+1=1

q Μετάδοση: Pi = Ai Å Bi: εάν 1 τότε Ci+1 = Ci

Full Adder (FA) Partial Full Adder (PFA)

Bi Ai Ai

Bi Si

Ci+1

Ci Si Gi Pi Ci

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.52 Μπλοκ CLA

qΥλοποίηση:

● C1 = G0+P0 C0

● C2 = G1+P1C1 = G1+P1(G0+P0C0) = G1+P1G0+P1P0C0

● C3 = G2 + P2C2 = G2+P2G1+P2P1G0+P2P1P0C0

● C4 = G3+P3G2+P3P2G1+P3P2P1G0 + P3P2P1P0 C0 = G0-3 + P0-3C0 Οµάδα Παραγωγής Οµάδα Κρατουµένου Μετάδοσης Κρατουµένου

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.53 Λογική Παραγωγής/Μετάδοσης για 4-bit CLA

Όλα 2-επιπέδων à Το Cout υπολογίζεται γρήγορα

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.54 Carry Lookahead

qFast Adder — Carry Lookahead (Scheme 1) ● Extended (CLA) 4-Bit Full Adder

Carry Lookahead (Scheme 1)

g g 4 P4 g3 P3 2 P2 g P1 C5 F F F 1 4 3 2 F1 (F.A.) (F.A.) (F.A.) (F.A.) C3 C2 C1 C4

B4 A 4 B3 A 3 B2 A 2 B1 A 1

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.55 Carry Lookahead

qFast Adder — Carry Lookahead (Scheme 1) ● Extended (CLA) 4-Bit Full Adder — Timing

ps and gs are generated in 1Dt

Cs are generated after another 2Dt

Fs are generated after another 2Dt à 5Dt (or logic levels) for 4-bits à for n-bits ??

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.56 Carry Lookahead

qFast Adder — Carry Lookahead (Scheme 1) - Extended (CLA) 4-Bit Full Adders in Ripple - What is the speedup w.r.t. a non-CLA (ripple) for n bits?

Bn-3 - Bn A n-3 - A n B5- B8 A 5- A 8 B1- B4 A1- A 4

Extended Extended Extended 4-Bit F.A. 4-Bit F.A. 4-Bit F.A. Carry-out C1

Fn-3 - Fn F5- F8 F1- F4

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.57 Carry Lookahead

qFast Adder — Carry Lookahead (Scheme 2)

CLA 2 CLA 2 CLA 2

B29-32 A29-32 B5 -B 8 A 5 - A8 B1 -B 4 A 1 -A 4 Carry-out 4-Bit F.A. 4-Bit F.A. 4-Bit F.A. C1

F29-32 F5 -F8 F1 -F4

● Timing CLA = 5Dt Cascades of CLAs overlap 1Dt operation

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.58 Carry Select qFast Adder ● Carry Select - Carry-in to a 4-bit full adder is either 0 or 1. - Duplicate each stage - e.g., 4-bit full adder. - Initiate each unit in a stage with carry-in of 0 and 1. - Use a multiplexer to select the correct answer.

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.59 Carry Select qFast Adder — Carry Select 8-bit

B5 - B 8 A 5 - A 8 B5 - B8 A5 - A8 B 1 - B4 A 1 - A4 1 0

Carry-in 4-B it 4-B it 4-B it Full Adder Full Adder Full Adder

" " ' ' F5 -F8 F5 - F8 F1 - F4

MUX 10Dt 12Dt

F4 - F8

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.60 ALU Questions - Practice qQuestions ● Calculate the execution time of a 16-bit adder using carry lookahead scheme 1. ● Formulate the execution time of an n-bit adder using carry lookahead scheme 1 (n is a multiple of 4). ● Calculate the execution time of a 16-bit adder using carry lookahead Scheme 2. ● Formulate the execution time of an n-bit adder using carry lookahead scheme 2 (n is a multiple of 4). ● Calculate the execution time of a 16-bit adder using carry select scheme. ● Formulate the execution time of an n-bit adder using carry select scheme. ● Is it possible to combine carry lookahead and carry select concepts to design a faster adder?

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.61 ΕΠΟΜΕΝΗ ΔΙΑΛΕΞΗ ΚΑΙ ΚΑΤ’ΟΙΚΟΝ ΜΕΛΕΤΗ

q ΕΠΟΜΕΝΗ ΕΝΟΤΗΤΑ – Αριθμητική Η/Υ και βελτιστοποίηση ALU (Computer Arithmetic and ALU Improvements)

q ΚΑΤ’ΟΙΚΟΝ ΜΕΛΕΤΗ ● Κεφάλαια 5-6 – Patterson&Hennessy (από το βιβλίο του ΗΜΥ212) ● Παραρτήματα Β και Ι του βιβλίου σας

ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.62